MAXIM MAX1242, MAX1243 User Manual
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__________________General Description
The MAX1242/MAX1243 are low-power, 10-bit analogto-digital converters (ADCs) available in 8-pin packages. They operate with a single +2.7V to +5.25V
supply and feature a 7.5µs successive-approximation
ADC, a fast track/hold (1.5µs), an on-chip clock, and a
high-speed, 3-wire serial interface.
Power consumption is only 3mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.
The MAX1242 has an internal 2.5V reference, while the
MAX1243 requires an external reference. The MAX1243
accepts signals from 0V to V
REF
, and the reference
input range includes the positive supply rail. An external clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and Microwire™.
Excellent AC characteristics and very low power combined with ease of use and small package size make
these converters ideal for remote-sensor and dataacquisition applications, or for other circuits with
demanding power consumption and space requirements. The MAX1242/MAX1243 are available in 8-pin
DIP and SO packages.
Applications
Portable Data Logging Process Control Monitoring
Test Equipment Temperature Measurement
Isolated Data Acquisition
________________________________Features
♦ +2.7V to +5.25V Single-Supply Operation
♦ 10-Bit Resolution
♦ Internal 2.5V Reference (MAX1242)
♦ Small Footprint: 8-Pin DIP and SO Packages
♦ Low Power: 3.7mW (73ksps, MAX1242)
3mW (73ksps, MAX1243)
66µW (1ksps, MAX1243)
5µW (power-down mode)
♦ Internal Track/Hold
♦ SPI™/QSPI™/Microwire™ 3-Wire Serial Interface
♦ Pin-Compatible 12-Bit Upgrades:
MAX1240/MAX1241
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
________________________________________________________________
Maxim Integrated Products
1
19-1156; Rev 2; 6/98
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Note:
Order the MAX1242A in place of the MAX1242C. Order the
MAX1242B in place of the MAX1242D.
________________Functional Diagram
7
AIN
T/H
DOUT
6
1
5
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC
2.5V
REFERENCE
MAX1242 ONLY
INT
CLOCK
10-BIT
SAR
8
2
3
REF
4
SHDN
SCLK
CS
MAX1242
MAX1243
V
DD
GND
Pin Configuration
_________________Ordering Information
±18 Plastic DIP-40°C to +85°CMAX1242BEPA
±1/28 Plastic DIP-40°C to +85°CMAX1242AEPA
±1/28 SO0°C to +70°CMAX1242ACSA
±1
±1
±1/2
INL
(LSB)
8 SO
8 Plastic DIP
8 Plastic DIP
PIN-
PACKAGE
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°CMAX1242BCSA
MAX1242BCPA
MAX1242ACPA
PART
查询MAX1242供应商
TOP VIEW
V
DD
1
AIN
2
3
4
MAX1242
MAX1243
DIP/SO
SHDN
REF
SCLK
8
CS
7
DOUT
6
5
GND
Gain Temperature Coefficient
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +5.25V; 73ksps; f
S
CLK
= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; V
REF
= 2.5V applied to REF pin; TA= T
MIN
to T
MAX
; unless otherwise noted.)
V
DD
to GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (V
DD
+ 0.3V)
REF to GND...............................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (V
DD
+ 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW
SO (derate 5.88mW/°C above +70°C)........................471mW
CERDIP (derate 8.00mW/°C above +70°C)................640mW
Operating Temperature Ranges
MAX1242/MAX1243_C_A..................................0°C to +70°C
MAX1242/MAX1243_E_ A..............................-40°C to +85°C
MAX1242/MAX1243_MJA ............................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ANALOG INPUT
CONVERSION RATE
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps, f
SCLK
= 2.1MHz)
DC ACCURACY (Note 1)
MAX124_B ±2
Input Voltage Range 0 V
REF
V
Input Capacitance
Aperture Jitter <50 ps
16 pF
MAX124_A
MAX124_B
MAX124_A
Aperture Delay t
AP
30 nsFigure 9
Track/Hold Acquisition Time t
ACQ
1.5 µs
Throughput Rate 73 kspsf
SCLK
= 2.1MHz
Conversion Time
PARAMETER SYMBOL MIN TYP MAX UNITS
±1
Offset Error
LSB
Differential Nonlinearity DNL ±1 LSB
±1.0
±2
Gain Error (Note 3)
±1
Resolution 10 Bits
Relative Accuracy (Note 2)
±0.5
LSB
t
CONV
5.5 7.5 µs
Small-Signal Bandwidth
Signal-to-Noise Plus
Distortion Ratio
SINAD 66 dB
2.25 MHz
Full-Power Bandwidth
Total Harmonic Distortion THD -70 dB
1.0
-3dB rolloff
MHz
CONDITIONS
Spurious-Free Dynamic Range
ppm/°C
No missing codes over temperature
MAX124_B
±0.25
SFDR 70
Up to the 5th harmonic
dB
MAX124_A
LSB
DC ACCURACY (Note1)
CONVERSION RATE
ANALOG INPUT
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5p-p, 73ksps, f
SCLK
=2.1MHz)
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V; 73ksps; f
S
CLK
= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external
reference; V
REF
= 2.5V applied to REF pin; TA= T
MIN
to T
MAX
; unless otherwise noted.)
Capacitive Bypass at REF 4.7 µF
Load Regulation (Note 5) 0.35 mV0mA to 0.2mA output load
REF Temperature Coefficient ±30 ppm/°CMAX1242
REF Short-Circuit Current 30 mA
REF Output Voltage 2.470 2.500 2.530 VTA= +25°C (Note 4)
Power-Supply Rejection (Note 7) PSR VDD= V
DD
(min)
to V
DD
(max)
, full-scale input
1.00 VDD+
50mV
Supply Current I
DD
3.0
0.8
VDD> 3.6V
I
SINK
= 16mA
Output Voltage High
SCLK, CS Input High Voltage
V
IH
2.0
V
SCLK, CS Input Low Voltage
Capacitive Bypass at REF 0.1 µF
V
IL
0.8
VDD≤ 3.6V
V
V
OH
VDD- 0.5 V
Three-State Leakage Current I
L
±0.01 ±10
I
SOURCE
= 0.5mA
µA
CS = V
DD
Three-State Output Capacitance C
OUT
15 pF
CS = V
DD
(Note 6)
Output Voltage Low V
OL
0.4
V
PARAMETER SYMBOL MIN TYP MAX UNITS
I
SINK
= 5MA
SHDN Input Mid Voltage
V
SM
1.1 VDD- 1.1 V
SHDN Voltage, Floating
V
FLT
VDD/ 2 V
SHDN Max Allowed Leakage,
Mid Input
±100
SHDN = float
nA
SHDN = float
SCLK, CS Input Capacitance
Input Voltage Range V
C
IN
15 pF
SHDN Input High Voltage
V
SH
VDD- 0.4
(Note 6)
V
SHDN Input Low Voltage
V
SL
0.4 V
Input Resistance
SHDN Input Current
±4.0
18 25 kΩ
REF Input Current in Shutdown
µA
SHDN = 0V or V
DD
SCLK, CS Input Hysteresis
V
HYST
±0.01 10 µA
SHDN = 0V
CONDITIONS
Input Current
0.2 V
SCLK, CS Input Leakage
I
IN
±0.01 ±1
100 150 µA
µAVIN= 0V or V
DD
Operating mode (MAX1242)
VDD= 5.25V
Operating mode (MAX1243)
VDD= 5.25V
VDD= 3.6V
Power-down
VDD= 5.25V
VDD= 3.6V
Supply Voltage V
DD
V
VDD= 3.6V
1.9 10
3.5 15
±0.3
1.6 2.5
0.9 1.5
1.8 3.0
1.4 2.0
2.7 5.25
mA
µA
mV
Operating mode (MAX1242)
EXTERNAL REFERENCE (VREF = 2.5V)
INTERNAL REFERENCE (MAX1242 only)
DIGITAL INPUTS: SCLK,
CCSS,SSHHDDNN
DIGITAL OUTPUT: DOUT
POWER REQUIREMENTS
MAX1242/MAX1243
+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD= +2.7V to +5.25V, circuit of Figure 9, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Tested at V
DD
= +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nulled.
Note 4: Sample tested to 0.1% AQL.
Note 5: External load should not change during conversion for specified accuracy.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Measured as [V
FS(VDD
(min)
) - VFS(V
DD
(max)
)].
Note 8: To guarantee acquisition time, t
ACQ
is the maximum time the device takes to acquire the signal, and is also the minimum
time needed for the signal to be acquired.
DOUT DOUT
6k
DGND
C
LOAD
= 50pF C
LOAD
= 50pF
6k
DGND
+2.7V
b) High-Z to V
OL
and VOH to V
OL
a) High-Z to VOH and VOL to V
OH
Figure 1. Load Circuits for DOUT Enable Time
Figure 2. Load Circuits for DOUT Disable Time
MAX124_ _M
MAX124_ _C/E
Figure 1, C
LOAD
= 50pF
Figure 1,
C
LOAD
= 50pF
CS = VDD(Note 8)
Figure 2, C
LOAD
= 50pF
CONDITIONS
ns240t
DV
CS Fall to Output Enable
ns
20 200
t
DO
µs1.5t
ACQ
Acquisition Time
SCLK Fall to Output Data Valid
ns240t
CS
CS Pulse Width
ns0t
STR
DOUT Rise to SCLK Rise (Note 6)
ns50t
CS0
SCLK Low to CS Fall Setup Time
ns240t
TR
CS Rise to Output Disable
MHz0 2.1f
SCLK
SCLK Clock Frequency
ns200t
CH
SCLK Pulse Width High
ns200t
CL
SCLK Pulse Width Low
UNITSMIN TYP MAX
SYMBOLPARAMETER
20 240
b) V
DOUT
to High-Za) V
OL
DOUT
OH
6k
DGND
to High-Z
C
= 50pF C
LOAD
+2.7V
6k
DGND
LOAD
= 50pF
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