MAXIM MAX1242, MAX1243 User Manual

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__________________General Description

The MAX1242/MAX1243 are low-power, 10-bit analog­to-digital converters (ADCs) available in 8-pin pack­ages. They operate with a single +2.7V to +5.25V
supply and feature a 7.5µs successive-approximation
ADC, a fast track/hold (1.5µs), an on-chip clock, and a
high-speed, 3-wire serial interface.

Power consumption is only 3mW (VDD= 3V) at the
73ksps maximum sampling speed. A 2µA shutdown
mode reduces power at slower throughput rates.

The MAX1242 has an internal 2.5V reference, while the
MAX1243 requires an external reference. The MAX1243
accepts signals from 0V to V

REF

, and the reference
input range includes the positive supply rail. An exter­nal clock accesses data from the 3-wire interface,
which connects directly to standard microcontroller I/O
ports. The interface is compatible with SPI™, QSPI™,
and Microwire™.

Excellent AC characteristics and very low power com­bined with ease of use and small package size make
these converters ideal for remote-sensor and data­acquisition applications, or for other circuits with
demanding power consumption and space require­ments. The MAX1242/MAX1243 are available in 8-pin
DIP and SO packages.

Applications

Portable Data Logging Process Control Monitoring
Test Equipment Temperature Measurement

Isolated Data Acquisition

________________________________Features

♦ +2.7V to +5.25V Single-Supply Operation
♦ 10-Bit Resolution
♦ Internal 2.5V Reference (MAX1242)
♦ Small Footprint: 8-Pin DIP and SO Packages
♦ Low Power: 3.7mW (73ksps, MAX1242)

3mW (73ksps, MAX1243)
66µW (1ksps, MAX1243)
5µW (power-down mode)

♦ Internal Track/Hold
♦ SPI™/QSPI™/Microwire™ 3-Wire Serial Interface
♦ Pin-Compatible 12-Bit Upgrades:

MAX1240/MAX1241

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

________________________________________________________________

Maxim Integrated Products

1

19-1156; Rev 2; 6/98

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

Ordering Information continued at end of data sheet.

Note:

Order the MAX1242A in place of the MAX1242C. Order the

MAX1242B in place of the MAX1242D.

________________Functional Diagram

7

AIN

T/H

DOUT

6

1

5

OUTPUT

SHIFT

REGISTER

CONTROL

LOGIC

2.5V

REFERENCE

MAX1242 ONLY

INT

CLOCK

10-BIT

SAR

8

2

3

REF

4

SHDN

SCLK

CS

MAX1242
MAX1243

V

DD

GND

Pin Configuration

_________________Ordering Information

±18 Plastic DIP-40°C to +85°CMAX1242BEPA

±1/28 Plastic DIP-40°C to +85°CMAX1242AEPA

±1/28 SO0°C to +70°CMAX1242ACSA
±1

±1

±1/2

INL

(LSB)

8 SO

8 Plastic DIP

8 Plastic DIP

PIN-

PACKAGE

TEMP. RANGE

0°C to +70°C
0°C to +70°C

0°C to +70°CMAX1242BCSA

MAX1242BCPA

MAX1242ACPA

PART

查询MAX1242供应商

TOP VIEW

V

DD

1

AIN

2
3
4

MAX1242
MAX1243

DIP/SO

SHDN

REF

SCLK

8

CS

7

DOUT

6
5

GND

Gain Temperature Coefficient

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

2 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS

(VDD= +2.7V to +5.25V; 73ksps; f

S

CLK

= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external

reference; V

REF

= 2.5V applied to REF pin; TA= T

MIN

to T

MAX

; unless otherwise noted.)

V

DD

to GND.............................................................-0.3V to +6V

AIN to GND................................................-0.3V to (V

DD

+ 0.3V)

REF to GND...............................................-0.3V to (V

DD

+ 0.3V)

Digital Inputs to GND...............................................-0.3V to +6V

DOUT to GND............................................-0.3V to (V

DD

+ 0.3V)

DOUT Current..................................................................±25mA

Continuous Power Dissipation (T

A

= +70°C)

Plastic DIP (derate 9.09mW/°C above +70°C)...........727mW

SO (derate 5.88mW/°C above +70°C)........................471mW

CERDIP (derate 8.00mW/°C above +70°C)................640mW

Operating Temperature Ranges

MAX1242/MAX1243_C_A..................................0°C to +70°C

MAX1242/MAX1243_E_ A..............................-40°C to +85°C

MAX1242/MAX1243_MJA ............................-55°C to +125°C

Storage Temperature Range............................-60°C to +150°C

Lead Temperature (soldering, 10sec)............................+300°C

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ANALOG INPUT

CONVERSION RATE

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5Vp-p, 73ksps, f

SCLK

= 2.1MHz)

DC ACCURACY (Note 1)

MAX124_B ±2

Input Voltage Range 0 V

REF

V

Input Capacitance

Aperture Jitter <50 ps

16 pF

MAX124_A
MAX124_B
MAX124_A

Aperture Delay t

AP

30 nsFigure 9

Track/Hold Acquisition Time t

ACQ

1.5 µs

Throughput Rate 73 kspsf

SCLK

= 2.1MHz

Conversion Time

PARAMETER SYMBOL MIN TYP MAX UNITS

±1

Offset Error

LSB

Differential Nonlinearity DNL ±1 LSB

±1.0

±2

Gain Error (Note 3)

±1

Resolution 10 Bits
Relative Accuracy (Note 2)

±0.5

LSB

t

CONV

5.5 7.5 µs

Small-Signal Bandwidth

Signal-to-Noise Plus
Distortion Ratio

SINAD 66 dB

2.25 MHz

Full-Power Bandwidth

Total Harmonic Distortion THD -70 dB

1.0

-3dB rolloff
MHz

CONDITIONS

Spurious-Free Dynamic Range

ppm/°C

No missing codes over temperature

MAX124_B

±0.25

SFDR 70

Up to the 5th harmonic

dB

MAX124_A

LSB

DC ACCURACY (Note1)

CONVERSION RATE

ANALOG INPUT

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.5p-p, 73ksps, f

SCLK

=2.1MHz)

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +5.25V; 73ksps; f

S

CLK

= 2.1MHz (50% duty cycle); MAX1242—4.7µF capacitor at REF pin, MAX1243—external

reference; V

REF

= 2.5V applied to REF pin; TA= T

MIN

to T

MAX

; unless otherwise noted.)

Capacitive Bypass at REF 4.7 µF

Load Regulation (Note 5) 0.35 mV0mA to 0.2mA output load

REF Temperature Coefficient ±30 ppm/°CMAX1242

REF Short-Circuit Current 30 mA

REF Output Voltage 2.470 2.500 2.530 VTA= +25°C (Note 4)

Power-Supply Rejection (Note 7) PSR VDD= V

DD

(min)

to V

DD

(max)

, full-scale input

1.00 VDD+
50mV

Supply Current I

DD

3.0

0.8

VDD> 3.6V

I

SINK

= 16mA

Output Voltage High

SCLK, CS Input High Voltage

V

IH

2.0
V

SCLK, CS Input Low Voltage

Capacitive Bypass at REF 0.1 µF

V

IL

0.8

VDD≤ 3.6V

V

V

OH

VDD- 0.5 V

Three-State Leakage Current I

L

±0.01 ±10

I

SOURCE

= 0.5mA

µA

CS = V

DD

Three-State Output Capacitance C

OUT

15 pF

CS = V

DD

(Note 6)

Output Voltage Low V

OL

0.4
V

PARAMETER SYMBOL MIN TYP MAX UNITS

I

SINK

= 5MA

SHDN Input Mid Voltage

V

SM

1.1 VDD- 1.1 V

SHDN Voltage, Floating

V

FLT

VDD/ 2 V

SHDN Max Allowed Leakage,
Mid Input

±100

SHDN = float

nA

SHDN = float

SCLK, CS Input Capacitance

Input Voltage Range V

C

IN

15 pF

SHDN Input High Voltage

V

SH

VDD- 0.4

(Note 6)

V

SHDN Input Low Voltage

V

SL

0.4 V

Input Resistance

SHDN Input Current

±4.0

18 25 kΩ

REF Input Current in Shutdown

µA

SHDN = 0V or V

DD

SCLK, CS Input Hysteresis

V

HYST

±0.01 10 µA

SHDN = 0V

CONDITIONS

Input Current

0.2 V

SCLK, CS Input Leakage

I

IN

±0.01 ±1

100 150 µA

µAVIN= 0V or V

DD

Operating mode (MAX1242)

VDD= 5.25V

Operating mode (MAX1243)

VDD= 5.25V

VDD= 3.6V

Power-down

VDD= 5.25V

VDD= 3.6V

Supply Voltage V

DD

V

VDD= 3.6V

1.9 10

3.5 15

±0.3

1.6 2.5

0.9 1.5

1.8 3.0

1.4 2.0

2.7 5.25

mA

µA
mV

Operating mode (MAX1242)

EXTERNAL REFERENCE (VREF = 2.5V)

INTERNAL REFERENCE (MAX1242 only)

DIGITAL INPUTS: SCLK,

CCSS,SSHHDDNN

DIGITAL OUTPUT: DOUT

POWER REQUIREMENTS

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(VDD= +2.7V to +5.25V, circuit of Figure 9, TA= T

MIN

to T

MAX

, unless otherwise noted.)

Note 1: Tested at V

DD

= +2.7V.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3: Offset nulled.
Note 4: Sample tested to 0.1% AQL.
Note 5: External load should not change during conversion for specified accuracy.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Measured as [V

FS(VDD

(min)

) - VFS(V

DD

(max)

)].

Note 8: To guarantee acquisition time, t

ACQ

is the maximum time the device takes to acquire the signal, and is also the minimum

time needed for the signal to be acquired.

DOUT DOUT

6k

DGND

C

LOAD

= 50pF C

LOAD

= 50pF

6k

DGND

+2.7V

b) High-Z to V

OL

and VOH to V

OL

a) High-Z to VOH and VOL to V

OH

Figure 1. Load Circuits for DOUT Enable Time

Figure 2. Load Circuits for DOUT Disable Time

MAX124_ _M

MAX124_ _C/E

Figure 1, C

LOAD

= 50pF

Figure 1,
C

LOAD

= 50pF

CS = VDD(Note 8)

Figure 2, C

LOAD

= 50pF

CONDITIONS

ns240t

DV

CS Fall to Output Enable

ns

20 200

t

DO

µs1.5t

ACQ

Acquisition Time
SCLK Fall to Output Data Valid

ns240t

CS

CS Pulse Width

ns0t

STR

DOUT Rise to SCLK Rise (Note 6)

ns50t

CS0

SCLK Low to CS Fall Setup Time

ns240t

TR

CS Rise to Output Disable

MHz0 2.1f

SCLK

SCLK Clock Frequency

ns200t

CH

SCLK Pulse Width High

ns200t

CL

SCLK Pulse Width Low

UNITSMIN TYP MAX

SYMBOLPARAMETER

20 240

b) V

DOUT

to High-Za) V

OL

DOUT

OH

6k

DGND

to High-Z

C

= 50pF C

LOAD

+2.7V

6k

DGND

LOAD

= 50pF

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

_______________________________________________________________________________________

5

2.00

0.50

2.25 2.75

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

1.75

1.25

1.50

1.00

0.75

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.75 5.253.25 4.25 4.75

MAX1242/43-01

RL = ∞
CODE = 1010101000

MAX1243

MAX1242

C

LOAD

= 20pF

C

LOAD

= 50pF

C

LOAD

= 50pF

C

LOAD

= 20pF

4.0

3.5

0

2.25 2.75

SHUTDOWN SUPPLY CURRENT

vs. SUPPLY VOLTAGE

3.0

2.5

1.5

2.0

1.0

0.5

SUPPLY VOLTAGE (V)

SHUTDOWN SUPPLY CURRENT (µA)

3.75 5.253.25 4.25 4.75

MAX1242/43-02

MAX1242/MAX1243

2.5015

2.4985

2.25

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

2.5000

2.5010

2.5005

2.4995

2.4990

SUPPLY VOLTAGE (V)

INTERNAL REFERENCE VOLTAGE (V)

3.752.75 3.25

MAX1242/43-03

MAX1242

0.8

0.9

1.0

1.1

1.2

1.3

-60 -20 20 60 100 140

SUPPLY CURRENT vs. TEMPERATURE

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

MAX1242/43-04

MAX1243

MAX1242

R

LOAD

= ∞

CODE = 1010101000

0

0.10

0.05

0.20

0.15

0.25

0.30

2.25 3.25 3.752.75 4.25 4.75 5.25

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

MAX1242/43-07

SUPPLY VOLTAGE (V)

INL (LSB)

MAX1242

MAX1243

1.00

1.50

1.25

1.75

2.25

2.00

2.75

2.50

3.00

-60 -20 20 60 100 140

SHUTDOWN CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

MAX1242/43-05

2.494

2.495

2.496

2.497

2.498

2.499

2.500

2.501

-60 -20-40 200 6040 100 12080 140

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

MAX1242/43-06

VDD = 2.7V

VDD = 5V

VDD = 3.6V

MAX1242

0

0.15

0.10

0.05

0.20

0.25

0.30

-60 200-40 -20 40 60 80 100 120 140

INTEGRAL NONLINEARITY

vs. TEMPERATURE

MAX1242/43-08

TEMPERATURE (°C)

INL (LSB)

VDD = 2.7V

MAX1242

MAX1243

0.15

INTEGRAL NONLINEARITY

vs. CODE

-0.15

0

-0.05

-0.10

0.10

0.05

MAX1242/43-09

INL (LSB)

CODE

256 512 768 10240

__________________________________________Typical Operating Characteristics

(VDD= +3.0V, V

REF

= 2.5V, f

SCLK

= 2.1MHz, C

LOAD

= 20pF, TA= +25°C, unless otherwise noted.)

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

6 _______________________________________________________________________________________

_______________Detailed Description

Converter Operation

The MAX1242/MAX1243 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 10-bit out­put. Figure 3 shows the MAX1242/MAX1243 in their
simplest configuration. The MAX1242/MAX1243 convert
input signals in the 0V to V

REF

range in 9µs, including
T/H acquisition time. The MAX1242’s internal reference
is trimmed to 2.5V, while the MAX1243 requires an
external reference. Both devices accept external refer­ence voltages from 1.0V to VDD. The serial interface
requires only three digital lines (SCLK,

CS,

and DOUT)
and provides an easy interface to microprocessors
(µPs).

The MAX1242/MAX1243 have two modes: normal and
shutdown. Pulling

SHDN

low shuts the device down and
reduces supply current below 10µA (VDD≤ 3.6V), while
pulling

SHDN

high or leaving it open puts the devices
into operational mode. A conversion is initiated by
pulling CS low. The conversion result is available at
DOUT in unipolar serial format. The serial-data stream
consists of a high bit, signaling the end of conversion
(EOC), followed by the data bits (MSB first).

Analog Input

Figure 4 illustrates the sampling architecture of the ana­log-to-digital converter’s (ADC’s) comparator. The full­scale input voltage is set by the voltage at REF.

Track/Hold

In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.

During acquisition, the analog input AIN charges
capacitor C

HOLD

. Bringing CSlow ends the acquisition
interval. At this instant, the T/H switches the input side
of C

HOLD

to GND. The retained charge on C

HOLD

repre­sents a sample of the input, unbalancing node ZERO at
the comparator’s input.

In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0V within the limits of 10­bit resolution. This action is equivalent to transferring a
charge from C

HOLD

to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C

HOLD

switches back to AIN, and C

HOLD

charges to the input signal again.
The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t

ACQ

, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:

t

ACQ

= 7(RS+ RIN) x 16pF

______________________________________________________________Pin Description

6 DOUT

Serial-Data Output. Data changes state at SCLK’s falling edge. High impedance when CS is high.

8 SCLK

3

SHDN

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1242/MAX1243 down to 15µA (max)
supply current. Both MAX1242 and MAX1243 are fully operational with either SHDN high or floating.
For the MAX1242, pulling SHDN high enables the internal reference, and letting SHDN float disables
the internal reference and allows for the use of an external reference.

4 REF

Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output for MAX1242;
bypass with a 4.7µF capacitor. External reference voltage input for MAX1243, or for MAX1242 with the
internal reference disabled. Bypass REF with a minimum of 0.1µF when using an external reference.

7

CS

Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.

5 GND Analog and Digital Ground

2 AIN Sampling Analog Input, 0V to V

REF

range

NAME FUNCTION

1 V

DD

Positive Supply Voltage: +2.7V to +5.25V

PIN

Serial-Clock Input. SCLK clocks data out at rates up to 2.1MHz.

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

_______________________________________________________________________________________ 7

AIN

TRACK

INPUT

HOLD

GND

TRACK

HOLD

9k
R

IN

C

HOLD

16pF

- +

C

SWITCH

COMPARATOR

ZERO

REF

CAPACITIVE DAC

AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.

Figure 3. Operational Diagram

Figure 4. Equivalent Input Circuit

where RIN= 9kΩ, RS= the input signal’s source imped­ance, and t

ACQ

is never less than 1.5µs. Source imped­ances below 4kΩ do not significantly affect the ADC’s
AC performance.

Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig­nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
aliasing of unwanted high-frequency signals into the
frequency band of interest, anti-alias filtering is recom­mended.

Analog Input Protection

Internal protection diodes, which clamp the analog
input to VDDand GND, allow the input to swing from
GND - 0.3V to VDD+ 0.3V without damage. However,
for accurate conversions near full scale, the input must
not exceed VDDby more than 50mV, or be lower than
GND by 50mV.

If the analog input exceeds 50mV beyond the supplies,
limit the input current to 2mA.

Internal Reference (MAX1242)

The MAX1242 has an on-chip voltage reference
trimmed to 2.5V. The internal reference output is con­nected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
400µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shut­down (see

Using SHDN to Reduce Supply Current

).
The internal reference is enabled by pulling the SHDN
pin high. Letting SHDN float disables the internal refer­ence, which allows the use of an external reference, as
described in the

External Reference

section.

External Reference

The MAX1242/MAX1243 operate with an external refer­ence at the REF pin. To use the MAX1242 with an
external reference, disable the internal reference by let­ting SHDN float. Stay within the voltage range 1.0V to
VDDto achieve specified accuracy. The minimum input
impedance is 18kΩ for DC currents. During conver­sion, the external reference must be able to deliver up
to 250µA of DC load current and have an output
impedance of 10Ω or less. The recommended mini­mum value for the bypass capacitor is 0.1µF. If the ref­erence has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.

+2.7V to +5.25V

0.1µF

4.7µF

ANALOG INPUT

0V TO V

REF

SHUTDOWN

INPUT

REFERENCE

INPUT

MAX1243

*4.7µF, MAX1242

0.1µF, MAX1243

1

V

DD

2

AIN

MAX1242
MAX1243

3

SHDN

4

REF

C*

SCLK

DOUT

GND

8

7

CS

6
5

SERIAL
INTERFACE

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

8 _______________________________________________________________________________________

Serial Interface

Initialization after Power-Up and

Starting a Conversion

When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 20ms to provide adequate
charge for specified accuracy. With an external refer­ence, the internal reset time is 10µs after the power
supplies have stabilized. No conversions should be
performed during these times.

To start a conversion, pull CSlow. At

CS’s

falling edge,
the T/H enters its hold mode and a conversion is initiat­ed. After an internally timed conversion period, the end
of conversion is signaled by DOUT pulling high. Data
can then be shifted out serially with the external clock.

Using

SSHHDDNN

to Reduce Supply Current

Power consumption can be reduced significantly by
shutting down the MAX1242/MAX1243 between con­versions. Figure 6 shows a plot of average supply cur­rent vs. conversion rate. Because the MAX1243 uses
an external reference voltage (assumed to be present
continuously), it “wakes up” from shutdown more quick­ly, providing lower average supply currents. The wake­up time, t

WAKE

, is the time from SHDN deasserted to
the time when a conversion may be initiated (Figure 5).
For the MAX1242, this time depends on the time in
shutdown (Figure 7) because the external 4.7µF refer­ence bypass capacitor loses charge slowly during
shutdown. The MAX1243’s wake-up time is largely
dependent on the external reference’s power-up time. If
the external reference is not shut down, the wake-up
time is approximately 4µs.

10,000

100

1000

1

0.1 1 10 100 1k 10k 100k

10

CONVERSIONS/SEC

SUPPLY CURRENT (µA)

V

DD

=

V

REF

R

LOAD

= ∞, C

LOAD

= 50pF

CODE = 0101010100

MAX1243-fig06

MAX1242
V

DD

= 3V

MAX1242
V

DD

= 5V

MAX1243
V

DD

= 3V

Figure 6. Average Supply Current vs. Conversion Rate

1.0

0.0

0.001 0.01 0.1 1 10

0.8

0.6

0.4

0.2

TIME IN SHUTDOWN

(sec)

POWER-UP DELAY (ms)

MAX1242/43-07

Figure 7. Typical Reference-Buffer Power-Up Delay vs. Time in
Shutdown

COMPLETE CONVERSION SEQUENCE

t

WAKE

POWERED UPPOWERED DOWNPOWERED UP

CONVERSION 0 CONVERSION 1

DOUT

CS

SHDN

Figure 5. Shutdown Sequence

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

_______________________________________________________________________________________ 9

EOC

INTERFACE IDLE

CONVERSION
IN PROGRESS

EOC

0µs

TRAILING

ZEROS

SUB

BITS

IDLE

CLOCK OUT SERIAL DATA

TRACK/HOLD
STATE

TRACK

HOLD

TRACK

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0

SCLK

1 4 8 12 16

7.5µs (t

CONV

)

HOLD

0µs

(tCS)

TOTAL = 13.7µs

12.5 × 0.476µs = 5.95µs

CYCLE TIME

CS

0.24µs

Figure 8a. Interface Timing Sequence

EOC

INTERFACE IDLE

CONVERSION

IN PROGRESS

EOC

0µs

IDLE

CLOCK OUT SERIAL DATA

TRACK/HOLD
STATE

TRACK

HOLD

TRACK

DOUT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

SCLK

1 4 8

7.5µs (t

CONV

)

HOLD

(tCS)

TOTAL = 12.74µs

10.5 × 0.476µs = 5µs

CYCLE TIME

CS

0.24µs

Figure 8b. Interface Timing Sequence—Minimum Cycle Time

…
…

…

…

CS

SCLK

DOUT

INTERNAL

T/H

(TRACK/ACQUIRE)

t

CS0

t

CONV

t

DV

t

STR

t

AP

(HOLD) (TRACK/ACQUIRE)

B0 S1 S0

t

CH

t

DO

t

CL

t

TR

t

CS

Figure 9. Detailed Serial-Interface Timing

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

10 ______________________________________________________________________________________

External Clock

The actual conversion does not require the external
clock. This allows the conversion result to be read back
at the µP’s convenience at any clock rate up to

2.1MHz. The clock duty cycle is unrestricted if each
clock phase is at least 200ns. Do not run the clock
while a conversion is in progress.

Timing and Control

Conversion-start and data-read operations are con­trolled by the CSand SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline serial-interface
operation.

A CSfalling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK must be kept low during the conver­sion. An internal register stores the data when the con­version is in progress.

EOC is signaled by DOUT going high. DOUT’s rising
edge can be used as a framing signal. SCLK shifts the
data out of this register any time after the conversion is
complete. DOUT transitions on SCLK’s falling edge.
The next falling clock edge produces the MSB of the
conversion at DOUT, followed by the remaining bits.
Since there are 10 data bits, two sub-bits, and one
leading high bit, at least 13 falling clock edges are
needed to shift out these bits. Extra clock pulses occur­ring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing zeros
at DOUT and have no effect on converter operation.

For minimum cycle time, use DOUT’s rising edge as
the EOC signal and then clock out the data with 10.5
clock cycles at full speed (Figure 8b). Pull CShigh after
reading the conversion’s LSB. After the specified mini­mum time, tCS, pull CSlow again to initiate the next
conversion.

Output Coding and Transfer Function

The data output from the MAX1242/MAX1243 is binary.
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive-integer
LSB values. If V

REF

= 2.5V, then 1LSB = 2.44mV or

2.5V / 1024.

__________Applications Information

Connection to Standard Interfaces

The MAX1242/MAX1243 serial interface is fully compat­ible with SPI, QSPI, and Microwire standard serial inter­faces (Figure 11).

CS
SCLK
DOUT

I/O

SCK

MISO

+3V

SS

a) SPI

CS
SCLK
DOUT

CS

SCK

MISO

+3V

SS

b) QSPI

MAX1242
MAX1243

MAX1242
MAX1243

MAX1242
MAX1243

CS
SCLK
DOUT

I/O

SK

SI

c) MICROWIRE

Figure 11. Common Serial-Interface Connections to the
MAX1242/MAX1243

Figure 10. Unipolar Transfer Function, Full Scale (FS) =
V

REF

- 1LSB, Zero Scale (ZS) = GND

11…111
11…110
11…101

00…011
00…010
00…001

00…000

0 1 2 FS

OUTPUT CODE

FS - 3/2LSBINPUT VOLTAGE (LSB)

FS = V

REF

- 1LSB

1LSB =

V

REF

1024

FULL-SCALE

TRANSITION

3

If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser­ial clock. Choose a clock frequency up to 2.1MHz.

1) Use a general-purpose I/O line on the CPU to pull

CS

low. Keep SCLK low.

2) Wait the maximum conversion time specified before
activating SCLK. Alternatively, look for a DOUT rising
edge to determine the end of conversion.

3) Activate SCLK for a minimum of 11 clock cycles. The
first falling clock edge produces the MSB of the
DOUT conversion. DOUT output data transitions on
SCLK’s falling edge and is available in MSB-first for­mat. Observe the SCLK-to-DOUT valid timing char­acteristic. Data can be clocked into the µP on
SCLK’s rising edge.

4) Pull CShigh at or after the 11th falling clock edge. If

CS

remains low, the two sub-bits and trailing zeros

are clocked out after the LSB.

5) With

CS

= high, wait the minimum specified time, tCS,

before initiating a new conversion by pulling

CS

low.
If a conversion is aborted by pulling CShigh before
the conversion’s end, wait the minimum acquisition
time, t

ACQ

, before starting a new conversion.

Data can be output in two bytes or continuously, as
shown in Figures 8a and 8b. The bytes contain the
result of the conversion padded with one leading 1, two
sub-bits, and trailing 0s if SCLK is still active with CS
kept low.

SPI and Microwire

When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CSfalling edge. DOUT goes
low, indicating a conversion is in progress. Wait until
DOUT goes high or until the maximum specified 7.5µs
conversion time elapses. Two consecutive 1-byte reads
are required to get the full 10+2 bits from the ADC.
DOUT output data transitions on SCLK’s falling edge
and is clocked into the µP on SCLK’s rising edge.

The first byte contains a leading 1, and seven bits of
conversion result. The second byte contains the remain­ing three bits, two sub-bits, and three trailing zeros. See
Figure 11 for connections and Figure 12 for timing.

QSPI

Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 10 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces­sary to clock in the data. The MAX1242/MAX1243 require
11 clock cycles from the µP to clock out the 10 bits of
data. Additional clock cycles clock out the two sub-bits
followed by trailing zeros (Figure 13). The maximum clock
frequency to ensure compatibility with QSPI is 2.097MHz.

Layout and Grounding

For best performance, use printed circuit boards. Wire­wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi­tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit

Serial ADCs in SO-8

______________________________________________________________________________________ 11

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0

HIGH-Z

t

CONV

DOUT

CS

SCLK

1ST BYTE READ 2ND BYTE READ

EOC

MSB LSB

Figure 12. SPI/Microwire Serial-Interface Timing (CPOL = CPHA = 0)

Figure 13. QSPI Serial-Interface Timing (CPOL = CPHA = 0)

SCLK

CS

t

CONV

DOUT

EOC

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0

MSB LSB

HIGH-Z

MAX1242/MAX1243

+2.7V to +5.25V, Low-Power, 10-Bit
Serial ADCs in SO-8

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Ordering Information (continued)

TRANSISTOR COUNT: 2559
SUBSTRATE CONNECTED TO GND

___________________Chip Information

________________________________________________________Package Information

*

Contact factory for availability and processing to MIL-STD-883.

Note:

Order the MAX1242A in place of the MAX1242C. Order the

MAX1242B in place of the MAX1242D.

PDIPN.EPS

SOICN.EPS

±1/28 SO0°C to +70°CMAX1243ACSA
±1

±1

±1/2

8 SO

8 Plastic DIP

8 Plastic DIP0°C to +70°C

0°C to +70°C

0°C to +70°CMAX1243BCSA

MAX1243BCPA

MAX1243ACPA

±1/28 CERDIP*-55°C to +125°CMAX1242AMJA

±18 CERDIP*-55°C to +125°CMAX1243BMJA

±1/28 CERDIP*-55°C to +125°CMAX1243AMJA

±1

±1

±1

±1/2

INL

(LSB)

8 SO-40°C to +85°CMAX1243BESA

±1/28 SO-40°C to +85°CMAX1243AESA

±18 Plastic DIP-40°C to +85°CMAX1243BEPA

±1/28 Plastic DIP-40°C to +85°CMAX1243AEPA

8 CERDIP*

8 SO

8 SO

PIN-

PACKAGE

TEMP. RANGE

-40°C to +85°C

-40°C to +85°C

-55°C to +125°CMAX1242BMJA

MAX1242BESA

MAX1242AESA

PART