The MAX1226/MAX1228/MAX1230 are serial 12-bit analog-to-digital converters (ADCs) with an internal reference
and an internal temperature sensor. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum
sampling rate is 300ksps using an external clock. The
MAX1230 has 16 input channels, the MAX1228 has 12
input channels, and the MAX1226 has 8 input channels.
All input channels are configurable for single-ended or
differential inputs in unipolar or bipolar mode. All three
devices operate from a +5V supply and contain a 10MHz
SPI™/QSPI™/MICROWIRE™-compatible serial port.
The MAX1230 is available in 28-pin 5mm x 5mm QFN
with exposed pad and 24-pin QSOP packages. The
MAX1226/MAX1228 are only available in QSOP packages. All three devices are specified over the extended
-40°C to +85°C temperature range.
________________________Applications
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
Features
♦ Internal Temperature Sensor (±1°C Accuracy)
♦ 16-Entry First-In/First-Out (FIFO)
♦ Analog Multiplexer with True Differential
Track/Hold
16-, 12-, 8-Channel Single Ended
8-, 6-, 4-Channel True Differential
(Unipolar or Bipolar)
♦ Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing
Codes Over Temperature
♦ Scan Mode, Internal Averaging, and Internal Clock
♦ Low-Power Single +5V Operation
1.9mA at 300ksps
♦ Internal 4.096V Reference or External Differential
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information
*Future product—contact factory for availability.
Ordering Information continued at end of data sheet.
TOP VIEW
Pin Configurations continued at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
查询MAX1226ACEE-T供应商
PARTTEMP RANGEPIN-PACKAGE
MAX1226ACEE-T*0°C to +70°C16 QSOP
MAX1226AEEE-T*-40°C to +85°C16 QSOP
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
REF-/AIN6
CNVST/AIN7
1
2
3
MAX1226
4
5
6
7
8
QSOP
16
EOC
15
DOUT
14
DIN
13
CS
12
SCLK
V
11
DD
GND
10
REF+
9
AIN0
AIN1
AIN2
AIN4
AIN5
AIN6
AIN8
2
3
4
MAX1228
5
6
7
8
9
10
QSOP
20
EOC
19
DOUT
18
DIN
17
CSAIN3
16
SCLK
15
V
14
GND
REF+AIN7
13
12
CNVST/AIN11
11
REF-/AIN10AIN9
DD
MAX1226/MAX1228/MAX1230
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (V
DD
+ 0.3V)
AIN0–AIN13, REF-/AIN_, CNVST/AIN_,
REF+ to GND.........................................-0.3V to (V
DD
+ 0.3V)
Maximum Current into Any Pin............................................50mA
Note 1: Tested at VDD= +5V, unipolar input mode.
Note 2: Offset nulled.
Note 3: Time for reference to power up and settle to within 1 LSB.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: The operational input voltage range for each individual input of a differentially configured pair is from GND to V
DD
. The
operational input voltage difference is from -V
REF
/ 2 to +V
REF
/ 2.
Note 6: See Figure 3 (Input Equivalent Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characterisitcs section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
Temperature measurements always use the internal reference.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5V ±5%, f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz (50% duty cycle), V
REF
= 4.096V, TA= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25°C.)
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
Input Voltage LowV
Input Voltage HighV
Input HysteresisV
Input Leakage CurrentI
Input CapacitanceC
DIGITAL OUTPUTS (DOUT,EOC)
Output Voltage LowV
Output Voltage HighV
Tri-State Leakage CurrentI
Tri-State Output CapacitanceC
POWER REQUIREMENTS
Supply VoltageV
Supply Current (Note 8)I
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Power-Supply RejectionPSRVDD = 4.75V to 5.25V; full-scale input±0.2±1.2mV
1517139REF+Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
16181410GNDGround
18191511V
20201612SCLK
MAX1230
QSOP
———N.C.No Connection. Not internally connected.
1–14——AIN0–13Analog Inputs
MAX1228 MAX1226NAMEFUNCTION
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
CNVST/
AIN15
CNVST/
AIN11
CNVST/
AIN7
DD
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
Power Input. Bypass to GND with a 0.1µF capacitor.
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40% to 60%.) See Table 3 for details on
programming the clock mode.
21211713CS
22221814DIN
23231915DOUT
24242016EOCEnd of Conversion Output. Data is valid after EOC pulls low.
Active-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling edge of
SCLK. High impedance when CS is connected to V
DD
.
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