MAXIM MAX1213N Technical data

MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications
________________________________________________________________ Maxim Integrated Products 1
19-3863; Rev 0; 4/06
EVALUATION KIT
AVAILABLE
General Description
The MAX1213N is a monolithic, 12-bit, 170Msps ana­log-to-digital converter (ADC) optimized for outstanding dynamic performance at high-IF frequencies beyond 300MHz. The product operates with conversion rates up to 170Msps while consuming only 720mW.
At 170Msps and an input frequency up to 100MHz, the MAX1213N achieves an 87dBc spurious-free dynamic range (SFDR) with excellent 67.2dB signal-to-noise ratio (SNR) that remains flat (within 2dB) for input tones up to 250MHz. This makes it ideal for wideband appli­cations such as communications receivers, cable-head end receivers, and power-amplifier predistortion in cel­lular base-station transceivers.
The MAX1213N operates from a single 1.8V power sup­ply. The analog input is designed for AC-coupled differ­ential or single-ended operation. The ADC also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 340MHz. A low­voltage differential signal (LVDS) sampling clock is recommended for best performance. The converter pro­vides LVDS-compatible digital outputs with data format selectable to be either two’s complement or offset binary.
The MAX1213N is available in a 68-pin QFN package with exposed paddle (EP) and is specified over the industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versions table for a complete selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in this family.
Applications
Base-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communications
Communications Test Equipment
Radar and Satellite Subsystems
Features
170Msps Conversion Rate
Excellent Low-Noise Characteristics
SNR = 67.2dB at fIN= 100MHz SNR = 65.2dB at fIN= 250MHz
Excellent Dynamic Range
SFDR = 87dBc at fIN= 100MHz SFDR = 79dBc at fIN= 250MHz
Single 1.8V Supply
720mW Power Dissipation at f
SAMPLE
= 170Msps
and fIN= 100MHz
On-Chip Track-and-Hold Amplifier
Internal 1.24V-Bandgap Reference
On-Chip Selectable Divide-by-2 Clock Input
LVDS Digital Outputs with Data Clock Output
MAX1213NEVKIT Available
PART
TEMP RANGE
PIN-
PKG
CODE
MAX1213NEGK-D
G6800-4
MAX1213NEGK+D
G6800-4
Ordering Information
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Pin-Compatible Versions
PART
RESOLUTION
(BITS)
SPEED GRADE
(Msps)
ON-CHIP
BUFFER
MAX1121 8 250 Yes
MAX1122 10 170 Yes
MAX1123 10 210 Yes
MAX1124 10 250 Yes
MAX1213 12 170 Yes
MAX1214 12 210 Yes
MAX1215 12 250 Yes
MAX1213N 12 170 No
MAX1214N 12 210 No
MAX1215N 12 250 No
Pin Configuration appears at end of data sheet.
PACKAGE
-40°C to +85°C
-40°C to +85°C
68 QFN-EP*
68 QFN-EP*
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OVCC.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AV
CC
+ 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV
CC
+ 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AV
CC
+ 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OV
CC
+ 0.3V)
Continuous Power Dissipation (TA= +70°C, multilayer board)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C).....3333mW
Current into Any Pin..........................................................±50mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity INL f
IN
= 10MHz (Note 2) -2
+2 LSB
Differential Nonlinearity DNL No missing codes (Note 2)
LSB
Transfer Curve Offset V
OS
(Note 2) -5 +5 mV
Offset Temperature Drift
µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range V
FS
mV
P-P
Full-Scale Range Temperature Drift
ppm/°C
Common-Mode Input Voltage V
CM
Internally self-biased 0.74 V
Differential Input Capacitance C
IN
2.5 pF
Differential Input Resistance R
IN
1.8 k
Full-Power Analog Bandwidth FPBW
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage V
REFIO
REFADJ = AGND
V
Reference Temperature Drift 90
ppm/°C
REFADJ Input High Voltage
Used to disable the internal reference AV
CC
- 0.3 V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate f
SAMPLE
MHz
Minimum Sampling Rate f
SAMPLE
20
MHz
Clock Duty Cycle Set by clock-management circuit
%
Aperture Delay t
AD
Figures 5, 11
ps
Aperture Jitter t
AJ
Figure 11
ps
RMS
SYMBOL
MIN TYP MAX
±0.55
-1.0 ±0.3 +1.3
±10
1160 1380
±50
V
REFADJ
1.18 1.24 1.30
170
40 to 60
700
620
0.15
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 3)
mV
P-P
Clock Input Common-Mode Voltage Range
Internally self-biased 1.15 ±0.25 V
Clock Differential Input Resistance
R
CLK
11 ±25% k
Clock Differential Input Capacitance
C
CLK
5pF
DYNAMIC CHARACTERISTICS (at AIN = -1dBFS)
fIN = 10MHz
fIN = 100MHz
fIN = 200MHz 66
Signal-to-Noise Ratio SNR
f
IN
= 250MHz
dB
fIN = 10MHz
fIN = 100MHz
fIN = 200MHz
Signal-to-Noise and Distortion SINAD
f
IN
= 250MHz
dB
fIN = 10MHz
88
fIN = 100MHz
fIN = 200MHz 80
Spurious-Free Dynamic Range SFDR
f
IN
= 250MHz 79
dBc
fIN = 10MHz -88
fIN = 100MHz -87
fIN = 200MHz -80
Worst Harmonics (HD2 or HD3)
f
IN
= 250MHz -79
dBc
Two-Tone Intermodulation Distortion
TTIMD
f
IN1
= 97MHz at -7dBFS,
f
IN2
= 100MHz at -7dBFS
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage |VOD|RL = 100
440 mV
Output Offset Voltage OV
OS
RL = 100
V
200 500
66.5 67.7
66.2 67.2
65.2
66.1 67.6
65.7 67.1
65.8
64.9
75.0
74.5 87.0
-86
280
1.125 1.340
-75.0
-74.5
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps ADC for Broadband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low V
IL
V
Digital Input-Voltage High V
IH
0.8 x AV
CC
V
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay t
PDL
Figure 5
ns
CLK-to-DCLK Propagation Delay
t
CPDL
Figure 5
ns
DCLK-to-Data Propagation Delay
Figure 5 (Note 3)
ns
LVDS Output Rise Time t
RISE
20% to 80%, CL = 5pF
ps
LVDS Output Fall Time t
FALL
20% to 80%, CL = 5pF
ps
Output Data Pipeline Delay
Figure 5 11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AV
CC
V
Digital Supply Voltage Range OV
CC
V
Analog Supply Current I
AVCC
fIN = 100MHz
366 mA
Digital Supply Current I
OVCC
fIN = 100MHz 63 69 mA
Analog Power Dissipation P
DISS
fIN = 100MHz
783 mW
Offset 1.8
mV/V
Power-Supply Rejection Ratio (Note 4)
PSRR
Gain 1.5
%FS/V
Note 1: Values at TA≥ +25°C guaranteed by production test, values at TA< +25°C guaranteed by design and characterization. Note 2: Static linearity and offset parameters are computed from an end-point curve fit. Note 3: Parameter guaranteed by design and characterization: T
A
= -40°C to +85°C.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
0.2 x AV
t
- t
CPDL
PDL
t
LATENCY
2.30 2.56 2.82
1.70 1.80 1.90
1.70 1.80 1.90
1.98
4.58
450
450
337
720
CC
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for Broadband Applications
_______________________________________________________________________________________ 5
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
2
f
SAMPLE
= 170MHz
f
IN
= 12.471MHz
A
IN
= -1.03dBFS SNR = 67.7dB SINAD = 67.6dB THD = -86.4dBc SFDR = 88.27dBc HD2 = -88.27dBc HD3 = -101.7dBc
3
4
5
706040
50
20 30100
80
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 99.962MHz
A
IN
= -0.997dBFS SNR = 67.2dB SINAD = 67.1dB THD = -85dBc SFDR = 86.2dBc HD2 = -95.6dBc HD3 = -86.2dBc
3
5
2
4
706040
50
20 30100
80
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 199.488MHz
A
IN
= -0.942dBFS SNR = 65.7dB SINAD = 65.3dB THD = -75.7dBc SFDR = 77.4dBc HD2 = -77.4dBc HD3 = -81.5dBc
706040
50
20 30100
80
5
4
2
3
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 250.040MHz
A
IN
= -0.997dBFS SNR = 64.85dB SINAD = 64.6dB THD = -77.3dBc SFDR = 79.2dBc HD2 = -79.2dBc HD3 = -83.3dBc
706040
50
20 30100
80
2
4
5
3
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
MAX1213N toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
IN2
f
SAMPLE
= 170MHz
f
IN1
= 96.973877MHz
f
IN2
= 99.9621582MHz
A
IN1
= A
IN2
= -7dBFS
IMD = -86dBc
2f
IN2
- f
IN1
2f
IN1
- f
IN2
f
IN1
706040
50
20 30100
80
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc06
f
IN
(MHz)
SNR/SINAD (dB)
25020015010050
50
55
60
65
70
45
0 300
SNR
SINAD
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc07
f
IN
(MHz)
SFDR/(-THD) (dBc)
25020015010050
50
55
60
65
70
75
80
85
90
95
100
45
0 300
SFDR
-THD
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc08
f
IN
(MHz)
HD2/HD3 (dBc)
25020015010050
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-110 0 300
HD2
HD3
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR/SINAD (dB)
-5-10-15-20-25-30-35-40-45-50
10
20
30
40
50
60
70
0
-55 0
SNR
SINAD
Typical Operating Characteristics
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test condi­tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA= +25°C.)
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for Broadband Applications
6 _______________________________________________________________________________________
SFDR/(-THD) vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc10
ANALOG INPUT AMPLITUDE (dBFS)
SFDR/(-THD) (dBc)
-5-10-20 -15-45 -40 -35 -30 -25-50
35
40
45
50
55
60
65
70
75
80
85
90
95
100
30
-55 0
SFDR
-THD
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc11
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
-5-10-50 -45 -40 -30 -25 -20-35 -15
-100
-90
-80
-70
-60
-50
-40
-30
-110
-55 0
HD2
HD3
SNR/SINAD vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc12
f
SAMPLE
(MHz)
SNR/SINAD (dB)
16014012010080604020
45
50
55
60
65
70
75
40
0 180
SNR
SINAD
MAX1213N toc13
f
SAMPLE
(MHz)
SFDR/(-THD) (dBc)
160140100 12040 60 8020
55
60
65
70
75
80
85
90
95
100
50
0 180
SFDR/(-THD) vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
SFDR
-THD
HD2/HD3 vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc14
f
SAMPLE
(MHz)
HD2/HD3 (dBc)
160140100 12040 60 8020
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-120 0 180
HD3
HD2
TOTAL POWER DISSIPATION vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc15
f
SAMPLE
(MHz)
P
DISS
(-15mW)
15514035 50 65 95 11080 125
0.610
0.635
0.660
0.685
0.710
0.735
0.760
0.785
0.585 20 170
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2560 3072 3584 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1213N toc16
DIGITAL OUTPUT CODE
INL (LSB)
fIN = 12.5MHz
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2560 3072 3584 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1213N toc17
DIGITAL OUTPUT CODE
DNL (LSB)
fIN = 12.5MHz
GAIN BANDWIDTH PLOT
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc18
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10 100
-6
-5
-4
-3
-2
-1
0
1
-7 1 1000
Typical Operating Characteristics (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test condi­tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA= +25°C.)
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for Broadband Applications
_______________________________________________________________________________________ 7
SINAD
60.5
63.5
62.5
61.5
64.5
65.5
66.5
67.5
68.5
69.5
70.5
-40 10-15 35 60 85
SNR/SINAD vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc19
TEMPERATURE (°C)
SNR/SINAD (dB)
SNR
50
55
60
65
70
75
80
85
90
-40 -15 10 35 60 85
SFDR/(-THD) vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc20
SFDR/(-THD) (dBc)
TEMPERATURE (°C)
SFDR
-THD
50
65
60
55
70
75
80
85
90
95
100
-40 10-15 35 60 85
HD2/HD3 vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc21
TEMPERATURE (°C)
HD2/HD3 (dBc)
HD2
HD3
SNR/SINAD vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc22
SUPPLY VOLTAGE (V)
SNR/SINAD (dB)
1.851.801.75
61
62
63
64
65
66
67
68
69
70
60
1.70 1.90
SNR
SINAD
Typical Operating Characteristics (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test condi­tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins differential RL = 100, TA= +25°C.)
SFDR/(-THD) vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc23
SUPPLY VOLTAGE (V)
SFDR/(-THD) (dBc)
1.851.801.75
73
76
79
82
85
88
91
94
97
100
70
1.70 1.90
-THD
SFDR
HD2/HD3 vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc24
SUPPLY VOLTAGE (V)
HD2/HD3 (dBc)
1.851.801.75
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-120
1.70 1.90
HD3
HD2
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc25
SUPPLY VOLTAGE (V)
V
REF
(V)
1.243
1.244
1.245
1.246
1.247
1.248
1.249
1.250
1.242
1.851.801.751.70 1.90
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