MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
________________________________________________________________ Maxim Integrated Products 1
19-3863; Rev 0; 4/06
EVALUATION KIT
AVAILABLE
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1213N is a monolithic, 12-bit, 170Msps analog-to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies beyond
300MHz. The product operates with conversion rates
up to 170Msps while consuming only 720mW.
At 170Msps and an input frequency up to 100MHz, the
MAX1213N achieves an 87dBc spurious-free dynamic
range (SFDR) with excellent 67.2dB signal-to-noise
ratio (SNR) that remains flat (within 2dB) for input tones
up to 250MHz. This makes it ideal for wideband applications such as communications receivers, cable-head
end receivers, and power-amplifier predistortion in cellular base-station transceivers.
The MAX1213N operates from a single 1.8V power supply. The analog input is designed for AC-coupled differential or single-ended operation. The ADC also features
a selectable on-chip divide-by-2 clock circuit that
accepts clock frequencies as high as 340MHz. A lowvoltage differential signal (LVDS) sampling clock is
recommended for best performance. The converter provides LVDS-compatible digital outputs with data format
selectable to be either two’s complement or offset binary.
The MAX1213N is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family.
Applications
Base-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communications
Communications Test Equipment
Radar and Satellite Subsystems
Features
♦ 170Msps Conversion Rate
♦ Excellent Low-Noise Characteristics
SNR = 67.2dB at fIN= 100MHz
SNR = 65.2dB at fIN= 250MHz
♦ Excellent Dynamic Range
SFDR = 87dBc at fIN= 100MHz
SFDR = 79dBc at fIN= 250MHz
♦ Single 1.8V Supply
♦ 720mW Power Dissipation at f
SAMPLE
= 170Msps
and fIN= 100MHz
♦ On-Chip Track-and-Hold Amplifier
♦ Internal 1.24V-Bandgap Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ MAX1213NEVKIT Available
PART
TEMP RANGE
PIN-
PKG
CODE
MAX1213NEGK-D
G6800-4
MAX1213NEGK+D
G6800-4
Ordering Information
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
Pin-Compatible Versions
PART
RESOLUTION
(BITS)
SPEED GRADE
(Msps)
ON-CHIP
BUFFER
MAX1121 8 250 Yes
MAX1122 10 170 Yes
MAX1123 10 210 Yes
MAX1124 10 250 Yes
MAX1213 12 170 Yes
MAX1214 12 210 Yes
MAX1215 12 250 Yes
MAX1213N 12 170 No
MAX1214N 12 210 No
MAX1215N 12 250 No
Pin Configuration appears at end of data sheet.
PACKAGE
-40°C to +85°C
-40°C to +85°C
68 QFN-EP*
68 QFN-EP*
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OVCC.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AV
CC
+ 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV
CC
+ 0.3V)
REFIO, REFADJ to AGND ........................-0.3V to (AV
CC
+ 0.3V)
All Digital Outputs to OGND ....................-0.3V to (OV
CC
+ 0.3V)
Continuous Power Dissipation (TA= +70°C, multilayer board)
68-Pin QFN-EP (derate 41.7mW/°C above +70°C).....3333mW
Current into Any Pin..........................................................±50mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity INL f
IN
= 10MHz (Note 2) -2
+2 LSB
Differential Nonlinearity DNL No missing codes (Note 2)
LSB
Transfer Curve Offset V
OS
(Note 2) -5 +5 mV
Offset Temperature Drift
µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range V
FS
mV
P-P
Full-Scale Range Temperature
Drift
ppm/°C
Common-Mode Input Voltage V
CM
Internally self-biased 0.74 V
Differential Input Capacitance C
IN
2.5 pF
Differential Input Resistance R
IN
1.8 kΩ
Full-Power Analog Bandwidth FPBW
MHz
REFERENCE (REFIO, REFADJ)
Reference Output Voltage V
REFIO
REFADJ = AGND
V
Reference Temperature Drift 90
ppm/°C
REFADJ Input High Voltage
Used to disable the internal reference AV
CC
- 0.3 V
SAMPLING CHARACTERISTICS
Maximum Sampling Rate f
SAMPLE
MHz
Minimum Sampling Rate f
SAMPLE
20
MHz
Clock Duty Cycle Set by clock-management circuit
%
Aperture Delay t
AD
Figures 5, 11
ps
Aperture Jitter t
AJ
Figure 11
ps
RMS
SYMBOL
MIN TYP MAX
±0.55
-1.0 ±0.3 +1.3
±10
1160 1380
±50
V
REFADJ
1.18 1.24 1.30
170
40 to 60
700
620
0.15
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 3)
mV
P-P
Clock Input Common-Mode
Voltage Range
Internally self-biased 1.15 ±0.25 V
Clock Differential Input
Resistance
R
CLK
11 ±25% kΩ
Clock Differential Input
Capacitance
C
CLK
5pF
DYNAMIC CHARACTERISTICS (at AIN = -1dBFS)
fIN = 10MHz
fIN = 100MHz
fIN = 200MHz 66
Signal-to-Noise Ratio SNR
f
IN
= 250MHz
dB
fIN = 10MHz
fIN = 100MHz
fIN = 200MHz
Signal-to-Noise and Distortion SINAD
f
IN
= 250MHz
dB
fIN = 10MHz
88
fIN = 100MHz
fIN = 200MHz 80
Spurious-Free Dynamic Range SFDR
f
IN
= 250MHz 79
dBc
fIN = 10MHz -88
fIN = 100MHz -87
fIN = 200MHz -80
Worst Harmonics
(HD2 or HD3)
f
IN
= 250MHz -79
dBc
Two-Tone Intermodulation
Distortion
TTIMD
f
IN1
= 97MHz at -7dBFS,
f
IN2
= 100MHz at -7dBFS
dBc
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage |VOD|RL = 100Ω
440 mV
Output Offset Voltage OV
OS
RL = 100Ω
V
200 500
66.5 67.7
66.2 67.2
65.2
66.1 67.6
65.7 67.1
65.8
64.9
75.0
74.5 87.0
-86
280
1.125 1.340
-75.0
-74.5
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref-
erence, digital output pins differential R
L
= 100Ω. Limits are for TA= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input-Voltage Low V
IL
V
Digital Input-Voltage High V
IH
0.8 x AV
CC
V
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay t
PDL
Figure 5
ns
CLK-to-DCLK Propagation Delay
t
CPDL
Figure 5
ns
DCLK-to-Data Propagation Delay
Figure 5 (Note 3)
ns
LVDS Output Rise Time t
RISE
20% to 80%, CL = 5pF
ps
LVDS Output Fall Time t
FALL
20% to 80%, CL = 5pF
ps
Output Data Pipeline Delay
Figure 5 11
Clock
cycles
POWER REQUIREMENTS
Analog Supply Voltage Range AV
CC
V
Digital Supply Voltage Range OV
CC
V
Analog Supply Current I
AVCC
fIN = 100MHz
366 mA
Digital Supply Current I
OVCC
fIN = 100MHz 63 69 mA
Analog Power Dissipation P
DISS
fIN = 100MHz
783 mW
Offset 1.8
mV/V
Power-Supply Rejection Ratio
(Note 4)
PSRR
Gain 1.5
%FS/V
Note 1: Values at TA≥ +25°C guaranteed by production test, values at TA< +25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are computed from an end-point curve fit.
Note 3: Parameter guaranteed by design and characterization: T
A
= -40°C to +85°C.
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
0.2 x AV
t
- t
CPDL
PDL
t
LATENCY
2.30 2.56 2.82
1.70 1.80 1.90
1.70 1.80 1.90
1.98
4.58
450
450
337
720
CC
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 5
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
2
f
SAMPLE
= 170MHz
f
IN
= 12.471MHz
A
IN
= -1.03dBFS
SNR = 67.7dB
SINAD = 67.6dB
THD = -86.4dBc
SFDR = 88.27dBc
HD2 = -88.27dBc
HD3 = -101.7dBc
3
4
5
706040
50
20 30100
80
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 99.962MHz
A
IN
= -0.997dBFS
SNR = 67.2dB
SINAD = 67.1dB
THD = -85dBc
SFDR = 86.2dBc
HD2 = -95.6dBc
HD3 = -86.2dBc
3
5
2
4
706040
50
20 30100
80
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 199.488MHz
A
IN
= -0.942dBFS
SNR = 65.7dB
SINAD = 65.3dB
THD = -75.7dBc
SFDR = 77.4dBc
HD2 = -77.4dBc
HD3 = -81.5dBc
706040
50
20 30100
80
5
4
2
3
FFT PLOT
(8192-POINT DATA RECORD)
MAX1213N toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
SAMPLE
= 170MHz
f
IN
= 250.040MHz
A
IN
= -0.997dBFS
SNR = 64.85dB
SINAD = 64.6dB
THD = -77.3dBc
SFDR = 79.2dBc
HD2 = -79.2dBc
HD3 = -83.3dBc
706040
50
20 30100
80
2
4
5
3
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
MAX1213N toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-110
f
IN2
f
SAMPLE
= 170MHz
f
IN1
= 96.973877MHz
f
IN2
= 99.9621582MHz
A
IN1
= A
IN2
= -7dBFS
IMD = -86dBc
2f
IN2
- f
IN1
2f
IN1
- f
IN2
f
IN1
706040
50
20 30100
80
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc06
f
IN
(MHz)
SNR/SINAD (dB)
25020015010050
50
55
60
65
70
45
0 300
SNR
SINAD
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc07
f
IN
(MHz)
SFDR/(-THD) (dBc)
25020015010050
50
55
60
65
70
75
80
85
90
95
100
45
0 300
SFDR
-THD
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc08
f
IN
(MHz)
HD2/HD3 (dBc)
25020015010050
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-110
0 300
HD2
HD3
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR/SINAD (dB)
-5-10-15-20-25-30-35-40-45-50
10
20
30
40
50
60
70
0
-55 0
SNR
SINAD
Typical Operating Characteristics
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for
Broadband Applications
6 _______________________________________________________________________________________
SFDR/(-THD) vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc10
ANALOG INPUT AMPLITUDE (dBFS)
SFDR/(-THD) (dBc)
-5-10-20 -15-45 -40 -35 -30 -25-50
35
40
45
50
55
60
65
70
75
80
85
90
95
100
30
-55 0
SFDR
-THD
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 170MHz, fIN = 64.985MHz)
MAX1213N toc11
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
-5-10-50 -45 -40 -30 -25 -20-35 -15
-100
-90
-80
-70
-60
-50
-40
-30
-110
-55 0
HD2
HD3
SNR/SINAD vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc12
f
SAMPLE
(MHz)
SNR/SINAD (dB)
16014012010080604020
45
50
55
60
65
70
75
40
0 180
SNR
SINAD
MAX1213N toc13
f
SAMPLE
(MHz)
SFDR/(-THD) (dBc)
160140100 12040 60 8020
55
60
65
70
75
80
85
90
95
100
50
0 180
SFDR/(-THD) vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
SFDR
-THD
HD2/HD3 vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc14
f
SAMPLE
(MHz)
HD2/HD3 (dBc)
160140100 12040 60 8020
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-120
0 180
HD3
HD2
TOTAL POWER DISSIPATION vs. SAMPLE FREQUENCY
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc15
f
SAMPLE
(MHz)
P
DISS
(-15mW)
15514035 50 65 95 11080 125
0.610
0.635
0.660
0.685
0.710
0.735
0.760
0.785
0.585
20 170
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2560 3072 3584 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1213N toc16
DIGITAL OUTPUT CODE
INL (LSB)
fIN = 12.5MHz
-1.0
-0.6
-0.8
-0.2
-0.4
0.2
0
0.4
0.8
0.6
1.0
0 1024 1536512 2048 2560 3072 3584 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1213N toc17
DIGITAL OUTPUT CODE
DNL (LSB)
fIN = 12.5MHz
GAIN BANDWIDTH PLOT
(f
SAMPLE
= 170MHz, AIN = -1dBFS)
MAX1213N toc18
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10 100
-6
-5
-4
-3
-2
-1
0
1
-7
1 1000
Typical Operating Characteristics (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
MAX1213N
1.8V, Low-Power 12-Bit, 170Msps ADC for
Broadband Applications
_______________________________________________________________________________________ 7
SINAD
60.5
63.5
62.5
61.5
64.5
65.5
66.5
67.5
68.5
69.5
70.5
-40 10-15 35 60 85
SNR/SINAD vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc19
TEMPERATURE (°C)
SNR/SINAD (dB)
SNR
50
55
60
65
70
75
80
85
90
-40 -15 10 35 60 85
SFDR/(-THD) vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc20
SFDR/(-THD) (dBc)
TEMPERATURE (°C)
SFDR
-THD
50
65
60
55
70
75
80
85
90
95
100
-40 10-15 35 60 85
HD2/HD3 vs. TEMPERATURE
(f
SAMPLE
= 170MHz, fIN = 100MHz, AIN = -1dBFS)
MAX1213N toc21
TEMPERATURE (°C)
HD2/HD3 (dBc)
HD2
HD3
SNR/SINAD vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc22
SUPPLY VOLTAGE (V)
SNR/SINAD (dB)
1.851.801.75
61
62
63
64
65
66
67
68
69
70
60
1.70 1.90
SNR
SINAD
Typical Operating Characteristics (continued)
(AV
CC
= OV
CC
= 1.8V, AGND = OGND = 0, f
SAMPLE
= 170MHz, A
IN
= -1dBFS, see each TOC for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA= +25°C.)
SFDR/(-THD) vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc23
SUPPLY VOLTAGE (V)
SFDR/(-THD) (dBc)
1.851.801.75
73
76
79
82
85
88
91
94
97
100
70
1.70 1.90
-THD
SFDR
HD2/HD3 vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc24
SUPPLY VOLTAGE (V)
HD2/HD3 (dBc)
1.851.801.75
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-120
1.70 1.90
HD3
HD2
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(f
IN
= 64.985MHz, AIN = -1dBFS)
MAX1213N toc25
SUPPLY VOLTAGE (V)
V
REF
(V)
1.243
1.244
1.245
1.246
1.247
1.248
1.249
1.250
1.242
1.851.801.751.70 1.90
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
AV
CC
Analog Supply Voltage. Bypass AVCC to AGND with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results. Connect all AV
CC
inputs together. See the Grounding,
Bypassing, and Board Layout Considerations section.
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGND Analog Converter Ground. Connect all AGND inputs together.
3 REFIO
Reference Input/Output. Pull REFADJ high to allow REFIO to accept an external reference.
Pull REFADJ low to activate the internal 1.24V-bandgap reference. Connect a 0.1µF capacitor
from REFIO to AGND for both internal and external reference.
4 REFADJ
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). Connect REFADJ to AV
CC
to override the internal reference with an external source
connected to REFIO. Connect REFADJ to AGND to allow the internal reference to determine the
FSR of the data converter. See the FSR Adjustment Using the Internal Bandgap Reference
section.
8 INP Positive Analog Input Terminal. Internally self-biased to 0.74V.
9 INN Negative Analog Input Terminal. Internally self-biased to 0.74V.
17 CLKDIV
Clock Divider Input. CLKDIV controls the sampling frequency relative to the input clock
frequency. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: Sampling frequency is at one-half the input clock frequency.
CLKDIV = 1: Sampling frequency is equal to the input clock frequency.
22 CLKP
True Clock Input. Apply an LVDS-compatible input level to CLKP. Internally self-biased to
1.15V.
23 CLKN
Complementary Clock Input. Apply an LVDS-compatible input level to CLKN. Internally selfbiased to 1.15V.
26, 45, 61 OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers. Connect all
OGND inputs together.
27, 28, 41, 44, 60
OV
CC
Digital Supply Voltage. Bypass OVCC with a 0.1µF capacitor to OGND. Connect all OVCC inputs
together. See the Grounding, Bypassing, and Board Layout Considerations section.
29 D0N Complementary Output Bit 0 (LSB)
30 D0P True Output Bit 0 (LSB)
31 D1N Complementary Output Bit 1
32 D1P True Output Bit 1
33 D2N Complementary Output Bit 2
34 D2P True Output Bit 2
35 D3N Complementary Output Bit 3
36 D3P True Output Bit 3
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
37 D4N Complementary Output Bit 4
38 D4P True Output Bit 4
39 D5N Complementary Output Bit 5
40 D5P True Output Bit 5
42 DCLKN
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.
43 DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.
46 D6N Complementary Output Bit 6
47 D6P True Output Bit 6
48 D7N Complementary Output Bit 7
49 D7P True Output Bit 7
50 D8N Complementary Output Bit 8
51 D8P True Output Bit 8
52 D9N Complementary Output Bit 9
53 D9P True Output Bit 9
54 D10N Complementary Output Bit 10
55 D10P True Output Bit 10
56 D11N Complementary Output Bit 11 (MSB)
57 D11P True Output Bit 11 (MSB)
58 ORN
Complementary Out-of-Range Control Bit Output. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
59 ORP
True Out-of-Range Control Bit Output. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.
68 T/B
Output Format Select. This LVCMOS-compatible input controls the digital output format of the
MAX1213N. T/B has an internal pulldown resistor.
T/B = 0: Two’s-complement output format.
T/B = 1: Binary output format.
—EP
Exposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to AGND.
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
10 ______________________________________________________________________________________
Detailed Description—
Theory of Operation
The MAX1213N uses a fully differential pipelined architecture that allows for high-speed conversion, optimized accuracy, and linearity while minimizing power
consumption.
Both positive (INP) and negative/complementary analog
input terminals (INN) are centered around a 0.74V common-mode voltage, and accept a differential analog
input voltage swing of ±VFS/ 4 each, resulting in a typical 1.38V
P-P
differential full-scale signal swing. Inputs
INP and INN are sampled when the differential sampling
clock signal transitions high. When using the clock-
divide mode, the analog inputs are sampled at every
other high transition of the differential sampling clock.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s-complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1213N architecture.
MAX1213N
AV
CC
900Ω
COMMONMODE
BUFFER
900Ω
D0P/N
DCLKP
DCLKN
D1P/N
D2P/N
LVDS
DATA
PORT
OV
CC
AGND
OGND
T/H
12-BIT PIPELINE
ADC
CLOCK
MANAGEMENT
REFERENCE
CLKDIV
CLKN
CLKP
REFADJ
REFIO
INP
INN
DIV1/DIV2
D11P/N
ORP/ORN
T/B
Figure 1. Block Diagram
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
______________________________________________________________________________________ 11
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1213N. Differential inputs usually feature good
rejection of even-order harmonics, which allows for
enhanced AC performance as the signals are progressing through the analog stages. The MAX1213N analog
inputs are self-biased at a 0.74V common-mode voltage
and allow a 1.38V
P-P
differential input voltage swing
(Figure 2). Both inputs are self-biased through 900Ω
resistors, resulting in a typical differential input resistance of 1.8kΩ. Drive the analog inputs of the
MAX1213N in AC-coupled configuration to achieve the
best dynamic performance. See the Transformer-
Coupled, Differential Analog Input Drive section.
MAX1213N
12-BIT PIPELINE
ADC
C
S
FROM CLOCKMANAGEMENT BLOCK
T/H
TO COMMON MODE
C
S
C
P
INP
INP
INP - INN
V
CM
+ V
FS
/ 4
VCM - V
FS
/ 4
+V
FS
/ 2
-V
FS
/ 2
GND
GND
V
CM
INN
INN
C
S
IS THE SAMPLING CAPACITANCE
C
P
IS THE PARASITIC CAPACITANCE ˜ 1pF
AV
CC
900Ω
900Ω
C
P
1.38V DIFFERENTIAL FSR
Figure 2. Simplified Analog Input Architecture and Allowable Input Voltage Range
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
12 ______________________________________________________________________________________
On-Chip Reference Circuit
The MAX1213N features an internal 1.24V-bandgap reference circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the FSR
of the MAX1213N. Bypass REFIO with a 0.1µF capacitor
to AGND. To compensate for gain errors or increase/decrease the ADC’s FSR, the voltage of this bandgap reference can be indirectly adjusted by adding an external
resistor (e.g., 100kΩ trim potentiometer) between
REFADJ and AGND or REFADJ and REFIO. See the
Applications Information section for a detailed description
of this process.
To disable the internal reference, connect REFADJ to
AVCC. Apply an external, stable reference to set the
converter’s full scale. To enable the internal reference,
connect REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Drive the clock inputs of the MAX1213N with an LVDSor LVPECL-compatible clock to achieve the best dynamic performance. The clock signal source must be of high
quality and low phase noise to avoid any degradation in
the noise performance of the ADC. The clock inputs
(CLKP, CLKN) are internally biased to 1.15V and accept
a typical 0.5V
P-P
differential signal swing (Figure 4). See
the Differential, AC-Coupled LVPECL-Compatible Clock
Input section for more circuit details on how to drive
CLKP and CLKN appropriately. Although not recommended, the clock inputs also accept a single-ended
input signal.
The MAX1213N also features an internal clock-management circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum 20MHz
clock frequency to allow the device to meet data sheet
specifications.
MAX1213N
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
1V
AV
CC
AV
CC
/ 2
G
CONTROL LINE TO
DISABLE REFERENCE BUFFER
REFERENCESCALING AMPLIFIER
REFIO
REFADJ*
0.1µF
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY.
REFT
REFB
Figure 3. Simplified Reference Architecture
2.89k
Ω
AV
DD
AGND
CLKN
CLKP
5.35k
Ω
5.35k
Ω
5.35k
Ω
Figure 4. Simplified Clock Input Architecture
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
______________________________________________________________________________________ 13
Data Clock Outputs (DCLKP, DCLKN)
The MAX1213N features a differential clock output,
which can be used to latch the digital output data with
an external latch or receiver. Additionally, the clock output can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
4.58ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 5 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1213N offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at onehalf the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OVCCdisables the divide-by-2 mode.
System Timing Requirements
Figure 5 shows the relationship between the clock input
and output, analog input, sampling event, and data output. The MAX1213N samples on the rising (falling)
edge of CLKP (CLKN). Output data is valid on the next
rising (falling) edge of the DCLKP (DCLKN) clock, but
has an internal latency of 11 clock cycles.
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input
T
/B
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compatible
input, which allows the user to select the desired output
format. Pulling T/B low outputs data in two’s complement
and pulling it high presents data in offset binary format
on the 12-bit parallel bus. T/B has an internal pulldown
resistor and may be left unconnected in applications
using only two’s-complement output format. All LVDS
outputs provide a typical 0.325V voltage swing around a
1.2V common-mode voltage, and must be terminated at
the far end of each transmission line pair (true and complementary) with 100Ω. Apply a 1.7V to 1.9V voltage
supply at OVCCto power the LVDS outputs.
The MAX1213N offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital outputs should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
SAMPLING EVENT
INP
INN
CLKN
CLKP
DCLKN
DCLKP
D0P/D0N–
D11P/D11N
ORP/N
t
PDL
t
CPDL
- t
PDL
~ 0.4 x t
SAMPLE
WITH t
SAMPLE
= 1 / f
SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
NN + 1 N + 10
N - 9N - 10
N - 1
N - 1
N + 11 N + 12
N + 1
N - 11
N - 11 N
N - 10
N + 1
N
SAMPLING EVENT
SAMPLING EVENT SAMPLING EVENT SAMPLING EVENT
t
LATENCY
t
CPDL
t
AD
t
CH
t
CL
Figure 5. Simplified LVDS Output Architecture
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
14 ______________________________________________________________________________________
Table 1. MAX1213N Digital Output Coding
INP ANALOG
INPUT VOLTAGE
LEVEL
INN ANALOG
INPUT VOLTAGE
LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY DIGITAL OUTPUT
CODE (D11P/N–D0P/N)
TWO’S-COMPLEMENT DIGITAL
OUTPUT CODE (D11P/N–D0P/N)
> VCM + V
FS
/ 4
< VCM - V
FS
/ 4 1 (0)
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
VCM + V
FS
/ 4 VCM - V
FS
/ 4 0 (1) 1111 1111 1111 (+FS) 0111 1111 1111 (+FS)
V
CM
V
CM
0 (1)
1000 0000 0000 or
0111 1111 1111 (FS/2)
0000 0000 0000 or
1111 1111 1111 (FS/2)
VCM - V
FS
/ 4 VCM + V
FS
/ 4 0 (1) 0000 0000 0000 (-FS) 1000 0000 0000 (-FS)
< VCM + V
FS
/ 4
> V
CM
- V
FS
/ 4 1 (0)
00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
Applications Information
FSR Adjustments Using the Internal
Bandgap Reference
The MAX1213N supports a 10% (±5%) full-scale
adjustment range. To decrease the full-scale signal
range, add an external resistor value ranging from
13kΩ to 1MΩ between REFADJ and AGND. Adding a
variable resistor, potentiometer, or predetermined resis-
tor value between REFADJ and REFIO increases the
FSR of the data converter. Figure 6a shows the two
possible configurations and their impact on the overall
full-scale range adjustment of the MAX1213N. Do not
use resistor values of less than 13kΩ to avoid instability
of the internal gain regulation loop for the bandgap reference. See Figure 6b for the resulting FSR for a series
of resistor values.
MAX1213N
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
CONFIGURATION TO INCREASE THE FSR OF THE MAX1213N
1V
AV
CC
AV
CC
/ 2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCESCALING
AMPLIFIER
REFIO
REFADJ
0.1µF
REFT
REFB
13kΩ TO
1MΩ
MAX1213N
REFERENCE
BUFFER
ADC FULL SCALE = REFT - REFB
CONFIGURATION TO DECREASE THE FSR OF THE MAX1213N
1V
AV
CC
AV
CC
/ 2
G
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
REFERENCESCALING
AMPLIFIER
REFIO
REFADJ
0.1µF
REFT
REFB
13kΩ TO
1MΩ
Figure 6a. Circuit Suggestions to Adjust the ADC’s Full-Scale Range
Differential, AC-Coupled, LVPECL-Compatible
Clock Input
The MAX1213N dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The preferred method of clocking the MAX1213N is differentially with LVDS- or LVPECL-compatible input levels. The
fast data transition rates of these logic families minimize
the clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ω reverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16 (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
______________________________________________________________________________________ 15
FS VOLTAGE
vs. FS ADJUST RESISTOR
MAX1213N fig06b
FS ADJUST RESISTOR (kΩ)
V
FS
(V)
800
900
700
500
600
200
300
400
100
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.14
0 1000
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES V
FS
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND REFIO INCREASES V
FS
Figure 6b. FS Adjustment Range vs. FS Adjustment Resistor
MC100LVEL16D
AGND
OGND
D0P/N–D11P/N, ORP/N
AV
CC
V
CLK
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
SINGLE-ENDED
INPUT TERMINAL
150Ω
150Ω
CLKP
CLKN
INP
INN
OV
CC
12
2
8
45
7
6
3
50Ω
10kΩ
510Ω510Ω
MAX1213N
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
16 ______________________________________________________________________________________
12
D0P/N–D11P/N,
ORP/N
AV
CC
OV
CC
AGND
0.1µF
0.1µF
INP
INN
ADT1-1WT
1
5
3
4
2
6
3
5
1
6
2
4
SINGLE-ENDED
INPUT TERMINAL
24.9 Ω
ADT1-1WT
24.9 Ω
10Ω
1%
10Ω
1%
OGND
0.1µF
MAX1213N
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
Figure 9. Single-Ended, AC-Coupled Analog Input Configuration
Transformer-Coupled, Differential
Analog Input Drive
The MAX1213N provides the best SFDR and THD with
fully differential input signals and it is not recommended
to drive the ADC inputs in single-ended configuration.
In differential input mode, even-order harmonics are
usually lower since INP and INN are balanced, and
each of the ADC inputs only requires half the signal
swing compared to a single-ended configuration.
Wideband RF transformers provide an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1213N to reach its
optimum dynamic performance. Apply a secondaryside termination of a 1:1 transformer (e.g., Mini-Circuit’s
ADT1-1WT) into two separate 24.9Ω resistors. Higher
source impedance values can be used at the expense
of degradation in dynamic performance. This configuration optimizes THD and SFDR performance of the
ADC by reducing the effects of transformer parasitics.
However, the source impedance combined with the
shunt capacitance provided by a PC board and the
ADC’s parasitic capacitance limit the ADC’s full-power
input bandwidth.
To further enhance THD and SFDR performance at high
input frequencies (> 100MHz), a second transformer
(Figure 8) should be placed in series with the singleended-to-differential conversion transformer. This transformer reduces the increase of even-order harmonics
at high frequencies.
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1213N can be used
in single-ended mode (Figure 9). AC-couple the analog
signals to the positive input INP through a 0.1µF capacitor
terminated with a 49.9Ω resistor to AGND. Terminate the
negative input INN with a 49.9Ω resistor in series with a
0.1µF capacitor to AGND. In single-ended mode, the
input range is limited to approximately half of the FSR of
the device, and dynamic performance usually degrades.
SINGLE-ENDED
INPUT TERMINAL
OV
AV
CC
CC
0.1µF
49.9Ω
1%
0.1µF
49.9Ω
1%
INP
INN
MAX1213N
AGND
OGND
D0P/N–D11P/N, ORP/N
12
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
______________________________________________________________________________________ 17
Grounding, Bypassing, and
Board Layout Considerations
The MAX1213N requires board-layout design techniques suitable for high-speed data converters. This
ADC provides separate analog and digital power supplies. The analog and digital supply voltage pins accept
1.7V to 1.9V input voltage ranges. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switching currents, which can couple into the analog supply
network. Isolate analog and digital supplies (AVCCand
OVCC) where they enter the PC board with separate networks of ferrite beads and capacitors to their corresponding grounds (AGND, OGND).
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1213N. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point so the noisy digital
ground currents do not interfere with the analog ground
plane. The dynamic currents that may need to travel
long distances before they are recombined at a common source ground, resulting in large and undesirable
ground loops, are a major concern with this approach.
Ground loops can degrade the input noise by coupling
back to the analog front-end of the converter, resulting
in increased spurious activity, leading to decreased
noise performance.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be positioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front-end and
the digital outputs.
AGND
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
BYPASSING—ADC LEVEL
BYPASSING—BOARD LEVEL
ANALOG POWERSUPPLY SOURCE
OGND
AGND
OGND
D0P/N–D11P/N, ORP/N
1µF
10µF
0.1µF0.1µF
47µF
AV
CC
OV
CC
12
MAX1213N
AV
CC
DIGITAL/OUTPUT
DRIVER POWERSUPPLY SOURCE
1µF
10µF47µF
OV
CC
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for the MAX1213N
The MAX1213N is packaged in a 68-pin QFN-EP package (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow soldering techniques.
Thermal efficiency is one of the factors for selecting a
package with an exposed paddle for the MAX1213N.
The exposed paddle improves thermal and ensures a
solid ground connection between the ADC and the PC
board’s analog ground layer.
Considerable care must be taken when routing the digital output traces for a high-speed, high-resolution data
converter. Keep trace lengths at a minimum and place
minimal capacitive loading (less than 5pF) on any digital trace to prevent coupling to sensitive analog sections of the ADC. It is recommended running the LVDS
output traces as differential lines with 100Ω matched
impedance from the ADC to the LVDS load device.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1213N are measured using the
histogram method with a 10MHz input frequency.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1213N’s DNL specification is measured with the
histogram method based on a 10MHz input tone.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 shows the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
[max]
= 6.02 x N + 1.76
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities also contribute to the SNR calculation and
should be considered when determining the signal-tonoise ratio in ADC. The SNR for the MAX1213N is specified in decibels (dB), however, SNR can also be
specified in dBFS. To obtain the SNR in dBFS, simply
subtract the amplitude of the input tone (this number is
given in dBFS) at which the SNR is measured from the
SNR number in dB. For example, an ADC having an
SNR of 67dB resulting from an input tone with amplitude
-1dBFS will have an SNR of 67 - (-1) = 68dBFS.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset. In the case of the MAX1213N,
SINAD is computed from a curve fit.
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
18 ______________________________________________________________________________________
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLKN
CLKP
Figure 11. Aperture Jitter/Delay Specifications
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal component) to the RMS
value of the next-largest noise or harmonic distortion
component. SFDR is usually measured in dBc with
respect to the carrier frequency amplitude or in dBFS
with respect to the ADC’s full-scale range.
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
The fundamental input tone amplitudes (V1and V2) are at
-7dBFS. The intermodulation products are the amplitudes
of the output spectrum at the following frequencies:
• Second-order intermodulation products: f
IN1
+ f
IN2
,
f
IN2
- f
IN1
• Third-order intermodulation products: 2 x f
IN1
- f
IN2
,
2 x f
IN2
- f
IN1
, 2 x f
IN1
+ f
IN2
, 2 x f
IN2
+ f
IN1
• Fourth-order intermodulation products: 3 x f
IN1
- f
IN2
,
3 x f
IN2
- f
IN1
, 3 x f
IN1
+ f
IN2
, 3 x f
IN2
+ f
IN1
• Fifth-order intermodulation products: 3 x f
IN1
- 2 x f
IN2
,
3 x f
IN2
- 2 x f
IN1
, 3 x f
IN1
+ 2 x f
IN2
, 3 x f
IN2
+ 2 x f
IN1
Full-Power Bandwidth
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB point is defined as
the full-power input bandwidth frequency of the ADC.
IMD
VV V V
VV
IM IM IM IMn
log
......
=×
++++
+
20
1
2
2
2
3
22
122
2
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
______________________________________________________________________________________ 19
Pin Configuration
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
AV
CC
AGND
AV
CC
TOP VIEW
AVCCOGND
OVCCORP
ORN
D11P
D11N
D10P
D10N
5253
D9P
D9N
AGND
AGND
AV
CC
CLKN
CLKP
AV
CC
AGND
OV
CC
OGND
D0N
OV
CC
D1N
D0P
D1P
D6P
D6N
OGND
OV
CC
DCLKP
DCLKN
OV
CC
D5P
D5N
D4P
35
36
37 D4N
D3P
D3N
AGND
INN
INP
AGND
AV
CC
AGND
AGND
AV
CC
AV
CC
AV
CC
AGND
REFADJ
REFIO
AGND
48 D7N
AV
CC
64
AGND
656667
AGND
AGND
AV
CC
68
T/B
2322212019 2726252418 2928 323130
D2N
D2P
3433
49
50
D8N
D7P
EP
51 D8P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
CLKDIV
EP = EXPOSED PADDLE
17
MAX1213N
QFN
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
20 ______________________________________________________________________________________
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
For the MAX1213N, the package code is G6800-4.
MAX1213N
1.8V, Low-Power, 12-Bit, 170Msps
ADC for Broadband Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
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