Maxim MAX1202BCPP, MAX1202BCAP, MAX1202ACAP, MAX1202BC-D, MAX1202ACPP Datasheet

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General Description

The MAX1202/MAX1203 are 12-bit data-acquisition
systems specifically designed for use in applications
with mixed +5V (analog) and +3V (digital) supply volt­ages. They operate with a single +5V analog supply or
dual ±5V analog supplies, and combine an 8-channel
multiplexer, high-bandwidth track/hold, and serial inter­face with high conversion speed and low power con­sumption.

A 4-wire serial interface connects directly to
SPI™/MICROWIRE™ devices without external logic,
and a serial strobe output allows direct connection to
TMS320-family digital signal processors. The
MAX1202/MAX1203 use either the internal clock or an
external serial-interface clock to perform successive­approximation analog-to-digital conversions. The serial
interface operates at up to 2MHz.

The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies
gain trim. They also have a VL pin that is the power
supply for the digital outputs. Output logic levels (3V,

3.3V, or 5V) are determined by the value of the voltage
applied to this pin.

These devices provide a hard-wired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power­down between conversions, supply current can drop
below 10µA at reduced sampling rates.

The MAX1202/MAX1203 are available in 20-pin SSOP
and DIP packages, and are specified for the commer­cial, extended, and military temperature ranges.

Applications

5V/3V Mixed-Supply Systems
Data Acquisition
High-Accuracy Process Control
Battery-Powered Instruments
Medical Instruments

Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Operates from Single +5V or Dual ±5V Supplies
♦ User-Adjustable Output Logic Levels

(2.7V to 5.25V)

♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference (MAX1202)
♦ SPI/MICROWIRE/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar/Bipolar Inputs
♦ 20-Pin DIP/SSOP

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

________________________________________________________________

Maxim Integrated Products

1

20
19

18
17
16
15
14
13
12

11

1
2
3
4
5
6
7
8
9

10

TOP VIEW

DIP/SSOP

V

DD

SCLK
CS
DIN
SSTRB
DOUT
VL
GND
REFADJ
REF

SHDN

V

SS

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

MAX1202
MAX1203

Pin Configuration

19-1173; Rev 2; 5/98

EVALUATION KIT

AVAILABLE

Typical Operating Circuit appears at end of data sheet.

SPI is a registered trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.

Ordering Information continued at end of data sheet.

*

Dice are specified at TA= +25°C, DC parameters only.

±1Dice*0°C to +70°CMAX1202BC/D

MAX1202BCAP

MAX1202ACAP

MAX1202BCPP

MAX1202ACPP

PART TEMP. RANGE

0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C 20 SSOP

20 SSOP

20 Plastic DIP

20 Plastic DIP

PIN-PACKAGE

INL

(LSB)

±1/2

±1

±1/2

±1

Ordering Information

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND ................................................................-0.3V to 6V

VL ...............................................................-0.3V to (V

DD

+ 0.3V)

V

SS

to GND.................................................................0.3V to -6V

V

DD

to VSS................................................................-0.3V to 12V

CH0–CH7 to GND............................(V

SS

- 0.3V) to (VDD+ 0.3V)

CH0–CH7 Total Input Current...........................................±20mA

REF to GND................................................-0.3V to (V

DD

+ 0.3V)

REFADJ to GND.........................................-0.3V to (V

DD

+ 0.3V)

Digital Inputs to GND .................................-0.3V to (V

DD

+ 0.3V)

Digital Outputs to GND.................................-0.3V to (VL + 0.3V)

Digital Output Sink Current.................................................25mA

Continuous Power Dissipation (T

A

= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW°C above +70°C).................889mW

Operating Temperature Ranges

MAX1202_C_P/MAX1203_C_P............................0°C to +70°C

MAX1202_E_P/MAX1203_E_P..........................-40°C to +85°C

MAX1202BMJP/MAX1203BMJP.....................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin;

T

A

= T

MIN

to T

MAX

; unless otherwise noted.)

-3dB rolloff MHz4.5

MAX1202A/MAX1203A

Small-Signal Bandwidth

kHz800

VIN= 4.096Vp-p, 65kHz (Note 4)

External reference, 4.096V

MAX1202B/MAX1203B
No missing codes over temperature

CONDITIONS

Full-Power Bandwidth

±3MAX1202 (all grades)

dB-85Channel-to-Channel Crosstalk

dB80SFDRSpurious-Free Dynamic Range

dB-80THD

Total Harmonic Distortion
(up to the 5th harmonic)

dB70SINADSignal-to-Noise + Distortion Ratio

LSB

±0.5

INLRelative Accuracy (Note 2)

Bits12Resolution

LSB±0.1

Channel-to-Channel
Offset Matching

ppm/°C±0.8Gain Temperature Coefficient

±1.0

LSB±1.0DNLDifferential Nonlinearity

UNITSMIN TYP MAXSYMBOLPARAMETER

LSB±3.0Offset Error

±1.5 LSB

±3

Gain Error (Note 3)

External reference, 4.096V

MAX1203A
MAX1203B

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar-input mode)

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin;

T

A

= T

MIN

to T

MAX

; unless otherwise noted.)

MAX1202AC

TA= +25°C

External clock, 2MHz, 12 clocks/conversion

(Note 6)

On/off leakage current, V

CH_

= ±5V

Bipolar, VSS= -5V

Unipolar, VSS= 0V

6

Used for data transfer only

Internal compensation mode (Note 6)

Internal clock

MAX1202AE

External compensation mode

External compensation mode, 4.7µF

±30 ±60

CONDITIONS

ppm/°C

±30 ±50

V

REF

Temperature Coefficient

mA30REF Short-Circuit Current

V4.076 4.096 4.116REF Output Voltage

pF16Input Capacitance

µA±0.01 ±1Multiplexer Leakage Current

±V

REF

/2

4.7

V

V

REF

Input Voltage Range, Single­Ended and Differential (Note 7)

0 2.0

±30

0.1 0.4

MAX1202B

µF

MHz

0.1 2.0

External Clock Frequency Range

MHz1.7Internal Clock Frequency

0.01

0mA to 0.5mA output load mV2.5Load Regulation (Note 8)

ns10Aperture Delay

µs1.5t

ACQ

Track/Hold Acquisition Time

µs

5.5 10

t

CONV

Conversion Time (Note 5)

Internal compensation mode

µF

0

Capacitive Bypass at REF
Capacitive Bypass at REFADJ

UNITSMIN TYP MAXSYMBOLPARAMETER

ps

%±1.5REFADJ Adjustment Range

V

2.50 VDD+
50mV

Input Voltage Range

µA200 350Input Current
kΩ

12 20Input Resistance

SHDN = 0V

µA1.5 10REF Input Current in Shutdown

V

VDD­50mV

REFADJ Buffer Disable Threshold

<50Aperture Jitter

CONVERSION RATE

INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)

ANALOG INPUT

EXTERNAL REFERENCE AT REF (Reference buffer disabled, V

REF

= 4.096V)

µA

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin;

T

A

= T

MIN

to T

MAX

; unless otherwise noted.)

Operating mode mA1.5 2.5

Internal compensation mode

VDD= 5V ±5%; external reference, 4.096V;
full-scale input

mV±0.06 ±0.5

V

Fast power-down (Note 9) 30 70

External compensation mode
MAX1202

MAX1202

CONDITIONS

2.70 5.25VLLogic Supply Voltage

VL = VDD= 5V µA10I

VL

Logic Supply Current (Notes 6, 10)

PSR

Positive Supply Rejection
(Note 11)

VSS= -5V ±5%; external reference, 4.096V;
full-scale input

mV±0.01 ±0.5PSR

Negative Supply Rejection
(Note 11)

External reference, 4.096V; full-scale input mV±0.06 ±0.5PSR

Logic Supply Rejection
(Note 12)

µA

µF

0

Capacitive Bypass at REF

V0 or -5 ±5%V

SS

Negative Supply Voltage

V5 ±5%V

DD

Positive Supply Voltage

4.7

1.68

±50

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX1203

V/V

1.64

Reference-Buffer Gain

MAX1203

µA

±5

REFADJ Input Current

Full power-down 10

Operating mode and fast power-down

µA

50

I

SS

Negative Supply Current

Full power-down (Note 9)

µA

I

DD

210

Positive Supply Current

EXTERNAL REFERENCE AT REFADJ

POWER REQUIREMENTS

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin;

T

A

= T

MIN

to

T

MAX

; unless otherwise noted.)

CS = VL (Note 6)

CS = VL

I

SOURCE

= 1mA

I

SINK

= 3mA

SHDN = open

SHDN = 0V

SHDN = V

DD

(Note 6)

VIN= 0V or V

DD

SHDN = open

I

SINK

= 5mA

CONDITIONS

pF15C

OUT

Three-State Output Capacitance

µA±10I

L

Three-State Leakage Current

VVL - 0.5V

OH

Output Voltage High

V

0.4

V

OL

Output Voltage Low

nA-100 100

SHDN Maximum Allowed
Leakage, Mid-Input

V2.75V

FLT

SHDN Voltage, Floating

µA-4.0I

SL

SHDN Input Current, Low

µA4.0I

SH

SHDN Input Current, High

VV

DD

- 0.5V

SH

SHDN Input High Voltage

V

0.4

V

OL

Output Voltage Low

V0.8V

IL

V2.0V

IH

DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage

I

SINK

= 8mA 0.3

V1.5 VDD- 1.5

I

SINK

= 6mA

V

SM

0.3

pF15C

IN

DIN, SCLK, CS Input Capacitance

µA±1I

IN

DIN, SCLK, CS Input Leakage

SHDN Input Mid-Voltage

I

SOURCE

= 1mA V

V0.15V

HYST

DIN, SCLK, CS Input Hysteresis

4V

OH

Output Voltage High

CS = 5V

µA±10I

L

Three-State Leakage Current

UNITSMIN TYP MAXSYMBOLPARAMETER

CS = 5V (Note 6)

pF15C

OUT

Three-State Output Capacitance

V0.5V

SL

SHDN Input Low Voltage

DIGITAL INPUTS: DIN, SCLK,

CCSS, SSHHDDNN

DIGITAL OUTPUTS: DOUT, SSTRB (VL = 2.7V to 3.6V)

DIGITAL OUTPUTS: DOUT, SSTRB (VL = 4.75V to 5.25V)

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface

6 _______________________________________________________________________________________

TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V, VSS= 0V or -5V ±5%, TA= T

MIN

to T

MAX

, unless otherwise noted.)

Note 1: Tested at V

DD

= 5.0V; VSS= 0V; unipolar-input mode.

Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (V

REF

= 4.096V), offset nulled.

Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V

SS

to VDD.

Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;

REFADJ = GND. Shutdown supply current is also dependent on V

IH

(Figure 12c).

Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are

active (CS low), the logic supply current depends on f

SCLK

, and on the static and capacitive load at DOUT and SSTRB.

Note 11: Measured at V

SUPPLY

+ 5% and V

SUPPLY

- 5% only.

Note 12: Measured at VL = 2.7V and VL = 3.6V.

ns100t

CSS

External-clock mode only, C

LOAD

= 100pF ns

CS to SCLK Rise Setup

240

C

LOAD

= 100pF ns

ns20 240

ns0

t

DO

SCLK Fall to Output Data Valid

t

CSH

CONDITIONS

CS to SCLK Rise Hold

240t

DV

CS Fall to Output Enable

C

LOAD

= 100pF ns240t

TR

CS Rise to Output Disable

t

SDV

CS Fall to SSTRB Output Enable
(Note 6)

External-clock mode only, C

LOAD

= 100pF ns240t

STR

CS Rise to SSTRB Output
Disable (Note 6)

Internal-clock mode only ns0t

SCK

SSTRB Rise to SCLK Rise
(Note 6)

ns200t

CH

SCLK Pulse Width High

ns200t

CL

SCLK Pulse Width Low

C

LOAD

= 100pF ns240t

SSTRB

SCLK Fall to SSTRB

C

LOAD

= 100pF

ns0t

DH

DIN to SCLK Hold

µs1.5t

ACQ

Acquisition Time

ns100t

DS

DIN to SCLK Setup

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

_______________________________________________________________________________________

7

1.0

2.0

1.8

1.6

1.4

1.2

4.5

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1202 TOC01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

5.34.7 5.1 5.54.9

MAX1202

MAX1203

0

-60

SUPPLY CURRENT

vs. TEMPERATURE

0.5

MAX1202 TOC02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

100

2.0

1.0

1.5

-20 60 140

3.0

2.5

20

MAX1202

MAX1203

6

5

0

-60

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

4

MAX1202 TOC03

TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT (µA)

60

2

1

-20 20

3

100

140

REFADJ = GND
FULL POWER-DOWN

0.8

0.6

0.7

0.5

0

-60

INTEGRAL NONLINEARITY

vs. TEMPERATURE

0.4

MAX1202 TOC04

TEMPERATURE (°C)

INL (LSB)

60

0.2

0.1

-20 20

0.3

100

140

3

2

-3

-60

CHANNEL-TO-CHANNEL OFFSET-ERROR

MATCHING vs. TEMPERATURE

1

MAX1202 TOC07

TEMPERATURE (°C)

OFFSET-ERROR MATCHING (LSB)

60

-1

-2

-20 20

0

100

140

2.0

1.0

1.5

0.5

-2.0

-60

OFFSET ERROR

vs. TEMPERATURE

0

MAX1202 TOC05

TEMPERATURE (°C)

OFFSET ERROR (LSB)

60

-1.0

-1.5

-20 20

-0.5

100

140

5

3

4

1

2

0

-5

-60

GAIN ERROR

vs. TEMPERATURE

-1

MAX1202 TOC06

TEMPERATURE (°C)

GAIN ERROR (LSB)

60

-3

-4

-20 20

-2

100

140

DIFFERENTIAL

SINGLE-ENDED

5

3

4

1

2

0

-5

-60

CHANNEL-TO-CHANNEL GAIN-ERROR

MATCHING vs. TEMPERATURE

-1

MAX1202 TOC08

TEMPERATURE (°C)

GAIN-ERROR MATCHING (LSB)

60

-3

-4

-20 20

-2

100

140

__________________________________________Typical Operating Characteristics

(VDD= 5V ±5%; VL = 2.7V to 3.6V; VSS= 0V; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle

(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin; TA = +25°C;

unless otherwise noted.)

______________________________________________________________Pin Description

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface

8 _______________________________________________________________________________________

-1.0

-0.8

-0.6

-0.4

0

INTEGRAL NONLINEARITY

vs. DIGITAL

1.0

0.4

0.6

0.8

MAX1202 TOC09

DIGITAL CODE

INL (LSB)

3000

0

-0.2

750 1500 2250

0.2

3750

4500

-120
0

FFT PLOT

20

MAX1202 TOC10

FREQUENCY (kHz)

AMPLITUDE (dB)

-20

-40

-60

-80

-100

33.25

0

66.50

VSS = -5V

____________________________Typical Operating Characteristics (continued)

(VDD= 5V ±5%; VL = 2.7V to 3.6V; VSS= 0V; f

SCLK

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle

(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V

REF

= 4.096V applied to REF pin; TA = +25°C;

unless otherwise noted.)

Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS
is high (external clock mode).

SSTRB16

Serial-Data Input. Data is clocked in at SCLK’s rising edge.DIN17
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

CS

18

Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

SCLK19

Positive Supply Voltage, +5V ±5%V

DD

20

Input to the Reference-Buffer Amplifier. Tie REFADJ to V

DD

to disable the reference-buffer amplifier.REFADJ12

Ground; IN- Input for Single-Ended ConversionsGND13
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of

the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.

VL14

Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

DOUT15

Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the refer­ence buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal buffer by pulling REFADJ to V

DD.

REF11

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to V

DD

puts the
reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference­buffer amplifier in external compensation mode.

SHDN

10

PIN

Negative Supply Voltage. Tie VSSto -5V ±5% or to GND.V

SS

9

Sampling Analog InputsCH0–CH71–8

FUNCTIONNAME