Maxim MAX1200BCMH, MAX1200AEMH, MAX1200ACMH, MAX1200BEMH Datasheet

General Description

The MAX1200 16-bit, monolithic, analog-to-digital con­verter (ADC) is capable of conversion rates up to
1Msps. This CMOS integrated circuit uses a fully differ­ential, pipelined architecture with digital error correction
and a short self-calibration to ensure 16-bit linearity at
full sample rates. An on-chip track/hold (T/H) maintains
superb dynamic performance up to the Nyquist frequen­cy. The MAX1200 operates from a single +5V supply.

The fully differential inputs allow an input swing of
±V

REF

. The reference is also differential with the posi­tive reference (RFPF) typically connected to +4.096V
and the negative reference (RFNF) connected to ana­log ground. Additional sensing pins (RFPS, RFNS) are
provided to compensate for any resistive divider action
that may occur. A single-ended input is also possible
using two operational amplifiers.

Power dissipation is typically only 273mW at +5V, at a
sampling rate of 1Msps. The device employs a CMOS­compatible, 16-bit parallel, two’s complement output
data format. For a higher sampling speed (up to

2.2Msps) but lower resolution (14-bit), select the
MAX1201, a pin-compatible version of the MAX1200.

The MAX1200 is available in an MQFP package and
operates over the commercial (0°C to +70°C) and
extended-industrial (-40°C to +85°C) temperature
ranges.

Applications

High-Resolution Imaging
Communications
Scanners
Data Acquisition
Instrumentation

Features

♦ Monolithic 16-Bit, 1Msps A/D Converter
♦ Single +5V Supply
♦ ±V

REF

Differential Input Voltage Range

♦ 87dB SNR for f

IN

= 100kHz

♦ 91dB SFDR for fIN= 100kHz
♦ 273mW Low-Power Dissipation
♦ ±0.5LSB Differential Nonlinearity Error
♦ Three-State, Two’s Complement Output Data
♦ On-Demand Self-Calibration
♦ Pin-Compatible 14-Bit Versions Available

(1Msps MAX1205, 2.2Msps MAX1201)

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

________________________________________________________________

Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

OE
DAV
CLK
DV

DD

DGND
DGND
DV

DD

TEST1
D0
D1
D2

ST_CAL

AGND

AV

DD

AGND
AGND

AV

DD

DOR

D15
D14
D13
D12

1
2
3
4
5
6
7
8

9
10
11

1213141516171819202122

4443424140393837363534

33
32
31
30
29
28
27
26
25
24
23

D11

D10

D9

D8

DRV

DD

DGND

D7D6D5D4D3

END_CAL

INN

N.C.

N.C.

INP

RFNS

RFNF

RFPS

RFPFCMTEST0

TOP VIEW

MQFP

MAX1200

19-1413; Rev 0; 12/98

Ordering Information

Pin Configuration

EVALUATION KIT

AVAILABLE

44 MQFP

44 MQFP

PIN-PACKAGETEMP. RANGE

0°C to +70°C
0°C to +70°CMAX1200BCMH

MAX1200ACMH

PART

—

±0.5

DNL

(LSB)

44 MQFP-40°C to +85°CMAX1200BEMH —

44 MQFP-40°C to +85°CMAX1200AEMH ±0.5

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= +5V ±5%, DV

DD

= DRV

DD

= +3.3V, V

RFPS

= +4.096V, V

RFNS

= AGND, VCM= +2.048V, VIN= -0.5dBFS, f

CLK

= 2.048MHz;

digital output load ≤ 20pF; TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto AGND, DGND..........................................................+7V

DV

DD

to DGND, AGND..........................................................+7V

DRV

DD

to DGND, AGND .......................................................+7V

INP, INN, RFPF, RFPS,

RFNF, RFNS, CLK, CM..........(AGND - 0.3V) to (AV

DD

+ 0.3V)

Digital Inputs to DGND............................-0.3V to (DV

DD

+ 0.3V)

Digital Output (DAV) to DGND..............-0.3V to (DRV

DD

+ 0.3V)

Other Digital Outputs to DGND.............-0.3V to (DRV

DD

+ 0.3V)

Continuous Power Dissipation (TA= +70°C)

44-Pin MQFP (derate 11.11mW/°C above +70°C).......889mW

Operating Temperature Ranges (T

A

)

MAX1200_CMH ..................................................0°C to +70°C

MAX1200_EMH................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

To full-scale step (0.006%)

ns

3

t

AD

Aperture Delay

ns

450

t

OVR

ns

125

t

ACQ

Acquisition Time
Overvoltage Recovery Time

MHz

3.3
MHz

78

Small-Signal Bandwidth

MAX1200A

After calibration, guaranteed for
MAX1200A only

f

SAMPLE

=

f

CLK

/

2

LSB

-1 ±0.5 +1

DNLDifferential Nonlinearity

LSB

±3.5

INL

Bits

16

RES

Resolution
(No missing codes; Note 5)

Integral Nonlinearity

f

SAMPLE

Cycles

4

Conversion Time
(Pipeline Delay/Latency)

Msps

1.024

f

SAMPLE

Maximum Sampling Rate

%FSR

-0.2 ±0.003 +0.2

Offset Error

%FSR

-5 -3 5

Gain Error

µV

RMS

75

Input-Referred Noise

Differential

Single-ended

Per side in track mode

CONDITIONS

±4.096

V

4.096

V

IN

Input Voltage Range (Note 2)

Ω

700 1000

R

REF

Reference Input Resistance

kΩ

55

R

I

Input Resistance (Note 3)

pF

21

C

I

Input Capacitance

V

4.096 4.5

V

REF

Reference Voltage (Note 4)

UNITSMIN TYP MAXSYMBOLPARAMETER

Full-Power Bandwidth

ps

RMS

5

t

AJ

Aperture Jitter

ANALOG INPUT

EXTERNAL REFERENCE

TRANSFER CHARACTERISTICS

DYNAMIC SPECIFICATIONS (Note 6)

MAX1200B

±0.6

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V ±5%, DV

DD

= DRV

DD

= +3.3V, V

RFPS

= +4.096V, V

RFNS

= AGND, VCM= +2.048V, VIN= -0.5dBFS, f

CLK

= 2.048MHz;

digital output load ≤ 20pF; TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

dB

55Gain

55Offset

PSRRPower-Supply Rejection Ratio

sec0.1Warm-Up Time

mW273 377PDSSPower Dissipation

10pF loads on D0–D15 and DAV mA0.1 0.6I(DRVDD)Output Drive Supply Current

V3DV

DD

DRV

DD

Output Drive Supply Voltage

V4.75 5 5.25AV

DD

Analog Supply Voltage

V3 5.25DV

DD

Digital Supply Voltage

mA0.4 1.2I(DVDD)Digital Supply Current

V

RFPS

= 4.096V,

V

RFNS

= AGND

V

RFPS

= 4.096V,

V

RFNS

= AGND

V

RFPS

= 4.096V,

V

RFNS

= AGND

V

RFPS

= 4.096V,

V

RFNS

= AGND

88

Spurious-Free Dynamic Range
(Note 5)

89

SFDR dB

84 91

81

82

dB

-87 -82

THD

Total Harmonic Distortion
(Note 5)

-86

-85

dB

80 84

SINAD

Signal-to-Noise Ratio plus
Distortion (Note 5)

83

84

dB

83 87

SNR

Signal-to-Noise Ratio
(Note 5)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

mA51 70I(AVDD)Analog Supply Current

V

RFPS

= 3.5V,

V

RFNS

= 1.5V

80

81

78 83

V

RFPS

= 3.5V,

V

RFNS

= 1.5V

90

91

85 92

V

RFPS

= 3.5V,

V

RFNS

= 1.5V

-90 -84

-89

-88

V

RFPS

= 3.5V,

V

RFNS

= 1.5V

79.5

80.5

77 82

POWER REQUIREMENTS

fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz
fIN= 99.5kHz
fIN= 300.5kHz
fIN= 504.5kHz

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

4 _______________________________________________________________________________________

DIGITAL INPUT AND OUTPUT CHARACTERISTICS

(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation.
Note 2: For unipolar mode, the analog input voltage, V

INP

, must be within 0 and V

REF

, V

INN

= V

CM

/ 2; where V

REF

= V

RFPS

- V

RFNS

.

For differential mode, the analog input voltages V

INP

and V

INN

must be within 0 and V

REF

; where V

REF

= V

RFPS

- V

RFNS

. The

common-mode voltage of the inputs INP and INN is V

CM

=

(V

RFPS

+

V

RFNS

) / 2.

Note 3: RIvaries inversely with sample rate.
Note 4: Minimum and maximum parameters are not tested. Guaranteed by design.
Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Guaranteed by design.
Note 6: All AC specifications are shown for the differential mode.

I

SOURCE

= 200µA

VIN= 0 or DV

DD

CONDITIONS

4Input Capacitance

DVDD- 0.8V

IH

0.8V

IL

Input LOW Voltage
Input HIGH Voltage

DV

DD

DV

DD

- 0.4 - 0.03

V

OH

Output High Voltage

0.8V

CLK

CLK Input LOW Voltage

AVDD- 0.8V

CLK

CLK Input HIGH Voltage

9C

CLK

CLK Input Capacitance

±0.1 ±10I

IN

Digital Input Current

MIN TYP MAX

SYMBOLPARAMETER

I

SINK

= 1.6mA 70 400V

OL

Output Low Voltage

±0.1 ±10I

LEAKAGE

Three-State Leakage Current

3.5C

OUT

Three-State Output Capacitance

mV

µA

pF

pF

V

V

V

V
V

pF

µA

UNITS

VIN= 0 or V

DD

±1 ±10I

CLK

CLK Input Current µA

CL= 20pF

CONDITIONS

ns187 244 301t

CH

Clock HIGH Time

ns488t

CLK

ns4 / f

SAMPLE

t

CONV

Conversion Time
Clock Period

ns16 75t

REL

Bus Relinquish Time

ns16 75t

AC

Data Access Time

ns187 244 301t

CL

Clock LOW Time

ns70 150t

OD

Output Delay

ns1 / f

CLK

t

DAV

DAV Pulse Width

ns65 145t

S

CLK-to-DAV Rising Edge

UNITSMIN TYP MAXSYMBOLPARAMETER

ST_CAL = DV

DD

f

CLK

Cycles

17,400t

CAL

Calibration Time

nst

CLK

/ 2t

ACQ

Acquisition Time

TIMING CHARACTERISTICS (Figures 7, 8, 9)

(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, f

CLK

= 2.048MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

T

A

= +25°C.) (Note 1)

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

_______________________________________________________________________________________

5

__________________________________________Typical Operating Characteristics__________________________________________Typical Operating Characteristics

(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V

RFPS

= +4.096V, V

RFNS

= AGND; VCM= +2.048V, differential input, f

CLK

= 2.048MHz,

calibrated, T

A

= +25°C, unless otherwise noted.)

-5

5

-3

-4

-2

-1

2
1
0

3

4

-32768 -16384 0 16384 32768

INTEGRAL NONLINEARITY vs.

TWO’S COMPLEMENT OUTPUT CODE

MAX1200 toc01

TWO’S COMPLEMENT OUTPUT CODE

INL (LSB)

-1.0

0

-0.25

-0.50

-0.75

0.25

0.75

0.50

1.0

-32,768

-16,384 0 16,384 32,768

DIFFERENTIAL NONLINEARITY vs.

TWO’S COMPLEMENT OUTPUT CODE

MAX1200toc02

TWO’S COMPLEMENT OUTPUT CODE

DNL (LSB)

30

50
40

80
70
60

110
100

90

120

-80 -50 -40-70 -60 -30 -20 -10 0

SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT AMPLITUDE (f

IN

= 99.5kHz)

MAX1200toc03

INPUT AMPLITUDE (dBFS)

SFDR (dB)

(dBFS)

(dBc)

68

72

74

76

78

80

82

84

86

1 10 100 1000

SIGNAL-TO-NOISE RATIO PLUS

DISTORTION vs. INPUT FREQUENCY

MAX1200 toc04

INPUT FREQUENCY (kHz)

SINAD (dB)

70

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

-90

-88

-86

-84

-82

-80

-78

-76

-74

1 10 100 1000

TOTAL HARMONIC DISTORTION

vs. INPUT FREQUENCY

MAX1200 toc05

INPUT FREQUENCY (kHz)

THD (dB)

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

-150

-105

-120

-135

-90

-75

-60

-45

-30

-15

0

0 200 400 600

TYPICAL FFT, f

IN

= 504.5MHz,

8192 VALUE RECORD

MAX1200 toc09

FREQUENCY (kHz)

AMPLITUDE (dBFS)

65

70

80

75

85

90

1 10 100 1000

SIGNAL-TO-NOISE RATIO

vs. INPUT FREQUENCY

vsMAX1200 toc06

INPUT FREQUENCY (kHz)

SNR (dB)

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

80

81

83

82

84

85

0.1 1 10

SIGNAL-TO-NOISE RATIO PLUS DISTORTION

vs. SAMPLING RATE (f

IN

= 99.5kHz)

MAX1200 toc07

SAMPLE RATE (Msps)

SINAD (dB)

-150

-105

-120

-135

-90

-75

-60

-45

-30

-15

0

0 200 400 600

TYPICAL FFT, f

IN

= 99.5kHz,

8192 VALUE RECORD

MAX1200 toc08

FREQUENCY (kHz)

AMPLITUDE (dBFS)

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

6 _______________________________________________________________________________________

-150

-105

-120

-135

-90

-75

-60

-45

-30

-15

0

0 200 400 600

TYPICAL FFT, f

IN

= 504.5MHz,

8192 VALUE RECORD

MAX1200 toc19

FREQUENCY (kHz)

AMPLITUDE (dBFS)

65

70

80

75

85

60

1 10 100 1000

SIGNAL-TO-NOISE RATIO

vs. INPUT FREQUENCY

MAX1200 toc16

INPUT FREQUENCY (kHz)

SNR (dB)

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

79

78

80

82

81

83

84

0.1 1 10

SIGNAL-TO-NOISE RATIO PLUS DISTORTION

vs. SAMPLING RATE (f

IN

= 99.5kHz)

MAX1200 toc17

SAMPLE RATE (Msps)

SINAD (dB)

-150

-105

-120

-135

-90

-75

-60

-45

-30

-15

0

0 200 400 600

TYPICAL FFT, f

IN

= 99.5kHz,

8192 VALUE RECORD

MAX1200 toc18

FREQUENCY (kHz)

AMPLITUDE (dBFS)

Typical Operating Characteristics

(AVDD= +5V ±5%, DVDD= DRVDD= +3.3V, V

RFPS

= +3.5V, V

RFNS

= +1.5V; VCM= +2.5V, differential input, f

CLK

= 2.048MHz,

calibrated, T

A

= +25°C, unless otherwise noted.)

-2.5

-1.5

-2.0

-0.5

-1.0

0.5
0

1.0

2.0

1.5

2.5

-32,768 -16,384 0 16,384 32,768

INTEGRAL NONLINEARITY vs.

TWO’S COMPLEMENT OUTPUT CODE

MAX1200 toc11

TWO’S COMPLEMENT OUTPUT CODE

INL (LSB)

-1.0

-0.6

-0.8

-0.2

-0.4

0.2
0

0.4

0.8

0.6

1.0

-32,768 -16,384 0 16,384 32,768

DIFFERENTIAL NONLINEARITY vs.

TWO’S COMPLEMENT OUTPUT CODE

MAX1200 toc12

TWO’S COMPLEMENT OUTPUT CODE

DNL (LSB)

0

20
10

40
30

100

60
50

70

80

90

110

-90 -70 -60 -50-80 -40 -20-30 -10 0

MAX1200 toc13

INPUT AMPLITUDE (dBFS)

SFDR (dB)

SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT AMPLITUDE (f

IN

= 99.5kHz)

(dBFS)

(dB)

74

76

80
78

82

84

62

64

68
66

70

72

1 10 100 1000

SIGNAL-TO-NOISE RATIO PLUS DISTORTION

vs. INPUT FREQUENCY

MAX1200 toc14

INPUT FREQUENCY (kHz)

SINAD (dB)

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

-87

-85

-83

-81

-79

-77

-91

-93

-89

1 10 100 1000

TOTAL HARMONIC DISTORTION

vs. INPUT FREQUENCY

MAX1200 TOC15

INPUT FREQUENCY (kHz)

THD (dB)

A

IN

= -0.5dBFS

A

IN

= -6dBFS

A

IN

= -20dBFS

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

_______________________________________________________________________________________ 7

Pin Description

12

18

17, 28, 29

16

1

PIN

15

8

7

3, 6

2, 4, 5

11

10

9

14

NAME

20

FUNCTION

19

13

D11 Bit 11

D7 Bit 7

DGND Digital Ground

DRV

DD

Digital Power Supply for the Output Drivers. +3V to +5.25V, DRVDD≤ DV

DD

D8 Bit 8

D9

ST_CAL

Digital Input to Start Calibration.
ST_CAL = 0: Normal conversion mode.
ST_CAL = 1: Start self-calibration.

Bit 9

D5 Bit 5

D6 Bit 6

D10

D15 Bit 15 (MSB)

Bit 10

DOR Data Out-of-Range Bit

AV

DD

Analog Power Supply, +5V ±5%

AGND Analog Ground

D12 Bit 12

D13 Bit 13

D14 Bit 14

21

23

22

D4 Bit 4

D2 Bit 2

D3 Bit 3

24

26

25

D1 Bit 1

TEST1

Test Pin 1. Do not connect.

D0 Bit 0 (LSB)

27, 30

32

31

DV

DD

Digital Power Supply, +3V to +5.25V

DAV

Data Valid Clock. This clock can be used to transfer the data to a memory or any other data
acquisition system.

CLK Input Clock. Receives power from AVDDto reduce jitter.

33

35

34

OE Output Enable. OE = 0: D0–D15 and DOR are high impedance. OE = 1: All bits are active.

CM

Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference
voltages.

TEST0

Test Pin 0. Do not connect.

36

38

37

RFPF Positive Reference Voltage, Force Input

RFNF Negative Reference Voltage, Force Input

RFPS Positive Reference Voltage, Sense Input

39

41, 42

40

RFNS Negative Reference Voltage, Sense Input

N.C. Not Connected. No internal connection.

INP Positive Input Voltage

43

44

INN Negative Input Voltage

END_CAL

Digital Output for End of Calibration.
END_CAL = 0: Calibration in progress.
END_CAL = 1: Normal conversion mode.

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

8 _______________________________________________________________________________________

Detailed Description

Converter Operation

The MAX1200 is a 16-bit, monolithic analog-to-digital
converter (ADC) capable of conversion rates up to
1Msps. It uses a multistage, fully differential, pipelined
architecture with digital error correction and self-cali­bration to provide typically 91dB spurious-free dynamic
range at a 1Msps sampling rate. It also provides excel­lent SNR and THD performance up to the Nyquist fre­quency. This makes the device suitable for applications
such as data acquisition, high-resolution imaging,
scanners, digital communication, and instrumentation.

Figure 1 shows the simplified, internal structure of the
ADC. A switched-capacitor, pipelined architecture is
used to digitize the signal at a high throughput rate.
The first four stages of the pipeline use a low-resolution
quantizer to approximate the input signal. The multiply­ing digital-to-analog converter (MDAC) stage is used to
subtract the quantized analog signal from the input.
The residue is then amplified with a fixed gain and
passed on to the next stage. The accuracy of the con­verter is improved by a digital calibration algorithm
which corrects for mismatches between the capacitors
in the switched-capacitor MDAC. Note that the pipeline

introduces latency of four sampling periods between
the input being sampled and the output appearing at
D15–D0.

While the device can handle both single-ended or dif­ferential inputs (see the

Requirements for Reference

and Analog Signal Inputs

section), the latter mode of
operation will guarantee best THD and SFDR perfor­mance. The differential input provides the following
advantages compared to a single-ended operation:

• Twice as much signal input span

• Common-mode noise immunity

• Virtual elimination of the even-order harmonics

• Less stringent requirements on the input signal pro-

cessing amplifiers

Requirements for Reference

and Analog Signal Inputs

Fully differential switched-capacitor circuits (SC) are used
for both the reference and analog inputs (Figure 2). This
allows either single-ended or differential signals to be
used in the reference and/or analog signal paths. The
signal voltage on these pins (INP, INN, RFP_, RFN_)
should never exceed the analog supply rail, AVDD, nor
fall below ground.

STAGE1

DAV

INP

CM AV

DD

RFN_RFP_ AGND

INN

CLK

DV

DD

DGND

DRV

DD

ST_CAL

DOR

D15–D0

ADC

ADC MDAC

8X

S/H

STAGE2 STAGE3 STAGE4

CORRECTION AND

CALIBRATION LOGIC

END_CAL

OE

OUTPUT DRIVERS

CLOCK

GENERATOR

MAX1200

Figure 1. Internal Functional Diagram

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

_______________________________________________________________________________________ 9

Choice of Reference

It is important to choose a low-noise reference such as
the MAX6341, which can provide both excellent load
regulation and low temperature drift. The equivalent
input circuit for the reference pins is shown in Figure 3.
Note that the reference pins drive approximately 1kΩ of
resistance on-chip. They also drive a switched capaci­tor of 21pF. To meet the dynamic performance, the ref­erence voltage is required to settle to 0.0015% within
one clock cycle. Carefully choose an appropriate driv­ing circuit (Figure 4). The capacitors at the reference
pins (RFPF, RFNF) provide the dynamic charge
required during each clock cycle, while the op amps
ensure accuracy of the reference signals. These
capacitors must have low dielectric-absorption charac­teristics, such as polystyrene or teflon capacitors.

The reference pins can be connected to either single­ended or differential voltages within the specified maxi­mum levels. Typically the positive reference pin (RFPF)
would be driven to +4.096V, and the negative refer­ence pin (RFNF) connected to analog ground for best
SNR performance. If THD performance is more impor­tant to the application than signal-to-noise ratio, choose
a lower level, differential voltage such as V

RFPS

=

+3.5V and V

RFNS

= +1.5V.

There are sense pins, RFPS and RFNS, which can be
used with external amplifiers to compensate for any
resistive drop on these lines, internal or external to the
chip. Ensure a correct reference voltage by using prop­er Kelvin connections at the sense pins.

Common-Mode Voltage

The switched-capacitor input circuit at the analog input
allows signals between AGND and the analog power
supply. Since the common-mode voltage has a strong

influence on the performance of the ADC, the best
results are obtained by choosing V

CM

= (V

RFPS

+

V

RFNS

) / 2. This can be achieved by using a resistive
divider between the two reference potentials. Figure 4
shows a typical driving circuit for good dynamic perfor­mance.

RFPF

INP

INN

RFPF

CM

CM

RFNF

Figure 2. Simplified MDAC Architecture

RFPF

RFPS

RFNF

RFNS

Figure 3. Equivalent Input at the Reference Pins. The sense
pins should not draw any DC current.

V

RFP

= +4.096V

V

RFN

= 0

5k

5k

MAX410

CHIP BOUNDARY

CM

RFNS

RFNF

RFPS

RFPF

MAX410

MAX410

Figure 4. Drive Circuit for Reference Pins and Common-Mode
Pin

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

10 ______________________________________________________________________________________

Analog Signal Conditioning

For single-ended inputs, the negative analog input pin
(INN) is connected to the common-mode voltage pin
(CM) and the positive analog input pin (INP) is connect­ed to the input.

To take full advantage of the ADC’s superior AC perform­ance up to the Nyquist frequency, drive the chip with
differential signals. In communication systems the sig­nals may inherently be available in differential mode;
however medical and/or other applications may only
provide single-ended inputs. In this case, convert the
single-ended signals into differential ones by using the
circuit recommended in Figure 5. Use low-noise, wide­band amplifiers, such as the MAX4108, to maintain the
signal purity over the full-power bandwidth of the
MAX1200 input.

Lowpass or bandpass signals may be required to
improve the signal-to-noise and distortion of the incom­ing signal. For low-frequency signals (<100kHz), active
filters may be used. For higher frequencies, passive fil­ters are more convenient.

Single-Ended to Differential

Conversion Using Transformers

An alternative single-ended to differential-ended con­version method is a balun transformer such as the
CTX03-13675 from Coiltronics. An important benefit of
these transformers is their ability to level-shift single­ended signals referred to ground on the primary side to
optimum common-mode voltages on the secondary
side. At frequencies below 20kHz the transformer core
begins to saturate, causing odd-order harmonics.

Clock Source Requirements

Pipelined ADCs typically need a 50% duty cycle clock.
To avoid this constraint, the MAX1200 provides a
divide-by-two circuit to relax this requirement. The
clock generator should be chosen commensurate with
the frequency range, amplitude, and slew rate of the
signal source. If the slew rate of the input signal is
small, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible signal-to-noise
ratio (SNR) due completely to clock jitter is given by:

For example, if fINis 500kHz and σ

JITTER

is 10ps RMS,
then the SNR limit due to jitter is about 90dB. Generating
such a clock source requires a low-noise comparator and
a low-phase-noise signal generator. The clock circuit
shown in Figure 6 is a possible solution.

SNR

1

2

MAX

IN JITTER

f

=

⋅

⋅⋅πσ

MAX4108

INP

INN

CM

V-

V+

IN

CM

V+

V-

MAX4108

Figure 5. A simple circuit generates differential signals from a
single-ended input referred to analog ground. The common­mode voltage at INP and INN is the same as CM.

MAX961

CLK

V+

V+

0.1µF

0.1µF

0.1µF

1k

1k

CLK_IN

5k

Figure 6. Clock Generation Circuit Using Low-Noise Comparator

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

______________________________________________________________________________________ 11

Calibration Procedure

Since the MAX1200 is based on a pipelined architec­ture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue amplified by the SC gain stage. This residue is
then passed on to the next stage.

The accuracy of the MAX1200 is limited by the preci­sion of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conver­sion of the input signal.

During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
initiated by a positive pulse with a minimum width of
four clock cycles, but not longer than about 17,400
clock cycles (Figure 8).

The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indi­cating that the calibration procedure is complete), the
ADC is ready for conversion.

Once calibrated, the MAX1200 is insensitive to small
changes (±5%) in power-supply voltage or tempera­ture. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.

Two’s Complement Output

The MAX1200 outputs data in two’s complement for­mat. Table 1 shows how to convert the various full­scale inputs into their two’s complement output codes.

Applications Information

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti­zation error (residual error). The ideal, theoretical mini­mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):

SNR

(MAX)

= (6.02 · N + 1.76)dB

In reality, there are other noise sources besides quanti­zation noise including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise which
includes all spectral components minus the fundamen­tal, the first nine harmonics, and the DC offset.

t

S

t

CH

t

CL

N

CLK

AIN

SAMPLE

CLOCK

DAV

N-3 N-2 N-1 N N+1

D0–D15

N+1

N+2

N+3

N+4

N+5

t

OD

Figure 8. Timing for Start and End of Calibration

Figure 7. Main Timing Diagram

Z

Z = HIGH IMPEDANCE (THREE-STATED)

Z

DOR

D0–D15

OE

t

AC

t

REL

Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)

CLK

ST_CAL

END_CAL

MIN 4 t

CLK

~17,400 CLK CYCLES

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

12 ______________________________________________________________________________________

Table 1. Two’s Complement Output Codes

Signal-to-Noise

Plus Distortion (SINAD)

SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to all other ADC output signals:

SINAD (dB) = 20log [Signal

RMS

/ (Noise +

Distortion)

RMS

]

Effective Number of Bits (ENOB)

ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC, the
effective number of bits can be calculated as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first nine har­monics of the input signal to the fundamental itself. This
is expressed as:

where V1is the fundamental amplitude, and V2through
V9are the amplitudes of the 2nd through 9th-order har­monics.

Spurious-Free

Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.

Grounding and Power-Supply Decoupling

Grounding and power-supply decoupling strongly influ­ence the performance of the MAX1200. At 16-bit reso­lution, unwanted digital crosstalk may couple through
the input, reference, power supply, and ground con­nections; this adversely affects the SNR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX1200.
Therefore, grounding and power-supply decoupling
guidelines should be closely followed.

First, a multilayer printed circuit board (PCB) with sepa­rate ground and power-supply planes is recommend­ed. Run high-speed signal traces directly above the
ground plane. Since the MAX1200 has separate analog
and digital ground buses (AGND and DGND respec­tively), the PCB should also have separate analog and
digital ground sections connected at only one point
(star ground). Digital signals should run above the digi­tal ground plane and analog signals should run above
the analog ground plane. Digital signals should be kept
far away from the sensitive analog inputs, reference
input senses, common-mode input, and clock input.

THD 20log

V

V

2

2

VV V

=

































+++⋅⋅⋅+

324

2

9

2

1

SCALE OFFSET BINARY ONE’S COMPLEMENT TWO’S COMPLEMENT

+FSR - 1LSB 1111 .... 1111 0111 .... 1111 0111 .... 1111

+3/4FSR 1110 .... 0000 0110 .... 0000 0110 .... 0000

+1/2FSR 1100 .... 0000 0100 .... 0000 0100 .... 0000

+1/4FSR 1010 .... 0000 0010 .... 0000 0010 .... 0000

+0 1000 .... 0000 0000 .... 0000 0000 .... 0000

-0 —— .... —— —— .... —— 1111 .... 1111

-1/4FSR 0110 .... 0000 1110 .... 0000 1101 .... 1111

-1/2FSR 0100 .... 0000 1100 .... 0000 1011 .... 1111

-3/4FSR 0010 .... 0000 1010 .... 0000 1001 .... 1111

-FSR +1LSB 0000 .... 0001 1000 .... 0001 1000 .... 0000

-FSR 0000 .... 0000 1000 .... 0000 —— .... ——

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

______________________________________________________________________________________ 13

The MAX1200 has three power-supply inputs: analog
VDD(AVDD), digital VDD(DVDD), and drive V

DD

(DRVDD). Each AVDD input should be decoupled with
parallel ceramic chip capacitors of values 0.1µF and

0.001µF, with these capacitors as close to the pin as
possible and with the shortest possible connection to
the ground plane. The DVDDpins should also have
separate 0.1µF capacitors again adjacent to their
respective pins, as should the DRVDDpin. Minimize the
digital load capacitance. However, if the total load
capacitance on each digital output exceeds 20pF, the
DRVDDdecoupling capacitor should be increased or,
preferably, digital buffers should be added.

The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PCB. Ferrite beads with additional
decoupling capacitors forming a pi network may
improve performance.

The analog power-supply input (AV

DD

) for the
MAX1200 is typically +5V while the digital supplies can
vary from +3V to +5V. Usually, DVDDand DRVDDpins

are connected to the same power supply. Note that the
DV

DD

supply voltage must be greater than or equal to
the DRVDDvoltage. For example, a digital +3.3V sup­ply could be connected to DRVDDwhile a cleaner +5V
supply is connected to DVDD, resulting in slightly
improved performance. Alternatively, the +3.3V supply
could be connected to both DRVDDand DVDD.
However, the +3.3V supply must not be connected to
DVDDwhile the +5V supply is connected to DRV

DD

(Table 2).

Table 2. Power-Supply Voltage
Combinations

Chip Information

TRANSISTOR COUNT: 56,577
SUBSTRATE CONNECTED TO AGND

AV

DD

(V)

DV

DD

(V)

DRV

DD

(V)

ALLOWED/

NOT ALLOWED

+5 +5 +5 Allowed
+5 +5 +3.3 Allowed
+5 +3.3 +3.3 Allowed

+5 +3.3 +5

Not

Allowed

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC

14 ______________________________________________________________________________________

Package Information

MQFP44.EPS

MAX1200

+5V Single-Supply, 1Msps, 16-Bit

Self-Calibrating ADC

______________________________________________________________________________________ 15

NOTES

MAX1200

+5V Single-Supply, 1Msps, 16-Bit
Self Calibrating ADC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

NOTES