MAXIM MAX1196 User Manual

General Description
The MAX1196 is a 3V, dual 8-bit analog-to-digital con­verter (ADC) featuring fully differential wideband track­and-hold (T/H) inputs, driving two ADCs. The MAX1196 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumenta­tion, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 87mW while delivering a typical signal-to-noise and dis­tortion (SINAD) of 48.4dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input ampli­fiers. The converters can also be operated with single­ended inputs. In addition to low operating power, the MAX1196 features a 3mA sleep mode as well as a
0.1µA power-down mode to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired for applications requiring increased accuracy or a different input voltage range.
The MAX1196 features parallel, multiplexed, CMOS­compatible three-state outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1196 is available in a 7mm × 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.
Pin-compatible, nonmultiplexed higher speed versions of the MAX1196 are also available. Refer to the MAX1198 data sheet for 100Msps, the MAX1197 data sheet for 60Msps, and the MAX1195 data sheet for 40Msps.
For a 10-bit, pin-compatible upgrade, refer to the MAX1186 data sheet. With the N.C. pins of the MAX1196 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1186.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Features
Single 2.7V to 3.6V Operation
Excellent Dynamic Performance
48.4dB/44.7dB SINAD at fIN= 20MHz/200MHz
68.9dB/53dBc SFDR at fIN= 20MHz/200MHz
-72dB Interchannel Crosstalk at fIN= 20MHz
Low Power
87mW (Normal Operation) 9mW (Sleep Mode)
0.3µW (Shutdown Mode)
0.05dB Gain and ±0.05° Phase MatchingWide ±1V
P-P
Differential Analog Input Voltage
Range
400MHz -3dB Input Bandwidth
On-Chip 2.048V Precision Bandgap Reference
User-Selectable Output Format—Two’s
Complement or Offset Binary
Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
________________________________________________________________ Maxim Integrated Products 1
N.C. N.C. OGND OV
DD
OV
DD
OGND A/B N.C. N.C. N.C. N.C. N.C.
COM
V
DD
GND INA+ INA-
V
DD
GND INB­INB+ GND
V
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP-EP
MAX1196
GND
V
DDVDD
GND
T/B
SLEEP
PD
OE
N.C.
N.C.
N.C.
N.C.
1314151617181920212223
24
4847464544434241403938
37
REFN
REFP
REFIN
REFOUT
D7A/B
D6A/B
D5A/B
D4A/B
D3A/B
D2A/B
D1A/B
D0A/B
Pin Configuration
Ordering Information
19-2600; Rev 0; 9/02
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed pad.
Functional Diagram appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1196ECM -40°C to +85°C 48 TQFP-EP*
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, TA= T
MIN
to T
MAX
,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND .............................................. -0.3V to +3.6V
OGND to GND...................................................... -0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (V
DD
+ 0.3V)
OE, PD, SLEEP, T/B,
D7A/B–D0A/B, A/B to OGND...............-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity INL fIN = 7.51MHz (Note 1)
±1 LSB
Differential Nonlinearity DNL
f
IN
= 7.51MHz, no missing codes
guaranteed (Note 1)
±1 LSB
Offset Error ±4
%FS
Gain Error ±4
%FS
Gain Temperature Coefficient
ppm/°C
ANALOG INPUT
Differential Input Voltage Range
V
DIFF
Differential or single-ended inputs
V
Common-Mode Input Voltage Range
V
CM
V
Input Resistance R
IN
Switched capacitor load
k
Input Capacitance C
IN
5pF
CONVERSION RATE
Maximum Clock Frequency f
CLK
40
MHz
CHA 5
Data Latency
CHB 5.5
Clock
Cycles
DYNAMIC CHARACTERISTICS (f
CLK
= 40MHz)
f
INA or B
= 2MHz at -1dB FS
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
Signal-to-Noise Ratio SNR
f
INA or B
= 101MHz at -1dB FS 48
dB
f
INA or B
= 2MHz at -1dB FS
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS 47
Signal-to-Noise and Distortion SINAD
f
INA or B
= 101MHz at -1dB FS 48
dB
SYMBOL
MIN TYP MAX
±0.3
±0.15
±100
±1.0
VDD / 2
± 0.2
140
48.7
48.7
47.5 48.5
48.6
48.7
48.4
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, TA= T
MIN
to T
MAX
,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
INA or B
= 2MHz at -1dB FS 69
f
INA or B
= 7.5MHz at -1dB FS 70
f
INA or B
= 20MHz at -1dB FS 60
Spurious-Free Dynamic Range SFDR
f
INA or B
= 101MHz at -1dB FS 65
dBc
f
INA or B
= 2MHz at -1dB FS -72
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS -75
Third-Harmonic Distortion HD3
f
INA or B
= 101MHz at -1dB FS -67
dBc
f
IN1(A or B)
= 1.997MHz at -7dB FS,
Intermodulation Distortion
( Fir st Fi ve Od d- Or der IM D s) ( N ote 2)
IMD
f
IN2(A or B)
= 2.046MHz at -7dB FS
-68
dBc
f
IN1(A or B)
= 1.997MHz at -7dB FS,
Third-Order Intermodulation Distortion (Note 2)
IM3
f
IN2(A or B)
= 2.046MHz at -7dB FS
dBc
f
INA or B
= 2MHz at -1dB FS -70
f
INA or B
= 7.5MHz at -1dB FS -69
f
INA or B
= 20MHz at -1dB FS -69 -57
Total Harmonic Distortion (First Four Harmonics)
THD
f
INA or B
= 101MHz at -1dB FS -63
dBc
Small-Signal Bandwidth Input at -20dB FS, differential inputs
Full-Power Bandwidth FPBW Input at -1dB FS, differential inputs
f
IN1(A or B)
= 106MHz at -1dB FS,
Gain Flatness (12MHz Spacing) (Note 3)
f
IN2(A or B)
= 118MHz at -1dB FS
dB
Aperture Delay t
AD
1ns
Aperture Jitter t
AJ
1dB SNR degradation at Nyquist 2
Overdrive Recovery Time For 1.5 × full-scale input 2 ns INTERNAL REFERENCE (REFIN = REFOUT through 10k resistor; REFP, REFN, and COM levels are generated internally.)
Reference Output Voltage
(Note 4)
V
Positive Reference Output Voltage
V
REFP
(Note 5)
V
Negative Reference Output Voltage
V
REFN
(Note 5)
V
Common-Mode Level V
COM
(Note 5)
V
Differential Reference Output Voltage Range
V
REF
V
REF
= V
REFP
- V
REFN
V
Reference Temperature Coefficient
TC
REF
V
REFOUT
68.9
-73.7
-73.2
500 MHz
400 MHz
0.05
2.048
±3%
2.012
0.988
VDD / 2
± 0.1
1.024
±3%
ps
RMS
±100 ppm/°C
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, TA= T
MIN
to T
MAX
,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
Positive Reference Output Voltage
V
REFP
(Note 5)
V
Negative Reference Output Voltage
V
REFN
(Note 5)
V
Common-Mode Level V
COM
(Note 5)
V
Differential Reference Output Voltage Range
V
REF
V
REF
= V
REFP
- V
REFN
V
REFIN Resistance R
REFIN
M
Maximum REFP, COM Source Current
5mA
Maximum REFP, C OM S i nk C ur r ent I
SINK
µA
Maximum REFN Source Current
µA
Maximum REFN Sink Current I
SINK
-5 mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
R
REFP
,
R
REFN
Measured between REFP and REFN 4 k
REFP, REFN, COM Input Capacitance
C
IN
15 pF
Differential Reference Input Voltage Range
V
REF
V
REF
= V
REFP
- V
REFN
V
COM Input Voltage Range V
COM
VDD / 2
V
REFP Input Voltage V
REFP
V
C OM
+
V
REFN Input Voltage V
REFN
V
COM
­V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8 ×
V
DD
Input High Threshold V
IH
PD, OE, SLEEP, T/B
0.8 ×
V
CLK
0.2 ×
Input Low Threshold V
IL
PD, OE, SLEEP, T/B
0.2 ×
V
SYMBOL
MIN TYP MAX UNITS
I
SOURCE
I
SOURCE
V
2.012
0.988
VDD / 2
±0.1
1.024
±2%
>50
-250
250
1.024
±10%
±5%
V
RE F
REF
/ 2
/ 2
OV
DD
V
DD
OV
DD
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, TA= T
MIN
to T
MAX
,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
Input Hysteresis V
HYST
V
I
IH
VIH = VDD = OV
DD
Input Leakage
I
IL
VIL = 0
µA
Input Capacitance C
IN
5pF
DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)
Output Voltage Low V
OL
I
SINK
= -200µA 0.2 V
Output Voltage High V
OH
I
SOURCE
= 200µA
OV
DD
-
0.2
V
Three-State Leakage Current I
LEAK
OE = OV
DD
±10 µA
Three-State Output Capacitance
C
OUT
OE = OV
DD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range V
DD
2.7 3 3.6 V
Output Supply Voltage Range OV
DD
1.7 3 3.6 V
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
29 36
Sleep mode 3
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
0.1 20 µA
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels (Note 6)
8mA
Sleep mode 3
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
310
µA
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
87 108
Sleep mode 9
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
0.3 60 µW
Offset, VDD ±5% ±3
Power-Supply Rejection PSRR
Gain, V
DD
±5% ±3
mV/V
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data Valid
t
DOA
CL = 20pF (Notes 1, 7) 6
ns
CLK Fall to CHB Output Data Valid
t
DOB
CL = 20pF (Notes 1, 7) 6
ns
Clock Rise/Fall to A/B Rise/Fall Time
t
DA/B
6ns
OE Fall to Output Enable Time
5ns
OE Rise to Output Disable Time
5ns
CLK Pulse Width High t
CH
Clock period: 25ns (Note 7)
12.5 ns
SYMBOL
MIN TYP MAX
t
ENABLE
t
DISABLE
0.15
±1.5
±20 ±20
8.25
8.25
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
6 _______________________________________________________________________________________
Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at f
IN1
and f
IN2
.
Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 6: Typical digital output current at f
INA&B
= 20MHz. For digital output currents vs. analog input frequency, see the Typical
Operating Characteristics.
Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to
50% of the data output level.
Note 8: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode. Note 9: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is
measured by calculating the power ratio of the fundamental of each channels FFT.
Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k resistor, V
IN
= 2V
P-P
(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, TA= T
MIN
to T
MAX
,
unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLK Pulse Width Low t
CL
Clock period: 25ns (Note 7)
12.5 ns
Wake-up from sleep mode 1
Wake-Up Time t
WAKE
Wake-up from shutdown mode (Note 8) 20
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f
INA or B
= 20MHz at -1dB FS (Note 9) -72 dB
Gain Matching f
INA or B
= 20MHz at -1dB FS (Note 10)
dB
Phase Matching f
INA or B
= 20MHz at -1dB FS (Note 11)
D eg r ees
±1.5
0.05
±0.05
MAX1196
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics
(VDD= OVDD= 3V, V
REFIN
= 2.048V, differential input at -1dB FS, f
CLK
= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 1.958036MHz
f
INB
= 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 1.958036MHz
f
INB
= 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 7.534287MHz
f
INB
= 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 7.534287MHz
f
INB
= 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 19.88798MHz
f
INB
= 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 19.88798MHz
f
INB
= 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHA
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-07
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 40.49374MHz
f
INB
= 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
FFT PLOT CHB
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-08
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
181612 144 6 8 102
-80
-70
-60
-50
-40
-30
-20
-10
0
-90 020
f
INA
f
CLK
= 40.0005678MHz
f
INA
= 40.49374MHz
f
INB
= 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING
f
INB
HD2
HD3
TWO-TONE IMD PLOT
(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)
MAX1196-09
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
4.54.03.0 3.51.5 2.0 2.51.0
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
0.5 5.0
f
CLK
= 40.001536MHz
f
INA
= 1.997147MHz
f
INB
= 2.045977MHz AIN = -7dB FS COHERENT SAMPLING
f
IN2
f
IN1
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