MAXIM MAX1196 User Manual

General Description

The MAX1196 is a 3V, dual 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1196 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.7V to 3.6V supply, consuming only 87mW while delivering a typical signal-to-noise and distortion (SINAD) of 48.4dB at an input frequency of 20MHz and a sampling rate of 40Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters can also be operated with singleended inputs. In addition to low operating power, the MAX1196 features a 3mA sleep mode as well as a

0.1µA power-down mode to conserve power during idle periods.

An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired for applications requiring increased accuracy or a different input voltage range.

The MAX1196 features parallel, multiplexed, CMOScompatible three-state outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing. The MAX1196 is available in a 7mm × 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40°C to +85°C) temperature range.

Pin-compatible, nonmultiplexed higher speed versions of the MAX1196 are also available. Refer to the MAX1198 data sheet for 100Msps, the MAX1197 data sheet for 60Msps, and the MAX1195 data sheet for 40Msps.

For a 10-bit, pin-compatible upgrade, refer to the MAX1186 data sheet. With the N.C. pins of the MAX1196 internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX1186.

Applications

Baseband I/Q Sampling

Multichannel IF Sampling

Ultrasound and Medical Imaging

Battery-Powered Instrumentation

WLAN, WWAN, WLL, MMDS Modems

Set-Top Boxes

VSAT Terminals

Features

♦ Single 2.7V to 3.6V Operation

♦ Excellent Dynamic Performance

48.4dB/44.7dB SINAD at fIN= 20MHz/200MHz

68.9dB/53dBc SFDR at fIN= 20MHz/200MHz

♦ -72dB Interchannel Crosstalk at fIN= 20MHz

♦ Low Power

87mW (Normal Operation) 9mW (Sleep Mode)

0.3µW (Shutdown Mode)

♦ 0.05dB Gain and ±0.05° Phase Matching ♦ Wide ±1V

P-P

Differential Analog Input Voltage

Range

♦ 400MHz -3dB Input Bandwidth

♦ On-Chip 2.048V Precision Bandgap Reference

♦ User-Selectable Output Format—Two’s

Complement or Offset Binary

♦ Pin-Compatible 8-Bit and 10-Bit Upgrades

Available

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

N.C. N.C. OGND OV

OGND A/B N.C. N.C. N.C. N.C. N.C.

COM

GND INA+ INA-

GND INBINB+ GND

CLK

TQFP-EP

MAX1196

GND

DDVDD

GND

T/B

SLEEP

N.C.

1314151617181920212223

4847464544434241403938

REFN

REFP

REFIN

REFOUT

D7A/B

D6A/B

D5A/B

D4A/B

D3A/B

D2A/B

D1A/B

D0A/B

Pin Configuration

Ordering Information

19-2600; Rev 0; 9/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad.

Functional Diagram appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1196ECM -40°C to +85°C 48 TQFP-EP*

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND .............................................. -0.3V to +3.6V

OGND to GND...................................................... -0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

REFIN, REFOUT, REFP, REFN, COM,

CLK to GND............................................-0.3V to (V

+ 0.3V)

OE, PD, SLEEP, T/B,

D7A/B–D0A/B, A/B to OGND...............-0.3V to (OV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

UNITS

DC ACCURACY

Resolution 8 Bits

Integral Nonlinearity INL fIN = 7.51MHz (Note 1)

±1 LSB

Differential Nonlinearity DNL

= 7.51MHz, no missing codes

guaranteed (Note 1)

±1 LSB

Offset Error ±4

%FS

Gain Error ±4

%FS

Gain Temperature Coefficient

ppm/°C

ANALOG INPUT

Differential Input Voltage Range

DIFF

Differential or single-ended inputs

Common-Mode Input Voltage Range

Input Resistance R

Switched capacitor load

kΩ

Input Capacitance C

5pF

CONVERSION RATE

Maximum Clock Frequency f

CLK

MHz

CHA 5

Data Latency

CHB 5.5

Clock

Cycles

DYNAMIC CHARACTERISTICS (f

CLK

= 40MHz)

INA or B

= 2MHz at -1dB FS

INA or B

= 7.5MHz at -1dB FS

INA or B

= 20MHz at -1dB FS

Signal-to-Noise Ratio SNR

INA or B

= 101MHz at -1dB FS 48

INA or B

= 2MHz at -1dB FS

INA or B

= 7.5MHz at -1dB FS

INA or B

= 20MHz at -1dB FS 47

Signal-to-Noise and Distortion SINAD

INA or B

= 101MHz at -1dB FS 48

SYMBOL

MIN TYP MAX

±0.3

±0.15

±100

±1.0

VDD / 2

± 0.2

140

48.7

47.5 48.5

48.6

48.7

48.4

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

INA or B

= 2MHz at -1dB FS 69

INA or B

= 7.5MHz at -1dB FS 70

INA or B

= 20MHz at -1dB FS 60

Spurious-Free Dynamic Range SFDR

INA or B

= 101MHz at -1dB FS 65

dBc

INA or B

= 2MHz at -1dB FS -72

INA or B

= 7.5MHz at -1dB FS

INA or B

= 20MHz at -1dB FS -75

Third-Harmonic Distortion HD3

INA or B

= 101MHz at -1dB FS -67

dBc

IN1(A or B)

= 1.997MHz at -7dB FS,

Intermodulation Distortion

( Fir st Fi ve Od d- Or der IM D s) ( N ote 2)

IMD

IN2(A or B)

= 2.046MHz at -7dB FS

-68

dBc

IN1(A or B)

= 1.997MHz at -7dB FS,

Third-Order Intermodulation Distortion (Note 2)

IM3

IN2(A or B)

= 2.046MHz at -7dB FS

dBc

INA or B

= 2MHz at -1dB FS -70

INA or B

= 7.5MHz at -1dB FS -69

INA or B

= 20MHz at -1dB FS -69 -57

Total Harmonic Distortion (First Four Harmonics)

THD

INA or B

= 101MHz at -1dB FS -63

dBc

Small-Signal Bandwidth Input at -20dB FS, differential inputs

Full-Power Bandwidth FPBW Input at -1dB FS, differential inputs

IN1(A or B)

= 106MHz at -1dB FS,

Gain Flatness (12MHz Spacing) (Note 3)

IN2(A or B)

= 118MHz at -1dB FS

Aperture Delay t

1ns

Aperture Jitter t

1dB SNR degradation at Nyquist 2

Overdrive Recovery Time For 1.5 × full-scale input 2 ns INTERNAL REFERENCE (REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)

Reference Output Voltage

(Note 4)

Positive Reference Output Voltage

REFP

(Note 5)

Negative Reference Output Voltage

REFN

(Note 5)

Common-Mode Level V

COM

(Note 5)

Differential Reference Output Voltage Range

∆V

REF

∆V

REF

= V

REFP

- V

REFN

Reference Temperature Coefficient

REF

REFOUT

68.9

-73.7

-73.2

500 MHz

400 MHz

0.05

2.048

±3%

2.012

0.988

VDD / 2

± 0.1

1.024

±3%

RMS

±100 ppm/°C

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

PARAMETER

CONDITIONS

BUFFERED EXTERNAL REFERENCE (V

REFIN

= 2.048V)

Positive Reference Output Voltage

REFP

(Note 5)

Negative Reference Output Voltage

REFN

(Note 5)

Common-Mode Level V

COM

(Note 5)

Differential Reference Output Voltage Range

∆V

REF

∆V

REF

= V

REFP

- V

REFN

REFIN Resistance R

REFIN

MΩ

Maximum REFP, COM Source Current

5mA

Maximum REFP, C OM S i nk C ur r ent I

SINK

µA

Maximum REFN Source Current

µA

Maximum REFN Sink Current I

SINK

-5 mA

UNBUFFERED EXTERNAL REFERENCE (V

REFIN

= AGND, reference voltage applied to REFP, REFN, and COM)

REFP, REFN Input Resistance

REFP

REFN

Measured between REFP and REFN 4 kΩ

REFP, REFN, COM Input Capacitance

15 pF

Differential Reference Input Voltage Range

∆V

REF

∆V

REF

= V

REFP

- V

REFN

COM Input Voltage Range V

COM

VDD / 2

REFP Input Voltage V

REFP

C OM

REFN Input Voltage V

REFN

COM

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

CLK

0.8 ×

Input High Threshold V

PD, OE, SLEEP, T/B

0.8 ×

CLK

0.2 ×

Input Low Threshold V

PD, OE, SLEEP, T/B

0.2 ×

SYMBOL

MIN TYP MAX UNITS

SOURCE

∆V

2.012

0.988

VDD / 2

±0.1

1.024

±2%

>50

-250

250

1.024

±10%

±5%

∆V

RE F

REF

/ 2

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

PARAMETER

CONDITIONS

UNITS

Input Hysteresis V

HYST

VIH = VDD = OV

Input Leakage

VIL = 0

µA

Input Capacitance C

5pF

DIGITAL OUTPUTS (D0A/B–D7A/B, A/B)

Output Voltage Low V

SINK

= -200µA 0.2 V

Output Voltage High V

SOURCE

= 200µA

0.2

Three-State Leakage Current I

LEAK

OE = OV

±10 µA

Three-State Output Capacitance

OUT

OE = OV

5pF

POWER REQUIREMENTS

Analog Supply Voltage Range V

2.7 3 3.6 V

Output Supply Voltage Range OV

1.7 3 3.6 V

Operating, f

INA&B

= 20MHz at -1dB FS

applied to both channels

29 36

Sleep mode 3

Analog Supply Current I

VDD

Shutdown, clock idle, PD = OE = OV

0.1 20 µA

Operating, f

INA&B

= 20MHz at -1dB FS

applied to both channels (Note 6)

8mA

Sleep mode 3

Output Supply Current I

OVDD

Shutdown, clock idle, PD = OE = OV

310

µA

Operating, f

INA&B

= 20MHz at -1dB FS

applied to both channels

87 108

Sleep mode 9

Analog Power Dissipation PDISS

Shutdown, clock idle, PD = OE = OV

0.3 60 µW

Offset, VDD ±5% ±3

Power-Supply Rejection PSRR

Gain, V

±5% ±3

mV/V

TIMING CHARACTERISTICS

CLK Rise to CHA Output Data Valid

DOA

CL = 20pF (Notes 1, 7) 6

CLK Fall to CHB Output Data Valid

DOB

CL = 20pF (Notes 1, 7) 6

Clock Rise/Fall to A/B Rise/Fall Time

DA/B

6ns

OE Fall to Output Enable Time

5ns

OE Rise to Output Disable Time

5ns

CLK Pulse Width High t

Clock period: 25ns (Note 7)

12.5 ns

SYMBOL

MIN TYP MAX

ENABLE

DISABLE

0.15

±1.5

±20 ±20

8.25

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

6 _______________________________________________________________________________________

Note 1: Guaranteed by design. Not subject to production testing. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 3: Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two

applied input signals with the same magnitude (peak-to-peak) at f

IN1

and f

IN2

Note 4: REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 5: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor. Note 6: Typical digital output current at f

INA&B

= 20MHz. For digital output currents vs. analog input frequency, see the Typical

Operating Characteristics.

Note 7: See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to

50% of the data output level.

Note 8: SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode. Note 9: Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is

measured by calculating the power ratio of the fundamental of each channel’s FFT.

Note 10:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-

mental of the calculated FFT.

Note 11:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of

the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.

ELECTRICAL CHARACTERISTICS (continued)

(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ resistor, V

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 5), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at T

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CLK Pulse Width Low t

Clock period: 25ns (Note 7)

12.5 ns

Wake-up from sleep mode 1

Wake-Up Time t

WAKE

Wake-up from shutdown mode (Note 8) 20

µs

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

INA or B

= 20MHz at -1dB FS (Note 9) -72 dB

Gain Matching f

INA or B

= 20MHz at -1dB FS (Note 10)

Phase Matching f

INA or B

= 20MHz at -1dB FS (Note 11)

D eg r ees

±1.5

0.05

±0.05

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(VDD= OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

FFT PLOT CHA

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 1.958036MHz

INB

= 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHB

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 1.958036MHz

INB

= 7.534287MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHA

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 7.534287MHz

INB

= 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHB

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 7.534287MHz

INB

= 1.958036MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHA

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 19.88798MHz

INB

= 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHB

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-06

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 19.88798MHz

INB

= 40.49374MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHA

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-07

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 40.49374MHz

INB

= 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

FFT PLOT CHB

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-08

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

181612 144 6 8 102

-80

-70

-60

-50

-40

-30

-20

-10

-90 020

INA

CLK

= 40.0005678MHz

INA

= 40.49374MHz

INB

= 19.88798MHz AINA = AINB = -1dB FS COHERENT SAMPLING

INB

HD2

HD3

TWO-TONE IMD PLOT

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-09

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

4.54.03.0 3.51.5 2.0 2.51.0

-80

-70

-60

-50

-40

-30

-20

-10

-90

0.5 5.0

CLK

= 40.001536MHz

INA

= 1.997147MHz

INB

= 2.045977MHz AIN = -7dB FS COHERENT SAMPLING

IN2

IN1

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

TWO-TONE IMD PLOT

(DIFFERENTIAL INPUT, 8192-POINT DATA RECORD)

MAX1196-10

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

12111098

-80

-70

-60

-50

-40

-30

-20

-10

-90 713

CLK

= 40.001536MHz

IN1

= 9.95643MHz

IN2

= 10.024799MHz AIN = -7dB FS COHERENT SAMPLING

IN1

IN2

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1196-11

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

1601208040

0 200

CHA

CHB

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1196-12

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

1601208040

0 200

CHA

CHB

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1196-13

ANALOG INPUT FREQUENCY (MHz)

THD (dBc)

1601208040

-78

-68

-58

-48

-38

-88 0 200

CHB

CHA

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

MAX1196-14

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

1601208040

0 200

CHA

CHB

1 10 100 1000

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL

MAX1196-15

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-4

-3

-2

-1

1 10 100 1000

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL

MAX1196-16

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-4

-3

-2

-1

VIN = 100mV

P-P

SIGNAL-TO-NOISE RATIO

vs. INPUT POWER (f

= 19.88798MHz)

MAX1196-17

INPUT POWER (dB FS)

SNR (dB)

-4-8-12-16

-20 0

SIGNAL-TO-NOISE + DISTORTION

vs. INPUT POWER (f

= 19.88798MHz)

MAX1196-18

INPUT POWER (dB FS)

SINAD (dB)

-4-8-12-16

-20 0

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(VDD= OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

GAIN ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE V

REFIN

= 2.048V

MAX1196-24

TEMPERATURE (°C)

GAIN ERROR (%FS)

603510-15

0.1

0.2

0.3

0.4

0.5

-0.1

-40 85

CHA

CHB

TOTAL HARMONIC DISTORTION

vs. INPUT POWER (f

= 19.88798MHz)

MAX1196-19

INPUT POWER (dB FS)

SINAD (dBc)

-4-8-12-16

-70

-65

-60

-55

-50

-45

-75

-20 0

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f

= 19.88798MHz)

MAX1196-20

INPUT POWER (dB FS)

SFDR (dBc)

-4-8-12-16

-20 0

SNR/SINAD, THD/SFDR

vs. CLOCK DUTY CYCLE

MAX1196-21

CLOCK DUTY CYCLE (%)

SNR/SINAD, THD/SFDR (dB, dBc)

56524844

40 60

THD

SINAD

SNR

SFDR

INA/B

= 7.534287MHz

INTEGRAL NONLINEARITY

(131,072-POINT DATA RECORD)

MAX1196-22

DIGITAL OUTPUT CODE

INL (LSB)

224192128 16064 9632

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5 0 256

= 7.534287MHz

DIFFERENTIAL NONLINEARITY

(131,072-POINT DATA RECORD)

MAX1196-23

DIGITAL OUTPUT CODE

DNL (LSB)

224192128 16064 9632

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

-0.5 0 256

= 7.534287MHz

OFFSET ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE V

REFIN

= 2.048V

MAX1196-25

TEMPERATURE (°C)

OFFSET ERROR (%FS)

603510-15

-0.6

-0.4

-0.2

0.2

-0.8

-40 85

CHB

CHA

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= OVDD= 3V, V

REFIN

= 2.048V, differential input at -1dB FS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

Pin Description

FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥0.1µF capacitor.

Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.

GND Analog Ground

4 INA+ Channel ‘A’ Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel ‘A’ Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel ‘B’ Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel ‘B’ Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

ANALOG SUPPLY CURRENT

(mA)

VDD

-40 85

2.040

2.036

2.032

(V)

REFOUT

2.028

2.024

2.020

vs. TEMPERATURE

MAX1196-26

(mA)

OVDD

6035-15 10

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

-40 85

TEMPERATURE (°C)

603510-15

DIGITAL SUPPLY CURRENT

vs. ANALOG INPUT FREQUENCY

MAX1196-27

2.0324

2.0320

2.0316

(V)

2.0312

REFOUT

2.0308

2.0304

2.0300

020

ANALOG INPUT FREQUENCY (MHz)

161284

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

2.70 3.60

SNR/SINAD, THD/SFDR

vs. SAMPLING SPEED

MAX1196-29

100

-20

-40

SNR/SINAD, THD/SFDR (dB, dBc)

-60

-80

-100

SNR

060

SAMPLING SPEED (Msps)

THD

SFDR

SINAD

= 20MHz

5040302010

MAX1196-28

3.453.303.153.002.85

(V)

MAX1196-30

NAME

2, 6, 11, 14, 15

3, 7, 10, 13, 16

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 11

Pin Description (continued)

FUNCTION

17 T/B

T/B selects the ADC digital output format. High: Two’s complement. Low: Straight offset binary.

Sleep Mode Input. High: Deactivates the two ADCs, but leaves the reference bias circuit active. Low: Normal operation.

19 PD

High-Active Power-Down Input. High: Power-down mode Low: Normal operation

20 OE

Low-Active Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled

21–29, 35, 36

N.C. No Connection. Do not connect.

30 A/B

A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to be present on the output. A/B follows the external clock signal with typically 6ns delay.

31, 34

Output-Driver Ground

32, 33

Output-Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with

0.1µF.

Three-State Digital Output, Bit 0. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or channel B data.

Three-State Digital Output, Bit 7 (MSB). Depending on status of A/B, output data reflects channel A or channel B data.

Reference Input. V

REFIN

= 2 × (V

REFP

- V

REFN

). Bypass to GND with a ≥0.1µF capacitor.

Negative Reference I/O. Conversion range is ±(V

REFP

- V

REFN

). Bypass to GND with a ≥0.1µF

capacitor.

NAME

SLEEP

OGND

D0A/B

D1A/B

D2A/B

D3A/B

D4A/B

D5A/B

D6A/B

D7A/B

REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.

REFIN

REFP Positive Reference I/O. Conversion range is ±(V

REFN

- V

REFP

). Bypass to GND with a ≥0.1µF capacitor.

REFN

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

12 ______________________________________________________________________________________

Detailed Description

The MAX1196 uses a 7-stage, fully differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHA and 5.5 clock cycles for CHB.

Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all 7 stages.

Both input channels are sampled on the rising edge of the clock and the resulting data is multiplexed at the output. CHA data is updated on the rising edge (5 clock cycles later) and CHB data is updated on the falling edge (5.5 clock cycles later) of the clock signal. The A/B indicator follows the clock signal with a typical delay time of 6ns and remains high when CHA data is updated and low when CHB data is updated.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a,

S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1196 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA-, and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1196 is determined by the internally generated voltage difference between REFP (VDD/2 + V

REFIN

/4) and REFN (VDD/2 - V

REFIN

/4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose.

INA

STAGE 1 STAGE 2

DIGITAL ALIGNMENT LOGIC

STAGE 6 STAGE 7

2-BIT FLASH

ADC

T/H

INB

STAGE 1 STAGE 2

DIGITAL ALIGNMENT LOGIC

STAGE 6 STAGE 7

2-BIT FLASH

ADC

T/H

OUTPUT MULTIPLEXER

D0A/B–D7A/B

Figure 1. Pipelined Architecture—Stage Blocks

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 13

The MAX1196 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g.,

10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a ≥0.1µF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP,

S3b

S3a

COM

S5b

S5a

INB+

INB-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

HOLD

CLK

INTERNAL NONOVERLAPPING CLOCK SIGNALS

TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

INA+

INA-

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

S2a

S2b

MAX1196

Figure 2. MAX1196 T/H Amplifiers

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

14 ______________________________________________________________________________________

DOB

CLK

DOA

DA/B

5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)

A/B CHB

D0A/B–D7A/B D0B

CHA

D1A

CHB

D1B

CHA

D2A

CHB

D2B

CHA

D3A

CHB

D3B

CHA

D4A

CHB

D4B

CHA

D5A

CHB

D5B

CHA

D6A

CHB

D6B

CHA

CHB

CLK

Figure 3. System Timing Diagram

and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources.

For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section.

Clock Input (CLK)

The MAX1196’s CLK input accepts CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows:

where fINrepresents the analog input frequency and t

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.

The MAX1196 clock input operates with a voltage threshold set to V

/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical

Characteristics.

System Timing Requirements

Figure 3 shows the relationship between clock and analog input, A/B indicator, and the resulting valid CHA/CHB data output. CHA and CHB data are sampled on the rising edge of the clock signal. Following the rising edge of the 5th clock cycles, the digitized value of the original CHA sample is presented at the output, followed one-half clock cycle later by the digitized value of the original CHB sample.

A channel selection signal (A/B indicator) allows the user to determine which output data represents which input channel. With A/B = 1, digitized data from CHA is present at the output and with A/B = 0 digitized data from CHB is present.

SNR

IN AJ

log =×

×× ×

 



 



2 π

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 15

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

Channel Selection (A/B)

All digital outputs, D0A/B–D7A/B (CHA or CHB data) and A/B are TTL/CMOS-logic compatible. The output coding can be chosen to be either offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on the digital outputs D0A/B–D7A/B should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1196, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1196, small-series resistors (e.g., 100Ω) can be added to the digital output paths, close to the MAX1196.

Figure 4 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1196 offers two power-save modes—sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3mA.

To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a VDD/2 output voltage for level-shifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed operational amplifiers. The user can select the R

ISO

and CINvalues to optimize the filter performance, to suit a particular application. For the application in Figure 5, an R

ISO

of 50Ω is placed before

the capacitive load to prevent ringing and oscillation. The 22pF CINcapacitor acts as a small filter capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1196 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion.

DIFFERENTIAL INPUT

VOLTAGE*

DIFFERENTIAL INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

REF

× 255/256 +Full Scale - 1LSB 1111 1111 0111 1111

REF

× 1/256 +1LSB 1000 0001 0000 0001

0 Bipolar Zero 1000 0000 0000 0000

-V

REF

× 1/256 -1LSB 0111 1111 1111 1111

-V

REF

× 255/256 -Full Scale + 1LSB 0000 0001 1000 0001

-V

REF

× 256/256 -Full Scale 0000 0000 1000 0000

Table 1. MAX1196 Output Codes for Differential Inputs

REF

= V

REFP

- V

REFN

OUTPUT

D0A/B–D7A/B

DISABLE

ENABLE

HIGH-ZHIGH-Z

VALID DATA

Figure 4. Output Timing Diagram

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

16 ______________________________________________________________________________________

INPUT

300Ω

-5V

+5V

0.1µF

-5V

600Ω

300Ω

INA-

INA+

LOWPASS FILTER

COM

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

+5V

0.1µF

300Ω

MAX4108

MAX1196

INB-

INB+

MAX4108

LOWPASS FILTER

INPUT

300Ω

-5V

+5V

0.1µF

22pF

-5V

600Ω

300Ω

LOWPASS FILTER

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

+5V

0.1µF

300Ω

MAX4108

300Ω

LOWPASS FILTER

IS0

50Ω

22pF

IS0

50Ω

22pF

IS0

50Ω

22pF

IS0

50Ω

Figure 5. Typical Application for Single-Ended-to-Differential Conversion

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 17

In general, the MAX1196 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.

Buffered External Reference Drives

Multiple ADCs

Multiple-converter systems based on the MAX1196 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source.

A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise voltage density of 150nV/√Hz. Its out- put passes through a one-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise

MAX1196

N.C.

22pF

0.1µF

2.2µF

25Ω

MINICIRCUITS

TT1-6-KK81

N.C.

22pF

0.1µF

2.2µF

25Ω

MINICIRCUITS

TT1-6-KK81

INA-

INA+

INB-

INB+

COM

Figure 6. Transformer-Coupled Input Drive

MAX1196

0.1µF

1kΩ

100Ω

22pF

INB+

INB-

COM

INA+

INA-

0.1µF

ISO

50Ω

ISO

50Ω

REFP

REFN

MAX4108

0.1µF

1kΩ

100Ω

22pF

0.1µF

ISO

50Ω

ISO

50Ω

REFP

REFN

MAX4108

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

18 ______________________________________________________________________________________

produced in the voltage-reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision-ADC operation.

Unbuffered External Reference Drives

Multiple ADCs

Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors.

Those three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individ-

ual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2V

P-P

. The 2.0V and 1.0V buffers drive

the ADCs’ internal ladder resistances between them.

Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down.

With the outputs of the MAX4252 matching better than

0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications requiring more than 32 matched ADCs, a voltage-reference and divider string common to all converters is highly recommended.

MAX4250

MAX6062

16.2kΩ

162Ω

3.3V

10Hz LOWPASS FILTER

REFOUT

REFP

REFIN

1µF

MAX1196

N = 1

REFN

29N.C.

2.048V

N.C.

COM

REFOUT

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 1000 ADCs.

REFP

REFIN

MAX1196

N = 1000

REFN

COM

0.1µF

3.3V

0.1µF0.1µF0.1µF

0.1µF

2.2µF

10V

0.1µF0.1µF

0.1µF

100µF

0.1µF

Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 19

Typical QAM Demodulation Application

A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread- spectrumbased systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier

component, where the Q component is 90 degrees phase-shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dual matched 3V, 8-bit ADC MAX1196, and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1196, the mixed-down signal components can be filtered by matched analog filters, such

1/4 MAX4252

MAX6066

1/4 MAX4252

1.47kΩ

21.5kΩ

47kΩ

3.3V

REFOUT

REFP

REFIN

1µF

10µF 6V

MAX1196

N = 1

REFN

29N.C.

N.C.

COM

REFOUT

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN CAN BE USED WITH UP TO 32 ADCs.

REFP

REFIN

MAX1196

N = 32

REFN

COM

2.0V AT 8mA

0.1µF

MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP.

3.3V

1.47kΩ

47kΩ

3.3V

1.5V

10µF 6V

1.5V AT 0mA

1.47kΩ

47kΩ

3.3V

10µF 6V

0.1µF0.1µF0.1µF

0.1µF

2.2µF 10V

0.1µF0.1µF

1.0V AT -8mA

330µF

2.0V

1.0V

Figure 9. External Unbuffered Reference Drive With MAX4252 and MAX6066

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

20 ______________________________________________________________________________________

as Nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.

Grounding, Bypassing,

and Board Layout

The MAX1196 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output-driver ground (OGND) on the ADC’s package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short.

Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route

high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 degree turns.

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1196 are measured using the best-straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 11).

0°

90°

DOWNCONVERTER

MAX2451

INA+

MAX1196

INA-

INB+ INB-

DSP

POST-

PROCESSING

A/B

CHA AND CHB DATA ALTERNATINGLY AVAILABLE ON 8-BIT MULTIPLEXED OUTPUT BUS.

Figure 10. Typical QAM Application Using the MAX1196

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 21

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):

SNR

dB[max]

= 6.02dB× N + 1.76

In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from:

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale.

Pin-Compatible Upgrades

(Sampling Speed and Resolution)

Chip Information

TRANSISTOR COUNT: 11,601

PROCESS: CMOS

THD

VVV V

log

=×





 





 

ENOB

SINAD

 



 



- 1.76

6.02

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

TRACK TRACK

CLK

Figure 11. T/H Aperture Timing

8-BIT PART 10-BIT PART

SAMPLING SPEED

(Msps)

N/A MAX1185 20

MAX1195 MAX1183 40

MAX1197 MAX1182 60

MAX1198 MAX1180 100

N/A MAX1190 120

MAX1196 MAX1186 40, multiplexed

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs

22 ______________________________________________________________________________________

GND

REFERENCE

OUTPUT DRIVERS

CONTROL

T/H

ADC

DEC

MUX

REFOUT

REFN

COM

REFP

REFIN

INA+

INA-

CLK

INB+

INB-

DEC

ADC

OGND OV

A/B

D7B–D0B OR D7A–D0A

T/B

PD SLEEP

MAX1196

Functional Diagram

MAX1196

Dual 8-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)

48L,TQFP.EPS

MAXIM MAX1196 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual