General Description
The MAX1192 is an ultra-low-power, dual, 8-bit, 22Msps
analog-to-digital converter (ADC). The device features
two fully differential wideband track-and-hold (T/H) inputs.
These inputs have a 440MHz bandwidth and accept fully
differential or single-ended signals. The MAX1192 delivers a typical signal-to-noise and distortion (SINAD) of
48.6dB at an input frequency of 5.5MHz and a sampling
rate of 22Msps while consuming only 27.3mW. This ADC
operates from a 2.7V to 3.6V analog power supply. A separate 1.8V to 3.6V supply powers the digital output driver.
In addition to ultra-low operating power, the MAX1192
features three power-down modes to conserve power
during idle periods. Excellent dynamic performance,
ultra-low power, and small size make the MAX1192 ideal
for applications in imaging, instrumentation, and digital
communications.
An internal 1.024V precision bandgap reference sets
the full-scale range of the ADC to ±0.512V. A flexible
reference structure allows the MAX1192 to use its internal reference or accept an externally applied reference
for applications requiring increased accuracy.
The MAX1192 features parallel, multiplexed, CMOScompatible tri-state outputs. The digital output format is
offset binary. A separate digital power input accepts a
voltage from 1.8V to 3.6V for flexible interfacing to different logic levels. The MAX1192 is available in a 5mm
× 5mm, 28-pin thin QFN package, and is specified for
the extended industrial (-40°C to +85°C) temperature
range.
For higher sampling frequency applications, refer to the
MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible
versions of the MAX1192 are also available. Refer to the
MAX1191 data sheet for 7.5Msps, and the MAX1193
data sheet for 45Msps.
Applications
Ultrasound and Medical Imaging
IQ Baseband Sampling
Battery-Powered Portable Instruments
Low-Power Video
WLAN, Mobile DSL, WLL Receiver
Features
o Ultra-Low Power
27.3mW (Normal Operation: 22Msps)
1.8µW (Shutdown Mode)
o Excellent Dynamic Performance
48.6dB/47.2dB SNR at f
IN
= 5.5MHz/125MHz
70dBc/69dBc SFDR at fIN= 5.5MHz/125MHz
o 2.7V to 3.6V Single Analog Supply
o 1.8V to 3.6V TTL/CMOS-Compatible Digital
Outputs
o Fully Differential or Single-Ended Analog Inputs
o Internal/External Reference Option
o Multiplexed CMOS-Compatible Tri-State Outputs
o 28-Pin Thin QFN Package
o Evaluation Kit Available (Order MAX1193EVKIT)
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
________________________________________________________________
Maxim Integrated Products
1
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
MAX1192
5mm x 5mm THIN QFN
TOP VIEW
PD0
EXPOSED PADDLE
PD1
REFIN
COM
REFN
REFP
V
DD
INA+
INA-
GND
CLK
GND
INB+
INB-
V
DD
V
DD
GND
OGND
OV
DD
D7
D6
D0
D1
D2
D3
A/B
D4
D5
Pin Configuration
Ordering Information
19-2835; Rev 2; 7/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX1192ETI-T -40°C to +85°C 28 Thin QFN-EP*
-
Denotes a package containing lead(Pb).
*EP = Exposed paddle.
T = Tape and reel.
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND .................-0.3V to (V
DD
+ 0.3V)
CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (V
DD
+ 0.3V)
PD0, PD1 to OGND .................................-0.3V to (OV
DD
+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin Thin QFN (derated 20.8mW/°C above +70°C) ..1667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS MIN TYP
UNITS
DC ACCURACY
Resolution 8 Bits
Integral Nonlinearity INL
LSB
Differential Nonlinearity DNL No missing codes over temperature
LSB
≥ +25°C ±4
Offset Error
< +25°C ±6
%FS
Gain Error Excludes REFP - REFN error ±2
%FS
DC Gain Matching
dB
Gain Temperature Coefficient ±30
ppm/°C
Offset (VDD ±5%)
Power-Supply Rejection
Gain (V
DD
±5%)
LSB
ANALOG INPUT
Differential Input Voltage Range
Differential or single-ended inputs
V
Common-Mode Input Voltage
Range
V
Input Resistance R
IN
Switched capacitor load 245 kΩ
Input Capacitance C
IN
5pF
CONVERSION RATE
Clock Frequency Range f
CLK
7.5 22
MHz
Channel A 5.0
Data Latency
Channel B 5.5
Clock
cycles
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)
fIN = 1.875MHz 48.6
fIN = 5.5MHz 47 48.6
Signal-to-Noise Ratio
(Note 2)
SNR
f
IN
= 11MHz 48.6
dB
fIN = 1.875MHz 48.7
fIN = 5.5MHz 47 48.6
Signal-to-Noise and Distortion
(Note 2)
fIN = 11MHz 48.6
dB
SYMBOL
±0.15 ±1.00
±0.14 ±1.00
MAX
V
V
SINAD
DIFF
COM
±0.01 ±0.2
±0.02
±0.05
±0.512
VDD / 2
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS MIN TYP
UNITS
fIN = 1.875MHz 70.8
fIN = 5.5MHz 59.0 70.0
Spurious-Free Dynamic Range
(Note 2)
fIN = 11MHz 70.4
dBc
fIN = 1.875MHz 75.8
fIN = 5.5MHz
Thi r d - H ar m oni c D i stor ti on
( N ote 2)
HD3
f
IN
= 11MHz
dBc
Intermodulation Distortion IMD
f
IN1
= 1MHz at -7dB FS, f
IN2
= 1.01MHz at
-7dB FS
-64
dBc
Third-Order Intermodulation IM3
f
IN1
= 1MHz at -7dB FS, f
IN2
= 1.01MHz at
-7dB FS
-67
dBc
fIN = 1.875MHz
fIN = 5.5MHz
Total Harmonic Distortion
(Note 2)
THD
f
IN
= 11MHz
dBc
Small-Signal Bandwidth
Input at -20dB FS 440
MHz
Full-Power Bandwidth
Input at -0.5dB FS 440
MHz
Aperture Delay t
AD
1.5 ns
Aperture Jitter t
AJ
2
ps
RMS
Overdrive Recovery Time 1.5 × full-scale input 2 ns
INTERNAL REFERENCE (REFIN = VDD; V
REFP
, V
REFN
, and V
COM
are generated internally)
REFP Output Voltage V
REFP
- V
COM
V
REFN Output Voltage V
REFN
- V
COM
V
COM Output Voltage
V
Differential Reference Output
V
REFP
- V
REFN
V
Differential Reference Output
Temperature Coefficient
±30
ppm/°C
Maximum REFP/REFN/COM
Source Current
2mA
Maximum REFP/REFN/COM Sink
Current
2mA
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 1.024V, V
REFP
, V
REFN
, and V
COM
are generated internally)
REFIN Input Voltage
V
COM Output Voltage
V
Differential Reference Output
V
REFP
- V
REFN
V
Maximum REFP/REFN/COM
Source Current
2mA
SYMBOL
SFDR
SSBW
FPBW
V
COM
V
REF
V
REFTC
I
SOURCE
-74.0
-74.8
-71.0
-70.0 -57.0
-70.2
0.256
-0.256
VDD / 2
- 0.15
V
DD
0.512
/ 2
MAX
V
DD
+ 0.15
/ 2
I
SINK
V
REFIN
V
COM
V
REF
I
SOURCE
VDD / 2
- 0.15
1.024
V
DD
0.512
/ 2
V
DD
+ 0.15
/ 2
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
Maximum REFP/REFN/COM Sink
Current
2mA
REFIN Input Resistance >500 kΩ
REFIN Input Current -0.7 µA
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, V
REFP
, V
REFN
, and V
COM
are applied externally)
REFP Input Voltage V
REFP
- V
COM
V
REFN Input Voltage V
REFN
- V
COM
V
COM Input Voltage
V
Differential Reference Input
Voltage
V
REFP
- V
REFN
V
REFP Input Resistance
Measured between REFP and COM 4 kΩ
REFN Input Resistance
Measured between REFN and COM 4 kΩ
DIGITAL INPUTS (CLK, PD0, PD1)
CLK
0.7 x
V
DD
Input High Threshold V
IH
PD0, PD1
0.7 x
V
CLK
0.3 x
V
DD
Input Low Threshold V
IL
PD0, PD1
0.3 x
V
Input Hysteresis
0.1 V
CLK at GND or V
DD
±5
Digital Input Leakage Current DI
IN
PD0 and PD1 at OGND or OV
DD
±5
µA
Digital Input Capacitance
5pF
DIGITAL OUTPUTS (D7–D0, A/B)
Output Voltage Low V
OLISINK
= 200µA
0.2 x
V
Output Voltage High V
OHISOURCE
= 200µA
0.8 x
V
Tri-State Leakage Current
±5 µA
Tri-State Output Capacitance
5pF
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
I
SINK
0.256
-0.256
V
COM
VDD / 2
V
R
R
REF
REFP
REFN
0.512
V
HYST
DC
IN
OV
DD
OV
DD
I
LEAK
C
OUT
OV
OV
DD
DD
MAX1192
PARAMETER
CONDITIONS MIN TYP
POWER REQUIREMENTS
Analog Supply Voltage V
DD
2.7 3.0 3.6 V
Digital Output Supply Voltage
1.8 V
DD
V
Normal operating mode, fIN = 1.875MHz
at -0.5dB FS, f
CLK
= 7.5MHz,
CLK input from GND to V
DD
4.2 5.0
Normal operating mode, fIN = 5.5MHz
at -0.5dB FS, f
CLK
= 22MHz,
CLK input from GND to V
DD
9.1 10.5
Idle mode (tri-state), fIN = 1.875MHz at -
0.5dB FS, f
CLK
= 7.5MHz, CLK input from
GND to V
DD
4.2
Idle mode (tri-state), fIN = 5.5MHz at
-0.5dB FS, f
CLK
= 22MHz, CLK input from
GND to V
DD
9.1
Standby mode, f
CLK
= 7.5MHz, CLK input
from GND to V
DD
2.3
Standby mode, f
CLK
= 22MHz, CLK input
from GND to V
DD
4.9
mA
Analog Supply Current I
DD
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.6 5.0 µA
Normal operating mode,
f
IN
= 1.875MHz at -0.5dB FS,
f
CLK
= 7.5MHz, CL ≈ 10pF
1.0
Normal operating mode,
f
IN
= 5.5MHz at -0.5dB FS,
f
CLK
= 22MHz, CL ≈ 10pF
2.9
mA
Idle mode (tri-state), DC input,
CLK = GND or V
DD,
PD0 = OVDD, PD1 = OGND
0.1 5.0
Standby mode, DC input, CLK = GND or
V
DD,
PD0 = OGND, PD1 = OV
DD
0.1
Digital Output Supply Current
(Note 3)
Shutdown mode, CLK = GND or VDD,
PD0 = PD1 = OGND
0.1 5.0
µA
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
_______________________________________________________________________________________ 5
SYMBOL
OV
DD
MAX UNITS
I
ODD
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Note 1: Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the
amplitude of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (CL).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the
second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
DOA
50% of C LK to 50% of d ata,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
CLK Fall to CHB Output Data
Valid
t
DOB
50% of C LK to 50% of d ata,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
CLK Rise/Fall to A/B Rise/Fall
Time
t
DA/B
50% of C LK to 50% of A/B,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
PD1 Rise to Output Enable t
EN
PD0 = OV
DD
5ns
PD1 Fall to Output Disable t
DIS
PD0 = OV
DD
5ns
CLK Duty Cycle 50 %
CLK Duty Cycle Variation ±10 %
Wake-Up Time from Shutdown
Mode
(Note 5) 20 µs
Wake-Up Time from Standby
Mode
(Note 5) 5.4 µs
Digital Output Rise/Fall Time 20% to 80% 2 ns
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
f
IN,X
= 5.5MHz at -0.5dB FS,
f
IN,Y
= 0.3MHz at -0.5dB FS (Note 6)
-75 dB
Amplitude Matching fIN = 5.5MHz at -0.5dB FS (Note 7)
dB
Phase Matching fIN = 5.5MHz at -0.5dB FS (Note 7) ±0.1
Degrees
t
WAKE, SD
t
WAKE, ST
±0.03
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
_______________________________________________________________________________________
7
FFT PLOT CHANNEL A (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 5.606183MHz
f
INB
= 8.056034MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INB
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 5.606183MHz
f
INB
= 8.056034MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INA
FFT PLOT CHANNEL A (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 8.056034MHz
f
INB
= 5.606183MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INB
FFT PLOT CHANNEL B (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 8.056034MHz
f
INB
= 5.606183MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INA
TWO-TONE IMD PLOT (DIFFERENTIAL
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
IN1
= 1.8MHz
f
IN2
= 2.3MHz
A
IN
= -7dB FS
f
IN2
f
IN1
Typical Operating Characteristics
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
8 _______________________________________________________________________________________
FFT PLOT CHANNEL A (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 5.606183MHz
f
INB
= 8.056034MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INB
FFT PLOT CHANNEL B (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc07
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 5.606183MHz
f
INB
= 8.056034MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INA
FFT PLOT CHANNEL B (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc09
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 8.056034MHz
f
INB
= 5.606183MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INA
FFT PLOT CHANNEL A (SINGLE-ENDED
INPUTS, 8192-POINT DATA RECORD)
MAX1192 toc08
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
108642
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
012
f
CLK
= 22.005678MHz
f
INA
= 8.056034MHz
f
INB
= 5.606183MHz
A
INA
= A
INB
= -0.5dB FS
HD3
HD2
f
INB
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
_______________________________________________________________________________________
9
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1192 toc10
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
1007525 50
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
46.0
0125
CHANNEL A
CHANNEL B
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1192 toc11
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
1007525 50
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
46.0
0125
CHANNEL A
CHANNEL B
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1192 toc12
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
1007525 50
-80
-75
-70
-65
-60
-55
-50
-45
-85
0125
CHANNEL A
CHANNEL B
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1192 toc13
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
1007525 50
50
55
60
65
70
75
80
85
45
0125
CHANNEL A
CHANNEL B
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
10 ______________________________________________________________________________________
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
MAX1192 toc17
ANALOG INPUT POWER (dB FS)
SFDR (dBc)
-5-10-15-20-25
40
50
60
70
80
30
-30 0
fIN = 5.512345MHz
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
MAX1192 toc14
ANALOG INPUT POWER (dB FS)
SNR (dB)
-5-10-15-20-25
10
20
30
40
50
60
0
-30 0
fIN = 5.512345MHz
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT POWER
MAX1192 toc15
ANALOG INPUT POWER (dB FS)
SINAD (dB)
-5-10-15-20-25
10
20
30
40
50
60
0
-30 0
fIN = 5.512345MHz
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
MAX1192 toc16
ANALOG INPUT POWER (dB FS)
THD (dBc)
-5-10-15-20-25
-70
-60
-50
-40
-30
-80
-30 0
fIN = 5.512345MHz
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________
11
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
MAX1192 toc21
f
CLK
(MHz)
SFDR (dBc)
5040302010
55
60
65
70
75
80
50
060
fIN = 5.512345MHz
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
MAX1192 toc18
f
CLK
(MHz)
SNR (dB)
5040302010
46
47
48
49
50
45
060
fIN = 5.512345MHz
SIGNAL-TO-NOISE AND DISTORTION
vs. SAMPLING RATE
MAX1192 toc19
f
CLK
(MHz)
SINAD (dB)
5040302010
46
47
48
49
50
45
060
fIN = 5.512345MHz
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
MAX1192 toc20
f
CLK
(MHz)
THD (dBc)
5040302010
-75
-70
-65
-60
-55
-50
-80
060
fIN = 5.512345MHz
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
12 ______________________________________________________________________________________
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
MAX1192 toc25
CLOCK DUTY CYCLE (%)
SFDR (dBc)
555045
62
64
66
68
70
72
74
76
78
80
60
40 60
fIN = 5.512345MHz
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
MAX1192 toc22
CLOCK DUTY CYCLE (%)
SNR (dB)
555045
46
47
48
49
50
45
40 60
fIN = 5.512345MHz
SIGNAL-TO-NOISE AND DISTORTION
vs. CLOCK DUTY CYCLE
MAX1192 toc23
CLOCK DUTY CYCLE (%)
SINAD (dB)
555045
46
47
48
49
50
45
40 60
fIN = 5.512345MHz
TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
MAX1192 toc24
CLOCK DUTY CYCLE (%)
THD (dBc)
555045
-78
-76
-74
-72
-70
-68
-66
-64
-62
-60
-80
40 60
fIN = 5.512345MHz
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________
13
GAIN ERROR
vs. TEMPERATURE
MAX1192 toc29
TEMPERATURE (°C)
GAIN ERROR (% FS)
6035-15 10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.10
-40 85
V
REFIN
= 1.024V
CHANNEL A
CHANNEL B
6
-10
1 100 1000
INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
-6
-8
-4
-2
0
2
4
MAX1192 toc30
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10
FULL-POWER
BANDWIDTH
-0.5dB FS
SMALL-SIGNAL
BANDWIDTH
-20dB FS
REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1192 toc31
VDD (V)
V
REFP
- V
REFN
(V)
3.53.43.33.23.13.02.92.8
0.5105
0.5110
0.5115
0.5120
0.5125
0.5130
0.5100
2.7 3.6
VDD = V
REFIN
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1192 toc32
TEMPERATURE (°C)
V
REFP
- V
REFN
(V)
603510-15
0.5105
0.5110
0.5115
0.5120
0.5125
0.5130
0.5100
-40 85
VDD = V
REFIN
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
MAX1192 toc26
DIGITAL OUTPUT CODE
INL (LSB)
224192128 16064 9632
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0256
DIFFERENTIAL NONLINEARITY
MAX1192 toc27
DIGITAL OUTPUT CODE
DNL (LSB)
224192128 16064 9632
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-0.5
0256
OFFSET ERROR
vs. TEMPERATURE
MAX1192 toc28
TEMPERATURE (°C)
OFFSET ERROR (% FS)
603510-15
-0.59
-0.58
-0.57
-0.56
-0.55
-0.54
-0.53
-0.52
-0.51
-0.50
-0.60
-40 85
V
REFIN
= 1.024V
CHANNEL A
CHANNEL B
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
14 ______________________________________________________________________________________
SUPPLY CURRENT
vs. INPUT FREQUENCY
MAX1192 toc33
fIN (MHz)
DIGITAL SUPPLY CURRENT (mA)
108642
0.5
1.0
1.5
2.0
2.5
3.0
0
ANALOG SUPPLY CURRENT (mA)
8.8
9.0
9.2
9.4
9.6
9.8
8.6
012
DIGITAL SUPPLY CURRENT
ANALOG SUPPLY CURRENT
SUPPLY CURRENT
vs. SAMPLING RATE
MAX1192 toc34
f
CLK
(MHz)
SUPPLY CURRENT (mA)
5030 402010
A: ANALOG SUPPLY CURRENT (I
DD
) - INTERNAL AND BUFFERED EXTERNAL
REFERENCE MODES
B: ANALOG SUPPLY CURRENT (I
DD
) - UNBUFFERED EXTERNAL REFERENCE MODE
C: DIGITAL SUPPLY CURRENT (I
ODD
) - ALL REFERENCE MODES
5
10
15
20
25
0
060
A
B
C
fIN = 5.5112345MHz
Pin Description
PIN NAME FUNCTION
1 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
2 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
3, 5, 10 GND Analog Ground. Connect all GND pins together.
4 CLK Converter Clock Input
6 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
7 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
8, 9, 28 V
DD
Converter Power Input. Connect to a 2.7V to 3.6V power supply. Bypass VDD to GND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
11 OGND Output Driver Ground
12 OV
DD
Output Driver Power Input. Connect to a 1.8V to VDD power supply. Bypass OVDD to GND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
13 D7 Tri-State Digital Output. D7 is the most significant bit (MSB).
14 D6 Tri-State Digital Output
15 D5 Tri-State Digital Output
16 D4 Tri-State Digital Output
17 A/B
Channel Data Indicator. This digital output indicates channel A data (A/B = 1) or channel B data
(A/B = 0) is present on the output.
18 D3 Tri-State Digital Output
19 D2 Tri-State Digital Output
20 D1 Tri-State Digital Output
21 D0 Tri-State Digital Output. D0 is the least significant bit (LSB).
22 PD1 Power-Down Digital Input 1. See Table 3.
Typical Operating Characteristics (continued)
(VDD= 3.0V, OVDD= 1.8V, V
REFIN
= VDD(internal reference), CL≈ 10pF at digital outputs, differential input at -0.5dB FS, f
CLK
=
22.005678MHz at 50% duty cycle, T
A
= +25°C, unless otherwise noted.)
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 15
Detailed Description
The MAX1192 uses a seven-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for channel A and
5.5 clock cycles for channel B.
At each stage, flash ADCs convert the held input voltages into a digital code. The following digital-to-analog
converter (DAC) converts the digitized result back into
an analog voltage, which is then subtracted from the
original held input signal. The resulting error signal is
then multiplied by two, and the product is passed along
to the next pipeline stage where the process is repeated
until the signal has been processed by all stages. Digital
error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing
codes. Figure 2 shows the MAX1192 functional diagram.
Pin Description (continued)
PIN NAME FUNCTION
23 PD0 Power-Down Digital Input 0. See Table 3.
24 REFIN Reference Input. Internally pulled up to VDD.
25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
26 REFN
Negative Reference I/O. Conversion range is ±(V
REFP
- V
REFN
). Bypass REFN to GND with a 0.33µF
capacitor.
27 REFP
Positive Reference I/O. Conversion range is ±(V
REFP
- V
REFN
). Bypass REFP to GND with a 0.33µF
capacitor.
— EP Exposed Paddle. Internally connected to pin 3. Externally connect EP to GND.
INA+
INA-
T/H
DIGITAL ERROR CORRECTION
/
D0–D7
FLASH
ADC
T/H
DAC
∑
-
+
x2
1.5 BITS
STAGE 1 STAGE 2 STAGE 7
Figure 1. Pipeline Architecture—Stage Blocks
INA+
INA-
DEC
/T/H
INB+
INB-
DEC/T/H
/
REFERENCE
SYSTEM AND
BIAS
CIRCUITS
PIPELINE
ADC
A
COM
REFIN
REFN
REFP
CLK
TIMING
OV
DD
OGND
MULTIPLEXER
OUTPUT
DRIVERS
POWER
CONTROL
D0–D7
/
/
V
DD
GND
A/B
PD0
PD1
PIPELINE
ADC
B
MAX1192
Figure 2. MAX1192 Functional Diagram
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
16 ______________________________________________________________________________________
Input Track-and-Hold (T/H) Circuits
Figure 3 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a,
S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two
capacitors (C2a and C2b) through switches S4a and
S4b. S2a and S2b set the common mode for the ampli-
fier input, and open simultaneously with S1, sampling
the input waveform. Switches S4a, S4b, S5a, and S5b
are then opened before switches S3a and S3b connect
capacitors C1a and C1b to the output of the amplifier
and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same
S3b
S3a
COM
S5b
S5a
INB+
INB-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD
HOLD
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
INA+
INA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX1192
Figure 3. Internal T/H Circuits
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 17
values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1192
to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (VDD/2) for optimum performance.
Analog Inputs and Reference
Configurations
The MAX1192 full-scale analog input range is ±V
REF
with a common-mode input range of VDD/2 ±0.2V. V
REF
is the difference between V
REFP
and V
REFN
. The
MAX1192 provides three modes of reference operation.
The voltage at REFIN (V
REFIN
) sets the reference oper-
ation mode (Table 1).
In internal reference mode, connect REFIN to VDDor
leave REFIN unconnected. V
REF
is internally generated
to be 0.512V ±3%. COM, REFP, and REFN are lowimpedance outputs with V
COM
= VDD/2, V
REFP
= VDD/2
+ V
REF
/2, and V
REFN
= VDD/2 - V
REF
/2. Bypass REFP,
REFN, and COM each with a 0.33µF capacitor.
In buffered external reference mode, apply a 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with V
COM
= VDD/2, V
REFP
=
VDD/2 + V
REFIN
/4, and V
REFN
= VDD/2 - V
REFIN
/4.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure 4) and can be driven through separate, external
reference sources. Drive V
COM
to VDD/2 ±10%, drive
V
REFP
to (VDD/2 +0.256V) ±10%, and drive V
REFN
to
(VDD/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM
each with a 0.33µF capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the
Applications Information
section.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and
fall times (<2ns). In particular, sampling occurs on the
rising edge of the clock signal, requiring this edge to
Figure 4. Unbuffered External Reference Mode Impedance
V
REFIN
REFERENCE MODE
>0.8 x V
DD
Internal reference mode. V
REF
is internally generated to be 0.512V. Bypass REFP, REFN, and COM
each with a 0.33µF capacitor.
1.024V ±10%
Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to
REFIN. V
REF
is internally generated to be V
REFIN
/2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
<0.3V
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. V
REF
is the difference between the externally applied V
REFP
and V
REFN
. Bypass REFP,
REFN, and COM each with a 0.33µF capacitor.
Table 1. Reference Modes
MAX1192
1.5V
1.25V
1.75V
62.5μA
0μA
COM
REFN
REFP
4kΩ
4kΩ
62.5μA
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
18 ______________________________________________________________________________________
provide lowest possible jitter. Any significant aperture
jitter would limit the SNR performance of the on-chip
ADCs as follows:
where fINrepresents the analog input frequency and
tAJis the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1192
clock input operates with a VDD/2 voltage threshold
and accepts a 50% ±10% duty cycle (see
Typical
Operating Characteristics
).
System Timing Requirements
Figure 5 shows the relationship between the clock, analog inputs, A/B indicator, and the resulting output data.
Channel A (CHA) and channel B (CHB) are simultaneously sampled on the rising edge of the clock signal
(CLK) and the resulting data is multiplexed at the output. CHA data is updated on the rising edge and CHB
data is updated on the falling edge of the CLK. The A/B
indicator follows CLK with a typical delay time of 6ns
and remains high when CHA data is updated and low
when CHB data is updated. Including the delay
through the output latch, the total clock-cycle latency is
5 clock cycles for CHA and 5.5 clock cycles for CHB.
Digital Output Data (D0–D7),
Channel Data Indicator (A/
BB
)
D0–D7 and A/B are TTL/CMOS-logic compatible. The
digital output coding is offset binary (Table 2, Figure 6).
The capacitive load on the digital outputs D0–D7
should be kept as low as possible (<15pF) to avoid
large digital currents feeding back into the analog portion of the MAX1192 and degrading its dynamic performance. Buffers on the digital outputs isolate them from
SNR
ft
IN AJ
log
=×
×× ×
⎛
⎝
⎜
⎞
⎠
⎟
20
1
2 π
t
DOB
t
CL
t
CH
t
CLK
t
DOA
t
DA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B CHB
D0–D7
D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
Figure 5. System Timing Diagram
Figure 6. Transfer Function
INPUT VOLTAGE (LSB)
-1-126 -125
256
2 x V
REF
1LSB =
V
REF
= V
REFP
- V
REFN
V
REF
V
REF
V
REF
V
REF
0+1-127 +126 +128+127-128 +125
(COM)
(COM)
OFFSET BINARY OUTPUT CODE (LSB)
0000 0000
0000 0001
0000 0010
0000 0011
1111 1111
1111 1110
1111 1101
0111 1111
1000 0000
1000 0001
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 19
heavy capacitive loads. To improve the dynamic performance of the MAX1192, add 100Ω resistors in series
with the digital outputs close to the MAX1192. Refer to
the MAX1193 Evaluation Kit schematic for an example
of the digital outputs driving a digital buffer through
100Ω series resistors.
Power Modes (PD0, PD1)
The MAX1192 has four power modes that are controlled with PD0 and PD1. Four power modes allow the
MAX1192 to efficiently use power by transitioning to a
low-power state when conversions are not required
(Table 3).
Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the
MAX1192 and placing the outputs in tri-state. The
wake-up time from shutdown mode is dominated by the
time required to charge the capacitors at REFP, REFN,
and COM. In internal reference mode and buffered
external reference mode, the wake-up time is typically
20µs. When operating in the unbuffered external reference mode, the wake-up time is dependent on the
external reference drivers. When the outputs transition
from tri-state to on, the last converted word is placed
on the digital outputs.
In standby mode, the reference and clock distribution
circuits are powered up, but the pipeline ADCs are
unpowered and the outputs are in tri-state. The wakeup time from standby mode is dominated by the 5.4µs
required to activate the pipeline ADCs. When the outputs transition from tri-state to on, the last converted
word is placed on the digital outputs.
DIFFERENTIAL INPUT VOLTAGE
(IN+ - IN-)
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(D7–D0)
OUTPUT DECIMAL CODE
+127
(+ full scale - 1 LSB)
1111 1111 255
+126
(+ full scale - 2 LSB)
1111 1110 254
+1 1000 0001 129
0 (bipolar zero) 1000 0000 128
-1 0111 1111 127
-127
(- full scale + 1 LSB)
0000 0001 1
- 128 (- full scale) 0000 0000 0
V
REF
×
127
128
V
REF
×
126
128
V
REF
×
1
128
V
REF
×
0
128
-V
REF
×
1
128
-V
REF
×
127
128
-V
REF
×
128
128
Table 2. Output Codes vs. Input Voltage
PD0 PD1 POWER MODE ADC
INTERNAL
REFERENCE
CLOCK DISTRIBUTION
OUTPUTS
0 0 Shutdown Off Off Off Tri-state
0 1 Standby Off On On Tri-state
1 0 Idle On On On Tri-state
1 1 Normal Operating On On On On
Table 3. Power Logic
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
20 ______________________________________________________________________________________
In idle mode, the pipeline ADCs, reference, and clock
distribution circuits are powered, but the outputs are
forced to tri-state. The wake-up time from idle mode is
dominated by the 5ns required for the output drivers to
start from tri-state. When the outputs transition from tristate to on, the last converted word is placed on the
digital outputs.
In the normal operating mode, all sections of the
MAX1192 are powered.
Applications Information
The circuit of Figure 7 operates from a single 3V supply
and accommodates a wide 0.5V to 1.5V input commonmode voltage range for the analog interface between
an RF quadrature demodulator (differential, DC-coupled signal source) and a high-speed ADC.
Furthermore, the circuit provides required SINAD and
SFDR to demodulate a wideband (BW = 3.84MHz),
QAM-16 communication link. R
ISO
isolates the op amp
output from the ADC capacitive input to prevent ringing
and oscillation. CINfilters high-frequency noise.
MAX1192
INA+
COM
INA-
A
V
= 6V/V
V
COM
= VDD/2
V
COM
= 1V TO 1.5V
V
SIG
= ±85mV
P-P
R
ISO
22Ω
R
ISO
22Ω
R11
600Ω
R9
600Ω
R2
300Ω
OPERATIONAL AMPLIFIERS
CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/
DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT.
CONNECT THE POSITIVE SUPPLY RAIL (V
CC
) TO 3V. CONNECT THE
NEGATIVE SUPPLY RAIL (V
EE
) TO GROUND. DECOUPLE VCC WITH A
0.1μF CAPACITOR TO GROUND.
RESISTOR NETWORKS
RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE
MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S
3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS
VISHAY'S 4R MODEL NUMBER 300197.
R10
600Ω
R8
600Ω
R5
600Ω
R4
600Ω
R7
600Ω
R6
600Ω
C
IN
5pF
C
IN
5pF
R1
600Ω
R3
600Ω
Figure 7. DC-Coupled Differential Input Driver
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 21
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1192 for
optimum performance. Connecting the center tap of the
transformer to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer can be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, can also improve the overall
distortion.
In general, the MAX1192 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for high input frequencies. In
differential input mode, even-order harmonics are lower
as both inputs (INA+, INA- and/or INB+, INB-) are bal-
anced, and each of the ADC inputs only requires half
the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion. Amplifiers such as the MAX4108 provide high
speed, high bandwidth, low noise, and low distortion to
maintain the input signal integrity.
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX1192 reference voltage and allows
multiple converters to use a common reference. To
drive one MAX1192 in buffered external reference
mode, the external circuit must sink 0.7µA, allowing one
reference circuit to easily drive the REFIN of multiple
converters to 1.024V ±10%.
MAX1192
T1
N.C.
V
IN
6
1
5
2
43
22pF
22pF
0.1μF
0.1μF
2.2μF
25Ω
25Ω
MINICIRCUITS
TT1-6-KK81
T1
N.C.
V
IN
6
1
5
2
4
3
22pF
22pF
0.1μF
0.1μF
2.2μF
25Ω
25Ω
MINICIRCUITS
TT1-6-KK81
INA-
INA+
INB-
INB+
COM
Figure 8. Transformer-Coupled Input Drive
MAX1192
0.1μF
1kΩ
1kΩ
100Ω
100Ω
C
IN
22pF
C
IN
22pF
INB+
INB-
COM
INA+
INA-
0.1μF
R
ISO
50Ω
R
ISO
50Ω
REFP
REFN
V
IN
MAX4108
0.1μF
1kΩ
1kΩ
100Ω
100Ω
C
IN
22pF
C
IN
22pF
0.1μF
R
ISO
50Ω
R
ISO
50Ω
REFP
REFN
V
IN
MAX4108
Figure 9. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
22 ______________________________________________________________________________________
Figure
10 shows the MAX6061 precision bandgap reference used as a common reference for multiple converters. The 1.248V output of the MAX6061 is divided
down to 1.023V as it passes through a one-pole, 10Hz,
lowpass filter to the MAX4250. The MAX4250 buffers
the 1.023V reference before its output is applied to the
MAX1192. The MAX4250 provides a low offset voltage
(for high gain accuracy) and a low noise level.
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX1192 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven
directly by a set of external reference sources.
MAX4250
3V
2
4
2
1.248V
3
5
10Hz
LOWPASS
FILTER
1
15Ω
1
REFIN
V
DD
MAX1192
N = 1
24
GND
1.023V
NOTE: ONE FRONT-END REFERENCE
CIRCUIT PROVIDES ±15mA OF OUTPUT
DRIVE AND SUPPORTS OVER
1000 MAX1192s.
3
0.1μF
0.1μF
3V
1μF
1%
20kΩ
1%
90.9kΩ
0.1μF
2.2μF
0.1μF
REFP
27
0.33μF
REFN
26
0.33μF
COM
25
0.33μF
REFIN
V
DD
MAX1192
N = 1000
24
GND
0.1μF
REFP
27
0.33μF
REFN
26
0.33μF
COM
25
0.33μF
MAX6061
Figure 10. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 23
Figure
11 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed
by a 10Hz lowpass filter and precision voltage-divider.
The MAX4254 buffers the taps of this divider to provide
the 1.75V, 1.5V, and 1.25V sources to drive REFP,
REFN, and COM. The MAX4254 provides a low offset
voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference-voltage and amplifier noise to a
level of 3nV/√Hz. The 1.75V and 1.25V reference volt-
ages set the differential full-scale range of the associated ADCs at ±0.5V.
The common power supply for all active components
removes any concern regarding power-supply
sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters support as many as 160 MAX1192s.
MAX4254
1/4
47Ω
3V
2
2
2.500V
3
1
1
REFP
V
DD
MAX1192
N = 1
27
GND
NOTE: ONE FRONT-END
REFERENCE CIRCUIT
SUPPORTS UP TO 160 MAX1192s
3
0.1μF
10μF
6V
1μF
1%
30.1kΩ
1%
10.0kΩ
0.1μF
2.2μF
330μF
6V
0.33μF
26
24
0.33μF
REFN
REFIN
REFIN
25
0.33μF
COM
MAX6066
1.748V
1%
10.0kΩ
1%
49.9kΩ
REFP
V
DD
MAX1192
N = 160
27
GND
0.33μF
26
24
0.33μF
REFN
25
0.33μF
COM
1.47kΩ
MAX4254
47Ω
6
5
7
10μF
6V
330μF
6V
1.498V
1.47kΩ
47Ω
9
10
8
10μF
6V
330μF
6V
1.248V
MAX4254
1.47kΩ
1MΩ
MAX4254
13
12
14
11
4
0.1μF
UNCOMMITTED
1MΩ
3V
1/4
1/4
1/4
Figure 11. External Unbuffered Reference Driving 160 ADCs with MAX4254 and MAX6066
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
24 ______________________________________________________________________________________
Typical QAM Demodulation Application
Quadrature amplitude modulation (QAM) is frequently
used in digital communications. Typically found in
spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the baseband
signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the
QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is
90° phase shifted with respect to the in-phase component. At the receiver, the QAM signal is demodulated
into analog I and Q components. Figure 12 displays the
demodulation process performed in the analog domain
using the MAX1192 dual-matched, 3V, 8-bit ADC and
the MAX2451 quadrature demodulator to recover and
digitize the I and Q baseband signals. Before being digitized by the MAX1192, the mixed-down signal components can be filtered by matched analog filters, such as
Nyquist or pulse-shaping filters. The filters remove
unwanted images from the mixing process, thereby
enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.
Grounding, Bypassing,
and Board Layout
The MAX1192 requires high-speed board layout design
techniques. Refer to the MAX1193 Evaluation Kit data
sheet for a board layout reference. Locate all bypass
capacitors as close to the device as possible, prefer-
ably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass V
DD
to
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF bipolar capacitor. Bypass OVDDto OGND with a
0.1µF ceramic capacitor in parallel with a 2.2µF bipolar
capacitor. Bypass REFP, REFN, and COM each to
GND with a 0.33µF ceramic capacitor.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity. Use
a split ground plane arranged to match the physical
location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC’s package.
Connect the MAX1192 exposed backside paddle to
GND. Join the two ground planes at a single point such
that the noisy digital ground currents do not interfere
with the analog ground plane. The ideal location of this
connection can be determined experimentally at a
point along the gap between the two ground planes,
which produces optimum results. Make this connection
with a low-value, surface-mount resistor (1Ω to 5Ω), a
ferrite bead, or a direct short. Alternatively, all ground
pins could share the same ground plane, if the ground
plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or
DSP ground plane).
Route high-speed digital signal traces away from the
sensitive analog traces of either channel. Make sure to
isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep
all signal lines short and free of 90° turns.
0°
90°
÷
8
DOWNCONVERTER
MAX2451
INA+
MAX1192
INA-
INB+
INB-
DSP
POST-
PROCESSING
A/B
Figure 12. Typical QAM Receiver Application
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
______________________________________________________________________________________ 25
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static linearity parameters for the MAX1192 are measured using
the end-point method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
Ideally, the midscale MAX1192 transition occurs at 0.5
LSB above midscale. The offset error is the amount of
deviation between the measured transition point and
the ideal transition point.
Gain Error
Ideally, the full-scale MAX1192 transition occurs at 1.5
LSB below full-scale. The gain error is the amount of
deviation between the measured transition point and
the ideal transition point with the offset error removed.
Dynamic Parameter Definitions
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (
Figure 13).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02 × N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
the fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
for a full-scale sinusoidal input waveform is computed
from:
ENOB
SINAD
.
.
=
-176
602
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
Figure 13. T/H Aperture Timing
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
26 ______________________________________________________________________________________
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2–V6are
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ±f2), (2 x f1), (2 x f2), (2 x f1 ±f2), (2 x f2
±f1). The individual input tone levels are at -7dB FS.
Third-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodulation product relative to the input power of either input
tone when two tones, f1 and f2, are present at the
inputs. The third-order intermodulation products are (2
x f1 ±f2), (2 x f2 ±f1). The individual input tone levels
are at -7dB FS.
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supplies are moved ±5%.
Small-Signal Bandwidth
A small -20dB FS analog input signal is applied to an
ADC in such a way that the signal’s slew rate will not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Chip Information
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 TQFN-EP T2855-3
21-0140
⎡
2
THD
log
20
=×
VVVVV
2
⎢
⎢
⎢
⎣
2
++++
3
2
4
V
1
2
5
⎤
2
6
⎥
⎥
⎥
⎦
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
27
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
2 7/09 Changed orientation of Maxim logo in Pin Configuration diagram 1
REVISION
NUMBER
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