General Description
The MAX1190 is a 3.3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1190 is
optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumentation,
and digital communications. This ADC operates from a
single 3.1V to 3.6V supply, consuming only 492mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 57dB at an input frequency of 60MHz and a sampling
rate of 120Msps. The T/H driven input stages incorporate
400MHz (-3dB) input amplifiers. The converters can also
be operated with single-ended inputs. In addition to low
operating power, the MAX1190 features a 3mA sleep
mode, as well as a 1µA power-down mode to conserve
power during idle periods.
An internal 2.048V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure
allows the use of this internal or an externally applied reference, if desired, for applications requiring increased
accuracy or a different input voltage range.
The MAX1190 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s
complement or straight offset binary through a single control pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1190 is available in a 7mm ✕
7mm, 48-pin TQFP-EP package, and is specified for the
extended industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1190 are
also available. Refer to the MAX1180–MAX1184 data
sheets for 105Msps/80Msps/65Msps/40Msps. In addition
to these speed grades, this family includes two multiplexed output versions (MAX1185/MAX1186 for
20Msps/40Msps), for which digital data is presented timeinterleaved and on a single, parallel 10-bit output port.
For lower speed, pin-compatible, 8-bit versions of the
MAX1190, refer to the MAX1195–MAX1198 data sheets.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Features
♦ Single 3.3V Operation
♦ Excellent Dynamic Performance
57dB SINAD at fIN= 60MHz
64dBc SFDR at fIN= 60MHz
♦ -71dBc Interchannel Crosstalk at fIN= 60MHz
♦ Low Power
492mW (Normal Operation)
10mW (Sleep Mode)
3.3µW (Shutdown Mode)
♦ 0.08dB Gain and 0.8° Phase Matching
♦ Wide ±1V
P-P
Differential Analog Input Voltage
Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s Complement
or Offset Binary
♦ Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit
Versions Available
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2524; Rev 1; 6/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
PKG CODE
MAX1190ECM
48 TQFP-EP*
C48E-7
MAX1190ECM+
48 TQFP-EP*
C48E-7
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
COM
V
DD
GND
INA+
INA-
V
DD
GND
INBINB+
GND
V
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP-EP
GND
V
DD
GND
V
DD
T/B
SLEEP
PD
OE
D9B
D8B
D7B
D6B
1314151617181920212223
24
4847464544434241403938
37
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
MAX1190
EP
Pin Configuration
*EP = Exposed paddle.
+Denotes lead-free package.
EP = EXPOSED PADDLE.
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A “+”.
-40°C to +85°C
-40°C to +85°C
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (VDD+ 0.3V)
OE, PD, SLEEP, T/B,
D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ..2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL fIN = 7.47MHz
±3 LSB
Differential Nonlinearity DNL
f
IN
= 7.47MHz, no missing codes
guaranteed
LSB
Offset Error
%FS
Gain Error 0 ±2
%FS
ANALOG INPUT
Differential Input Voltage Range V
DIFF
Differential or single-ended inputs
V
Common-Mode Input Voltage
Range
V
CM
V
Input Resistance R
IN
Switched capacitor load 20 kΩ
Input Capacitance C
IN
5pF
CONVERSION RATE
Maximum Clock Frequency f
CLK
MHz
Data Latency 5
Clock
Cycles
DYNAMIC CHARACTERISTICS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
55
f
INA or B
= 30.09MHz at -0.5dBFS
Signal-to-Noise Ratio SNR
f
INA or B
= 59.74MHz at -0.5dBFS 58
dB
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS 57
Signal-to-Noise and Distortion SINAD
f
INA or B
= 59.74MHz at -0.5dBFS 57
dB
SYMBOL
MIN TYP MAX
±0.75
-1.0 ±0.4 +1.5
< ±1 ±1.8
±1.0
VDD / 2
± 0.5
120
58.5
54.5 57.5
58.2
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
58 67
f
INA or B
= 30.09MHz at -0.5dBFS 67
Spurious-Free Dynamic Range SFDR
f
INA or B
= 59.74MHz at -0.5dBFS 64
dBc
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
-67
f
INA or B
= 30.09MHz at -0.5dBFS -67
Third-Harmonic
Distortion
HD3
f
INA or B
= 59.74MHz at -0.5dBFS -64
dBc
Intermodulation Distortion
(First Five Odd-Order IMDs)
IMD
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
-73 dBc
Third-Order Intermodulation
Distortion
IM3
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
-83 dBc
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
-65 -58
f
INA or B
= 30.09MHz at -0.5dBFS -65
Total Harmonic Distortion
(First Four Harmonics)
THD
f
INA or B
= 59.74MHz at -0.5dBFS -63
dBc
Small-Signal Bandwidth Input at -20dBFS, differential inputs
MHz
Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs
MHz
Aperture Delay t
AD
1ns
Aperture Jitter t
AJ
2
ps
RMS
Overdrive Recovery Time For 1.5× full-scale input 2 ns
INTERNAL REFERENCE
Reference Output Voltage
V
Load Regulation
mV/mA
Reference Temperature
Coefficient
TC
REF
60
ppm/°C
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
Positive Reference Output
Voltage
V
REFP
(Note 2)
V
Negative Reference Output
Voltage
V
REFN
(Note 2)
V
Common-Mode Level V
COM
(Note 2)
V
Differential Reference Output
Voltage Range
ΔV
REF
ΔV
REF
= V
REFP
- V
REFN
V
REFIN Resistance R
REFIN
MΩ
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
500
400
V
REFOUT
2.048
±3%
1.25
2.162
1.138
1.651
0.95 1.024 1.09
> 50
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
4 _______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
5mA
Maximum REFP, COM Sink
Current
I
SINK
µA
Maximum REFN Source Current
µA
Maximum REFN Sink Current I
SINK
-5 mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
R
REFP
,
R
REFN
Measured between REFP and COM, and
REFN and COM
3.4 kΩ
Differential Reference Input
Voltage Range
ΔV
REF
ΔV
REF
= V
REFP
- V
REFN
1.024
±10%
V
COM Input Voltage Range V
COM
V
REFP Input Voltage V
REFP
V
REFN Input Voltage V
REFN
V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8 ×
Input High Threshold V
IH
PD, OE, SLEEP, T/B
0.8 ×
V
CLK
0.2 ×
Input Low Threshold V
IL
PD, OE, SLEEP, T/B
0.2 ×
V
Input Hysteresis V
HYST
0.1 V
VIH = VDD (CLK) ±5
I
IH
VIH = OVDD (PD, OE, SLEEP, T/B) ±5Input Leakage
I
IL
VIL = 0 ±5
µA
Input Capacitance C
IN
5pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output-Voltage Low V
OL
I
SINK
= -200µA 0.2 V
Output-Voltage High V
OH
I
SOURCE
= 200µA
OV
DD
-
0.2
V
Three-State Leakage Current I
LEAK
OE = OV
DD
±10 µA
C
OUT
OE = OV
DD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range V
DD
3.1 3.3 3.6 V
Output Supply Voltage Range OV
DD
1.7 2.5 3.6 V
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
I
SOURCE
I
SOURCE
-250
250
VDD / 2 ± 10%
V
COM
V
COM
V
DD
OV
DD
+ ΔV
- ΔV
REF
REF
/ 2
/ 2
V
DD
OV
DD
Three-State Output Capacitance
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Note 3: Digital outputs settle to V
IH
, VIL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
185
Sleep mode 3
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
115µA
Op er ati ng , f
IN A and B
= 20.01M H z at - 0.5d BFS ;
see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
16 mA
Sleep mode
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
210
µA
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
611
Sleep mode 10
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
3.3 50 µW
Offset, VDD ±5%
mV/V
Power-Supply Rejection Ratio PSRR
Gain, V
DD
±5%
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
DO
CL = 20pF (Note 3)
7.4 ns
OE Fall to Output Enable Time
ns
OE Rise to Output Disable Time
ns
CLK Pulse-Width High t
CH
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
ns
CLK Pulse-Width Low t
CL
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
ns
Wake up from sleep mode (Note 4)
Wake-Up Time t
WAKE
Wake up from shutdown mode (Note 4)
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f
INA or B
= 20.01MHz at -0.5dBFS
dBc
Gain Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 5)
dB
Phase Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 6)
Degrees
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
t
ENABLE
t
DISABLE
149
100
492
±3.4
±0.81
4.8
4.7
1.2
4.17
4.17
0.65
1.2
-71
0.08 ±0.2
0.8
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc01a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 20.0119MHz
f
INB
= 12.9799MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHA
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc01b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
CHB
f
INA
= 12.9799MHz
f
INB
= 20.0119MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
f
INB
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc02a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
CHA
f
INA
= 31.0873MHz
f
INB
= 23.9967MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc02b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 23.9967MHz
f
INB
= 31.0873MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHB
f
INB
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc03a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 59.7427MHz
f
INB
= 49.0189MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHA
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc03b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 49.0189MHz
f
INB
= 59.7427MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHB
f
INB
TWO-TONE IMD PLOT
(8192-POINT RECORD)
MAX1190 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
IN1
= 43.3933MHz
f
IN2
= 48.9017MHz
f
CLK
= 120.0128MHz
A
IN
= -6.5dBFS
f
IN1
f
IN2
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1190 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
52
54
56
58
60
50
CHB
CHA
100
80
604020
90
70
503010
0
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1190 toc06
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
100
80
604020
90
70
503010
52
54
56
58
60
50
0
CHA
CHB
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 7
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1190 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
-72
-64
-56
-48
-40
-80
CHA
CHB
100
80
604020
90
70
503010
0
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1190 toc08
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
48
56
64
72
80
40
CHB
CHA
100
80
604020
90
70
503010
0
SNR/SINAD, -THD/SFDR
vs. CLOCK DUTY CYCLE
MAX1190 toc09
CLOCK DUTY CYCLE (%)
SNR/SINAD, -THD/SFDR (dB, dBc)
56524844
20
40
60
80
100
0
40 60
SFDR
SINAD
f
INA/B
= 20.02536MHz
SNR
-THD
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1190 toc10
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-7
-4
-1
2
5
-10
11000
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1190 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-6
-4
-2
0
2
4
6
-8
11000
VIN = 100mV
P-P
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc13
ANALOG INPUT POWER (dBFS)
SINAD (dB)
-4-8-12-16
44
48
52
56
60
40
-20 0
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc14
ANALOG INPUT POWER (dBFS)
THD (dBc)
-4-8-12-16
-74
-68
-62
-56
-50
-80
-20 0
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc15
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
-4-8-12-16
56
62
68
74
80
50
-20 0
Typical Operating Characteristics (continued)
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc12
ANALOG INPUT POWER (dBFS)
SNR (dB)
-4-8-12-16
44
48
52
56
60
40
-20 0
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
8 _______________________________________________________________________________________
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1190 toc16
DIGITAL OUTPUT CODE
INL (LSB)
341 682
-0.2
-0.4
0.2
0.6
0
0.4
-0.6
0 1023
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1190 toc17
DIGITAL OUTPUT CODE
DNL (LSB)
341 6820 1023
-0.1
-0.2
0.1
0
0.3
0.2
-0.3
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE
MAX1190 toc18
TEMPERATURE (°C)
GAIN ERROR (%FS)
603510-15
-0.1
0.1
0.3
0.5
-0.3
-40 85
CHB
CHA
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE
MAX1190 toc19
TEMPERATURE (°C)
OFFSET ERROR (%FS)
603510-15
-0.7
-0.2
0.3
0.8
-1.2
-40 85
CHB
CHA
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1190 toc20
TEMPERATURE (°C)
I
VDD
(mA)
603510-15
130
140
150
160
170
180
120
-40 85
DIGITAL SUPPLY CURRENT
vs. ANALOG INPUT FREQUENCY
MAX1190 toc21
ANALOG INPUT FREQUENCY (MHz)
I
OVDD
(mA)
54484236302418126
5
10
15
20
25
30
0
060
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAx1190 toc22
TEMPERATURE (°C)
V
REFOUT
(V)
603510-15
2.014
2.018
2.022
2.026
2.030
2.034
2.038
2.010
-40 85
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1190 toc23
VDD (V)
V
REFOUT
(V)
3.453.303.153.002.85
2.020
2.025
2.030
2.035
2.015
2.70 3.60
Typical Operating Characteristics (continued)
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 9
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = -40°C)
MAX1190 toc24
ANALOG INPUT POWER (dBFS)
SNR (dB)
-5-10-15-20
40
45
50
55
60
35
-25 0
3.1V
3.3V
3.6V
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +25°C)
MAX1190 toc25
ANALOG INPUT POWER (dBFS)
SNR (dB)
-5-10-15-20
40
45
50
55
60
35
-25 0
3.1V
3.3V
3.6V
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +85°C)
MAX1190 toc26
ANALOG INPUT POWER (dBFS)
SNR (dB)
-5-10-15-20
40
45
50
55
60
35
-25 0
3.1V
3.3V
3.6V
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = -40°C)
MAX1190 toc27
ANALOG INPUT POWER (dBFS)
THD (dBc)
-5-10-15-20
-65
-60
-55
-50
-45
-70
-25 0
3.1V
3.3V
3.6V
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +25°C)
MAX1190 toc28
ANALOG INPUT POWER (dBFS)
THD (dBc)
-5-10-15-20
-65
-60
-55
-50
-45
-70
-25 0
3.1V
3.3V
3.6V
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +85°C)
MAX1190 toc29
ANALOG INPUT POWER (dBFS)
THD (dBc)
-5-10-15-20
-65
-60
-55
-50
-45
-70
-25 0
3.1V
3.3V
3.6V
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = -40°C)
MAX1190 toc30
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
-5-10-15-20
55
60
65
70
75
45
50
-25 0
3.6V
3.1V
3.3V
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +25°C)
MAX1190 toc31
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
-5-10-15-20
55
60
65
70
75
45
50
-25 0
3.6V
3.3V
3.1V
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
(f
IN
= 20MHz, TA = +85°C)
MAX1190 toc32
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
-5-10-15-20
55
60
65
70
75
45
50
-25 0
3.6V
3.3V
3.1V
Typical Operating Characteristics (continued)
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 COM Common-Mode Voltage I/O. Bypass to GND with a ≥ 0.1µF capacitor.
2, 6, 11,
14, 15
V
DD
Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog supply accepts
a 3.1V to 3.6V input range.
3, 7, 10,
13, 16
GND Analog Ground
4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
12 CLK Converter Clock Input
17 T/B
T/B selects the ADC Digital Output Format:
High: Two’s complement
Low: Straight offset binary
18 SLEEP
Sleep-Mode Input:
High: Disables both quantizers, but leaves the reference bias circuit active
Low: Normal operation
19 PD
High-Active Power-Down Input:
High: Power-down mode
Low: Normal operation
20 OE
Low-Active Output Enable Input:
High: Digital outputs disabled
Low: Digital outputs enabled
21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B
22 D8B Three-State Digital Output, Bit 8, Channel B
23 D7B Three-State Digital Output, Bit 7, Channel B
24 D6B Three-State Digital Output, Bit 6, Channel B
25 D5B Three-State Digital Output, Bit 5, Channel B
26 D4B Three-State Digital Output, Bit 4, Channel B
27 D3B Three-State Digital Output, Bit 3, Channel B
28 D2B Three-State Digital Output, Bit 2, Channel B
29 D1B Three-State Digital Output, Bit 1, Channel B
30 D0B Three-State Digital Output, Bit 0, Channel B
31, 34 OGND Output Driver Ground
32, 33 OV
DD
Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output driver
supply accepts a 1.7V to 3.6V input range.
35 D0A Three-State Digital Output, Bit 0, Channel A
36 D1A Three-State Digital Output, Bit 1, Channel A
37 D2A Three-State Digital Output, Bit 2, Channel A
38 D3A Three-State Digital Output, Bit 3, Channel A
39 D4A Three-State Digital Output, Bit 4, Channel A
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 11
Detailed Description
The MAX1190 uses a nine-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by 2, and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages.
Input Track-and-Hold Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuits sample the input
signals onto the two capacitors (C2a and C2b) through
switches S4a and S4b. S2a and S2b set the common
mode for the amplifier input, and open simultaneously
with S1, sampling the input waveform. Switches S4a,
S4b, S5a, and S5b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier and switch S4c is closed. The
resulting differential voltages are held on capacitors
C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on
C2a and C2b.
Pin Description (continued)
PIN NAME FUNCTION
40 D5A Three-State Digital Output, Bit 5, Channel A
41 D6A Three-State Digital Output, Bit 6, Channel A
42 D7A Three-State Digital Output, Bit 7, Channel A
43 D8A Three-State Digital Output, Bit 8, Channel A
44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A
45
Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.
46 REFIN Reference Input. V
REFIN
= 2 × (V
REFP
- V
REFN
). Bypass to GND with a > 0.1µF capacitor.
47 REFP Positive Reference I/O. Conversion range is ±(V
REFP
- V
REFN
). Bypass to GND with a > 0.1µF capacitor.
48 REFN
Negative Reference I/O. Conversion range is ±(V
REFP
- V
REFN
). Bypass to GND with a > 0.1µF capacitor.
— EP Exposed Paddle. Connect to analog ground.
Figure 1. Pipelined Architecture—Stage Blocks
REFOUT
2-BIT FLASH
ADC
STAGE 8
STAGE 9
STAGE 1 STAGE 2
DIGITAL ALIGNMENT LOGIC
T/H
V
INA
10
D9A–D0A
V
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
INA
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
V
INB
STAGE 1 STAGE 2
DIGITAL ALIGNMENT LOGIC
T/H
V
INB
10
D9B–D0B
2-BIT FLASH
ADC
STAGE 8 STAGE 9
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
12 ______________________________________________________________________________________
These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing
inputs. The wide input bandwidth T/H amplifiers allow the
MAX1190 to track and sample/hold analog inputs of high
frequencies (> Nyquist). Both ADC inputs (INA+, INB+,
INA- and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as
well as INB+ and INB-, and set the common-mode voltage to midsupply (V
DD
/ 2) for optimum performance.
S3b
S3a
COM
S5b
S5a
INB+
INB-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLD
HOLD
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
TRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
INA+
INA-
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX1190
Figure 2. MAX1190 T/H Amplifiers
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 13
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1190 is determined by the
internally generated voltage difference between REFP
(VDD/ 2 + V
REFIN
/ 4) and REFN (VDD/ 2 - V
REFIN
/ 4).
The full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
The MAX1190 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a > 10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a > 10kΩ resistor.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high-impedance inputs and can be
driven through separate, external reference sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
The MAX1190’s CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows:
where fINrepresents the analog input frequency and t
AJ
is the time of the aperture jitter. Clock jitter is especially
critical for undersampling applications. The clock input
should always be considered as an analog input and
routed away from any analog input or other digital signal
lines. The MAX1190 clock input operates with a voltage
threshold set to V
DD
/ 2. Clock inputs with a duty cycle
other than 50%, must meet the specifications for high and
low periods as stated in the Electrical Characteristics.
SNR
ft
IN AJ
=×
×× ×
⎛
⎝
⎜
⎞
⎠
⎟
20
1
2
log
π
N - 6
N
N - 5
N + 1
N - 4
N + 2
N - 3
N + 3
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 1
5-CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
D9A–D0A
t
DO
t
CH
t
CL
N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1
DATA OUTPUT
D9B–D0B
t
AD
Figure 3. System Timing Diagram
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
14 ______________________________________________________________________________________
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1190
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data (D0A/B–D9A/B), Output
Data Format Selection (T/B), Output
Enable (
OE
)
All digital outputs, D0A–D9A (channel A) and D0B–D9B
(channel B), are TTL/CMOS-logic compatible. There is
a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capacitive load on digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (< 15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1190, thereby degrading its
dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1190, small series
resistors (e.g., 100Ω) can be added to the digital output
paths, close to the MAX1190.
Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wakeup and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1190 offers two power-save modes—sleep
mode and full power-down mode. In sleep mode
(SLEEP = 1), only the reference bias circuit is active
(both ADCs are disabled), and current consumption is
reduced to 3mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a VDD/ 2 output voltage for levelshifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed operational amplifiers. The
user can select the R
ISO
and CINvalues to optimize the
filter performance to suit a particular application. For
the application in Figure 5, a R
ISO
of 50Ω is placed
before the capacitive load to prevent ringing and oscillation. The 22pF CINcapacitor acts as a small filter
capacitor.
OUTPUT
D9A–D0A
OE
t
DISABLE
t
ENABLE
HIGH IMPEDANCEHIGH IMPEDANCE
VALID DATA
OUTPUT
D9B–D0B
HIGH IMPEDANCEHIGH IMPEDANCE
VALID DATA
Figure 4. Output Timing Diagram
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
T/B = 0
TWO’S COMPLEMENT
T/B = 1
V
REF
× 512/512 +FULL SCALE - 1 LSB 11 1111 1111 01 1111 1111
V
REF
× 1/512 +1 LSB 10 0000 0001 00 0000 0001
0 Bipolar Zero 10 0000 0000 00 0000 0000
-V
REF
× 1/512 -1 LSB 01 1111 1111 11 1111 1111
-V
REF
× 511/512 -FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001
-V
REF
× 512/512 -FULL SCALE 00 0000 0000 10 0000 0000
Table 1. MAX1190 Output Codes For Differential Inputs
*V
REF
= V
REFP
- V
REFN
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 15
INPUT
300Ω
-5V
+5V
0.1μF
0.1μF
0.1μF
-5V
600Ω
300Ω
INA-
INA+
LOWPASS FILTER
COM
600Ω
+5V
-5V
0.1μF
600Ω
300Ω
600Ω
300Ω
0.1μF
0.1μF
0.1μF
+5V
0.1μF
300Ω
MAX4108
MAX1190
INB-
INB+
MAX4108
MAX4108
LOWPASS FILTER
INPUT
300Ω
-5V
+5V
0.1μF
0.1μF
0.1μF
C
IN
22pF
-5V
600Ω
300Ω
LOWPASS FILTER
600Ω
+5V
-5V
0.1μF
600Ω
300Ω
600Ω
300Ω
0.1μF
0.1μF
0.1μF
+5V
0.1μF
300Ω
MAX4108
MAX4108
MAX4108
LOWPASS FILTER
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω
C
IN
22pF
R
IS0
50Ω
300Ω
300Ω
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
16 ______________________________________________________________________________________
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1190 for optimum
performance. Connecting the center tap of the transformer to COM provides a V
DD
/ 2 DC level shift to the
input. Although a 1:1 transformer is shown, a step-up
transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such
as an op amp, can also improve the overall distortion.
In general, the MAX1190 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1190 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source.
A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and
exhibits a noise voltage density of 150nV/√Hz. Its output
passes through a 1-pole lowpass filter (with 10Hz cutoff
frequency) to the MAX4250, which buffers the reference
before its output is applied to a second 10Hz lowpass
filter. The MAX4250 provides a low offset voltage (for
MAX1190
T1
N.C.
V
IN
6
1
5
2
43
22pF
22pF
0.1μF
0.1μF
2.2μF
25Ω
25Ω
MINICIRCUITS
TT1–6-KK81
T1
N.C.
V
IN
6
1
5
2
4
3
22pF
22pF
0.1μF
0.1μF
2.2μF
25Ω
25Ω
MINICIRCUITS
TT1-6-KK81
INA-
INA+
INB-
INB+
COM
Figure 6. Transformer-Coupled Input Drive
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 17
high-gain accuracy) and a low noise level. The passive
10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This
filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision-ADC operation.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider, the MAX6066
generates a DC level of 2.500V. The buffered outputs of
this divider are set to 2.0V, 1.5V, and 1.0V, with an
accuracy that depends on the tolerance of the divider
resistors (Figure 9).
Those three voltages are buffered by the MAX4252,
which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass
filters, which filter both the reference voltage and amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the
associated ADCs at 2V
P-P
. The 2.0V and 1.0V buffers
drive the ADCs’ internal ladder resistances between
them. Note that the common power supply for all active
components removes any concern regarding powersupply sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications that require more than 32 matched ADCs,
a voltage reference and divider string common to all
converters is highly recommended.
MAX1190
0.1μF
1kΩ
1kΩ
100Ω
100Ω
C
IN
22pF
C
IN
22pF
INB+
INB-
COM
INA+
INA-
0.1μF
R
ISO
50Ω
R
ISO
50Ω
REFP
REFN
V
IN
MAX4108
0.1μF
1kΩ
1kΩ
100Ω
100Ω
C
IN
22pF
C
IN
22pF
0.1μF
R
ISO
50Ω
R
ISO
50Ω
REFP
REFN
V
IN
MAX4108
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
18 ______________________________________________________________________________________
Typical QAM Demodulation Application
A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread-spectrum-based
systems, a QAM signal represents a carrier frequency
modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature
outputs, a local oscillator followed by subsequent
upconversion can generate the QAM signal. The result
is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90° phase shifted with
respect to the in-phase component. At the receiver, the
QAM signal is divided down into its I and Q components,
essentially representing the modulation process
reversed. Figure 10 displays the demodulation process
performed in the analog domain, using the dual-matched
3.3V, 10-bit ADC MAX1190 and the MAX2451 quadrature
demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1190,
the mixed-down signal components can be filtered by
matched analog filters, such as Nyquist or pulse-shaping
filters, which remove unwanted images from the mixing
process, thereby enhancing the overall SNR performance and minimizing intersymbol interference.
MAX4250
MAX6062
16.2kΩ
162Ω
3.3V
2
4
2
3
5
10Hz LOWPASS
FILTER
10Hz LOWPASS
FILTER
1
1
REFOUT
REFP
REFIN
1μF
MAX1190
N = 1
REFN
29N.C.
2.048V
N.C.
31
32
1
2
29
31
32
1
2
COM
REFOUT
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
REFP
REFIN
MAX1190
N = 1000
REFN
COM
3
0.1μF
0.1μF
3.3V
0.1μF0.1μF0.1μF
0.1μF
0.1μF
2.2μF
10V
0.1μF0.1μF
0.1μF
100μF
0.1μF
Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 19
1/4 MAX4252
MAX6066
1/4 MAX4252
1/4 MAX4252
1.47kΩ
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
21.5kΩ
47Ω
3.3V
3.3V
11
2
2
3
4
1
1
REFOUT
REFP
REFIN
1μF
10μF
6V
MAX1190
N = 1
REFN
29N.C.
N.C.
31
32
1
2
29
31
32
1
2
COM
REFOUT
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
REFP
REFIN
MAX1190
N = 32
REFN
COM
2.0V AT 8mA
3
0.1μF
0.1μF
MAX4254 POWER-SUPPLY
BYPASSING. PLACE CAPACITOR
AS CLOSE AS POSSIBLE TO
THE OP AMP.
3.3V
1.47kΩ
47Ω
3.3V
1.5V
11
6
5
4
7
10μF
6V
1.5V AT 0mA
1.47kΩ
47Ω
3.3V
11
9
10
4
8
10μF
6V
0.1μF0.1μF0.1μF
0.1μF
0.1μF
2.2μF
10V
0.1μF0.1μF
1.0V AT -8mA
330μF
6V
330μF
6V
330μF
6V
2.0V
1.0V
Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066
0°
90°
÷
8
DOWNCONVERTER
MAX2451
INA+
MAX1190
INA-
INB+
INB-
DSP
POST-
PROCESSING
Figure 10. Typical QAM Application Using the MAX1190
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
20 ______________________________________________________________________________________
Grounding, Bypassing, and
Board Layout
The MAX1190 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to the
device as possible, preferably on the same side as the
ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two
parallel 0.1µF ceramic capacitors and a 2.2µF bipolar
capacitor to GND. Follow the same rules to bypass the
digital supply (OVDD) to OGND. Multilayer boards with
separated ground and power planes produce the
highest level of signal integrity. Consider the use of a split
ground plane arranged to match the physical location of
the analog ground (GND) and the digital output driver
ground (OGND) on the ADC’s package. The two ground
planes should be joined at a single point such that the
noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection
can be determined experimentally at a point along the
gap between the two ground planes, which produces
optimum results. Make this connection with a low-value,
surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a
direct short. Alternatively, all ground pins could share the
same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate the
analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines
short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity
parameters for the MAX1190 are measured using the
best-straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error
specification of less than 1 LSB guarantees no missing
codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02
dB
✕ N + 1.76
dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ENOB
SINAD=−
⎛
⎝
⎜
⎞
⎠
⎟
176
602..
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
t
AD
t
AJ
TRACK TRACK
CLK
Figure 11. T/H Aperture Timing
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
______________________________________________________________________________________ 21
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are
at -6.5dB full scale and their envelope is at -0.5dB full
scale.
THD
VVVV
V
=×
+++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20
2
2
3
2
4
2
5
2
1
log
GND
REFERENCE
OUTPUT
DRIVERS
CONTROL
T/H
T/H
ADC
DEC
OUTPUT
DRIVERS
REFOUT
REFN
COM
REFP
REFIN
INA+
INA-
CLK
INB+
INB-
V
DD
DEC
ADC
OGND
OV
DD
D9A–D0A
OE
D9B–D0B
T/B
PD
SLEEP
MAX1190
10
10
10
10
Functional Diagram
Revision History
Pages changed at Rev 1: 1–15, 17, 19, 20, 21.
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
48L,TQFP.EPS
G
1
2
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
G
2
2
21-0065
PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION
MAX1190 Package Code: C48E-7
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