MAXIM MAX1190 Technical data
General Description
The MAX1190 is a 3.3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1190 is
optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumentation,
and digital communications. This ADC operates from a
single 3.1V to 3.6V supply, consuming only 492mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 57dB at an input frequency of 60MHz and a sampling
rate of 120Msps. The T/H driven input stages incorporate
400MHz (-3dB) input amplifiers. The converters can also
be operated with single-ended inputs. In addition to low
operating power, the MAX1190 features a 3mA sleep
mode, as well as a 1µA power-down mode to conserve
power during idle periods.
An internal 2.048V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference structure
allows the use of this internal or an externally applied reference, if desired, for applications requiring increased
accuracy or a different input voltage range.
The MAX1190 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s
complement or straight offset binary through a single control pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1190 is available in a 7mm ✕
7mm, 48-pin TQFP-EP package, and is specified for the
extended industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1190 are
also available. Refer to the MAX1180–MAX1184 data
sheets for 105Msps/80Msps/65Msps/40Msps. In addition
to these speed grades, this family includes two multiplexed output versions (MAX1185/MAX1186 for
20Msps/40Msps), for which digital data is presented timeinterleaved and on a single, parallel 10-bit output port.
For lower speed, pin-compatible, 8-bit versions of the
MAX1190, refer to the MAX1195–MAX1198 data sheets.
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Features
♦ Single 3.3V Operation
♦ Excellent Dynamic Performance
57dB SINAD at fIN= 60MHz
64dBc SFDR at fIN= 60MHz
♦ -71dBc Interchannel Crosstalk at fIN= 60MHz
♦ Low Power
492mW (Normal Operation)
10mW (Sleep Mode)
3.3µW (Shutdown Mode)
♦ 0.08dB Gain and 0.8° Phase Matching
♦ Wide ±1V
P-P
Differential Analog Input Voltage
Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s Complement
or Offset Binary
♦ Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit
Versions Available
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2524; Rev 1; 6/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Functional Diagram appears at end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
PKG CODE
MAX1190ECM
48 TQFP-EP*
C48E-7
MAX1190ECM+
48 TQFP-EP*
C48E-7
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
COM
V
DD
GND
INA+
INA-
V
DD
GND
INBINB+
GND
V
DD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
TQFP-EP
GND
V
DD
GND
V
DD
T/B
SLEEP
PD
OE
D9B
D8B
D7B
D6B
1314151617181920212223
24
4847464544434241403938
37
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
MAX1190
EP
Pin Configuration
*EP = Exposed paddle.
+Denotes lead-free package.
EP = EXPOSED PADDLE.
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGES IS REPLACED BY A “+”.
-40°C to +85°C
-40°C to +85°C
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (VDD+ 0.3V)
OE, PD, SLEEP, T/B,
D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 30.4mW/°C above +70°C) ..2430mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL fIN = 7.47MHz
±3 LSB
Differential Nonlinearity DNL
f
IN
= 7.47MHz, no missing codes
guaranteed
LSB
Offset Error
%FS
Gain Error 0 ±2
%FS
ANALOG INPUT
Differential Input Voltage Range V
DIFF
Differential or single-ended inputs
V
Common-Mode Input Voltage
Range
V
CM
V
Input Resistance R
IN
Switched capacitor load 20 kΩ
Input Capacitance C
IN
5pF
CONVERSION RATE
Maximum Clock Frequency f
CLK
MHz
Data Latency 5
Clock
Cycles
DYNAMIC CHARACTERISTICS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
55
f
INA or B
= 30.09MHz at -0.5dBFS
Signal-to-Noise Ratio SNR
f
INA or B
= 59.74MHz at -0.5dBFS 58
dB
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
f
INA or B
= 30.09MHz at -0.5dBFS 57
Signal-to-Noise and Distortion SINAD
f
INA or B
= 59.74MHz at -0.5dBFS 57
dB
SYMBOL
MIN TYP MAX
±0.75
-1.0 ±0.4 +1.5
< ±1 ±1.8
±1.0
VDD / 2
± 0.5
120
58.5
54.5 57.5
58.2
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
58 67
f
INA or B
= 30.09MHz at -0.5dBFS 67
Spurious-Free Dynamic Range SFDR
f
INA or B
= 59.74MHz at -0.5dBFS 64
dBc
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
-67
f
INA or B
= 30.09MHz at -0.5dBFS -67
Third-Harmonic
Distortion
HD3
f
INA or B
= 59.74MHz at -0.5dBFS -64
dBc
Intermodulation Distortion
(First Five Odd-Order IMDs)
IMD
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
-73 dBc
Third-Order Intermodulation
Distortion
IM3
f
IN1(A or B)
= 43.393MHz at -6.5dBFS,
f
IN2(A or B)
= 48.9017MHz at -6.5dBFS
(Note 1)
-83 dBc
f
INA or B
= 20.01MHz at -0.5dBFS,
T
A
= +25°C
-65 -58
f
INA or B
= 30.09MHz at -0.5dBFS -65
Total Harmonic Distortion
(First Four Harmonics)
THD
f
INA or B
= 59.74MHz at -0.5dBFS -63
dBc
Small-Signal Bandwidth Input at -20dBFS, differential inputs
MHz
Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs
MHz
Aperture Delay t
AD
1ns
Aperture Jitter t
AJ
2
ps
RMS
Overdrive Recovery Time For 1.5× full-scale input 2 ns
INTERNAL REFERENCE
Reference Output Voltage
V
Load Regulation
mV/mA
Reference Temperature
Coefficient
TC
REF
60
ppm/°C
BUFFERED EXTERNAL REFERENCE (V
REFIN
= 2.048V)
Positive Reference Output
Voltage
V
REFP
(Note 2)
V
Negative Reference Output
Voltage
V
REFN
(Note 2)
V
Common-Mode Level V
COM
(Note 2)
V
Differential Reference Output
Voltage Range
ΔV
REF
ΔV
REF
= V
REFP
- V
REFN
V
REFIN Resistance R
REFIN
MΩ
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
500
400
V
REFOUT
2.048
±3%
1.25
2.162
1.138
1.651
0.95 1.024 1.09
> 50
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
4 _______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
5mA
Maximum REFP, COM Sink
Current
I
SINK
µA
Maximum REFN Source Current
µA
Maximum REFN Sink Current I
SINK
-5 mA
UNBUFFERED EXTERNAL REFERENCE (V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
R
REFP
,
R
REFN
Measured between REFP and COM, and
REFN and COM
3.4 kΩ
Differential Reference Input
Voltage Range
ΔV
REF
ΔV
REF
= V
REFP
- V
REFN
1.024
±10%
V
COM Input Voltage Range V
COM
V
REFP Input Voltage V
REFP
V
REFN Input Voltage V
REFN
V
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
CLK
0.8 ×
Input High Threshold V
IH
PD, OE, SLEEP, T/B
0.8 ×
V
CLK
0.2 ×
Input Low Threshold V
IL
PD, OE, SLEEP, T/B
0.2 ×
V
Input Hysteresis V
HYST
0.1 V
VIH = VDD (CLK) ±5
I
IH
VIH = OVDD (PD, OE, SLEEP, T/B) ±5Input Leakage
I
IL
VIL = 0 ±5
µA
Input Capacitance C
IN
5pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output-Voltage Low V
OL
I
SINK
= -200µA 0.2 V
Output-Voltage High V
OH
I
SOURCE
= 200µA
OV
DD
-
0.2
V
Three-State Leakage Current I
LEAK
OE = OV
DD
±10 µA
C
OUT
OE = OV
DD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range V
DD
3.1 3.3 3.6 V
Output Supply Voltage Range OV
DD
1.7 2.5 3.6 V
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
I
SOURCE
I
SOURCE
-250
250
VDD / 2 ± 10%
V
COM
V
COM
V
DD
OV
DD
+ ΔV
- ΔV
REF
REF
/ 2
/ 2
V
DD
OV
DD
Three-State Output Capacitance
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 5
Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Note 3: Digital outputs settle to V
IH
, VIL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
185
Sleep mode 3
mA
Analog Supply Current I
VDD
Shutdown, clock idle, PD = OE = OV
DD
115µA
Op er ati ng , f
IN A and B
= 20.01M H z at - 0.5d BFS ;
see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
16 mA
Sleep mode
Output Supply Current I
OVDD
Shutdown, clock idle, PD = OE = OV
DD
210
µA
Operating, f
INA and B
= 20.01MHz at
-0.5dBFS
611
Sleep mode 10
mW
Analog Power Dissipation PDISS
Shutdown, clock idle, PD = OE = OV
DD
3.3 50 µW
Offset, VDD ±5%
mV/V
Power-Supply Rejection Ratio PSRR
Gain, V
DD
±5%
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
t
DO
CL = 20pF (Note 3)
7.4 ns
OE Fall to Output Enable Time
ns
OE Rise to Output Disable Time
ns
CLK Pulse-Width High t
CH
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
ns
CLK Pulse-Width Low t
CL
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
ns
Wake up from sleep mode (Note 4)
Wake-Up Time t
WAKE
Wake up from shutdown mode (Note 4)
µs
CHANNEL-TO-CHANNEL MATCHING
Crosstalk f
INA or B
= 20.01MHz at -0.5dBFS
dBc
Gain Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 5)
dB
Phase Matching f
INA or B
= 20.01MHz at -0.5dBFS (Note 6)
Degrees
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3.3V; OVDD= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V
REFIN
= 2.048V; VIN= 2V
P-P
(differential with respect to COM); CL= 10pF at digital outputs; f
CLK
= 120MHz; TA=
T
MIN
to T
MAX
, unless otherwise noted; ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization;
typical values are at T
A
= +25°C.)
t
ENABLE
t
DISABLE
149
100
492
±3.4
±0.81
4.8
4.7
1.2
4.17
4.17
0.65
1.2
-71
0.08 ±0.2
0.8
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc01a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 20.0119MHz
f
INB
= 12.9799MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHA
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc01b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
CHB
f
INA
= 12.9799MHz
f
INB
= 20.0119MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
f
INB
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc02a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
CHA
f
INA
= 31.0873MHz
f
INB
= 23.9967MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc02b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 23.9967MHz
f
INB
= 31.0873MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHB
f
INB
FFT PLOT CHA (8192-POINT RECORD)
MAX1190 toc03a
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 59.7427MHz
f
INB
= 49.0189MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHA
f
INA
FFT PLOT CHB (8192-POINT RECORD)
MAX1190 toc03b
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
INA
= 49.0189MHz
f
INB
= 59.7427MHz
f
CLK
= 120.0128MHz
A
INA/AINB
= -0.52dBFS
CHB
f
INB
TWO-TONE IMD PLOT
(8192-POINT RECORD)
MAX1190 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
48362412
-100
-75
-50
-25
0
-125
060
f
IN1
= 43.3933MHz
f
IN2
= 48.9017MHz
f
CLK
= 120.0128MHz
A
IN
= -6.5dBFS
f
IN1
f
IN2
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1190 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
52
54
56
58
60
50
CHB
CHA
100
80
604020
90
70
503010
0
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1190 toc06
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
100
80
604020
90
70
503010
52
54
56
58
60
50
0
CHA
CHB
MAX1190
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
_______________________________________________________________________________________ 7
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1190 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
-72
-64
-56
-48
-40
-80
CHA
CHB
100
80
604020
90
70
503010
0
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1190 toc08
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
48
56
64
72
80
40
CHB
CHA
100
80
604020
90
70
503010
0
SNR/SINAD, -THD/SFDR
vs. CLOCK DUTY CYCLE
MAX1190 toc09
CLOCK DUTY CYCLE (%)
SNR/SINAD, -THD/SFDR (dB, dBc)
56524844
20
40
60
80
100
0
40 60
SFDR
SINAD
f
INA/B
= 20.02536MHz
SNR
-THD
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1190 toc10
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-7
-4
-1
2
5
-10
11000
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1190 toc11
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
10010
-6
-4
-2
0
2
4
6
-8
11000
VIN = 100mV
P-P
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc13
ANALOG INPUT POWER (dBFS)
SINAD (dB)
-4-8-12-16
44
48
52
56
60
40
-20 0
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc14
ANALOG INPUT POWER (dBFS)
THD (dBc)
-4-8-12-16
-74
-68
-62
-56
-50
-80
-20 0
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc15
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
-4-8-12-16
56
62
68
74
80
50
-20 0
Typical Operating Characteristics (continued)
(VDD= 3.3V, OVDD= 2.5V, V
REFIN
= 2.048V, differential input at -0.5dBFS, f
CLK
= 120MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (f
IN
= 20.02536MHz)
MAX1190 toc12
ANALOG INPUT POWER (dBFS)
SNR (dB)
-4-8-12-16
44
48
52
56
60
40
-20 0
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