MAXIM MAX1186 User Manual

General Description

The MAX1186 is a 3V, dual 10-bit analog-to-digital con­verter (ADC) featuring fully-differential wideband track­and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1186 is optimized for low-power, high
dynamic performance applications in imaging, instru­mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con­suming only 105mW while delivering a typical signal-to­noise ratio (SNR) of 59.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and the falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli­fiers. The converters may also be operated with single­ended inputs. In addition to low operating power, the
MAX1186 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.

An internal 2.048V precision bandgap reference sets
the full-scale range of the ADCs. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.

The MAX1186 features parallel, multiplexed, CMOS­compatible three-state outputs. The digital output for­mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1186 is available in a
7mm x 7mm, 48-pin TQFP-EP package, and is speci­fied for the extended industrial (-40°C to +85°C) tem­perature range.

Pin-compatible, nonmultiplexed, high-speed versions of
the MAX1186 are also available. Please refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
the MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps. For a pin-compatible lower
speed version (20Msps) of the MAX1186, please refer
to the MAX1185 data sheet.

Applications

Features

♦ Single 3V Operation
♦ Excellent Dynamic Performance:

59.4dB SNR at fIN= 20MHz
72dBc SFDR at fIN= 20MHz

♦ Low Power:

35mA (Normal Operation)

2.8mA (Sleep Mode)
1µA (Shutdown Mode)

♦ 0.02dB Gain and 0.25° Phase Matching
♦ Wide ±1V

P-P

Differential Analog Input Voltage

Range

♦ 400MHz, -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ Single 10-Bit Bus for Multiplexed, Digital Outputs
♦ User-Selectable Output Format—Two’s

Complement or Offset Binary

♦ 48-Pin TQFP Package with Exposed Paddle For

Improved Thermal Dissipation

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

D1A/B
D0A/B
OGND
OV

DD

OV

DD

OGND
A/B
N.C.
N.C.
N.C.
N.C.
N.C.

COM

V

DD

GND

INA+

INA-

V

DD

GND
INB-

INB+

GND

V

DD

CLK

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

48 TQFP-EP

GND

V

DD

GND

V

DD

T/B

SLEEP

PD

OE

N.C.

N.C.

N.C.

N.C.

1314151617181920212223

24

4847464544434241403938

37

REFN

REFP

REFIN

REFOUT

D9A/B

D8A/B

D7A/B

D6A/B

D5A/B

D4A/B

D3A/B

D2A/B

MAX1186

EP

NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.

Pin Configuration

19-2263; Rev 1; 4/06

Ordering Information

PART

TEMP RANGE

PIN­PACKAGE

PKG
CODE

MAX1186ECM

C48E-7

MAX1186ECM+

C48E-7

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Functional Diagram appears at end of data sheet.

High-Resolution Imaging

I/Q Channel Digitization

Multichannel IF Sampling

Instrumentation

Video Application

Ultrasound

+Denotes lead-free package.
*EP = Exposed paddle.

Pin-Compatible Versions table at end of data sheet.

-40°C to +85°C 48 TQFP-EP*

-40°C to +85°C 48 TQFP-EP*

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND ...............................................-0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

DD

REFIN, REFOUT, REFP, REFN, COM,

CLK to GND............................................-0.3V to (V

DD

+ 0.3V)

OE, PD, SLEEP, T/B, D9A/B–D0A/B,

A/B to OGND .......................................-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

48-Pin TQFP-EP (derate 30.4mW/°C

above +70°C).........................................................2430mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

UNITS

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.5MHz

LSB

Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed

LSB

Offset Error

% FS

Gain Error 0 ±2

% FS

ANALOG INPUT

Differential Input Voltage
Range

V

DIFF

Differential or single-ended inputs ±1V

Common-Mode Input Voltage
Range

V

CM

V

D D

/ 2

V

Input Resistance R

IN

Switched capacitor load 100 kΩ

Input Capacitance C

IN

5pF

CONVERSION RATE

Maximum Clock Frequency f

CLK

40

MHz

CHA 5

Data Latency

CHB 5.5

Clock

cycles

DYNAMIC CHARACTERISTICS

f

INA or B

= 7.5MHz, TA = +25°C

Signal-to-Noise Ratio
(Note 3)

SNR

f

INA or B

= 20MHz, TA = +25°C

dB

f

INA or B

= 7.5MHz, TA = +25°C57

Signal-to-Noise and Distortion
(Note 3)

f

INA or B

= 20MHz, TA = +25°C

dB

f

INA or B

= 7.5MHz, TA = +25°C6474

Spurious-Free Dynamic Range
(Note 3)

SFDR

f

INA or B

= 20MHz, TA = +25°C6472

dBc

SYMBOL

MIN TYP MAX

±0.5 ±1.7

±0.25 ±1.0

< ±1 ±2.3

SINAD

± 0.5

57.3 59.5

56.8 59.4

56.5 59.2

59.4

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

f

INA or B

= 7.5MHz, TA = +25°C -72 -64

Total Harmonic Distortion
(First 4 Harmonics) (Note 3)

THD

f

INA or B

= 20MHz, TA = +25°C -71 -63

dBc

f

INA or B

= 7.5MHz -74

Third-Harmonic Distortion
(Note 3)

HD3

f

INA or B

= 20MHz -72

dBc

f

INA or B

= 11.6066MHz at -6.5dBFS

Intermodulation Distortion IMD

f

I N A o r B

= 13.3839M H z at - 6.5d BFS ( N ote 4)

-76

dBc

Small-Signal Bandwidth Input at -20dBFS, differential inputs

MHz

Full-Power Bandwidth

Input at -0.5dBFS, differential inputs

MHz

Aperture Delay t

AD

1ns

Aperture Jitter t

AJ

2

ps

RMS

Overdrive Recovery Time For 1.5x full-scale input 2 ns

Differential Gain ±1%

Differential Phase

D egr ees

Output Noise INA+ = INA- = INB+ = INB- = COM 0.2

LSB

RMS

INTERNAL REFERENCE

Reference Output Voltage

V

Reference Temperature
Coefficient

60

ppm/°C

Load Regulation

mV/mA

BUFFERED EXTERNAL REFERENCE (V

REFIN

= 2.048V)

REFIN Input Voltage

V

Positive Reference Output
Voltage

V

Negative Reference Output
Voltage

V

Differential Reference Output
Voltage Range

∆V

REF

= V

REFP

- V

REFN

V

REFIN Resistance

MΩ

SYMBOL

FPBW

REFOUT

TC

REF

V

REFIN

V

REFP

V

REFN

∆V

REF

R

REFIN

MIN TYP MAX

0.95 1.024 1.10

500

400

±0.25

2.048
±3%

1.25

2.048

2.012

0.988

> 50

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

Maximum REFP, COM Source
Current

5

mA

Maximum REFP, COM Sink
Current

I

SINK

µA

Maximum REFN Source Current

µA

Maximum REFN Sink Current I

SINK

-5

mA

UNBUFFERED EXTERNAL REFERENCE (V

REFIN

= GND, reference voltage applied to REFP, REFN, and COM)

REFP, REFN Input Resistance

R

REFP

,

Measured between REFP and COM, and
REFN and COM

4kΩ

Differential Reference Input
Voltage

∆V

REF

= V

REFP

- V

REFN

V

COM Input Voltage V

COM

VDD / 2

V

REFP Input Voltage

V

COM

+

∆V

REF

/ 2

V

REFN Input Voltage

V

COM

-

∆V

REF

/ 2

V

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

CLK

0.8

Input High Threshold V

IH

PD, OE, SLEEP, T/B

0.8

V

CLK

0.2

Input Low Threshold V

IL

PD, OE, SLEEP, T/B

0.2

V

Input Hysteresis

0.1 V

I

IH

VIH = OV

DD

or V

DD

(CLK) ±5

Input Leakage

I

IL

VIL = 0 ±5

µA

Input Capacitance C

IN

5pF

DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)

Output-Voltage Low V

OL

I

SINK

= -200µA 0.2 V

Output-Voltage High V

OH

I

SOURCE

= 200µA

- 0.2

V

Three-State Leakage Current I

LEAK

OE = OV

DD

±10 µA

Three-State Output Capacitance

C

OUT

OE = OV

DD

5pF

SYMBOL

I

SOURCE

MIN TYP MAX

I

SOURCE

R

REFN

∆V

REF

V

REFP

V

REFN

V

HYST

V

DD

x OV

DD

-250

250

1.024
±10%

±10%

x V

x OV

DD

DD

OV

DD

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential w.r.t. COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

, unless

otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

POWER REQUIREMENTS

Analog Supply Voltage Range V

DD

2.7 3.0 3.6 V

Output Supply Voltage Range OV

DD

1.7 2.5 3.6 V

Operating, f

INA or B

= 20MHz at -0.5dBFS 35 50

Sleep mode 2.8

mA

Analog Supply Current I

VDD

Shutdown, clock idle, PD = OE = OV

DD

115µA

Operating, CL = 15pF, f

INA or B

= 20MHz at

-0.5dBFS

9mA

Sleep mode

Output Supply Current

Shutdown, clock idle, PD = OE = OV

DD

210

µA

Operating, f

INA or B

= 20MHz at -0.5dBFS

Sleep mode 8.4

mW

Power Dissipation

Shutdown, clock idle, PD = OE = OV

DD

345µW

Offset

mV/V

Power-Supply Rejection Ratio PSRR

Gain

%/V

TIMING CHARACTERISTICS

CLK Rise to CHA Output Data
Valid

t

DOA

Figure 3 (Note 5) 5 8 ns

CLK Fall to CHB Output Data
Valid

t

DOB

Figure 3 (Note 5) 5 8 ns

Clock Rise/Fall to A/B Rise/Fall
Time

t

DA/B

6ns

Output Enable Time

Figure 4 10 ns

Output Disable Time

Figure 4 1.5 ns

CLK Pulse Width High t

CH

Figure 3, clock period: 25ns

12.5 ±3.8

ns

CLK Pulse Width Low t

CL

Figure 3, clock period: 25ns

12.5 ±3.8

ns

Wake-up from sleep mode (Note 6)

Wake-Up Time

Wake-up from shutdown (Note 6) 1.5

µs

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

INA or B

= 20MHz at -0.5dBFS -70 dB

Gain Matching f

INA or B

= 20MHz at -0.5dBFS

dB

Phase Matching f

INA or B

= 20MHz at -0.5dBFS

D eg r ees

Note 1: Equivalent dynamic performance is obtainable over full OVDDrange with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a ±1.024V full-scale

input voltage range.

Note 4: Intermodulation distortion power of the intermodulation products relative to the individual carrier. This number is 6dB or bet-

ter, if referenced to the two-tone envelope.

Note 5: Digital outputs settle to V

IH

and VIL. Parameter guaranteed by design.

Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

SYMBOL

I

OVDD

PDISS

t

ENABLE

t

DISABLE

t

WAKE

MIN TYP MAX

100

105 150

±0.2

±0.1

0.41

0.02 ±0.2

0.25

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

046821012141816 20

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1186 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHA

f

CLK

= 40.0005678MHz

f

INA

= 6.1475482MHz

f

INB

= 7.5342866MHz

A

INA

= -0.552dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

046821012141816 20

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1186 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHB

f

CLK

= 40.0005678MHz

f

INA

= 6.1475482MHz

f

INB

= 7.5342866MHz

A

INB

= -0.534dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 46821012141816 20

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1186 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHAf

CLK

= 40.0005678MHz

f

INA

= 19.8879776MHz

f

INB

= 24.9661747MHz

A

INA

= -0.516dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 46821012141816 20

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1186 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

CHBf

CLK

= 40.0005678MHz

f

INA

= 19.8879776MHz

f

INB

= 24.9661747MHz

A

INB

= -0.498dBFS

HD3

HD2

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 46821012141816 20

TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1186 toc05

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

IM2

IM3

IM3

f

CLK

= 40.0005678MHz

f

IN1

= 11.606610MHz

f

IN2

= 13.383979MHz

A

IN

= -6.5dBFS

IM2

f

IN2

f

IN1

57

56

55

59

58

60

61

0 102030405060708090100110

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1186 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

CHB

CHA

62

61

60

59

58

57

54

56

55

0102030 5040 60 8070 90 100 110

SIGNAL-TO-NOISE AND DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1186 toc07

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

CHB

CHA

-72

-76

-80

-68

-64

-60

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1186 toc08

ANALOG INPUT FREQUENCY (MHz)

THD (dBc)

0102030405060708090100110

CHA

CHB

60

64

72

68

76

80

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

MAX1186 toc09

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

0 102030405060708090100110

CHA

CHB

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 7

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX1186 toc10

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

-8

-4

-6

0

-2

4

2

6

1 10 100 1000

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED

MAX1186 toc11

ANALOG INPUT FREQUENCY (MHz)

GAIN (dB)

VIN = 100mV

P-P

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER (f

IN

= 19.89MHz)

MAX1186 toc12

ANALOG INPUT POWER (dBFS)

SNR (dB)

-12-16 -8 -4

35

45

40

55

50

60

65

-20 0

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 19.89MHz)

MAX1186 toc13

ANALOG INPUT POWER (dBFS)

SINAD (dB)

-12-16 -8 -4

-80

-75

-65

-70

-60

-55

-20 -12-16 -8 -4 0

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER (f

IN

= 19.89MHz)

MAX1186 toc14

ANALOG INPUT POWER (dBFS)

THD (dBc)

65

60

75

70

80

-20 -12-16 -8 -4 0

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER (f

IN

= 19.89MHz)

MAX1186 toc15

ANALOG INPUT POWER (dBFS)

SFDR (dBc)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

INTEGRAL NONLINEARITY

(BEST ENDPOINT FIT)

MAX1186 toc16

DIGITAL OUTPUT CODE

INL (LSB)

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 256128 384 512 640 768 896 1024

DIFFERENTIAL NONLINEARITY

MAX1186 toc17

DIGITAL OUTPUT CODE

DNL (LSB)

-0.1

-0.2

0.1

0

0.3

0.2

0.4

-40 85

GAIN ERROR vs. TEMPERATURE

EXTERNAL REFERENCE (V

REFIN

= 2.048V)

MAX1186 toc18

TEMPERATURE (°C)

GAIN ERROR (%FS)

10-15 35 60

CHB

CHA

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

8 _______________________________________________________________________________________

-0.4

-0.2

-0.3

0

-0.1

0.1

0.2

-40 85

OFFSET ERROR vs. TEMPERATURE

EXTERNAL REFERENCE (V

REFIN

= 2.048V)

MAX1186 toc19

TEMPERATURE (°C)

OFFSET ERROR (%FS)

10-15 35 60

CHB

CHA

35

37

41

39

43

45

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1186 toc20

VDD (V)

I

VDD

(mA)

36

38

37

40

39

41

42

-40 10-15 35 60 85

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1186 toc21

TEMPERATURE (°C)

I

VDD

(mA)

0

0.08

0.24

0.16

0.32

0.40

2.70 3.002.85 3.15 3.30 3.45 3.60

ANALOG POWER-DOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1186 toc22

VDD (V)

I

VDD

(µA)

OE = PD = OV

DD

50

56

68

62

74

80

30 35 4540 5550 60 65 70

SNR/SINAD, -THD/SFDR

vs. CLOCK DUTY CYCLE

MAX1186 toc23

CLOCK DUTY CYCLE (%)

SNR/SINAD, -THD/SFDR (dB, dBc)

SFDR

f

INA/B

= 7.53MHz

SNR

SINAD

-THD

2.0000

2.0020

2.0060

2.0040

2.0080

2.0100

2.70 3.002.85 3.15 3.30 3.45 3.60

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1186 toc24

VDD (V)

V

REFOUT

(V)

1.994

2.002

1.998

2.006

2.010

2.014

-40 85

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1186 toc25

TEMPERATURE (°C)

V

REOUT

(V)

10-15 35 60

0

21,000

14,000

7,000

28,000

35,000

42,000

49,000

56,000

63,000

70,000

OUTPUT NOISE HISTOGRAM (DC INPUT)

MAX1186 toc26

DIGITAL OUTPUT CODE

COUNTS

64,515

N

869

N-1

152

N+1

0

N+2

0

N-2

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40MHz, CL≈ 10pF, TA= +25°C, unless otherwise noted.)

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11, 14, 15

V

DD

Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog

supply accepts a 2.7V to 3.6V input range.

3, 7, 10, 13, 16

GND Analog Ground

4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.

18 SLEEP

Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.

19 PD

Power-Down Input.
High: Power-down mode.
Low: Normal operation.

20 OE

Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.

21–29 N.C. No Connection

30 A/B

A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0) to

be present on the output. A/B follows the external clock signal with typically 6ns delay.

31, 34 OGND Output Driver Ground

32, 33 OV

DD

Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor.

Output driver supply accepts a 1.7V to 3.6V input range.

35 D0A/B

Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects

channel A or channel B data.

36 D1A/B

Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A or
channel B data.

37 D2A/B

Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A or
channel B data.

38 D3A/B

Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A or
channel B data.

39 D4A/B

Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A or
channel B data.

40 D5A/B

Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A or
channel B data.

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

10 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

41 D6A/B

Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A or
channel B data.

42 D7A/B

Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A or
channel B data.

43 D8A/B

Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A or
channel B data.

44 D9A/B

Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects
channel A or channel B data.

45 REFOUT

Internal Reference Voltage Output. Maybe connected to REFIN through a resistor or a resistor­divider.

46 REFIN Reference Input. V

REFIN

= 2 x (V

REFP

- V

REFN

). Bypass to GND with a > 1nF capacitor.

47 REFP

Positive Reference Input/Output. Conversion range is ±(V

REFP

- V

REFN

). Bypass to GND with a

> 0.1µF capacitor.

48 REFN

Negative Reference Input/Output. Conversion range is ±(V

REFP

- V

REFN

). Bypass to GND with

a > 0.1µF capacitor.

— EP Exposed Paddle. Connect to analog ground.

Detailed Description

The MAX1186 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high­speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every one-half clock cycle. Including
the delay through the output latch, the total clock-cycle
latency is five clock cycles.

1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con­verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.

Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (5 clock
cycles later) and CHB data is updated on the falling
edge (5.5 clock cycles later) of the clock signal. The A/B
indicator follows the clock signal with a typical delay

time of 6ns and remains high when CHA data is updat­ed and low when CHB data is updated.

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track- and hold­mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully-differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out­put of the amplifier and switch S4c is closed. The result­ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang­ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1186 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA-,
as well as INB+ and INB-, and set the common-mode
voltage to midsupply (V

DD

/ 2) for optimum performance.

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 11

T/H

V

OUT

x2

Σ

FLASH

ADC

DAC

1.5 BITS

10

V

INA

V

IN

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASH

ADC

T/H

T/H

V

OUT

x2

Σ

FLASH

ADC

DAC

1.5 BITS

10

V

INB

V

IN

STAGE 1 STAGE 2

DIGITAL CORRECTION LOGIC

STAGE 8 STAGE 9

2-BIT FLASH

ADC

T/H

OUTPUT

MULTIPLEXER

10

D0A/B–D9A/B

Figure 1. Pipelined Architecture—Stage Blocks

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

12 ______________________________________________________________________________________

S3b

S3a

COM

S5b

S5a

INB+

INB-

S1

OUT

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

HOLD

HOLD

CLK

INTERNAL
NONOVERLAPPING
CLOCK SIGNALS

TRACK

TRACK

S2a

S2b

S3b

S3a

COM

S5b

S5a

INA+

INA-

S1

OUT

OUT

C2a

C2b

S4c

S4a

S4b

C1b

C1a

INTERNAL

BIAS

INTERNAL

BIAS

COM

S2a

S2b

MAX1186

Figure 2. MAX1186 T/H Amplifiers

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 13

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1186 is determined by the
internally generated voltage difference between REFP
(V

DD

/ 2 + V

REFIN

/ 4) and REFN (V

DD

/ 2 - V

REFIN

/ 4).
The full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.

REFOUT, REFP, COM (V

DD

/ 2), and REFN are internally

buffered low-impedance outputs.

The MAX1186 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal reference
output REFOUT to REFIN through a resistor (e.g., 10kΩ)
or resistor-divider, if an application requires a reduced
full-scale range. For stability and noise filtering purposes,
bypass REFIN with a > 10nF capacitor to GND. In internal
reference mode, REFOUT, COM, REFP, and REFN
become low-impedance outputs.

In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu­rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con­nected to REFIN through a > 10kΩ resistor.

In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.

Clock Input (CLK)

The MAX1186’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit­ter and fast rise and fall times (< 2ns). In particular, sam­pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:

SNRdB= 20 x log10(1 / [2π x fINx tAJ])

where fINrepresents the analog input frequency and t

AJ

is the time of the aperture jitter.

Clock jitter is especially critical for undersampling appli­cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.

The MAX1186 clock input operates with a voltage thresh­old set to VDD/2. Clock inputs with a duty cycle other
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.

System Timing Requirements

Figure 3 shows the relationship between clock and ana­log input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output. This
followed one-half clock cycle later by the digitized
value of the original CHB sample.

A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

OE

), Channel

Selection (A/B)

All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple­ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com­plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(< 15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1186, thereby
degrading its dynamic performance. Using buffers on the
digital outputs of the ADCs can further isolate the digital
outputs from heavy capacitive loads. To further improve
the dynamic performance of the MAX1186, small-series
resistors (e.g., 100Ω) may be added to the digital output
paths, close to the MAX1186.

Figure 4 displays the timing relationship between output
enable and data output valid as well as power­down/wake-up and data output valid.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1186 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to

2.8mA.
To enter full power-down mode, pull PD high. With OE

simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high, forces
the digital outputs into a high-impedance state.

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

14 ______________________________________________________________________________________

Applications Information

Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V

DD

/ 2 output voltage for level
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat­ed with high-speed operational amplifiers that follows

the amplifiers. The user may select the R

ISO

and C

IN

values to optimize the filter performance, to suit a par­ticular application. For the application in Figure 5, a
R

ISO

of 50Ω is placed before the capacitive load to pre-

vent ringing and oscillation. The 22pF CINcapacitor
acts as a small bypassing capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1186 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V

DD

/ 2 DC level shift to
the input. Although a 1:1 transformer is shown, a step­up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over­all distortion.

In general, the MAX1186 provides better SFDR and
THD with fully differential input signals than single­ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.

t

DOB

t

CL

t

CH

t

CLK

t

DOA

t

DA/B

5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)

A/B CHB

D0A/B–D9A/B D0B

CHA

D1A

CHB

D1B

CHA

D2A

CHB

D2B

CHA

D3A

CHB

D3B

CHA

D4A

CHB

D4B

CHA

D5A

CHB

D5B

CHA

D6A

CHB

D6B

CHA

CHB

CLK

Figure 3. Timing Diagram for Multiplexed Outputs

Figure 4. Output Timing Diagram

OE

t

DISABLE

VALID DATA

OUTPUT

D0A/B–D9A/B

HIGH

IMPEDANCE

t

ENABLE

HIGH

IMPEDANCE

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 15

Table 1. MAX1186 Output Codes For Differential Inputs

*V

REF

= V

REFP

- V

REFN

DIFFERENTIAL INPUT

VOLTAGE*

DIFFERENTIAL

INPUT

STRAIGHT OFFSET

BINARY

T/B = 0

TWO’S COMPLEMENT

T/B = 1

V

REF

x 511/512 +FULL SCALE - 1 LSB 11 1111 1111 01 1111 1111

V

REF

x 1/512 +1 LSB 10 0000 0001 00 0000 0001

0 Bipolar Zero 10 0000 0000 00 0000 0000

-V

REF

x 1/512 -1 LSB 01 1111 1111 11 1111 1111

-V

REF

x 511/512 -FULL SCALE + 1 LSB 00 0000 0001 10 0000 0001

-V

REF

x 512/512 -FULL SCALE 00 0000 0000 10 0000 0000

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended applica­tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain
the integrity of the input signal.

Typical QAM Demodulation Application

The most frequently used modulation technique for digital
communications applications is probably the Quadrature
Amplitude Modulation (QAM). Typically found in spread­spectrum based systems, a QAM signal represents a
carrier frequency modulated in both amplitude and
phase. At the transmitter, modulating the baseband sig­nal with quadrature outputs, a local oscillator followed by
subsequent up-conversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degree phase­shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into it’s I and Q
components, essentially representing the modulation
process reversed. Figure 8 displays the demodulation
process performed in the analog domain, using the dual
matched 3V, 10-bit ADC MAX1186, and the MAX2451
quadrature demodulator to recover and digitize the
I and Q baseband signals. Before being digitized by the
MAX1186, the mixed-down signal components may be fil­tered by matched analog filters, such as Nyquist or
pulse-shaping filters. These remove any unwanted
images from the mixing process, thereby enhancing the
overall signal-to-noise (SNR) performance and minimizing
intersymbol interference.

Grounding, Bypassing, and

Board Layout

The MAX1186 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro­duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi­mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer or DSP ground plane). Route
high-speed digital signal traces away from the sensitive
analog traces of either channel. Make sure to isolate
the analog input lines to each respective converter to
minimize channel-to-channel crosstalk. Keep all signal
lines short and free of 90 degree turns.

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

16 ______________________________________________________________________________________

Figure 5. Typical Application for Single-Ended-to-Differential Conversion

INPUT

300Ω

-5V

+5V

0.1µF

0.1µF

0.1µF

-5V

600Ω

300Ω

300Ω

INA+

INA-

LOWPASS FILTER

COM

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

0.1µF

0.1µF

+5V

0.1µF

300Ω

MAX4108

MAX1186

INB+

INB-

MAX4108

MAX4108

LOWPASS FILTER

INPUT

300Ω

-5V

+5V

0.1µF

0.1µF

0.1µF

C

IN

22pF

-5V

600Ω

300Ω

300Ω

LOWPASS FILTER

600Ω

+5V

-5V

0.1µF

600Ω

300Ω

600Ω

300Ω

0.1µF

0.1µF

0.1µF

+5V

0.1µF

300Ω

MAX4108

MAX4108

MAX4108

300Ω

LOWPASS FILTER

R

IS0

50Ω

C

IN

22pF

R

IS0

50Ω

C

IN

22pF

R

IS0

50Ω

C

IN

22pF

R

IS0

50Ω

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 17

Figure 6. Transformer-Coupled Input Drive

MAX1186

T1

N.C.

V

IN

6

1

5

2

43

22pF

22pF

0.1µF

0.1µF

2.2µF

25Ω

25Ω

MINICIRCUITS

TT1–6

T1

N.C.

V

IN

6

1

5

2

4

3

22pF

22pF

0.1µF

0.1µF

2.2µF

25Ω

25Ω

MINICIRCUITS

TT1–6

INA-

INA+

INB-

INB+

COM

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin­earity parameters for the MAX1186 are measured using
the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

18 ______________________________________________________________________________________

tion error only and results directly from the ADC’s reso­lution (N-Bits):

SNR

dB[max]

= 6.02 x N + 1.76

In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har­monics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to all spectral components minus the fundamental
and the DC offset.

MAX1186

0.1µF

1kΩ

1kΩ

100Ω

100Ω

C

IN

22pF

C

IN

22pF

INB+

INB-

COM

INA+

INA-

0.1µF

R

ISO

50Ω

R

ISO

50Ω

REFP

REFN

V

IN

MAX4108

0.1µF

1kΩ

1kΩ

100Ω

100Ω

C

IN

22pF

C

IN

22pF

0.1µF

R

ISO

50Ω

R

ISO

50Ω

REFP

REFN

V

IN

MAX4108

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

______________________________________________________________________________________ 19

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:

where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest spurious
component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter­modulation products. The individual input tone levels
are backed off by 6.5dBFS from full scale.

THD

VVVV

V

=×

+++















20

10

22324

252

1

log

0°

90°

÷

8

DOWNCONVERTER

MAX2451

INA+

A/B

CHA AND CHB DATA
ALTERNATINGLY
AVAILABLE ON 10-BIT,
MULTIPLEXED
OUTPUT BUS

MAX1186

INA-

INB+
INB-

DSP

POST

PROCESSING

Figure 8. Typical QAM Application, Using the MAX1186

HOLD

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

t

AD

t

AJ

TRACK TRACK

CLK

Figure 9. T/H Aperture Timing

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs

GND

REFERENCE

OUTPUT

DRIVERS

CONTROL

T/H

T/H

PIPELINE

ADC

DEC

MUX

REFOUT

REFN

COM

REFP

REFIN

INA+

INA-

CLK

INB+

INB-

V

DD

DEC

PIPELINE

ADC

OGND

OV

DD

A/B

OE

D0A/B–D9A/B

T/B

PD
SLEEP

MAX1186

10

10

Functional Diagram

20 ______________________________________________________________________________________

PART

RESOLUTION

(Bits)

SPEED GRADE

(Msps)

OUTPUT BUS

MAX1190 10 120 Full duplex

MAX1180 10 105 Full duplex

MAX1181 10 80 Full duplex

MAX1182 10 65 Full duplex

MAX1183 10 40 Full duplex

MAX1186 10 40 Half duplex

MAX1184 10 20 Full duplex

MAX1185 10 20 Half duplex

MAX1198 8 100 Full duplex

MAX1197 8 60 Full duplex

MAX1196 8 40 Half duplex

MAX1195 8 40 Full duplex

Pin-Compatible Versions

MAX1186

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Multiplexed Parallel Outputs

Package Information

48L,TQFP.EPS

G

1

2

21-0065

PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION

G

2

2

21-0065

PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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