MAXIM MAX1183 Technical data

General Description

The MAX1183 is a 3V, dual 10-bit analog-to-digital con­verter (ADC) featuring fully differential wideband track­and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1183 is optimized for low-power, high
dynamic performance applications in imaging, instrumen­tation, and digital communication applications. This ADC
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a typical signal-to-noise ratio
(SNR) of 59.6dB at an input frequency of 20MHz and a
sampling rate of 40Msps. The T/H driven input stages
incorporate 400MHz (-3dB) input amplifiers. The convert­ers may also be operated with single-ended inputs. In
addition to low operating power, the MAX1183 features a

2.8mA sleep mode as well as a 1µA power-down mode to
conserve power during idle periods.

An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.

The MAX1183 features parallel, CMOS-compatible
three-state outputs. The digital output format can be set
to two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of 1.7V to 3.6V for flexible interfac­ing. The MAX1183 is available in a 7mm ✕7mm, 48-pin
TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.

Pin-compatible lower and higher speed versions of the
MAX1183 are also available. See Table 2 at end of data
sheet for a list of pin-compatible versions. Refer to the
MAX1180 data sheet for 105Msps, the MAX1181 data
sheet for 80Msps, the MAX1182 data sheet for 65Msps,
and the MAX1184 data sheet for 20Msps. In addition to
these speed grades, this family includes a multiplexed
output version, for which digital data is presented time­interleaved and on a single, parallel 10-bit output port.

Applications

High-Resolution Imaging

I/Q Channel Digitization

Multichannel IF Sampling

Instrumentation

Video Application

Ultrasound

Features

♦ Single 3V Operation
♦ Excellent Dynamic Performance:

59.6dB SNR at f

IN

= 20MHz

73dB SFDR at fIN= 20MHz

♦ Low Power:

40mA (Normal Operation)

2.8mA (Sleep Mode)
1µA (Shutdown Mode)

♦ 0.02dB Gain and 0.25° Phase Matching
♦ Wide ±1V

P-P

Differential Analog Input Voltage

Range

♦ 400MHz -3dB Input Bandwidth
♦ On-Chip 2.048V Precision Bandgap Reference
♦ User-Selectable Output Format—Two’s

Complement or Offset Binary

♦ 48-Pin TQFP Package with Exposed Paddle for

Improved Thermal Dissipation

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-2173; Rev 1; 7/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Functional Diagram appears at end of data sheet.

*EP = Exposed paddle.
+Denotes lead-free package.

NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE PACKAGE IS REPLACED BY A “+” SIGN.

PART TEMP RANGE PIN-PACKAGE

MAX1183ECM -40°C to +85°C 48 TQFP-EP*

MAX1183ECM+ -40°C to +85°C 48 TQFP-EP*

REFN

REFP

REFIN

REFOUT

D9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

4847464544434241403938

COM

1

V

2

DD

GND

3

INA+

4

INA-

5

V

6

DD

GND

7

INB-

8

INB+

9

GND

10

V

11

DD

CLK

12

EP

1314151617181920212223

GND

DD

DD

V

V

MAX1183

PD

T/B

GND

SLEEP

48 TQFP-EP

OE

D9B

D8B

D7B

37

24

D6B

36

D1A
D0A

35

OGND

34

OV

33

DD

OV

32

DD

OGND

31

D0B

30

D1B

29

D2B

28

D3B

27

D4B

26

D5B

25

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDD, OVDDto GND .............................................. -0.3V to +3.6V

OGND to GND.......................................................-0.3V to +0.3V

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

DD

REFIN, REFOUT, REFP, REFN,

COM, CLK to GND .................................-0.3V to (V

DD

+ 0.3V)

OE, PD, SLEEP, T/B

D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

48-Pin TQFP-EP

(derate 30.4mW/°C above +70°C)..........................2430mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 7.51MHz ±0.5 ±1.7 LSB

Differential Nonlinearity DNL fIN = 7.51MHz, no missing codes guaranteed ±0.25 ±1.0 LSB

Offset Error <±1 ±1.8 % FS

Gain Error 0±2% FS

ANALOG INPUT

Differential Input Voltage Range V

Common-Mode Input Voltage
Range

Input Resistance R

Input Capacitance C

CONVERSION RATE

Maximum Clock Frequency f

Data Latency 5

DYNAMIC CHARACTERISTICS

Signal-to-Noise Ratio
(Note 3)

Signal-to-Noise and Distortion
(Note 3)

Spurious-Free Dynamic Range
(Note 3)

Total Harmonic Distortion
(First 4 harmonics) (Note 3)

Third-Harmonic Distortion
(Note 3)

Intermodulation Distortion IMD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFF

V

CLK

SNR

SINAD

SFDR

THD

HD3

Differential or single-ended inputs ±1.0 V

CM

Switched capacitor load 50 kΩ

IN

IN

f

f

f

f

f

f

f

f

f

f

f
f
(Note 4)

= 7.51MHz, TA = +25°C 57.3 59.6

INA or B

= 20MHz, TA = +25°C 56.8 59.6

INA or B

= 7.51MHz, TA = +25°C 57 59.4

INA or B

= 20MHz, TA = +25°C 56.5 59

INA or B

= 7.51MHz, TA = +25°C 65 76

INA or B

= 20MHz, TA = +25°C 65 73

INA or B

= 7.51MHz, TA = +25°C -73 -64

INA or B

= 20MHz, TA = +25°C -73 -63

INA or B

= 7.51MHz -76

INA or B

= 20MHz -73

INA or B

= 11.6066MHz at -6.5dBFS,

INA or B

= 13.3839MHz at -6.5dBFS

INA or B

VDD/2

±0.5

5pF

40 MHz

-78 dBc

V

Clock

Cycles

dB

dB

dBc

dBc

dB

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Small-Signal Bandwidth Input at -20dBFS, differential inputs 500 MHz

Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs 400 MHz

Aperture Delay t

Aperture Jitter t

Overdrive Recovery Time For 1.5 x full-scale input 2 ns

Differential Gain ±1 %

Differential Phase ±0.25 Degrees

Output Noise INA+ = INA- = INB+ = INB- = COM 0.2 LSB

INTERNAL REFERENCE

Reference Output Voltage REFOUT

Reference Temperature
Coefficient

Load Regulation 1.25 mV/mA

BUFFERED EXTERNAL REFERENCE (V

REFIN Input Voltage V

Positive Reference Output
Voltage

Negative Reference Output
Voltage

Differential Reference Output
Voltage Range

REFIN Resistance R

Maximum REFP, COM
Source Current

Maximum REFP, COM
Sink Current

Maximum REFN Source Current I

Maximum REFN Sink Current I

UNBUFFERED EXTERNAL REFERENCE (V

REFP, REFN Input Resistance

Differential Reference Input
Voltage Range

COM Input Voltage Range V

REFP Input Voltage V

REFN Input Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TC

REFIN

V

REFP

V

REFN

∆V

REFIN

I

SOURCE

I

SINK

SOURCE

SINK

R

REFP

R

REFN

∆V

COM

REFP

REFN

AD

AJ

REF

= 2.048V)

REFIN

REF

∆V

REFIN

,

Measured between REFP and COM and
REFN and COM

REF

∆V

REF

= V

REFP

- V

REFN

= AGND, reference voltage applied to REFP, REFN, and COM)

REF

= V

REFP

- V

REFN

1ns

2ps

2.048
±3%

60

ppm/

2.048 V

2.012 V

0.988 V

0.95 1.024 1.10 V

>50 MΩ

5mA

-250 µA

250 µA

-5 mA

4kΩ

1.024
±10%

VDD/2
±10%

V

+

COM

/2

∆V

REF

V

-

COM

/2

∆V

REF

RMS

RMS

V

°C

V

V

V

V

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

Input High Threshold V

Input Low Threshold V

Input Hysteresis V

Input Leakage

Input Capacitance C

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output Voltage Low V

Output Voltage High V

Three-State Leakage Current I

Three-State Leakage
Capacitance

POWER REQUIREMENTS

Analog Supply Voltage Range V

Output Supply Voltage Range OV

Analog Supply Current I

Output Supply Current I

Power Dissipation PDISS

Power-Supply Rejection Ratio PSRR

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid t

Output Enable Time t

Output Disable Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLK

IH

PD, OE, SLEEP, T/B

CLK

IL

PD, OE, SLEEP, T/B

HYST

I

I

LEAK

C

OUT

VDD

IH

IL

OL

OH

DD

VIH = OV

or VDD (CLK) ±5

DD

VIL = 0V ±5

IN

I

= -200µA 0.2 V

SINK

I

OE = OV

OE = OV

DD

Operating, f

SOURCE

= 200µA

DD

DD

INA or B

= 20MHz at -0.5dBFS 40 60

Sleep mode 2.8
Shutdown, clock idle, PD = OE = OV

DD

Operating, CL = 15pF,

= 20MHz at -0.5dBFS

f

OVDD

INA or B

Sleep mode 100
Shutdown, clock idle, PD = OE = OV

Operating, f

= 20MHz at -0.5dBFS 120 180

INA or B

DD

0.8 x
V

DD

0.8 x

OV

DD

0.2 x
V

DD

0.2 x

OV

DD

0.1 V

5pF

OV

DD

- 0.2

±10 µA

5pF

2.7 3 3.6 V

1.7 2.5 3.6 V

115µA

5.8 mA

210

Sleep mode 8.4
Shutdown, clock idle, PD = OE = OV

DD

345µW

Offset ±0.2 mV/V

Gain ±0.1 %V

DO

ENABLE

DISABLE

Figure 3 (Note 5) 5 8 ns

Figure 4 10 ns

Figure 4 1.5 ns

V

V

µA

V

mA

µA

mW

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 3V, OVDD= 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor, V

IN

= 2V

P-P

(differential with respect to COM), CL= 10pF at digital outputs (Note 1), f

CLK

= 40MHz, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Note 1: Equivalent dynamic performance is obtainable over full OVDDrange with reduced CL.
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale

input voltage range.

Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is

6dB better, if referenced to the two-tone envelope.

Note 5: Digital outputs settle to V

IH

, VIL. Parameter guaranteed by design.

Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

Typical Operating Characteristics

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40.0006MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

046821012141816 20

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1183 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f

CLK

= 40.0006MHz

f

INA

= 7.5343MHz

f

INB

= 6.1475MHz

A

INA

= -0.498dBFS

HD3

HD2

CHA

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 46821012141816 20

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1183 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f

CLK

= 40.0006MHz

f

INB

= 6.1475MHz

f

INA

= 7.5343MHz

A

INB

= -0.534dBFS

HD3

HD2

CHB

-100

-80

-90

-60

-70

-40

-50

-30

-10

-20

0

0 46821012141816 20

FFT PLOT CHA (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1183 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f

CLK

= 40.0006MHz

f

INA

= 24.9662MHz

f

INB

= 19.888MHz

A

INA

= -0.552dBFS

HD3

HD2

CHA

CLK Pulse Width High t

CLK Pulse Width Low t

Wake-Up Time t

CHANNEL-TO-CHANNEL MATCHING

Crosstalk f

Gain Matching f

Phase Matching f

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

WAKE

CH

CL

Figure 3, clock period: 25ns

Figure 3, clock period: 25ns

Wake up from sleep mode (Note 6) 0.41

Wake up from shutdown (Note 6) 1.5

= 20MHz at -0.5dBFS -70 dB

INA or B

= 20MHz at -0.5dBFS 0.02 ±0.2 dB

INA or B

= 20MHz at -0.5dBFS 0.25 Degrees

INA or B

12.5

±3.8

12.5

±3.8

ns

ns

µs

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40.0006MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

FFT PLOT CHB (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

0

f

= 40.0006MHz

CLK

-10

= 24.9662MHz

f

INA

= 19.888MHz

f

INB

-20

= -0.525dBFS

A

INB

-30

-40

-50

-60

AMPLITUDE (dB)

-70

HD2

-80

-90

-100
046821012141816 20

ANALOG INPUT FREQUENCY (MHz)

TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,

8192-POINT DATA RECORD)

MAX1183 toc04

0

f

= 40.0006MHz

CLK

-10

= 11.6066MHz

f

IN1

= 13.3834MHz

f

-20

IN2

= A

= -6.5dBFS

A

IN1

-30

-40

-50

-60

AMPLITUDE (dB)

-70

-80

-90

-100

IN2

IM2

0 46821012141816 20

ANALOG INPUT FREQUENCY (MHz)

CHB

HD3

IM3

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

61

60

IM2

MAX1183 toc05

59

58

SNR (dB)

57

56

55

0 1020304050607080

CHB

ANALOG INPUT FREQUENCY (MHz)

f

IN2

f

IN1

IM3

CHA

MAX1183 toc06

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

62

60

58

SINAD (dB)

56

54

CHB

0 1020304050607080

ANALOG INPUT FREQUENCY (MHz)

CHA

FULL-POWER INPUT BANDWIDTH vs.

ANALOG INPUT FREQUENCY, SINGLE-ENDED

6

4

2

0

GAIN (dB)

-2

-4

-6

MAX1183 toc07

MAX1183 toc10

TOTAL HARMONIC DISTORTION vs.

ANALOG INPUT FREQUENCY

-50

CHA

-60

-70

THD (dBc)

-80

-90

-100
0 1020304050607080

ANALOG INPUT FREQUENCY (MHz)

CHB

SMALL-SIGNAL INPUT BANDWIDTH vs.

ANALOG INPUT FREQUENCY, SINGLE-ENDED

6

4

2

0

GAIN (dB)

-2

-4

-6

VIN = 100mV

P-P

MAX1183 toc08

MAX1183 toc11

SPURIOUS-FREE DYNAMIC RANGE vs.

ANALOG INPUT FREQUENCY

90

80

70

SFDR (dBc)

60

50

40

0 1020304050607080

ANALOG INPUT FREQUENCY (MHz)

CHB

CHA

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT POWER (f

65

60

55

50

SNR (dB)

45

40

= 19.888MHz)

IN

MAX1183 toc09

MAX1183 toc12

-8
1 10 100 1000

ANALOG INPUT FREQUENCY (MHz)

-8
1 10 100 1000

ANALOG INPUT FREQUENCY (MHz)

35

-20 0
ANALOG INPUT POWER (dBFS)

-12-16 -8 -4

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40.0006MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

SIGNAL-TO-NOISE PLUS DISTORTION vs.

ANALOG INPUT POWER (f

65

60

55

50

SINAD (dB)

45

40

35

-20 0

-12-16 -8 -4

ANALOG INPUT POWER (dBFS)

INTEGRAL NONLINEARITY

0.3

0.2

0.1

TOTAL HARMONIC DISTORTION vs.

= 19.888MHz)

IN

MAX1183 toc13

MAX1183 toc16

ANALOG INPUT POWER (f

-55

-60

-65

THD (dBc)

-70

-75

-80

-20 -16 -12 -8 -4 0
ANALOG INPUT POWER (dBFS)

DIFFERENTIAL NONLINEARITY

0.3

0.2

0.1

= 19.888MHz)

IN

SPURIOUS-FREE DYNAMIC RANGE vs.

= 19.888MHz)

IN

MAX1183 toc14

ANALOG INPUT POWER (f

80

76

72

SFDR (dBc)

68

64

60

-20 -16 -12 -8 -4 0
ANALOG INPUT POWER (dBFS)

GAIN ERROR vs. TEMPERATURE

0.5

0.4

MAX1183 toc17

0.3

CHB

MAX1183 toc15

MAX1183 toc18

0

INL (LSB)

-0.1

-0.2

-0.3
0 256128 384 512 640 768 896 1024

DIGITAL OUTPUT CODE

OFFSET ERROR vs. TEMPERATURE

0.2

0.1

0

-0.1

-0.2

OFFSET ERROR (% FS)

-0.3

-0.4

-40 85

CHB

CHA

10-15 35 60

TEMPERATURE (°C)

MAX1183 toc19

0

DNL (LSB)

-0.1

-0.2

-0.3
0256128 384 512 640 768 896 1024

DIGITAL OUTPUT CODE

ANALOG SUPPLY CURRENT vs.

ANALOG SUPPLY VOLTAGE

50

46

42

(mA)

VDD

I

38

34

30

2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)

GAIN ERROR (% FS)

MAX1183 toc20

(mA)

I

0.2

0.1

0

-0.1

-40 85

10-15 35 60

TEMPERATURE (°C)

CHA

ANALOG SUPPLY CURRENT vs.

TEMPERATURE

50

46

42

VDD

38

34

30

-40 10-15 35 60 85
TEMPERATURE (°C)

MAX1183 toc21

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VDD= 3V, OVDD= 2.5V, V

REFIN

= 2.048V, differential input at -0.5dBFS, f

CLK

= 40.0006MHz, CL≈ 10pF, TA= +25°C, unless

otherwise noted.)

ANALOG POWER-DOWN CURRENT vs.

ANALOG SUPPLY VOLTAGE

0.5

OE = PD = OV

0.4

DD

SNR/SINAD, -THD/SFDR vs.

CLOCK DUTY CYCLE

90

SFDR

MAX1183 toc22

80

f

= 7.5343MHz

INA

= 6.1475MHz

f

INB

INTERNAL REFERENCE VOLTAGE vs.

ANALOG SUPPLY VOLTAGE

2.0020

MAX1183 toc23

2.0014

0.3

(µA)

VDD

I

0.2

70

SNR

-THD

60

2.0008

(V)

REFOUT

V

2.0002

MAX1183 toc24

0.1

0

2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)

INTERNAL REFERENCE VOLTAGE vs.

TEMPERATURE

2.010

2.005

2.000

(V)

1.995

REFOUT

V

1.990

1.985

1.980

-40 85

10-15 35 60

TEMPERATURE (°C)

50

SNR/SINAD, -THD/SFDR (dB, dBc)

40

30 35 40 45 50 55 60 65 70

CLOCK DUTY CYCLE (%)

MAX1183 toc25

SINAD

1.9996

1.9990

2.70 3.002.85 3.15 3.30 3.45 3.60

OUTPUT NOISE HISTOGRAM (DC INPUT)

70,000

63,000

56,000

49,000

42,000

35,000

COUNTS

28,000

21,000

14,000

7,000

0

0

N-2

64,515

869

N

N-1

DIGITAL OUTPUT CODE

152

N+1

VDD (V)

MAX1183 toc26

0

N+2

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1 COM Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.

2, 6, 11,

14, 15

3, 7, 10,

13, 16

4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+.

5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to COM.

8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to COM.

9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+.

12 CLK Converter Clock Input

17 T/B

18 SLEEP

19 PD

20 OE

21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B

22 D8B Three-State Digital Output, Bit 8, Channel B

23 D7B Three-State Digital Output, Bit 7, Channel B

24 D6B Three-State Digital Output, Bit 6, Channel B

25 D5B Three-State Digital Output, Bit 5, Channel B

26 D4B Three-State Digital Output, Bit 4, Channel B

27 D3B Three-State Digital Output, Bit 3, Channel B

28 D2B Three-State Digital Output, Bit 2, Channel B

29 D1B Three-State Digital Output, Bit 1, Channel B

30 D0B Three-State Digital Output, Bit 0 (LSB), Channel B

31, 34 OGND Output Driver Ground

32, 33 OV

35 D0A Three-State Digital Output, Bit 0 (LSB), Channel A

36 D1A Three-State Digital Output, Bit 1, Channel A

37 D2A Three-State Digital Output, Bit 2, Channel A

38 D3A Three-State Digital Output, Bit 3, Channel A

39 D4A Three-State Digital Output, Bit 4, Channel A

40 D5A Three-State Digital Output, Bit 5, Channel A

V

DD

GND Analog Ground

DD

Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor.
The analog supply accepts an input range of 2.7V to 3.6V.

T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.

Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.

Power-Down Input.
High: Power-down mode.
Low: Normal operation.

Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.

Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor.
The output driver supply accepts an input range of 1.7V to 3.6V.

MAX1183

Detailed Description

The MAX1183 uses a nine-stage, fully differential,
pipelined architecture (Figure 1) that allows for high­speed conversion while minimizing power consump­tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.

One-and-a-half bit (2-comparator) flash ADCs convert
the held-input voltages into a digital code. The digital-

to-analog converters (DACs) convert the digitized
results back into analog voltages, which are then sub­tracted from the original held-input signals. The resulting
error signals are then multiplied by two, and the residues
are passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

10 ______________________________________________________________________________________

Figure 1. Pipelined Architecture—Stage Blocks

Pin Description (continued)

PIN NAME FUNCTION

41 D6A Three-State Digital Output, Bit 6, Channel A

42 D7A Three-State Digital Output, Bit 7, Channel A

43 D8A Three-State Digital Output, Bit 8, Channel A

44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A

45 REFOUT

46 REFIN Reference Input. V

47 REFP

48 REFN

— EP Exposed Pad. Connect to analog ground.

Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor
divider.

= 2 x (V

REFIN

Positive Reference Input/Output. Conversion range is ± (V

REFP

- V

). Bypass to GND with a >1nF capacitor.

REFN

REFP

- V

REFN

).

Bypass to GND with a > 0.1µF capacitor.

Negative Reference Input/Output. Conversion range is ± (V

REFP

- V

REFN

).

Bypass to GND with a > 0.1µF capacitor.

V

IN

T/H

FLASH

ADC

1.5 BITS

STAGE 1 STAGE 2

T/H

Σ

DAC

DIGITAL CORRECTION LOGIC

V

OUT

x2

2-BIT FLASH

ADC

STAGE 8

10

STAGE 9

V

IN

T/H

FLASH

ADC

1.5 BITS

STAGE 1 STAGE 2

T/H

Σ

DAC

DIGITAL CORRECTION LOGIC

V

OUT

x2

2-BIT FLASH

ADC

STAGE 8 STAGE 9

10

V

INA

D9A–D0A

V

= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

INA

= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

V

INB

V

INB

D9B–D0B

Input Track-and-Hold (T/H) Circuits

Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switch­es S3a and S3b connect capacitors C1a and C1b to
the output of the amplifier and switch S4c is closed.
The resulting differential voltages are held on capaci­tors C2a and C2b. The amplifiers are used to charge
capacitors C1a and C1b to the same values originally
held on C2a and C2b. These values are then presented
to the first-stage quantizers and isolate the pipelines
from the fast-changing inputs. The wide input bandwidth
T/H amplifiers allow the MAX1183 to track-and-sam­ple/hold analog inputs of high frequencies (> Nyquist).

The ADC inputs (INA+, INB+, INA- and INB-) can be
driven either differentially or single-ended. Match the
impedance of INA+ and INA-, as well as INB+ and INB­and set the common-mode voltage to midsupply
(V

DD

/2) for optimum performance.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1183 is determined by
the internally generated voltage difference between
REFP (VDD/2 + V

REFIN

/4) and REFN (VDD/2 -

V

REFIN

/4). The full-scale range for both on-chip ADCs is
adjustable through the REFIN pin, which is provided for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.

The MAX1183 provides three modes of reference
operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal refer­ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.

In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu­rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or
connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for REFP, COM, and REFN. With their buffers shut
down, these nodes become high impedance and may
be driven through separate external reference sources.

Clock Input (CLK)

The MAX1183’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR perfor­mance of the on-chip ADCs as follows:

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 11

Figure 2. MAX1183 T/H Amplifiers

SNR

ft

IN AJ

log =×

×× ×

⎛

⎝

⎜

⎞

⎠

⎟

20

1

2 π

INA+

INA-

INB+

INB-

INTERNAL

BIAS

S2a

S4a

C2a

S4c

S4b

S4a

S4c

S4b

C2b

C2a

C2b

S1

INTERNAL

BIAS

INTERNAL

BIAS

S2a

S1

INTERNAL

BIAS

S2b

S2b

COM

S5a

C1a

S3a

OUT

OUT

C1b

S3b

S5b

COM

HOLD

COM

S5a

C1a

S3a

TRACK

OUT

OUT

HOLD

TRACK

CLK

INTERNAL
NONOVERLAPPING
CLOCK SIGNALS

MAX1183

C1b

S3b

S5b

COM

MAX1183

where fINrepresents the analog input frequency and
tAJis the time of the aperture jitter.

Clock jitter is especially critical for undersampling
applications. The clock input should always be consid­ered as an analog input and routed away from any ana­log input or other digital signal lines.

The MAX1183 clock input operates with a voltage thresh­old set to VDD/2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics.

System Timing Requirements

Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1183
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.

Digital Output Data, Output Data Format

Selection (T/B), Output Enable (

OE

)

All digital outputs, D0A–D9A (Channel A) and D0B–D9B
(Channel B) are TTL/CMOS logic-compatible. There is a
five-clock-cycle latency between any particular sample
and its corresponding output data. The output coding
can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci­tive load on the digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the ana­log portion of the MAX1183, thereby degrading its
dynamic performance. Using buffers on the digital out­puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1183, small-series
resistors (e.g., 100Ω) may be added to the digital out­put paths close to the MAX1183.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

12 ______________________________________________________________________________________

Figure 3. System Timing Diagram

5-CLOCK-CYCLE LATENCY

ANALOG INPUT

CLOCK INPUT

t

DO

DATA OUTPUT

D9A–D0A

DATA OUTPUT

D9B–D0B

N

N - 6

N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N N + 1

N - 5

N + 1

N - 4

N + 2

t

CH

N - 3

N + 3

N - 2

N + 4

t

CL

N - 1

N + 5

N + 6

N

N + 1

Figure 4 displays the timing relationship between output
enable and data output valid, as well as power­down/wake-up and data output valid.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1183 offers two power-save modes—sleep and
full power-down modes. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to 2.8mA.

To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a VDD/2 output voltage for level­shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat­ed with high-speed op amps follows the amplifiers. The
user may select the R

ISO

and CINvalues to optimize

the filter performance, to suit a particular application.

For the application in Figure 5, a R

ISO

of 50Ω is placed

before the capacitive load to prevent ringing and
oscillation. The 22pF CINcapacitor acts as a small
bypassing capacitor.

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent solu­tion to convert a single-ended source signal to a fully dif­ferential signal, required by the MAX1183 for optimum
performance. Connecting the center tap of the trans­former to COM provides a VDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a step-up
transformer may be selected to reduce the drive require­ments. A reduced signal swing from the input driver, such
as an op amp, may also improve the overall distortion.

In general, the MAX1183 provides better SFDR and
THD with fully differential input signals than single­ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended applica­tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to main­tain the integrity of the input signal.

Typical QAM Demodulation Application

The most frequently used modulation technique for dig­ital communications applications is probably the quad­rature amplitude modulation (QAM). Typically found in
spread-spectrum-based systems, a QAM signal repre­sents a carrier frequency modulated in both amplitude
and phase. At the transmitter, modulating the base­band signal with quadrature outputs, a local oscillator
followed by subsequent up-conversion can generate
the QAM signal. The result is an in-phase (I) and
a quadrature (Q) carrier component, where the Q

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 13

Figure 4. Output Timing Diagram

Table 1. MAX1183 Output Codes for Differential Inputs

*V

REF

= V

REFP

- V

REFN

OE

t

ENABLE

OUTPUT

D9A–D0A

OUTPUT

D9B–D0B

t

DISABLE

VALID DATA

VALID DATA

HIGH-ZHIGH-Z

HIGH-ZHIGH-Z

DIFFERENTIAL INPUT

VOLTAGE*

V

x 511/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111

REF

V

x 1/512 + 1LSB 10 0000 0001 00 0000 0001

REF

- V

REF

-V

x 512/512 -FULL SCALE +1LSB 00 0000 0001 10 0000 0001

REF

-V

x 512/512 -FULL SCALE 00 0000 0000 10 0000 0000

REF

DIFFERENTIAL INPUT

0 Bipolar Zero 10 0000 0000 00 0000 0000

x 1/512 - 1LSB 01 1111 1111 11 1111 1111

STRAIGHT OFFSET BINARY

T/B = 0

TWO'S COMPLEMENT

T/B = 1

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

14 ______________________________________________________________________________________

Figure 5. Typical Application for Single-Ended to Differential Conversion

+5V

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

0.1µF

300Ω

300Ω

300Ω

300Ω

300Ω

300Ω

600Ω

600Ω

0.1µF

0.1µF

0.1µF

MAX4108

-5V

+5V

MAX4108

-5V

+5V

MAX4108

-5V

600Ω

0.1µF

0.1µF

0.1µF

600Ω

0.1µF

0.1µF

0.1µF

LOWPASS FILTER

R

IS0

50Ω

LOWPASS FILTER

R

IS0

50Ω

LOWPASS FILTER

R

IS0

50Ω

C
22pF

C
22pF

C
22pF

INA+

IN

COM

INA-

IN

MAX1183

INB+

IN

+5V

MAX4108

-5V

600Ω

0.1µF

0.1µF

600Ω

LOWPASS FILTER

R

IS0

50Ω

C
22pF

INB-

IN

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

0.1µF

300Ω

600Ω

0.1µF

600Ω

300Ω

300Ω

component is 90 degree phase-shifted with respect to
the in-phase component. At the receiver, the QAM signal
is divided down into its I and Q components, essentially
representing the modulation process reversed. Figure 8
displays the demodulation process performed in the
analog domain, using the dual matched 3V, 10-bit ADC
(MAX1183), and the MAX2451 quadrature demodulator
to recover and digitize the I and Q baseband signals.
Before being digitized by the MAX1183, the mixed-down
signal components may be filtered by matched analog
filters, such as Nyquist or pulse-shaping filters, which
remove any unwanted images from the mixing process,
thereby enhancing the overall signal-to-noise (SNR) per­formance and minimizing intersymbol interference.

Grounding, Bypassing, and

Board Layout

The MAX1183 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V

DD

, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV

DD

) to OGND. Multilayer
boards with separated ground and power planes pro­duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi­mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 15

Figure 6. Transformer-Coupled Input Drive

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive

0.1µF

0.1µF

REFP

REFN

REFP

REFN

1kΩ

1kΩ

1kΩ

1kΩ

R
50Ω

0.1µF

R
50Ω

0.1µF

ISO

C

IN

22pF

R

ISO

50Ω

C

IN

22pF

ISO

C

IN

22pF

R

ISO

50Ω

C

IN

22pF

INA+

COM

INA-

MAX1183

INB+

INB-

25Ω

22pF

0.1µF

V

IN

N.C.

MINICIRCUITS

0.1µF

V

IN

N.C.

MINICIRCUITS

6

1

T1

5

2

2.2µF

43

TT1–6

6

1

T1

5

2

TT1–6

2.2µF

4

3

0.1µF

25Ω

22pF

25Ω

22pF

0.1µF

25Ω

22pF

INA+

COM

INA-

INB+

INB-

MAX1183

V

IN

MAX4108

100Ω

100Ω

V

IN

MAX4108

100Ω

100Ω

MAX1183

(1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if the
ground plane is sufficiently isolated from any noisy, digital
systems ground plane (e.g. downstream output buffer or
DSP ground plane). Route high-speed digital signal
traces away from the sensitive analog traces of either
channel. Make sure to isolate the analog input lines to
each respective converter to minimize channel-to-chan­nel crosstalk. Keep all signal lines short and free of 90
degree turns.

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin­earity parameters for the MAX1183 are measured using
the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.

Dynamic Parameter Definitions

Aperture Jitter

Figure 9 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital sam­ples, the theoretical maximum SNR is the ratio of the full­scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana­log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N-Bits):

SNR

dB[max]

= 6.02 ✕ N + 1.76

In reality, there are other noise sources besides quanti­zation noise (thermal noise, reference noise, clock jitter,
etc.). SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har­monics, and the DC offset.

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

16 ______________________________________________________________________________________

Figure 8. Typical QAM Application, Using the MAX1183

Figure 9. T/H Aperture Timing

DOWNCONVERTER

MAX2451

÷

8

SAMPLED

DATA (T/H)

0°

90°

CLK

ANALOG

INPUT

INA+
INA-

DSP

MAX1183

INB+
INB-

t

AD

t

AJ

POST-

PROCESSING

TRACK TRACK

T/H

HOLD

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to all spectral components minus the fundamental
and the DC offset.

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:

where V1is the fundamental amplitude, and V2through
V

5

are the amplitudes of the 2nd- through 5th-order

harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next largest spurious
component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter­modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with

Internal Reference and Parallel Outputs

______________________________________________________________________________________ 17

Functional Diagram

Table 2. Pin-Compatible Versions

THD

=×

20

log

⎛

⎛

+++

VVVV

2232425

⎜

⎝

⎜

10

⎜
⎜
⎝

V

1

⎞

2

⎞

⎟

⎠

⎟
⎟

⎟
⎠

PART

MAX1190 10 120 Full-Duplex
MAX1180 10 105 Full-Duplex
MAX1181 10 80 Full-Duplex
MAX1182 10 65 Full-Duplex
MAX1183 10 40 Full-Duplex
MAX1186 10 40 Half-Duplex
MAX1184 10 20 Full-Duplex
MAX1185 10 20 Half-Duplex
MAX1198 8 100 Full-Duplex
MAX1197 8 60 Full-Duplex
MAX1196 8 40 Half-Duplex
MAX1195 8 40 Full-Duplex

RESOLUTION

(BITS)

SPEED

GRADE

(Msps)

OUTPUT

BUS

V

DD

GND

INA+

T/H

INA-

CLK

INB+

T/H

INB-

REFOUT

CONTROL

REFN

REFERENCE

COM

REFP

PIPELINE

ADC

PIPELINE

ADC

DEC

DEC

REFIN



10



10

OUTPUT

DRIVERS

OUTPUT

DRIVERS

MAX1183

10



10

OGND

OV

DD

D9A–D0A

OE

D9B–D0B

T/B

PD
SLEEP

MAX1183

Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

Revision History

Pages changed at Rev 1: Title change—all pages,
1-13, 15-18

48L,TQFP.EPS

PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION

21-0065

PACKAGE OUTLINE,
48L TQFP, 7x7x1.0mm EP OPTION

21-0065

1

G

2

2

G

2