MAXIM MAX1127 Technical data

General Description

The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to

1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a

19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.

An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt­age range.

A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia­tions in input-clock duty cycle. An on-chip phase­locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.

The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.

Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.

The MAX1127 is available in a small, 10mm x 10mm x

0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.

Applications

Ultrasound and Medical Imaging

Positron Emission Tomography (PET) Imaging

Multichannel Communication Systems

Instrumentation

Features

♦ Four ADC Channels with Serial LVDS/SLVS

Outputs

♦ Excellent Dynamic Performance

69.6dB SNR at fIN= 19.3MHz
92dBc SFDR at f

IN

= 19.3MHz

-87dB Channel Isolation

♦ Ultra-Low Power

135mW per Channel (Normal Operation)

1.2mW Total (Shutdown Mode)

♦ Accepts 20% to 80% Clock Duty Cycle

♦ Self-Aligning Data-Clock to Data-Output Interface

♦ Fully Differential Analog Inputs
♦ Wide ±1.4V

P-P

Differential Input Voltage Range

♦ Internal/External Reference Option

♦ Test Mode for Digital Signal Integrity

♦ LVDS Outputs Support Up to 30in FR-4 Backplane

Connections

♦ Small, 68-Pin QFN with Exposed Paddle

♦ Evaluation Kit Available (MAX1127EVKIT)

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3144; Rev 2; 9/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration

PART TEMP RANGE PIN-PACKAGE

MAX1127EGK -40°C to +85°C

68 QFN 10mm x
x 10mm x 0.9mm

REFADJ

6768

1GND

2IN0P

3IN0N

4GND

5IN1P

6IN1N

7GND

8AV

DD

9AV

DD

10AV

DD

11GND

12IN2P

13IN2N

14GND

15IN3P

16IN3N

17GND

18

19

DD

AV

CMOUT

65

EP

20

21

22

DD

DD

GND

AV

CV

T/B

6364

23

CLK

10mm x 10mm x 0.9mm

59

60

61

62

MAX1127

24

25

26

27

28DT29 30

DD

DD

DD

GND

AV

AV

AV

QFN

PLL031PLL132PLL233PLL3

SLVS/LVDS

DD

DD

DD

DD

DD

AV

AV

AV

AV

LVDSTEST

GND66REFIO

GND

DD

OV

PD054PD155PD256PD357PDALL58AV

52

53

51 OUT0P

50 OUT0N

49 OV

DD

48 OUT1P

47 OUT1N

46 OV

DD

45 CLKOUTP

CLKOUTN

44

OV

43

DD

FRAMEP

42

41 FRAMEN

40 OV

DD

39 OUT2P

38 OUT2N

37 OV

DD

36 OUT3P

35 OUT3N

34

DD

OV

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto GND.........................................................-0.3V to +2.0V

CV

DD

to GND ........................................................-0.3V to +3.6V

OV

DD

to GND ........................................................-0.3V to +2.0V

IN_P, IN_N to GND...................................-0.3V to (AV

DD

+ 0.3V)

CLK to GND.............................................-0.3V to (CV

DD

+ 0.3V)

OUT_P, OUT_N, FRAME_,

CLKOUT_ to GND................................-0.3V to (OV

DD

+ 0.3V)

DT, SLVS/LVDS to GND...........................-0.3V to (AV

DD

+ 0.3V)

PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV

DD

+ 0.3V)

PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV

DD

+ 0.3V)

T/B, LVDSTEST to GND ...........................-0.3V to (AV

DD

+ 0.3V)

REFIO, REFADJ, CMOUT to GND ...........-0.3V to (AV

DD

+ 0.3V)

I.C. to GND...............................................-0.3V to (AV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)
68-Pin QFN 10mm x 10mm x 0.9mm

(derated 41.7mW/°C above +70°C)........................3333.3mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature Range (soldering, 10s)......................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution N 12 Bits
Integral Nonlinearity INL (Note 2) ±0.4 LSB
Differential Nonlinearity DNL (Note 2) ±0.25 LSB

Offset Error

Gain Error

ANALOG INPUTS (IN_P, IN_N)

Input Differential Range V

Common-Mode Voltage Range V

Differential Input Impedance R

Differential Input Capacitance C

CONVERSION RATE

Maximum Conversion Rate f

Minimum Conversion Rate f

Data Latency 6.5 Cycles

DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)

Signal-to-Noise and Distortion
(First Four Harmonics) (Note 2)

ID

CMO

IN

IN

SMAX

SMIN

SINAD

Fixed external reference (Note 2) ±1
Fixed external reference (Note 2) ±1.5

Differential input 1.4 V

(Note 3) 0.76 V
Switched capacitor load 2 kΩ

fIN = 5.3MHz at -0.5dBFS 69.7

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 66.6 69.6Signal-to-Noise Ratio (Note 2) SNR

f

IN

fIN = 5.3MHz at -0.5dBFS 69.6

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 66.5 69.5

f

IN

fIN = 5.3MHz at -0.5dBFS 11.4

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 11.4Effective Number of Bits (Note 2) ENOB

f

IN

= 30.3MHz at -0.5dBFS 69.4

= 30.3MHz at -0.5dBFS 69.3

= 30.3MHz at -0.5dBFS 11.3

12.5 pF

65 MHz

4 MHz

% FS

% FS

P-P

dB

dB

Bits

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Spurious-Free Dynamic Range
(Note 2)

Inter m od ul ati on D i stor ti on IMD

Third-Order Intermodulation IM3 (Note 2) 95.7 dBc

Aperture Jitter t

Aperture Delay t

Small-Signal Bandwidth SSBW Input at -20dBFS (Notes 2 and 4) 100 MHz

Full-Power Bandwidth LSBW Input at -0.5dBFS (Notes 2 and 4) 100 MHz

Output Noise INP = IN_N 0.45 LSB

Overdrive Recovery Time t

COMMON-MODE OUTPUT (CMOUT)

CMOUT Output Voltage V

INTERNAL REFERENCE (REFADJ = GND, bypass REFIO to GND with 0.1µF)

REFADJ Internal Reference Mode
Enable Voltage

REFADJ Low-Leakage Current 1.6 mA

REFIO Output Voltage V

Reference Temperature
Coefficient

EXTERNAL REFERENCE (REFADJ = AVDD)

REFADJ External Reference
Mode Enable Voltage

REFADJ High-Leakage Current 125 µA

REFIO Input Voltage Range 1.24 V

REFIO Input Voltage Tolerance ±5 %

REFIO Input Current I

CLOCK INPUT (CLK)

Input High Voltage V

Input Low Voltage V

Clock Duty Cycle 50 %

Clock Duty-Cycle Tolerance ±30 %

SFDR

AJ

AD

OR

CMOUT

REFIO

TC

REFIO

REFIO

CLKH

CLKL

fIN = 5.3MHz at -0.5dBFS 93.3

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 77.5 92

f

IN

fIN = 5.3MHz at -0.5dBFS -91

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C -91 -77.5Total H ar m oni c D i st or ti on ( N ote 2) THD

f

IN

f

1

f

2

(Note 2) < 0.4 ps

(Note 2) 1 ns

RS = 25Ω, CS = 50pF 1

(Note 5) 0.1 V

(Note 5)

= 30.3MHz at -0.5dBFS 88.9

= 30.3MHz at -0.5dBFS -88

= 12.348685MHz at -6.5dBFS,
= 13.650845MHz at -6.5dBFS ( N ote 2)

91.2 dBc

0.76 V

1.18 1.24 1.30 V

100 ppm/°C

AV

-

DD

0.1V

< 1 µA

0.8 x

AV

DD

0.2 x

AV

DD

Clock

cycles

dBc

dBc

RMS

RMS

V

V

V

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage DI

Input Capacitance DC

DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)

Input High Threshold V

Input Low Threshold V

Input Leakage DI

Input Capacitance DC

Input at GND 5

IN

Input at AV

IN

IH

IL

Input at GND 5

IN

Input at AV

IN

DD

DD

LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0)

Differential Output Voltage V

OHDIFFRTERM

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

OCM

R

F

= 100Ω 250 450 mV

R

= 100Ω 1.125 1.375 V

TERM

R

= 100Ω, C

TERM

R

TERM

= 100Ω, C

LOAD

LOAD

SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1

Differential Output Voltage V

OHDIFFRTERM

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

OCM

R

F

= 100Ω 205 mV

R

= 100Ω 220 mV

TERM

R

= 100Ω, C

TERM

R

TERM

= 100Ω, C

LOAD

LOAD

POWER-DOWN

PD Fall to Output Enable t

PD Rise to Output Disable t

ENABLE

DISABLE

POWER REQUIREMENTS

AVDD Supply Voltage AV

OVDD Supply Voltage OV

CVDD Supply Voltage CV

DD

DD

DD

= 5pF 150 ps

= 5pF 150 ps

= 5pF 120 ps

= 5pF 120 ps

80

5pF

0.8 x

AV

DD

0.2 x

AV

DD

80

5pF

132 µs

10 ns

1.7 1.8 1.9 V

1.7 1.8 1.9 V

1.7 1.8 3.6 V

µA

V

V

µA

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVDD Supply Current I

OVDD Supply Current I

AVDD

OVDD

f

=

IN

19.3MHz at

-0.5dBFS

f

=

IN

19.3MHz at

-0.5dBFS

PDALL = 0, all channels
active

PDALL = 0, all channels
active, DT = 1

PDALL = 0, 1 channel active 82

PDALL = 0, PD[3:0] = 1111 23

PDALL = 1, global power
down, PD[3:0] =1111, no
clock input

PDALL = 0, all channels
active

PDALL = 0, all channels
active, DT = 1

PDALL = 0, 1 channel active 42

PDALL = 0, PD[3:0] = 1111 37

PDALL = 1, global power­down, PD[3:0] =1111, no
clock input

257 295

257

300 µA

56 65

72

375 µA

mA

mA

CVDD Supply Current I

Power Dissipation P

TIMING CHARACTERISTICS (Note 6)

Data Valid to CLKOUT Rise/Fall t

CLKOUT Output Width High t

CLKOUT Output Width Low t

FRAME Rise to CLKOUT Rise t

Sample CLK Rise to Frame Rise t

CVDD

DISSfIN

OD

CH

CL

CF

SF

CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2

= 19.3MHz at -0.5dBFS 563 648 mW

(t

SAMPLE

f

= 65MHz, Figure 5 (Notes 6 and 7)

CLK

Figure 5

Figure 5

Figure 4 (Note 7)

Figure 4 (Notes 7 and 8)

24)

- 0.15

(t

SAMPLE

24)

- 0.15

(t

SAMPLE

+0.9

2)

0mA

/

t

SAMPLE

t

S AMP LE

t

S AMP LE

/

t

SAMPLE

/

(t

SAMPLE

24

12

12

24

2)

+1.3

/

/

/

/

/

(t

SAMPLE

24)

+ 0.15

( t

SAMPLE

24)

+ 0.15

(t

SAMPLE

2)

+1.7

/

ns

ns

ns

/

ns

/

ns

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

6 _______________________________________________________________________________________

Note 1: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 2: See definition in the Parameter Definitions section.
Note 3: The MAX1127 internally sets the common-mode voltage to 0.76V (typ) (see Figure 1). The common-mode voltage can be

overdriven to between 0.55V and 0.85V.

Note 4: Limited by MAX1127EVKIT input circuitry.
Note 5: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AV

DD

directly to disable the inter-

nal bandgap reference and enable external reference mode.

Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7: Guaranteed by design and characterization. Not subject to production testing.
Note 8: Sample CLK rise to FRAME rise timing is measured from 50% of sample clock input level to 50% of FRAME output level.

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHANNEL-TO-CHANNEL MATCHING

Crosstalk (Note 2) -87 dB

Gain Matching fIN = 30.3MHz (Note 2) ±0.1 dB

Phase Matching fIN = 30.3.MHz (Note 2) ±1 Degrees

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

FFT PLOT

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

FREQUENCY (MHz)

CROSSTALK

(4096-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110
032

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 0.
f

IN(IN1)

f

IN(IN0)

FREQUENCY (MHz)

f

= 65.04448MHz

CLK

= 5.301935MHz

f

IN

= -0.5dBFS

A

IN

SNR = 69.5dB
SINAD = 69.47dB
THD = -90.94dBc
SFDR = 93.27dBc

HD3

HD2

= 5.3489349MHz
= 30.2683055MHz

MAX1127 toc01

284 8 12 2016 24

CROSSTALK

(4096-POINT DATA RECORD)

0

-10

-20

MAX1127 toc03

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

284 8 12 2016 24

032

FREQUENCY (MHz)

FFT PLOT

f

= 65.04448MHz

CLK

= 30.30301MHz

f

IN

= -0.5dBFS

A

IN

SNR = 69.45dB
SINAD = 69.4dB
THD = -89.3dBc
SFDR = 89.7dBc

HD2

FREQUENCY (MHz)

HD3

CROSSTALK

(4096-POINT DATA RECORD)

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 3.

= 5.3489349MHz

f

IN(IN1)

= 30.2683055MHz

f

IN(IN3)

FREQUENCY (MHz)

284 8 12 2016 24

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2.

= 5.3489349MHz

f

IN(IN1)

= 30.2683055MHz

f

IN(IN2)

284 8 12 2016 24

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

0

-10

-20

MAX1127 toc04

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110
032

MAX1127toc02

MAX1127 toc05

284 8 12 2016 24

TWO-TONE INTERMODULATION DISTORTION

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

f

IN(IN1)

f

IN(IN2)

= -6.5dBFS

A

IN1

= -6.5dBFS

A

IN2

IMD = 91.2dBc
IM3 = 95.7dBc

FREQUENCY (MHz)

= 12.348685MHz
= 13.650845MHz

284 8 12 2016 24

MAX1127 toc06

GAIN (dB)

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

GAIN BANDWIDTH PLOT

SMALL-SIGNAL
BANDWIDTH

-20dBFS

FULL-POWER
BANDWIDTH

-0.5dBFS

1 100 1000

10

ANALOG INPUT FREQUENCY (MHz)

MAX1127 toc07

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

72

71

70

69

68

67

SNR (dB)

66

65

64

63

62

0 175

fIN (MHz)

MAX1127 toc08

15012575 1005025

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

72

71

70

69

68

67

SINAD (dB)

66

65

64

63

62

0175

MAX1127 toc09

15012575 1005025

fIN (MHz)

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

-55

-60

-65

-70

-75

-80

THD (dBc)

-85

-90

-95

-100
0175

fIN (MHz)

MAX1127 toc10

15012575 1005025

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

100

95

90

85

80

75

SFDR (dBc)

70

65

60

55

0175

fIN (MHz)

MAX1127 toc11

15012575 1005025