The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a
19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input voltage range.
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide variations in input-clock duty cycle. An on-chip phaselocked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.
The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.
The MAX1127 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
Applications
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
Features
♦ Four ADC Channels with Serial LVDS/SLVS
Outputs
♦ Excellent Dynamic Performance
69.6dB SNR at fIN= 19.3MHz
92dBc SFDR at f
IN
= 19.3MHz
-87dB Channel Isolation
♦ Ultra-Low Power
135mW per Channel (Normal Operation)
1.2mW Total (Shutdown Mode)
♦ Accepts 20% to 80% Clock Duty Cycle
♦ Self-Aligning Data-Clock to Data-Output Interface
, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto GND.........................................................-0.3V to +2.0V
CV
DD
to GND ........................................................-0.3V to +3.6V
OV
DD
to GND ........................................................-0.3V to +2.0V
IN_P, IN_N to GND...................................-0.3V to (AV
DD
+ 0.3V)
CLK to GND.............................................-0.3V to (CV
DD
+ 0.3V)
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND................................-0.3V to (OV
DD
+ 0.3V)
DT, SLVS/LVDS to GND...........................-0.3V to (AV
DD
+ 0.3V)
PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV
DD
+ 0.3V)
PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV
DD
+ 0.3V)
T/B, LVDSTEST to GND ...........................-0.3V to (AV
DD
+ 0.3V)
REFIO, REFADJ, CMOUT to GND ...........-0.3V to (AV
DD
+ 0.3V)
I.C. to GND...............................................-0.3V to (AV
Note 1: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2: See definition in the Parameter Definitions section.
Note 3: The MAX1127 internally sets the common-mode voltage to 0.76V (typ) (see Figure 1). The common-mode voltage can be
overdriven to between 0.55V and 0.85V.
Note 4: Limited by MAX1127EVKIT input circuitry.
Note 5: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AV
DD
directly to disable the inter-
nal bandgap reference and enable external reference mode.
Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7: Guaranteed by design and characterization. Not subject to production testing.
Note 8: Sample CLK rise to FRAME rise timing is measured from 50% of sample clock input level to 50% of FRAME output level.