MAXIM MAX1127 Technical data

General Description

The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to

1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a

19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.

An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt­age range.

A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia­tions in input-clock duty cycle. An on-chip phase­locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.

The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.

Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.

The MAX1127 is available in a small, 10mm x 10mm x

0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.

Applications

Ultrasound and Medical Imaging

Positron Emission Tomography (PET) Imaging

Multichannel Communication Systems

Instrumentation

Features

♦ Four ADC Channels with Serial LVDS/SLVS

Outputs

♦ Excellent Dynamic Performance

69.6dB SNR at fIN= 19.3MHz
92dBc SFDR at f

IN

= 19.3MHz

-87dB Channel Isolation

♦ Ultra-Low Power

135mW per Channel (Normal Operation)

1.2mW Total (Shutdown Mode)

♦ Accepts 20% to 80% Clock Duty Cycle

♦ Self-Aligning Data-Clock to Data-Output Interface

♦ Fully Differential Analog Inputs
♦ Wide ±1.4V

P-P

Differential Input Voltage Range

♦ Internal/External Reference Option

♦ Test Mode for Digital Signal Integrity

♦ LVDS Outputs Support Up to 30in FR-4 Backplane

Connections

♦ Small, 68-Pin QFN with Exposed Paddle

♦ Evaluation Kit Available (MAX1127EVKIT)

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3144; Rev 2; 9/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration

PART TEMP RANGE PIN-PACKAGE

MAX1127EGK -40°C to +85°C

68 QFN 10mm x
x 10mm x 0.9mm

REFADJ

6768

1GND

2IN0P

3IN0N

4GND

5IN1P

6IN1N

7GND

8AV

DD

9AV

DD

10AV

DD

11GND

12IN2P

13IN2N

14GND

15IN3P

16IN3N

17GND

18

19

DD

AV

CMOUT

65

EP

20

21

22

DD

DD

GND

AV

CV

T/B

6364

23

CLK

10mm x 10mm x 0.9mm

59

60

61

62

MAX1127

24

25

26

27

28DT29 30

DD

DD

DD

GND

AV

AV

AV

QFN

PLL031PLL132PLL233PLL3

SLVS/LVDS

DD

DD

DD

DD

DD

AV

AV

AV

AV

LVDSTEST

GND66REFIO

GND

DD

OV

PD054PD155PD256PD357PDALL58AV

52

53

51 OUT0P

50 OUT0N

49 OV

DD

48 OUT1P

47 OUT1N

46 OV

DD

45 CLKOUTP

CLKOUTN

44

OV

43

DD

FRAMEP

42

41 FRAMEN

40 OV

DD

39 OUT2P

38 OUT2N

37 OV

DD

36 OUT3P

35 OUT3N

34

DD

OV

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto GND.........................................................-0.3V to +2.0V

CV

DD

to GND ........................................................-0.3V to +3.6V

OV

DD

to GND ........................................................-0.3V to +2.0V

IN_P, IN_N to GND...................................-0.3V to (AV

DD

+ 0.3V)

CLK to GND.............................................-0.3V to (CV

DD

+ 0.3V)

OUT_P, OUT_N, FRAME_,

CLKOUT_ to GND................................-0.3V to (OV

DD

+ 0.3V)

DT, SLVS/LVDS to GND...........................-0.3V to (AV

DD

+ 0.3V)

PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV

DD

+ 0.3V)

PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV

DD

+ 0.3V)

T/B, LVDSTEST to GND ...........................-0.3V to (AV

DD

+ 0.3V)

REFIO, REFADJ, CMOUT to GND ...........-0.3V to (AV

DD

+ 0.3V)

I.C. to GND...............................................-0.3V to (AV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)
68-Pin QFN 10mm x 10mm x 0.9mm

(derated 41.7mW/°C above +70°C)........................3333.3mW

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature Range (soldering, 10s)......................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution N 12 Bits
Integral Nonlinearity INL (Note 2) ±0.4 LSB
Differential Nonlinearity DNL (Note 2) ±0.25 LSB

Offset Error

Gain Error

ANALOG INPUTS (IN_P, IN_N)

Input Differential Range V

Common-Mode Voltage Range V

Differential Input Impedance R

Differential Input Capacitance C

CONVERSION RATE

Maximum Conversion Rate f

Minimum Conversion Rate f

Data Latency 6.5 Cycles

DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)

Signal-to-Noise and Distortion
(First Four Harmonics) (Note 2)

ID

CMO

IN

IN

SMAX

SMIN

SINAD

Fixed external reference (Note 2) ±1
Fixed external reference (Note 2) ±1.5

Differential input 1.4 V

(Note 3) 0.76 V
Switched capacitor load 2 kΩ

fIN = 5.3MHz at -0.5dBFS 69.7

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 66.6 69.6Signal-to-Noise Ratio (Note 2) SNR

f

IN

fIN = 5.3MHz at -0.5dBFS 69.6

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 66.5 69.5

f

IN

fIN = 5.3MHz at -0.5dBFS 11.4

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 11.4Effective Number of Bits (Note 2) ENOB

f

IN

= 30.3MHz at -0.5dBFS 69.4

= 30.3MHz at -0.5dBFS 69.3

= 30.3MHz at -0.5dBFS 11.3

12.5 pF

65 MHz

4 MHz

% FS

% FS

P-P

dB

dB

Bits

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Spurious-Free Dynamic Range
(Note 2)

Inter m od ul ati on D i stor ti on IMD

Third-Order Intermodulation IM3 (Note 2) 95.7 dBc

Aperture Jitter t

Aperture Delay t

Small-Signal Bandwidth SSBW Input at -20dBFS (Notes 2 and 4) 100 MHz

Full-Power Bandwidth LSBW Input at -0.5dBFS (Notes 2 and 4) 100 MHz

Output Noise INP = IN_N 0.45 LSB

Overdrive Recovery Time t

COMMON-MODE OUTPUT (CMOUT)

CMOUT Output Voltage V

INTERNAL REFERENCE (REFADJ = GND, bypass REFIO to GND with 0.1µF)

REFADJ Internal Reference Mode
Enable Voltage

REFADJ Low-Leakage Current 1.6 mA

REFIO Output Voltage V

Reference Temperature
Coefficient

EXTERNAL REFERENCE (REFADJ = AVDD)

REFADJ External Reference
Mode Enable Voltage

REFADJ High-Leakage Current 125 µA

REFIO Input Voltage Range 1.24 V

REFIO Input Voltage Tolerance ±5 %

REFIO Input Current I

CLOCK INPUT (CLK)

Input High Voltage V

Input Low Voltage V

Clock Duty Cycle 50 %

Clock Duty-Cycle Tolerance ±30 %

SFDR

AJ

AD

OR

CMOUT

REFIO

TC

REFIO

REFIO

CLKH

CLKL

fIN = 5.3MHz at -0.5dBFS 93.3

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C 77.5 92

f

IN

fIN = 5.3MHz at -0.5dBFS -91

fIN = 19.3MHz at -0.5dBFS, TA ≥ +25°C -91 -77.5Total H ar m oni c D i st or ti on ( N ote 2) THD

f

IN

f

1

f

2

(Note 2) < 0.4 ps

(Note 2) 1 ns

RS = 25Ω, CS = 50pF 1

(Note 5) 0.1 V

(Note 5)

= 30.3MHz at -0.5dBFS 88.9

= 30.3MHz at -0.5dBFS -88

= 12.348685MHz at -6.5dBFS,
= 13.650845MHz at -6.5dBFS ( N ote 2)

91.2 dBc

0.76 V

1.18 1.24 1.30 V

100 ppm/°C

AV

-

DD

0.1V

< 1 µA

0.8 x

AV

DD

0.2 x

AV

DD

Clock

cycles

dBc

dBc

RMS

RMS

V

V

V

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage DI

Input Capacitance DC

DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)

Input High Threshold V

Input Low Threshold V

Input Leakage DI

Input Capacitance DC

Input at GND 5

IN

Input at AV

IN

IH

IL

Input at GND 5

IN

Input at AV

IN

DD

DD

LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0)

Differential Output Voltage V

OHDIFFRTERM

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

OCM

R

F

= 100Ω 250 450 mV

R

= 100Ω 1.125 1.375 V

TERM

R

= 100Ω, C

TERM

R

TERM

= 100Ω, C

LOAD

LOAD

SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1

Differential Output Voltage V

OHDIFFRTERM

Output Common-Mode Voltage V

Rise Time (20% to 80%) t

Fall Time (80% to 20%) t

OCM

R

F

= 100Ω 205 mV

R

= 100Ω 220 mV

TERM

R

= 100Ω, C

TERM

R

TERM

= 100Ω, C

LOAD

LOAD

POWER-DOWN

PD Fall to Output Enable t

PD Rise to Output Disable t

ENABLE

DISABLE

POWER REQUIREMENTS

AVDD Supply Voltage AV

OVDD Supply Voltage OV

CVDD Supply Voltage CV

DD

DD

DD

= 5pF 150 ps

= 5pF 150 ps

= 5pF 120 ps

= 5pF 120 ps

80

5pF

0.8 x

AV

DD

0.2 x

AV

DD

80

5pF

132 µs

10 ns

1.7 1.8 1.9 V

1.7 1.8 1.9 V

1.7 1.8 3.6 V

µA

V

V

µA

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVDD Supply Current I

OVDD Supply Current I

AVDD

OVDD

f

=

IN

19.3MHz at

-0.5dBFS

f

=

IN

19.3MHz at

-0.5dBFS

PDALL = 0, all channels
active

PDALL = 0, all channels
active, DT = 1

PDALL = 0, 1 channel active 82

PDALL = 0, PD[3:0] = 1111 23

PDALL = 1, global power
down, PD[3:0] =1111, no
clock input

PDALL = 0, all channels
active

PDALL = 0, all channels
active, DT = 1

PDALL = 0, 1 channel active 42

PDALL = 0, PD[3:0] = 1111 37

PDALL = 1, global power­down, PD[3:0] =1111, no
clock input

257 295

257

300 µA

56 65

72

375 µA

mA

mA

CVDD Supply Current I

Power Dissipation P

TIMING CHARACTERISTICS (Note 6)

Data Valid to CLKOUT Rise/Fall t

CLKOUT Output Width High t

CLKOUT Output Width Low t

FRAME Rise to CLKOUT Rise t

Sample CLK Rise to Frame Rise t

CVDD

DISSfIN

OD

CH

CL

CF

SF

CVDD is used only to bias ESD-protection
diodes on CLK input, Figure 2

= 19.3MHz at -0.5dBFS 563 648 mW

(t

SAMPLE

f

= 65MHz, Figure 5 (Notes 6 and 7)

CLK

Figure 5

Figure 5

Figure 4 (Note 7)

Figure 4 (Notes 7 and 8)

24)

- 0.15

(t

SAMPLE

24)

- 0.15

(t

SAMPLE

+0.9

2)

0mA

/

t

SAMPLE

t

S AMP LE

t

S AMP LE

/

t

SAMPLE

/

(t

SAMPLE

24

12

12

24

2)

+1.3

/

/

/

/

/

(t

SAMPLE

24)

+ 0.15

( t

SAMPLE

24)

+ 0.15

(t

SAMPLE

2)

+1.7

/

ns

ns

ns

/

ns

/

ns

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

6 _______________________________________________________________________________________

Note 1: Specifications at TA≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization and not subject to production testing.

Note 2: See definition in the Parameter Definitions section.
Note 3: The MAX1127 internally sets the common-mode voltage to 0.76V (typ) (see Figure 1). The common-mode voltage can be

overdriven to between 0.55V and 0.85V.

Note 4: Limited by MAX1127EVKIT input circuitry.
Note 5: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AV

DD

directly to disable the inter-

nal bandgap reference and enable external reference mode.

Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7: Guaranteed by design and characterization. Not subject to production testing.
Note 8: Sample CLK rise to FRAME rise timing is measured from 50% of sample clock input level to 50% of FRAME output level.

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD

= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, C

REFIO

to GND = 0.1µF,

f

CLK

= 65MHz (50% duty cycle), DT = 0, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHANNEL-TO-CHANNEL MATCHING

Crosstalk (Note 2) -87 dB

Gain Matching fIN = 30.3MHz (Note 2) ±0.1 dB

Phase Matching fIN = 30.3.MHz (Note 2) ±1 Degrees

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 7

Typical Operating Characteristics

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

FFT PLOT

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

FREQUENCY (MHz)

CROSSTALK

(4096-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110
032

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 0.
f

IN(IN1)

f

IN(IN0)

FREQUENCY (MHz)

f

= 65.04448MHz

CLK

= 5.301935MHz

f

IN

= -0.5dBFS

A

IN

SNR = 69.5dB
SINAD = 69.47dB
THD = -90.94dBc
SFDR = 93.27dBc

HD3

HD2

= 5.3489349MHz
= 30.2683055MHz

MAX1127 toc01

284 8 12 2016 24

CROSSTALK

(4096-POINT DATA RECORD)

0

-10

-20

MAX1127 toc03

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

284 8 12 2016 24

032

FREQUENCY (MHz)

FFT PLOT

f

= 65.04448MHz

CLK

= 30.30301MHz

f

IN

= -0.5dBFS

A

IN

SNR = 69.45dB
SINAD = 69.4dB
THD = -89.3dBc
SFDR = 89.7dBc

HD2

FREQUENCY (MHz)

HD3

CROSSTALK

(4096-POINT DATA RECORD)

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 3.

= 5.3489349MHz

f

IN(IN1)

= 30.2683055MHz

f

IN(IN3)

FREQUENCY (MHz)

284 8 12 2016 24

MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2.

= 5.3489349MHz

f

IN(IN1)

= 30.2683055MHz

f

IN(IN2)

284 8 12 2016 24

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

0

-10

-20

MAX1127 toc04

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110
032

MAX1127toc02

MAX1127 toc05

284 8 12 2016 24

TWO-TONE INTERMODULATION DISTORTION

(32,768-POINT DATA RECORD)

0

-10

-20

-30

-40

-50

-60

-70

AMPLITUDE (dBFS)

-80

-90

-100

-110

-120
032

f

IN(IN1)

f

IN(IN2)

= -6.5dBFS

A

IN1

= -6.5dBFS

A

IN2

IMD = 91.2dBc
IM3 = 95.7dBc

FREQUENCY (MHz)

= 12.348685MHz
= 13.650845MHz

284 8 12 2016 24

MAX1127 toc06

GAIN (dB)

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

GAIN BANDWIDTH PLOT

SMALL-SIGNAL
BANDWIDTH

-20dBFS

FULL-POWER
BANDWIDTH

-0.5dBFS

1 100 1000

10

ANALOG INPUT FREQUENCY (MHz)

MAX1127 toc07

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

72

71

70

69

68

67

SNR (dB)

66

65

64

63

62

0 175

fIN (MHz)

MAX1127 toc08

15012575 1005025

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

72

71

70

69

68

67

SINAD (dB)

66

65

64

63

62

0175

MAX1127 toc09

15012575 1005025

fIN (MHz)

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

-55

-60

-65

-70

-75

-80

THD (dBc)

-85

-90

-95

-100
0175

fIN (MHz)

MAX1127 toc10

15012575 1005025

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

100

95

90

85

80

75

SFDR (dBc)

70

65

60

55

0175

fIN (MHz)

MAX1127 toc11

15012575 1005025

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT POWER

72

fIN = 5.301935MHz

67

62

57

52

SNR (dB)

47

42

37

32

-30 0
ANALOG INPUT POWER (dBFS)

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT POWER

-55
fIN = 5.301935MHz

-60

-65

-70

-75

-80

THD (dBc)

-85

-90

-95

-100

-30 0
ANALOG INPUT POWER (dBFS)

MAX1127 toc12

-5-10-25 -20 -15

MAX1127 toc14

-5-10-25 -20 -15

SIGNAL TO NOISE + DISTORTION

vs. ANALOG INPUT POWER

72

fIN = 5.301935MHz

67

62

57

52

SINAD (dB)

47

42

37

32

-30 0
ANALOG INPUT POWER (dBFS)

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT POWER

100

fIN = 5.301935MHz

95

90

85

80

75

SFDR (dBc)

70

65

60

55

-30 0
ANALOG INPUT POWER (dBFS)

MAX1127 toc13

-5-10-25 -20 -15

MAX1127 toc15

-5-10-25 -20 -15

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. SAMPLING RATE

72

fIN = 5.301935MHz

71

70

69

68

67

SNR (dB)

66

65

64

63

62

0

45 50 55 60

353020 2510 155

40

f

(MHz)

CLK

MAX1127 toc16

65

SIGNAL-TO-NOISE PLUS DISTORTION

vs. SAMPLING RATE

72

fIN = 5.301935MHz

71

70

69

68

67

SINAD (dB)

66

65

64

63

62

f

CLK

353020 2510 1550

(MHz)

45 50 55 60

40

MAX1127 toc17

65

-75

-80

-85

-90

THD (dBc)

-95

-100

-105

TOTAL HARMONIC DISTORTION

vs. SAMPLING RATE

fIN = 5.301935MHz

45 50 55 60

353020 2510 1550

40

f

(MHz)

CLK

65

MAX1127 toc18

SPURIOUS-FREE DYNAMIC RANGE

vs. SAMPLING RATE

105

fIN = 5.301935MHz

100

95

90

SFDR (dBc)

85

80

75

f

CLK

353020 2510 1550

(MHz)

45 50 55 60

40

MAX1127 toc19

65

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 11

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. CLOCK DUTY CYCLE

72

fIN = 5.301935MHz

71

70

69

68

67

SNR (dB)

66

65

64

63

62

30 70

CLOCK DUTY CYCLE (%)

TOTAL HARMONIC DISTORTION

vs. CLOCK DUTY CYCLE

-75
fIN = 5.301935MHz

-80

-85

6040 50

MAX1127 toc20

MAX1127 toc22

SIGNAL-TO-NOISE + DISTORTION

vs. CLOCK DUTY CYCLE

72

fIN = 5.301935MHz

71

70

69

68

67

SINAD (dB)

66

65

64

63

62

30 70

CLOCK DUTY CYCLE (%)

6040 50

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK DUTY CYCLE

100

fIN = 5.301935MHz

95

90

MAX1127 toc21

MAX1127 toc23

-90

THD (dBc)

-95

-100

-105
30 70

40 6050

CLOCK DUTY CYCLE (%)

85

SFDR (dBc)

80

75

70

30 70

40 6050

CLOCK DUTY CYCLE (%)

ANALOG SUPPLY CURRENT

vs. SAMPLING RATE

f

CLK

(MHz)

I

AVDD

(mA)

30 504025 45 605535

MAX1127 toc28

240

250

230

260

270

220

20 65

DIGITAL SUPPLY CURRENT

vs. SAMPLING RATE

f

CLK

(MHz)

I

OVDD

(mA)

30 504025 45 605535

MAX1127 toc29

20

40

10

60

30

50

70

0

20 65

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO

vs. TEMPERATURE

TEMPERATURE (°C)

SNR (dB)

-15 10 6035

66

68

64

70

72

62

-40 85

MAX1127 toc24

f

CLK

= 65.04065041MHz

f

IN

= 19.29703379MHz

4096-POINT DATA RECORD

SIGNAL-TO-NOISE + DISTORTION

vs. TEMPERATURE

TEMPERATURE (°C)

SINAD (dB)

-15 10 6035

66

68

64

70

72

62

-40 85

MAX1127 toc25

f

CLK

= 65.04065041MHz

f

IN

= 19.29703379MHz

4096-POINT DATA RECORD

TOTAL HARMONIC DISTORTION

vs. TEMPERATURE

TEMPERATURE (°C)

THD (dBc)

-15 10 6035

-95

-90

-100

-85

-80

-75

-105

-40 85

MAX1127 toc26

f

CLK

= 65.04065041MHz

f

IN

= 19.29703379MHz

4096-POINT DATA RECORD

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE

TEMPERATURE (°C)

SFDR (dBc)

-15 10 6035

85

90

80

75

95

100

70

-40 85

MAX1127 toc27

f

CLK

= 65.04065041MHz

f

IN

= 19.29703379MHz

4096-POINT DATA RECORD

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 13

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

V

REFIO

(V)

2.01.91.8

1.236

1.237

1.238

1.239

1.235

1.7 2.1

MAX1127 toc34

AVDD = OV

DD

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

V

REFIO

(V)

603510-15

1.23

1.24

1.25

1.26

1.22

-40 85

MAX1127 toc35

AVDD = OV

DD

INTERNAL REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT

I

REFIO

(µA)

V

REFIO

(V)

300200-300 -200 -100 0 100

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.00

-400 400

MAX1127 toc36

NEGATIVE CURRENT
FLOWS INTO REFIO

OFFSET ERROR

vs. TEMPERATURE

0.06

0.05

0.04

0.03

OFFSET ERROR (%FS)

0.02

0.01

-15 10 6035

-40 85

TEMPERATURE (°C)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

0.5

0.4

0.3

0.2

0.1

0

INL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5

1024 30722048512 2560 35841536

0 4096

DIGITAL OUTPUT CODE

MAX1127 toc30

MAX1127 toc32

GAIN ERROR

vs. TEMPERATURE

1.0

0.8

0.6

0.4

0.2

0

-.0.2

GAIN ERROR (%FS)

-0.4

-0.6

-0.8

-1.0

-15 10 6035

-40 85

TEMPERATURE (°C)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

0.5

0.4

0.3

0.2

0.1

0

DNL (LSB)

-0.1

-0.2

-0.3

-0.4

-0.5
1024 30722048512 2560 35841536

0

DIGITAL OUTPUT CODE

MAX1127 toc31

MAX1127 toc33

4096

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

14 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 1.8V, OVDD= 1.8V, CVDD= 1.8V, GND = 0, external V

REFIO

= 1.24V, REFADJ = AVDD, differential input at -0.5dBFS,

f

CLK

= 65MHz (50% duty cycle), DT = low, C

LOAD

= 10pF, TA= +25°C, unless otherwise noted.)

CMOUT VOLTAGE

vs. SUPPLY VOLTAGE

MAX1127 toc37

SUPPLY VOLTAGE (V)

V

CMOUT

(V)

2.01.91.8

0.757

0.759

0.761

0.763

0.765

0.755

1.7 2.1

AVDD = OV

DD

CMOUT VOLTAGE

vs. TEMPERATURE

MAX1127 toc38

TEMPERATURE (°C)

V

CMOUT

(V)

603510-15

0.757

0.759

0.761

0.763

0.765

0.755

-40 85

AVDD = OV

DD

CMOUT VOLTAGE

vs. LOAD CURRENT

MAX1127 toc39

I

CMOUT

(µA)

V

CMOUT

(V)

2500200015001000500

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0

0 3000

NEGATIVE CURRENT
FLOWS INTO CMOUT

Pin Description

PIN NAME FUNCTION

1, 4, 7, 11,
14, 17, 22,

24, 65, 68

2 IN0P Channel 0 Positive Analog Input

3 IN0N Channel 0 Negative Analog Input

5 IN1P Channel 1 Positive Analog Input

6 IN1N Channel 1 Negative Analog Input

8, 9, 10, 18,

20, 25, 26,

27, 58–62

12 IN2P Channel 2 Positive Analog Input

13 IN2N Channel 2 Negative Analog Input

15 IN3P Channel 3 Positive Analog Input

16 IN3N Channel 3 Negative Analog Input

19 CMOUT Common-Mode Reference Voltage Output. Bypass CMOUT to GND with a 0.1µF capacitor

21 CV

23 CLK Single-Ended CMOS Clock Input

28 DT

GND Ground. Connect all GND pins to the same potential.

Analog Power Input. Connect AVDD to a 1.7V to 1.9V power supply. Bypass each AVDD to GND with

AV

DD

a 0.1µF capacitor as close to the device as possible. Bypass the AV
ground plane with a bulk ≥ 2.2µF capacitor as close to the device as possible. Connect all AV
to the same potential.

Clock Power Input. Connect CVDD to a 1.7V to 3.6V supply. Bypass CVDD to GND with a 0.1µF

DD

capacitor in parallel with a ≥ 2.2µF capacitor. Install the bypass capacitors as close to the device as
possible.

Double Termination Select Input. Drive DT high to select the internal 100Ω termination between the
differential output pairs. Drive DT low to select no internal output termination.

power plane to the GND

DD

DD

pins

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 15

Pin Description (continued)

PIN NAME FUNCTION

29 SLVS/LVDS

30 PLL0 PLL Control Input 0. PLL0 is reserved for factory testing only and must always be connected to GND.

31 PLL1 PLL Control Input 1. See Table 1 for details.

32 PLL2 PLL Control Input 2. See Table 1 for details.

33 PLL3 PLL Control Input 3. See Table 1 for details.

34, 37, 40,
43, 46, 49,

52

35 OUT3N Channel 3 Negative LVDS/SLVS Output

36 OUT3P Channel 3 Positive LVDS/SLVS Output

38 OUT2N Channel 2 Negative LVDS/SLVS Output

39 OUT2P Channel 2 Positive LVDS/SLVS Output

41 FRAMEN

42 FRAMEP

44 CLKOUTN Negative LVDS/SLVS Serial Clock Output

45 CLKOUTP Positive LVDS/SLVS Serial Clock Output

47 OUT1N Channel 1 Negative LVDS/SLVS Output

48 OUT1P Channel 1 Positive LVDS/SLVS Output

50 OUT0N Channel 0 Negative LVDS/SLVS Output

51 OUT0P Channel 0 Positive LVDS/SLVS Output

53 PD0

54 PD1

55 PD2

56 PD3

57 PDALL

63 T/B

OV

DD

Differential Output Signal Format Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive
SLVS/LVDS low to select LVDS outputs.

Output-Driver Power Input. Connect OVDD to a 1.7V to 1.9V power supply. Bypass each OVDD to
GND with a 0.1µF capacitor as close to the device as possible. Bypass the OV
GND ground plane with a bulk ≥ 2.2µF capacitor as close to the device as possible. Connect all

pins to the same potential.

OV

DD

Negative Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.

Positive Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to
a valid D0 in the output data stream.

Channel 0 Power-Down Input. Drive PD0 high to power-down channel 0. Drive PD0 low for normal
operation.

Channel 1 Power-Down Input. Drive PD1 high to power-down channel 1. Drive PD1 low for normal
operation.

Channel 2 Power-Down Input. Drive PD2 high to power-down channel 2. Drive PD2 low for normal
operation.

Channel 3 Power-Down Input. Drive PD3 high to power-down channel 3. Drive PD3 low for normal
operation.

Global Power-Down Input. Drive PDALL high to power-down all channels and reference. Drive PDALL
low for normal operation.

Output Format Select Input. Drive T/B high to select binary output format. Drive T/B low to select two’s
complement output format.

power plane to the

DD

64 LVDSTEST

LVDS Test Pattern Enable Input. Drive LVDSTEST high to enable the output test pattern
(000010111101 MSB→LSB). As with the analog conversion results, the test pattern data is output
LSB first. Drive LVDSTEST low for normal operation.

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

16 ______________________________________________________________________________________

Functional Diagram

Pin Description (continued)

PIN NAME FUNCTION

Reference Input/Output. For internal reference operation (REFADJ = GND), the reference output

66 REFIO

67 REFADJ

voltage is 1.24V. For external reference operation (REFADJ = AV
at REFIO. Bypass to GND with a 0.1µF capacitor.

Internal/External Reference Mode Select Input. For internal reference mode, connect REFADJ directly
to GND. For external reference mode, connect REFADJ directly to AVDD. For reference-adjust mode,
see the Full-Scale Range Adjustments Using the Internal Reference section.

), apply a stable reference voltage

DD

—EP

CMOUT

IN0P

IN0N

IN1P

IN1N

IN2P

IN2N

Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve
specified performance.

REFADJ

REFIO

REFERENCE

SYSTEM

PDALL PD0 PD1 PD2 PD3

POWER CONTROL

ICMV*

T/H

T/H

T/H

12-BIT

PIPELINE

12-BIT

PIPELINE

12-BIT

PIPELINE

ADC

ADC

ADC

AV

DD

MAX1127

SERIALIZER

SERIALIZER

SERIALIZER

OV

12:1

12:1

12:1

DT

DD

SLVS/LVDS

OUTPUT

CONTROL

LVDS/SLVS

OUTPUT

DRIVERS

LVDSTEST

T/B

OUT0P

OUT0N

OUT1P

OUT1N

OUT2P

OUT2N

OUT3P

OUT3N

IN3P

IN3N

CLK

*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED)

CLOCK

CIRCUITRY

CV

DD PLL3PLL0 PLL1 PLL2

T/H

12-BIT

PIPELINE

ADC

PLL

6x

12:1

SERIALIZER

GND

FRAMEP

FRAMEN

CLKOUTP

CLKOUTN

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 17

Detailed Description

The MAX1127 ADC features fully differential inputs, a
pipelined architecture, and digital error correction for
high-speed signal conversion. The ADC pipeline archi­tecture moves the samples taken at the inputs through
the pipeline stages every half clock cycle. The convert­ed digital results are serialized and sent through the
LVDS/SLVS output drivers. The total latency from input
to output is 6.5 input clock cycles.

The MAX1127 offers four separate fully differential
channels with synchronized inputs and outputs.
Configure the outputs for binary or two’s complement
with the T/B digital input. Power-down each channel
individually or globally to minimize power consumption.

Input Circuit

Figure 1 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a, S2b,
S4a, S4b, S5a, and S5b are closed. The fully differential
circuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the operational transcon-

ductance amplifier (OTA), and open simultaneously with
S1, sampling the input waveform. Switches S4a, S4b,
S5a, and S5b are then opened before switches S3a and
S3b connect capacitors C1a and C1b to the output of
the amplifier and switch S4c is closed. The resulting dif­ferential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These val­ues are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs.
Analog inputs IN_P to IN_N are driven differentially. For
differential inputs, balance the input impedance of IN_P
and IN_N for optimum performance.

The MAX1127 analog inputs are self-biased at a com­mon-mode voltage of 0.76V (typ) and allow a differen­tial input voltage swing of 1.4V

P-P

. The common-mode
voltage can be overdriven to between 0.55V to 0.85V.
Drive the analog inputs of the MAX1127 in AC-coupled
configuration to achieve best dynamic performance.
See the Using Transformer Coupling section for a
detailed discussion of this configuration.

Figure 1. Internal Input Circuitry

INTERNAL

COMMON-MODE

BIAS*

SWITCHES SHOWN IN TRACK MODE

INTERNALLY
GENERATED

INTERNAL

BIAS*

COMMON-MODE

LEVEL*

AV

DD

IN_P

IN_N

GND

*NOT EXTERNALLY ACCESSIBLE

S4a

S4b

INTERNAL

COMMON-MODE

BIAS*

MAX1127

C2a

S4c S1

C2b

S2a

S2b

INTERNAL

BIAS*

S5a

C1a

S3a

OUT

OTA

OUT

C1b

S3b

S5b

INTERNALLY

GENERATED

COMMON-MODE

LEVEL*

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

18 ______________________________________________________________________________________

Reference Configurations

(REFIO and REFADJ)

The MAX1127 provides an internal 1.24V bandgap ref­erence or can be driven with an external reference volt­age. The MAX1127 full-scale analog differential input
range is ±FSR. Full-scale range (FSR) is given by the
following equation:

where V

REFIO

is the voltage at REFIO, generated inter-

nally or externally. For a V

REFIO

= 1.24V, the full-scale

input range is ±700mV (1.4V

P-P

).

Internal Reference Mode

Connect REFADJ to GND to use the internal bandgap
reference directly. The internal bandgap reference gen­erates REFIO to be 1.24V with a 100ppm/°C tempera­ture coefficient in internal reference mode. Connect an
external ≥ 0.1µF bypass capacitor from REFIO to GND
for stability. REFIO sources up to 200µA and sinks up
to 200µA for external circuits, and REFIO has a load
regulation of 83mV/mA. The global power-down input
(PDALL) enables and disables the reference circuit.
REFIO has > 1MΩ resistance to GND when the
MAX1127 is in power-down mode. The internal refer­ence circuit requires 132µs to power-up and settle
when power is applied to the MAX1127 or when PDALL
transitions from high to low.

To compensate for gain errors or to decrease or
increase the ADC’s full-scale range (FSR), add an
external resistor between REFADJ and GND or REFADJ
and REFIO. This adjusts the internal reference value of
the MAX1127 by up to ±5% of its nominal value. See
the Full-Scale Range Adjustments Using the Internal
Reference section.

External Reference Mode

The external reference mode allows for more control
over the MAX1127 reference voltage and allows multi­ple converters to use a common reference. Connect
REFADJ to AV

DD

to disable the internal reference and

enter external reference mode. Apply a stable 1.18V to

1.30V source at REFIO. Bypass REFIO to GND with a

0.1µF capacitor. The REFIO input impedance is >1MΩ.

Clock Input (CLK)

The MAX1127 accepts a CMOS-compatible clock sig­nal with a wide 20% to 80% input-clock duty cycle.
Drive CLK with an external single-ended clock signal.
Figure 2 shows the simplified clock input diagram.

Low clock jitter is required for the specified SNR perfor­mance of the MAX1127. Analog input sampling occurs
on the rising edge of CLK, requiring this edge to pro­vide the lowest possible jitter. Jitter limits the maximum
SNR performance of any ADC according to the follow­ing relationship:

where fINrepresents the analog input frequency and t

J

is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 69.4dB of SNR with an input fre­quency of 30.3MHz, the system must have less than

1.8ps of clock jitter. In actuality, there are other noise
sources, such as thermal noise and quantization noise,
that contribute to the system noise requiring the clock
jitter to be less than 0.5ps to obtain the specified

69.4dB of SNR at 30.3MHz.

Figure 2. Clock Input Circuitry

Table 1. PLL1, PLL2, and PLL3 Configuration

*PLL0 is reserved for factory testing and must always be con­nected to GND.

V

FSR mV

=×700

REFIO

124.

V

AV

CV

DD

DD

CLK

GND

MAX1127

DUTY-CYCLE

EQUALIZER

SNR

20

log

=×

⎛
⎜

2

π

×× ×

⎝

1

⎞
⎟

ft

⎠

IN J

CLOCK INPUT RANGE

PLL1 PLL2 PLL3

0

0

0

0

1

1

1

1

0 0 45.0 65.0

0 1 32.5 45.0

1 0 22.5 32.5

1 1 16.3 22.5

0 0 11.3 16.3

0 1 8.1 11.3

1 0 5.6 8.1

1 1 4.0 5.6

(MHz)

MIN MAX

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 19

The MAX1127 features a PLL that generates an output
clock signal with six times the frequency of the input
clock. The output clock signal is used to clock data out
of the MAX1127 (see the System Timing Requirements
section). Set the PLL1, PLL2, and PLL3 bits according
to the input clock range provided in Table 1. PLL0 is
reserved for factory testing and must always be con­nected to GND.

System Timing Requirements

Figure 3 shows the relationship between the analog
inputs, input clock, frame alignment output, serial clock
output, and serial data output. The differential analog
input (IN_P and IN_N) is sampled on the rising edge of
the CLK signal and the resulting data appears at the
digital outputs 6.5 clock cycles later. Figure 4 provides
a detailed, two-conversion timing diagram of the rela­tionship between the inputs and the outputs.

(V

Figure 3. Global Timing Diagram

Figure 4. Detailed Two-Conversion Timing Diagram

V

(V

CLKOUTP

V

(V

(V

IN_P

V

IN_N

FRAMEP

FRAMEN

CLKOUTN

OUT_P

V

OUT_N

CLK

N

­)

-

)*

­)

­)

t

SAMPLE

N + 1

N + 2

N + 3

N + 4

6.5 CLOCK-CYCLE DATA LATENCY

N + 5

N + 6

N + 7

N + 8

N + 9

OUTPUT

DATA FOR

SAMPLE

N - 6

*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.

N

(V

- V

)

IN_P

IN_N

t

SAMPLE

CLK

-

(V

FRAMEP

)*

V

FRAMEN

(V

-

CLKOUTP

)

V

CLKOUTN

-

(V

OUT_P

D5

N-7D6N-7D7N-7D8N-7D9N-7

)

V

OUT_N

*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.

D10

N-7

t

CF

D11

N-7D0N-6D1N-6D2N-6D3N-6D4N-6D5N-6D6N-6D7N-6D8N-6D9N-6

OUTPUT

DATA FOR

SAMPLE N

N + 2

N + 1

t

SF

D10

D11

N-6

N-6D0N-5D1N-5D2N-5D3N-5D4N-5D5N-5D6N-5

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

20 ______________________________________________________________________________________

Clock Output (CLKOUTP, CLKOUTN)

The MAX1127 provides a differential clock output that
consists of CLKOUTP and CLKOUTN. As shown in
Figure 4, the serial output data is clocked out of the
MAX1127 on both edges of the clock output. The fre­quency of the output clock is 6 times the frequency
of CLK.

Frame Alignment Output (FRAMEP, FRAMEN)

The MAX1127 provides a differential frame alignment
signal that consists of FRAMEP and FRAMEN. As shown
in Figure 4, the rising edge of the frame alignment sig­nal corresponds to the first bit (D0) of the 12-bit serial
data stream. The frequency of the frame alignment sig­nal is identical to the frequency of the sample clock.

Serial Output Data (OUT_P, OUT_N)

The MAX1127 provides its conversion results through
individual differential outputs consisting of OUT_P and
OUT_N. The results are valid 6.5 input clock cycles
after the sample is taken. As shown in Figure 3, the out­put data is clocked out on both edges of the output
clock, LSB (D0) first. Figure 5 provides the detailed ser­ial output timing diagram.

Output Data Format (

T

/B), Transfer Functions

The MAX1127 output data format is either offset binary or
two’s complement, depending on the logic input T/B.
With T/B low, the output data format is two’s comple­ment. With T/B high, the output data format is offset bina­ry. The following equations, Table 2, Figure 6, and Figure
7 define the relationship between the digital output and
the analog input. For two’s complement (T/B = 0):

and for offset binary (T/B = 1):

where CODE

10

is the decimal equivalent of the digital
output code as shown in Table 2. FSR is the full-scale
range as shown in Figures 6 and 7.

Keep the capacitive load on the MAX1127 digital out­puts as low as possible.

LVDS and SLVS Signals (SLVS/

LVDS

)

Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS
high for scalable low-voltage signaling (SLVS) levels at
the MAX1127 outputs (OUT_P, OUT_N, CLKOUT_P,
CLKOUT_N, FRAMEP_, and FRAMEN_). For SLVS lev­els, enable double termination by driving OT high. See
the Electrical Characteristics table for LVDS and SLVS
output voltage levels.

Figure 5. Serialized Output Detailed Timing Diagram

TWO’S COMPLEMENT DIGITAL OUTPUT CODE

(T/B = 0)

OFFSET BINARY DIGITAL OUTPUT CODE

(T/B = 1)

BINARY

D11  D0

HEXADECIMAL

OF

D11  D0

DECIMAL

OF

D11  D0

BINARY

D11  D0

HEXADECIMAL

OF

D11  D0

DECIMAL

OF

D11  D0

V

IN_P

- V

IN_P

(mV)

(V

REFIO

= 1.24V)

0111 1111 1111

0x7FF +2047

0xFFF +4095 +699.66

0111 1111 1110

0x7FE +2046

0xFFE +4094 +699.32

0000 0000 0001

0x001 +1

0x801 +2049 +0.34

0000 0000 0000

0x000 0

0x800 +2048 0

1111 1111 1111

0xFFF -1

0x7FF +2047 -0.34

1000 0000 0001

0X801 -2047

0x001 +1 -699.66

1000 0000 0000

0x800 -2048

0x000 0 -700.00

Table 2. Output Code Table (V

REFIO

= 1.24V)

(V

-

CLKOUTP

)

V

CLKOUTN

-

(V

OUT_P

)

V

OUT_N

V V FSR

IN P IN N__

t

CH

D0 D1 D2 D3

V V FSR

−=××2

IN P IN N__

−=××

t

CL

t

OD

t

OD

CODE

10

4096

CODE

10

−22048

4096

EQUIVALENT

EQUIVALENT

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

0111 1111 1111

0000 0000 0001

0000 0000 0000

EQUIVALENT

EQUIVALENT

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 21

LVDS Test Pattern (LVDSTEST)

Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101 MSB→LSB. As with the ana­log conversion results, the test pattern data is output
LSB first. Drive LVDSTEST low for normal operation
(test pattern disabled).

Common-Mode Output Voltage (CMOUT)

CMOUT provides a common-mode reference for DC­coupled analog inputs. If the input is DC-coupled,
match the output common-mode voltage of the circuit
driving the MAX1127 to the output voltage at V

CMOUT

to within ±50mV. It is recommended that the output
common-mode voltage of the driving circuit be derived
from CMOUT.

Double Termination (DT)

As shown in Figure 8, the MAX1127 offers an optional,
internal 100Ω termination between the differential output
pairs (OUT_P and OUT_N, CLKOUTP and CLKOUTN,
FRAMEP and FRAMEN). In addition to the termination
at the end of the line, a second termination directly at
the outputs helps eliminate unwanted reflections down
the line. This feature is useful in applications where
trace lengths are long (> 5in) or with mismatched
impedance. Drive DT high to select double termination,
or drive DT low to disconnect the internal termination
resistor (single termination). Selecting double termina­tion increases the OVDDsupply current (see the
Electrical Characteristics table).

Power-Down Modes

The MAX1127 offers two types of power-down inputs,
PD0–PD3 and PDALL. The power-down modes allow
the MAX1127 to use power efficiently by transitioning to
a low-power state when conversions are not required.

Figure 6. Bipolar Transfer Function with Two’s Complement
Output Code (

T

/B = 0)

Figure 7. Bipolar Transfer Function with Offset Binary Output
Code (

T

/B = 1)

Figure 8. Double Termination

2 x FSR

1 LSB =

4096

0x7FF
0x7FE

0x7FD

0x001
0x000
0xFFF

0x803
0x802
0x801

TWO'S COMPLEMENT OUTPUT CODE (LSB)

0x800

-2045 +2047+2045-1 0 +1-2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

FSR = 700mV x

FSR FSR

V

REFIO

1.24V

Z

0

= 50Ω

V

REFIO

1.24V

2 x FSR

1 LSB =

4096

0xFFF
0xFFE

0xFFD

0x801
0x800
0x7FF

0x003
0x002

OFFSET BINARY OUTPUT CODE (LSB)

0x800
0x000

-2045 +2047+2045-1 0 +1-2047

DIFFERENTIAL INPUT VOLTAGE (LSB)

DT

OUT_P/
CLKOUTP/
FRAMEP

FSR = 700mV x

FSR FSR

100Ω 100Ω

= 50Ω

Z

OUT_N/

MAX1127

SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.

CLKOUTN/
FRAMEN

0

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

22 ______________________________________________________________________________________

Independent Channel Power-Down (PD0–PD3)

PD0–PD3 control the power-down mode of each chan­nel independently. Drive a power-down input high to
power down its corresponding input channel. For exam­ple, to power down channel 1, drive PD1 high. Drive a
power-down input low to place the corresponding input
channel in normal operation. The differential output
impedance of a powered-down output channel is
approximately 378Ω, when DT is low. The output imped­ance of OUT_P, with respect to OUT_N, is 100Ω when
DT is high. See the Electrical Characteristics table for
typical supply currents with powered-down channels.

The state of the internal reference is independent of the
PD0–PD3 inputs. To power down the internal reference
circuitry, drive PDALL high (see the Global Power-
Down (PDALL) section).

Global Power-Down (PDALL)

PDALL controls the power-down mode of all channels
and the internal reference circuitry. Drive PDALL high to
enable global power-down. In global power-down mode,
the output impedance of all the LVDS/SLVS outputs is
approximately 378Ω, if DT is low. The output impedance
of the differential LVDS/SLVS outputs is 100Ω when DT is
high. See the Electrical Characteristics table for typical
supply currents with global power-down. The following list
shows the state of the analog inputs and digital outputs in
global power-down mode:

• IN_P, IN_N analog inputs are disconnected from the
internal input amplifier.

• REFIO has > 1MΩ resistance to GND.

• OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 378Ω between the
output pairs when DT is low. When DT is high, the dif­ferential output pairs have 100Ω between each pair.

When operating from the internal reference, the wake­up time from global power-down is typically 132µs.
When using an external reference, the wake-up time is
dependent on the external reference drivers.

Applications Information

Full-Scale Range Adjustments Using the

Internal Reference

The MAX1127 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, add a
25kΩ to 250kΩ external resistor or potentiometer
(R

ADJ

) between REFADJ and GND. To increase the full-

scale range, add a 25kΩ to 250kΩ resistor between
REFADJ and REFIO. Figure 9 shows the two possible
configurations.

The following equations provide the relationship between
R

ADJ

and the change in the analog full-scale range:

for R

ADJ

connected between REFADJ and REFIO, and

for R

ADJ

connected between REFADJ and GND.

Figure 9. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range

ADC FULL-SCALE = REFT - REFB

1V

FSR V

=+

07 1

FSR V

=

REFT
REFB

REFERENCE

CONTROL LINE TO

DISABLE REFERENCE

G

BUFFER

BUFFER

⎛

125.. Ω

⎜
⎝

⎛

125.. Ω

−07 1

⎜

R

⎝

REFERENCE-

SCALING

AMPLIFIER

R

ADJ

ADJ

REFIO

REFADJ

⎞

k

⎟
⎠

⎞

k

⎟
⎠

0.1µF

25kΩ
TO 250k

Ω

25kΩ
TO 250k

Ω

MAX1127

AV

CCAVCC

/ 2

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 23

Using Transformer Coupling

An RF transformer (Figure 10) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX1127
for optimum performance. The MAX1127 input com­mon-mode voltage is internally biased to 0.76V (typ)
with f

CLK

= 65MHz. Although a 1:1 transformer is
shown, a step-up transformer can be selected to
reduce the drive requirements. A reduced signal swing
from the input driver, such as an op amp, can also
improve the overall distortion.

Grounding, Bypassing, and Board Layout

The MAX1127 requires high-speed board layout design
techniques. Refer to the MAX1127 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side as the ADC, using surface-mount devices
for minimum inductance. Bypass AVDDto GND with a

0.1µF ceramic capacitor in parallel with a ≥ 2.2µF
ceramic capacitor. Bypass OVDDto GND with a 0.1µF
ceramic capacitor in parallel with a ≥ 2.2µF ceramic
capacitor. Bypass CVDDto GND with a 0.1µF ceramic
capacitor in parallel with a ≥ 2.2µF ceramic capacitor.

Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. Connect
MAX1127 ground pins and the exposed backside pad­dle to the same ground plane. The MAX1127 relies on
the exposed backside paddle connection for a low-

inductance ground connection. Isolate the ground
plane from any noisy digital system ground planes.

Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.

Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal­ly. Refer to the MAX1127 EV kit data sheet for an exam­ple of symmetric input layout.

Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX1127, this straight line is between the end points of
the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics table.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX1127, DNL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics table.

Offset Error

Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. For the MAX1127, the ideal
midscale digital output transition occurs when there is

-1/2 LSB across the analog inputs (Figures 6 and 7).
Bipolar offset error is the amount of deviation between
the measured midscale transition point and the ideal
midscale transition point.

Gain Error

Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1127, the gain
error is the difference of the measured full-scale and
zero-scale transition points minus the difference of the
ideal full-scale and zero-scale transition points.

Figure 10. Transformer-Coupled Input Drive

10

0.1µF
1

V

IN

2

N.C.

3
MINICIRCUITS

T1

ADT1-1WT

6

5

4

Ω

39pF

0.1µF

10

Ω

39pF

IN_P

MAX1127

IN_N

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

24 ______________________________________________________________________________________

For the bipolar devices (MAX1127), the full-scale transi­tion point is from 0x7FE to 0x7FF for two’s complement
output format (0xFFE to 0xFFF for offset binary) and the
zero-scale transition point is from 0x800 to 0x801 for
two’s complement (0x000 to 0x001 for offset binary).

Crosstalk

Crosstalk indicates how well each analog input is isolat­ed from the others. For the MAX1127, a 5.3MHz,

-0.5dBFS analog signal is applied to one channel while
a 30.3MHz, -0.5dBFS analog signal is applied to all
other channels. An FFT is taken on the channel with the

5.3MHz analog signal. From this FFT, the crosstalk is
measured as the difference in the 5.3MHz and

30.3MHz amplitudes.

Aperture Delay

Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken. See Figure 11.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in
the aperture delay. See Figure 11.

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):

SNR

dB[max]

= 6.02dBx N x 1.76

dB

In reality, there are other noise sources besides quantiza­tion noise: thermal noise, reference noise, clock jitter, etc.

For the MAX1127, SNR is computed by taking the ratio
of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre­quency excluding the fundamental, the first six harmon­ics (HD2–HD7), and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig­nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency, excluding the fundamental and the
DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC
at a specific input frequency and sampling rate. An
ideal ADC’s error consists of quantization noise only.
ENOB for a full-scale sinusoidal input waveform is
computed from:

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of the first six harmon­ics of the input signal to the fundamental itself. This is
expressed as:

Figure 11. Aperture Jitter/Delay Specifications

THD

CLK

ANALOG

INPUT

SAMPLED

DATA

T/H

HOLD TRACK HOLD

ENOB

⎡
⎢

log

=×

20

⎢
⎢

⎣

t

AD

t

AJ

⎛

SINAD=−

⎜

602..

⎝

VVVVVV

+++++

22324

⎞

176

⎟
⎠

2526272

V

1

⎤
⎥
⎥
⎥

⎦

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next-largest spurious
component, excluding DC offset. SFDR is specified in
decibels relative to the carrier (dBc).

Intermodulation Distortion (IMD)

IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi­vidual input tone levels are at -6.5dBFS. The intermodu­lation products are as follows:

• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1

• 3rd-order intermodulation products (IM3): 2 x f1 - f2,
2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1

• 4th-order intermodulation products (IM4): 3 x f1 - f2,
3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1

• 5th-order intermodulation products (IM5): 3 x f1 - 2 x
f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1

Third-Order Intermodulation (IM3)

IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f1 and f2. The indi­vidual input tone levels are at -6.5dBFS. The 3rd-order
intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x
f1 + f2, 2 x f2 + f1.

Small-Signal Bandwidth

A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver­sion result has decreased by -3dB.

Full-Power Bandwidth

A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full­power input bandwidth frequency.

Gain Matching

Gain matching is a figure of merit that indicates how
well the gain of all four ADC channels is matched to
each other. For the MAX1127, gain matching is mea­sured by applying the same 30.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 65MHz and the maximum deviation in
amplitude is reported in dB as gain matching in the
Electrical Characteristics table.

Phase Matching

Phase matching is a figure of merit that indicates how
well the phase of all four ADC channels is matched to
each other. For the MAX1127, phase matching is mea­sured by applying the same 30.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 65MHz and the maximum deviation in
phase is reported in degrees as phase matching in the
Electrical Characteristics table.

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with

Serial LVDS Outputs

______________________________________________________________________________________ 25

MAX1127

Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

Note: For the MAX1127 Exposed Pad Variation,
the package code is G6800-4.

68L QFN.EPS

PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

21-0122

PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM

21-0122

C

C

1

2

1

2