The MAX1121 is a monolithic 8-bit, 250Msps analog-todigital converter (ADC) optimized for outstanding
dynamic performance at high IF frequencies up to
500MHz. The product operates with conversion rates of
up to 250Msps while consuming only 477mW.
At 250Msps and an input frequency of 100MHz, the
MAX1121 achieves a spurious-free dynamic range
(SFDR) of 68dBc. Its excellent signal-to-noise ratio
(SNR) of 48.9dB at 10MHz remains flat (within 0.5dB)
for input tones up to 500MHz. This makes the MAX1121
ideal for wideband applications such as digital predistortion in cellular base-station transceiver systems.
The MAX1121 requires a single 1.8V supply. The analog input is designed for either differential or singleended operation and can be AC- or DC-coupled. The
ADC also features a selectable on-chip divide-by-2
clock circuit, which allows the user to apply clock frequencies as high as 500MHz. This helps to reduce the
phase noise of the input clock source. A differential
LVDS sampling clock is recommended for best performance. The converter’s digital outputs are LVDS compatible, and the data format can be selected to be
either two’s complement or offset binary.
The MAX1121 is available in a 68-pin QFN with
exposed pad (EP) and is specified over the industrial
(-40°C to +85°C) temperature range.
For pin-compatible, higher resolution versions of the
MAX1121, refer to the MAX1122 (170Msps), the
MAX1123 (210Msps), and the MAX1124 (250Msps)
data sheets.
Applications
Wireless and Wired Broadband Communication
Digital Oscilloscopes
Digital Predistortion Receivers
Communications Test Equipment
Radar and Satellite Subsystems Antenna Array
Processing
Instrumentation
Features
♦ 250Msps Conversion Rate
♦ SNR = 48.8dB/48.7dB at f
IN
= 100MHz/500MHz
♦ SFDR = 68dBc/63.8dBc at f
IN
= 100MHz/500MHz
♦ Single 1.8V Supply
♦ 477mW Power Dissipation at 250Msps
♦ On-Chip Track-and-Hold and Internal Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ Evaluation Kit Available (Order MAX1124EVKIT)
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
E
Pin Configuration
Ordering Information
19-3077; Rev 2; 8/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCCto AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
AV
CC
to OVCC.......................................................-0.3V to +2.1V
AGND to OGND ....................................................-0.3V to +0.3V
Analog Inputs to AGND ...........................-0.3V to (AV
CC
+ 0.3V)
Digital Inputs to AGND.............................-0.3V to (AV
CC
+ 0.3V)
REF, REFADJ to AGND............................-0.3V to (AV
CC
+ 0.3V)
Digital Outputs to OGND.........................-0.3V to (OV
CC
+ 0.3V)
ESD on All Pins (Human Body Model).............................±2000V
internal reference, digital output pins differential R
L
= 100Ω ±1%, CL= 5pF, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥ +25°C
guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Note 1: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range is defined as 1023 x slope of the line.
Note 2: Parameter guaranteed by design and characterization; T
A
= T
MIN
to T
MAX
.
Note 3: PSRR is measured with both analog and digital supplies connected to the same potential.
Output Offset Voltage OVOS 1.125 1.310 V
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low VIL
Digital Input Voltage High V
TIMING CHARACTERISTICS
CLK to Data Propagation Delay t
CLK to DCLK Propagation Dela y t
Data Valid to DCLK Rising Edge
LVDS Output Rise-Time t
LVDS Output Fall-Time t
Output Data Pipeline Delay t
POWER REQUIREMENTS
Analog Supply Voltage Range AVCC 1.70 1.80 1.90 V
Digital Supply Voltage Range OVCC 1.70 1.80 1.90 V
Analog Supply Current
Digital Supply Current I
Total Power Dissipation P
Power-Supply Rejection Ratio
(Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
IH
Figure 4 1.5 ns
PDL
Figure 4 2.85 ns
CPDL
t
-
CPDL
t
PDL
20% to 80%, CL = 5pF 460 ps
RISE
20% to 80%, CL = 5pF 460 ps
FALL
LATENCY
fIN = 100MHz 220 290 mA
I
AVCC
fIN = 100MHz 45 75 mA
OVCC
fIN = 100MHz 477 657 mW
DISS
PSRR
Figure 4 (Note 2) 0.92 1.35 1.86 ns
8
Offset 1.6mV/V
Gain 1.9%FS/V
0.8 x
AV
CC
0.2 x
AV
V
CC
V
Clock
cycles
MAX1121
1.8V, 8-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Typical Operating Characteristics
(AVCC= OVCC= 1.8V, V
AGND
= V
OGND
= 0, f
SAMPLE
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
= 250.0057MHz, -0.5dBFS; see TOCs for detailed information on test conditions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R
L
= 100Ω, TA= +25°C.)
-90
-65
-75
-85
-70
-80
-50
-55
-60
-40
-45
-35
-30
-30-20-15-25-10-50
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
SAMPLE
= 250.0057MHz, fIN = 60.0294MHz)
MAX1121 toc10
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBc)
HD3
HD2
SNR vs. f
SAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1121 toc11
f
SAMPLE
(MHz)
SNR (dB)
60
47.0
47.5
48.0
48.5
49.0
46.5
20260180140100220
SFDR vs. f
SAMPLE
(fIN = 60.0294MHz, AIN = -0.5dBFS)
MAX1121 toc12
f
SAMPLE
(MHz)
SFDR (dBc)
22014010060
50
60
70
80
90
40
20260180
HD2/HD3 vs. f
SAMPLE
(fIN = 60.03294MHz, AIN = -0.5dBFS)
MAX1121 toc13
f
SAMPLE
(MHz)
HD2/HD3 (dBc)
22018014010060
-92
-84
-76
-68
-60
-100
20260
HD3
HD2
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
TWO-TONE IMD PLOT (8192-POINT
DATA RECORD, COHERENT SAMPLING)
MAX1121 toc14
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
040608020100140120
f
SAMPLE
= 250.0057MHz
f
IN1
= 99.0318MHz
f
IN2
= 101.046MHz
A
IN1
= A
IN2
= -7dBFS
IMD = -70dBc
2f
IN1
- f
IN2
2f
IN2
-
f
IN1
f
IN1
f
IN2
-0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
64 96320128 160 192 224 256
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1121 toc15
DIGITAL OUTPUT CODE
INL (LSB)
-0.5
-0.4
-0.2
0.1
0.3
0.5
0.4
0
-0.3
-0.1
0.2
64 96320128 160 192 224 256
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1121 toc16
DIGITAL OUTPUT CODE
DNL (LSB)
2
0
-2
-4
-6
-8
-10
-12
101001000
GAIN BANDWIDTH PLOT
(f
SAMPLE
= 250.0057MHz, AIN = -0.5dBFS)
MAX1121 toc17
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)
SNR vs. TEMPERATURE (fIN = 65.0108MHz,
f
SAMPLE
= 249.856MHz, AIN = -0.5dBFS)
MAX1121 toc18
TEMPERATURE (°C)
SNR (dB)
603510-15
47.0
46.5
48.0
47.5
49.0
48.5
49.5
50.0
46.0
-4085
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