Maxim MAX108CHC Datasheet

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General Description

The MAX108 PECL-compatible, 1.5Gsps, 8-bit analog­to-digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX108 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.

The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (typically 7.5 effective bits)
at the Nyquist frequency. A fully differential comparator
design and decoding circuitry reduce out-of-sequence
code errors (thermometer bubbles or sparkle codes)
and provide excellent metastable performance. Unlike
other ADCs that can have errors resulting in false full­or zero-scale outputs, the MAX108 limits the error mag­nitude to 1LSB.

The analog input is designed for either differential or
single-ended use with a ±250mV input voltage range.
Dual, differential, positive-referenced emitter-coupled
logic (PECL)-compatible output data paths ensure easy
interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V
or +5V referenced systems. Control inputs are provided
for interleaving additional MAX108 devices to increase
the effective system sampling rate.

The MAX108 is packaged in a 25mm x 25mm, 192-con­tact Enhanced Super Ball-Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) tempera­ture range. For pin-compatible, lower speed versions of
the MAX108, see the MAX104 (1Gsps) and the MAX106
(600Msps) data sheets.

Applications

Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems

Features

♦ 1.5Gsps Conversion Rate
♦ 2.2GHz Full-Power Analog Input Bandwidth
♦ 7.5 Effective Bits at f

IN

= 750MHz (Nyquist

Frequency)

♦ ±0.25LSB INL and DNL
♦ 50Ω Differential Analog Inputs
♦ ±250mV Input Signal Range
♦ On-Chip, +2.5V Precision Bandgap Voltage

Reference

♦ Latched, Differential PECL Digital Outputs
♦ Selectable 8:16 Demultiplexer
♦ Internal Demux Reset Input with Reset Output
♦ 192-Contact ESBGA Package
♦ Pin Compatible with MAX104 (1Gsps) and

MAX106 (600Msps)

MAX108

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

________________________________________________________________

Maxim Integrated Products

1

19-1492; Rev 0; 9/99

PART

MAX108CHC 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

192 ESBGA

EVALUATION KIT

AVAILABLE

Ordering Information

ESBGA

TOP VIEW

MAX108

Typical Operating Circuit appears at end of data sheet.

192-Contact ESBGA

Ball Assignment Matrix

ESBGA is a trademark of Amkor/Anam.

PCB land pattern appears at end of data sheet.

MAX108

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCA to GNDA .........................................................-0.3V to +6V

V

CC

D to GNDD.........................................................-0.3V to +6V

V

CC

I to GNDI............................................................-0.3V to +6V

V

CC

O to GNDD........................................-0.3V to (VCCD + 0.3V)

AUXEN1, AUXEN2 to GND .....................-0.3V to (V

CC

D + 0.3V)

V

EE

to GNDI..............................................................-6V to +0.3V

Between GNDs......................................................-0.3V to +0.3V

V

CC

A to VCCD .......................................................-0.3V to +0.3V

V

CC

A to VCCI.........................................................-0.3V to +0.3V

PECL Digital Output Current...............................................50mA

REFIN to GNDR ........................................-0.3V to (V

CC

I + 0.3V)

REFOUT Current ................................................+100µA to -5mA

ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V

TTL/CMOS Control Inputs

(DEMUXEN, DIVSELECT) ......................-0.3V to (V

CC

D + 0.3V)

RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V)

VOSADJ Adjust Input ................................-0.3V to (V

CC

I + 0.3V)

CLK+ to CLK- Voltage Difference..........................................±3V

CLK+, CLK-.....................................(V

EE

- 0.3V) to (GNDD + 1V)

CLKCOM.........................................(V

EE

- 0.3V) to (GNDD + 1V)

VIN+ to VIN- Voltage Difference............................................±2V

VIN+, VIN- to GNDI................................................................±2V

Continuous Power Dissipation (T

A

= +70°C)

192-Contact ESBGA (derate 61mW/°C above +70°C) ....4.88W

(with heatsink and 200 LFM airflow,

derate 106mW/°C above +70°C) .....................................8.48W

Operating Temperature Range

MAX108CHC.........................................................0°C to +70°C

Operating Junction Temperature.....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS

Missing Codes None Codes

Differential Nonlinearity (Note 1) DNL -0.5 ±0.25 0.5 LSB

Full-Scale Input Range V

FSR

475 500 525 mVp-p

Common-Mode Input Range V

CM

±0.8 V

Input Resistance R

IN

49 50 51 Ω

Input Resistance Temperature
Coefficient

TC

R

150 ppm/°C

Resolution RES 8 Bits
Integral Nonlinearity (Note 1) INL -0.5 ±0.25 0.5 LSB

Input Resistance (Note 2) R

VOS

14 25 kΩ

Input VOSAdjust Range ±4 ±5.5 LSB

Reference Output Voltage REFOUT 2.475 2.50 2.525 V
Reference Output Load

Regulation

∆REFOUT 5 mV

Reference Input Resistance R

REF

45 kΩ

CONDITIONS

No missing codes guaranteed

TA= +25°C

Note 1
Signal + offset w.r.t. GNDI

VOSADJ = 0 to 2.5V

VIN+ and VIN- to GNDI, TA= +25°C

Driving REFIN input only

0 < I

SOURCE

< 2.5mA

Referenced to GNDR

TA= +25°C

ACCURACY

ANALOG INPUTS

VOS ADJUST CONTROL INPUT

REFERENCE INPUT AND OUTPUT

MAX108

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

PECL DIGITAL OUTPUTS (Note 5)

Negative Power-Supply
Rejection Ratio (Note 8)

PSRR- 40 68 dB(Note 10)

Common-Mode Rejection Ratio
(Note 7)

CMRR 40 68 dB

Positive Power-Supply Rejection
Ratio (Note 8)

PSRR+ 40 73 dB

VIN+ = VIN- = ±0.1V

(Note 9)

Positive Analog Supply Current ICCA 480 780 mA
Positive Input Supply Current ICCI 108 150 mA
Negative Input Supply Current I

EE

-290 -210 mA
Digital Supply Current ICCD 205 340 mA
Output Supply Current (Note 6) ICCO 75 115 mA
Power Dissipation (Note 6) P

DISS

5.25 W

Digital Output High Voltage V

OH

-1.025 -0.880 V

Digital Output Low Voltage V

OL

-1.810 -1.620 V

PARAMETER SYMBOL MIN TYP MAX UNITS

High-Level Input Voltage V

IH

2.0 V

Low-Level Input Voltage V

IL

0.8 V

High-Level Input Current I

IH

50 µA

Clock Input Resistance R

CLK

48 50 52 Ω

Input Resistance Temperature
Coefficient

TC

R

150 ppm/°C

Low-Level Input Current I

IL

-1 1 µA

Digital Input High Voltage V

IH

-1.165 V

Digital Input Low Voltage V

IL

-1.475 V

CONDITIONS

VIL= 0

VIH= 2.4V

CLK+ and CLK- to CLKCOM, TA= +25°C

CLOCK INPUTS (Note 3)

TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)

DEMUX RESET INPUT (Note 4)

POWER REQUIREMENTS

PECL DIGITAL OUTPUTS (Note 5)

MAX108

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

Transfer Curve Offset V

OS

-2.0 0 +2.0 LSBVOSADJ control input open

Single-ended

Differential 45.7 48.2

Signal-to-Noise Ratio and
Distortion (Note 11)

SINAD

250

48.2

dB

fIN= 250MHz

Single-ended

Differential 44.5 47.0

Single-ended

Differential

SINAD

750

47.1

44.3

SINAD

1500

44.4

fIN= 1500MHz

fIN= 750MHz

Single-ended

Differential 55.0 61.6

Spurious-Free Dynamic Range

SFDR

250

61.7

dB

fIN= 250MHz

Single-ended

Differential 50.0 54.0

Single-ended

Differential

SFDR

750

54.1

44.6

SFDR

1500

45.5

fIN= 1500MHz

fIN= 750MHz

Single-ended

Differential -55.5 -60.2

Total Harmonic Distortion
(Note 12)

THD

250

-61.3

dB

fIN= 250MHz

Single-ended

Differential -49.0 -52.1

Single-ended

Differential

THD

750

-52.8

-44.5

THD

1500

-44.2

fIN= 1500MHz

fIN= 750MHz

Single-ended

Differential 44.2 47.4

Signal-to-Noise Ratio
(No Harmonics)

SNR

250

47.4

dB

fIN= 250MHz

Single-ended

Differential 43.3 46.8

SNR

750

46.9

fIN= 750MHz

Single-ended

Differential 7.3 7.71

Effective Number of Bits
(Note 11)

ENOB

250

7.71

Bits

Single-ended

Differential

fIN= 250MHz

44.8

SNR

1500

44.9

fIN= 1500MHz

Single-ended

Differential 7.1 7.51

ENOB

750

7.53

fIN= 750MHz

Single-ended

Differential

PARAMETER SYMBOL MIN TYP MAX UNITS

7.07

Analog Input VSWR VSWR 1.1:1 V/V

Analog Input Full-Power
Bandwidth

BW

-3dB

2.2 GHz

ENOB

1500

7.07

Two-Tone Intermodulation IMD -66.8 dB

CONDITIONS

fIN= 1500MHz

fIN= 500MHz

f

IN1

= 247MHz, f

IN2

= 253MHz,

at -7dB below full-scale

ANALOG INPUT

DYNAMIC SPECIFICATIONS

MAX108

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________ 5

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

DIV4 mode

DIV1, DIV2 modes

7.5DIV4 mode

DIV1, DIV2 modes

Figures 6, 7, 8t

PDP

Auxiliary Port Pipeline
Delay

t

PDA

9.5

Clock

Cycles

Figures 6, 7, 8

8.5

DREADY to DATA Propagation
Delay (Note 14)

t

PD2

-50 150 350 psFigure 17

CLK to DREADY Propagation
Delay

t

PD1

2.2 nsFigure 17

Reset Input Data Hold Time
(Note 13)

t

HD

0 psFigure 15

Clock Pulse Width High t

PWH

0.3 5 nsFigure 17

PARAMETER SYMBOL MIN TYP MAX UNITS

Aperture Jitter t

AJ

<0.5 ps

Aperture Delay t

AD

100 ps

Reset Input Data Setup Time
(Note 13)

t

SU

0 ps

DATA Rise Time t

RDATA

420 ps

Maximum Sample Rate f

MAX

1.5 Gsps

Clock Pulse Width Low t

PWL

0.3 ns

DATA Fall Time t

FDATA

360 ps

DREADY Rise Time t

RDREADY

220 ps

DREADY Fall Time t

FDREADY

180 ps

Primary Port Pipeline
Delay

7.5

Clock

Cycles

CONDITIONS

Figure 4

Figure 4

Figure 15

20% to 80%, CL= 3pF
20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

Figure 17

TIMING CHARACTERISTICS

Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale

range (FSR) is defined as 256 times the slope of the line.

Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit

voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.

Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings

on the CLK+ and CLK- inputs.

Note 4: Input logic levels are measured with respect to the V

CC

O power-supply voltage.

Note 5: All PECL digital outputs are loaded with 50Ωto V

CC

O - 2.0V. Measurements are made with respect to the VCCO power-

supply voltage.

Note 6: The current in the V

CC

O power supply does not include the current in the digital output’s emitter followers, which is a func-

tion of the load resistance and the V

TT

termination voltage.

Note 7: Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the

change in the common-mode voltage, expressed in dB.

Note 8: Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change

in power-supply voltage, expressed in dB.

Note 9: Measured with the positive supplies tied to the same potential; V

CC

A = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.

Note 10: V

EE

varies from -5.25V to -4.75V.

MAX108

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

6 _______________________________________________________________________________________

Note 11: Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to

the theoretical full-scale range.

Note 12: Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse width one clock period long or greater.
Note 14: Guaranteed by design. The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the

DREADY signal (when the output data changes) to the 50% point on a data output bit. This places the falling edge of the
DREADY signal in the middle of the data output valid window, within the differences between the DREADY and DATA rise
and fall times, which gives maximum setup and hold time for latching external data latches.

Typical Operating Characteristics

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)

6.25
100 20001000

EFFECTIVE NUMBER OF BITS

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

6.75

6.50

7.00

7.25

7.50

7.75

8.00

MAX108 toc01

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

10

-1dBFS

-12dBFS

-6dBFS

6.25
100 20001000

EFFECTIVE NUMBER OF BITS

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

6.75

6.50

7.00

7.25

7.50

7.75

8.00

MAX108 toc02

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

10

-1dBFS

-12dBFS

-6dBFS

40

100 20001000

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

42

41

43

44

45

46

47

48

49

50

MAX108 toc03

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

10

-6dBFS

-1dBFS

-12dBFS

40

100 20001000

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

42

41

43

44

45

46

47

48

49

50

MAX108 toc04

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

10

-1dBFS

-12dBFS

-6dBFS

30

100 20001000

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

42

38

34

46

50

MAX108 toc05

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

10

-1dBFS

-12dBFS

-6dBFS

30

100 20001000

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

42

38

34

46

50

MAX108 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

10

-1dBFS

-12dBFS

-6dBFS

MAX108

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________

7

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

70

65

60

55

SFDR (dB)

50

45

40

35

10

-6dBFS

-1dBFS

-12dBFS

ANALOG INPUT FREQUENCY (MHz)

100 20001000

EFFECTIVE NUMBER OF BITS vs.

CLOCK POWER

(f

= 250MHz, -1dBFS)

8.00

7.75

7.50

7.25

ENOB (Bits)

7.00

IN

DIFFERENTIAL CLOCK DRIVE

SINGLE-ENDED CLOCK DRIVE

MAX108 toc07

MAX108toc10

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

70

65

60

55

SFDR (dB)

50

45

40

35

10

-6dBFS

-1dBFS

-12dBFS

ANALOG INPUT FREQUENCY (MHz)

100 20001000

EFFECTIVE NUMBER OF BITS

vs. V

I = VCCA = VCCD

CC

(f

= 250MHz, -1dBFS)

8.00

7.75

7.50

7.25

ENOB (Bits)

7.00

IN

MAX108 toc08

MAX108-11

EFFECTIVE NUMBER OF BITS

vs. CLOCK FREQUENCY

(f

= 250MHz, 1dBFS)

8.00

7.75

7.50

7.25

ENOB (Bits)

7.00

6.75

6.50
100 1000 1500

IN

CLOCK FREQUENCY (MHz )

EFFECTIVE NUMBER OF BITS vs. V

(fIN = 250MHz, -1dBFS)

8.00

7.75

7.50

7.25

ENOB (Bits)

7.00

EE

MAX108 toc09

MAX108-12

6.75

6.50

-12 -10

-6

-2 2 6-8 -4 0 4 108

CLOCK POWER (dBm) PER SIDE

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK POWER

(f

= 250MHz, -1dBFS)

67

65

63

61

59

57

SFDR (dB)

55

53

51

49

47

-12 -10 -8 -6 -4 -2 0 2 4 8610

IN

SINGLE-ENDED CLOCK DRIVE

DIFFERENTIAL CLOCK DRIVE

CLOCK POWER (dBm) PER SIDE

MAX108toc13

6.75

6.50

4.5 4.94.7 5.1 5.3 5.5
VCC (V)

SPURIOUS-FREE DYNAMIC RANGE

vs. V

I = VCCA = VCCD

CC

(f

= 250MHz, -1dBFS)

67

66

65

64

63

62

SFDR (dB)

61

60

59

58

57

4.5 4.7 4.9 5.1 5.3 5.5

IN

VCC (V)

MAX108-14

6.75

6.50

-5.5 -5.1-5.3 -4.9 -4.7 -4.5
VEE (V)

SPURIOUS-FREE DYNAMIC RANGE vs. V

(fIN = 250MHz, -1dBFS)

67

66

65

64

63

62

SFDR (dB)

61

60

59

58

57

-5.5 -5.3 -5.1 -4.9 -4.7 -4.5
VEE (V)

EE

MAX108-15

MAX108

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)

-64

-62

-63

-60

-61

-58

-59

-57

-55

-56

-54

4.5 4.7 4.9 5.1 5.3 5.5

TOTAL HARMONIC DISTORTION

vs. V

CC

I = VCCA = VCCD

(f

IN

= 250MHz, -1dBFS)

MAX108-16

V

CC

(V)

THD (dB)

-64

-62

-63

-60

-61

-58

-59

-57

-55

-56

-54

-5.5 -5.3 -5.1 -4.9 -4.7 -4.5

TOTAL HARMONIC DISTORTION vs. V

EE

(f

IN

= 250MHz, -1dBFS)

MAX108-17

V

EE

(V)

THD (dB)

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 300150 450 600 750

FFT PLOT

(f

IN

= 250.9460449MHz,

RECORD LENGTH 16,384)

MAX108 toc18

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.73
SINAD = 48.3dB
SNR = 47.3dB
THD = -59.9dB
SFDR = 61.5dB

H3

H2

FUNDAMENTAL

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 300150 450 600 750

FFT PLOT

(f

IN

= 747.1618562MHz,

RECORD LENGTH 16,384)

MAX108 toc19

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.61
SINAD = 47.6dB
SNR = 46.7dB
THD = -56.5dB
SFDR = 59.4dB

H3

H2

FUNDAMENTAL

-5

-6

-7

-8

-9

-10
500 1500 2500

ANALOG INPUT BANDWIDTH

-6dB BELOW FULL SCALE

MAX108toc22

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SMALL-SIGNAL BANDWIDTH = 2.4GHz

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 300150 450 600 750

FFT PLOT

(f

IN

= 1503.021240MHz,

-1dBFS, RECORD LENGTH 16,384)

MAX108 toc20

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.12
SINAD = 44.6dB
SNR = 44.7dB
THD = -44.4dB
SFDR = 44.4dB

H3

H2

FUNDAMENTAL

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 300150 450 600 750

FFT PLOT

(f

IN

= 1503.021240MHz,

-3dBFS, RECORD LENGTH 16,384)

MAX108 toc21

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.60
SINAD = 47.5dB
SNR = 42.0dB
THD = -51.3dB
SFDR = 51.3dB

H3

H2

FUNDAMENTAL

0

-1

-2

-3

-4

-5
500 1500 2500

ANALOG INPUT BANDWIDTH

FULL POWER

MAX108toc23

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

FULL-POWER BANDWIDTH = 2.2GHz

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO-LOOP DATA)

MAX108toc24

OUTPUT CODE

INL (LSB)

MAX108

±5V, 1.5Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________

9

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1.5Gsps, TA= +25°C, unless otherwise
noted.)

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO-LOOP DATA)

MAX108toc25

OUTPUT CODE

DNL (LSB)

DREADY
200mV/div

DATA
200mV/div

DREADY RISE/FALL TIME,

DATA-OUTPUT RISE/FALL TIME

MAX108 toc26

500ps/div

1.0

1.1

1.2

1.3

1.4

1.5

0 1000500 1500 2000 2500

VSWR vs. ANALOG INPUT FREQUENCY

MAX108toc27

ANALOG INPUT FREQUENCY (MHz)

VSWR

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 300150 450 600 750

TWO-TONE INTERMODULATION FFT PLOT

(f

IN1

= 247.1008301MHz, f

IN2

= 253.3264160MHz,

7dB BELOW FULL SCALE, RECORD LENGTH 16,384)

MAX108 toc28

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fIN1

fIN2

Pin Description

NAME FUNCTION

A1–A4, A6, A7, B1, B2, C1, C2, D1–D3,

G1, H1, J2, J3, K1–K3, L2, L3, M1, N1,

T2, T3, U1, V1, V2, W1–W4

GNDI

Analog Ground. For T/H amplifier, clock distribution, bandgap
reference, and reference amplifier.

A5, B5, C5, H2, H3, M2, M3, U5, V5, W5 VCCI

Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distri­bution, bandgap reference, and reference amplifier.

CONTACT

A8, B8, C8, U6, V6, W6 GNDA Analog Ground. For comparator array.
A9, B9, C9, U7, V7, W7 VCCA Analog Supply Voltage, +5V. Supplies analog comparator array.

A11, B11, B16, B17, C11, C16, U9, U17,

V9, V17, V18, W9

GNDD Digital Ground

A10, E17, F2, P3, R17, R18 TESTPOINT (T.P.)

Test Point. Do not connect.

MAX108

±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

10 ______________________________________________________________________________________

Pin Description (continued)

H18 P3+ Primary Output Data Bit 3

H17 P3- Complementary Primary Output Data Bit 3

F17 P2- Complementary Primary Output Data Bit 2

G17 A2- Complementary Auxiliary Output Data Bit 2
G18 A2+ Auxiliary Output Data Bit 2

F18 P2+ Primary Output Data Bit 2

E18 DEMUXEN

TTL/CMOS Demux Enable Control
1: Enable Demux
0: Disable Demux

F1 VOSADJ Offset Adjust Input

E2 IPTAT

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

C7 REFOUT Reference Output

C15 A1- Complementary Auxiliary Output Data Bit 1

D18 AUXEN2

Connect to VCCO to power the auxiliary port, or connect to GNDD
to power down.

E1 ICONST

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

D17 DIVSELECT

TTL/CMOS Demux Divide Selection Input
1: Decimation DIV4 mode
0: Demultiplexed DIV2 mode

C13 A0- Complementary Auxiliary Output Data Bit 0 (LSB)
C14 P1- Complementary Primary Output Data Bit 1

C12 P0- Complementary Primary Output Data Bit 0 (LSB)

B13 A0+ Auxiliary Output Data Bit 0 (LSB)

B15 A1+ Auxiliary Output Data Bit 1

C6 REFIN Reference Input

B14 P1+ Primary Output Data Bit 1

B10, B18, C10, C17, C18, T17, T18, U8,

U18, V8, W8

VCCD Digital Supply Voltage, +5V

B12 P0+ Primary Output Data Bit 0 (LSB)

B6, B7 GNDR

Reference Ground. Must be connected to GNDI.

NAME FUNCTION

A12–A19, B19, C19, D19, E19, F19,

G19, H19, J19, K19, L19, M19, N19,

P19, T19, U19, V19, W10–W19

VCCO PECL Supply Voltage, +3V to +5V

CONTACT

B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,

U2–U4, V3, V4

V

EE

Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.