MAXIM MAX1076, MAX1078 Technical data

General Description

The MAX1076/MAX1078 are low-power, high-speed, seri­al-output, 10-bit, analog-to-digital converters (ADCs) that
operate at up to 1.8Msps and have an internal reference.
These devices feature true-differential inputs, offering bet­ter noise immunity, distortion improvements, and a wider
dynamic range over single-ended inputs. A standard
SPI™/QSPI™/MICROWIRE™ interface provides the clock
necessary for conversion. These devices easily interface
with standard digital signal processor (DSP) synchronous
serial interfaces.

The MAX1076/MAX1078 operate from a single +4.75V to
+5.25V supply voltage. The MAX1076/MAX1078 include
a 4.096V internal reference. The MAX1076 has a unipolar
analog input, while the MAX1078 has a bipolar analog
input. These devices feature a partial power-down mode
and a full power-down mode for use between conver­sions, which lower the supply current to 2mA (typ) and
1µA (max), respectively. Also featured is a separate
power-supply input (VL), which allows direct interfacing to
+1.8V to VDDdigital logic. The fast conversion speed,
low-power dissipation, excellent AC performance, and DC
accuracy (±0.5 LSB INL) make the MAX1076/MAX1078
ideal for industrial process control, motor control, and
base-station applications.

The MAX1076/MAX1078 come in a 12-pin TQFN pack­age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.

Applications

Data Acquisition Communications
Bill Validation Portable Instruments
Motor Control

Features

♦ 1.8Msps Sampling Rate
♦ Only 50mW (typ) Power Dissipation
♦ Only 1µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial Interface
♦ 61dB S/(N + D) at 525kHz Input Frequency
♦ Internal True-Differential Track/Hold (T/H)
♦ Internal 4.096V Reference
♦ No Pipeline Delays
♦ Small 12-Pin TQFN Package

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

Typical Operating Circuit

19-3291; Rev 0; 5/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.

查询MAX1076CTC-T供应商

PART TEMP RANGE

MAX1076CTC-T 0°C to +70°C 12 TQFN-12 Unipolar

MAX1076ETC-T -40°C to +85°C 12 TQFN-12 Unipolar
MAX1078CTC-T 0°C to +70°C 12 TQFN-12 Bipolar
MAX1078ETC-T -40°C to +85°C 12 TQFN-12 Bipolar

PIN­PACKAGE

INPUT

TOP VIEW

1

AIN-

2REF

3

AIN+11N.C.10SCLK

12

CNVST

9

DOUT

MAX1076
MAX1078

45

N.C.6GND

V

DD

TQFN

8

V

7RGND

+4.75V TO +5.25V

DIFFERENTIAL

VOLTAGE

L

4.7µF

+1.8V TO V

DD

INPUT

0.01µF

0.01µF

V

DD

+

AIN+

-

AIN-

MAX1076
MAX1078

REF

RGND

V

GND

0.01µF

L

DOUT

CNVST

SCLK

10µF10µF

µC/DSP

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL= VDD, f

SCLK

= 28.8MHz, 50% duty cycle, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

V

L

to GND ................-0.3V to the lower of (VDD+ 0.3V) and +6V

Digital Inputs

to GND .................-0.3V to the lower of (V

DD

+ 0.3V) and +6V

Digital Output

to GND....................-0.3V to the lower of (V

L

+ 0.3V) and +6V

Analog Inputs and

REF to GND..........-0.3V to the lower of (V

DD

+ 0.3V) and +6V

RGND to GND .......................................................-0.3V to +0.3V

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (T

A

= +70°C)

12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW

Operating Temperature Ranges

MAX107_ CTC ...................................................0°C to +70°C

MAX107_ ETC.................................................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution 10 Bits
Relative Accuracy INL (Note 1) ±0.5 LSB
Differential Nonlinearity DNL (Note 2) ±0.5 LSB
Offset Error ±2 LSB

Offset-Error Temperature
Coefficient

Gain Error Offset nulled ±2 LSB
Gain Temperature Coefficient ±2 ppm/°C
DYNAMIC SPECIFICATIONS (f
Signal-to-Noise Plus Distortion

Total Harmonic Distortion
Spurious-Free Dynamic Range SFDR -80 -74 dB

Intermodulation Distortion IMD f
Full-Power Bandwidth -3dB point, small-signal method 20 MHz
Full-Linear Bandwidth S/(N + D) > 56dB, single ended 2 MHz

CONVERSION RATE

Minimum Conversion Time t
Maximum Throughput Rate 1.8 Msps
M i ni m um Thr oug hp ut Rate ( N ote 4) 10 ksps
Track-and-Hold Acquisition Time t
Aperture Delay 5ns
Aperture Jitter (Note 6) 30 ps
External Clock Frequency f

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

= 525kHz sine wave, VIN = V

IN

SINAD 60 61 dB

THD Up to the 5th harmonic -80 -74 dB

= 250kHz, f

IN1

CONV

ACQ

SCLK

(Note 3) 0.556 µs

(Note 5) 104 ns

, unless otherwise noted.)

REF

= 300kHz -78 dB

IN2

±1 ppm/°C

28.8 MHz

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL= VDD, f

SCLK

= 28.8MHz, 50% duty cycle, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

ANALOG INPUTS (AIN+, AIN-)

Differential Input Voltage Range V

Absolute Input Voltage Range 0 V
DC Leakage Current ±1 µA
Input Capacitance Per input pin 16 pF
Input Current (Average) Time averaged at maximum throughput rate 75 µA

REFERENCE OUTPUT (REF)

REF Output Voltage Range Static, TA = +25°C 4.086 4.096 4.106 V
Voltage Temperature Coefficient ±50 ppm/°C

Load Regulation

Line Regulation VDD = 4.75V to 5.25V, static 0.5 mV/V

DIGITAL INPUTS (SCLK, CNVST)

Input-Voltage Low VIL 0.3 x V
Input-Voltage High VIH 0.7 x V
Input Leakage Current I

DIGITAL OUTPUT (DOUT)

Output Load Capacitance C
Output-Voltage Low V
Output-Voltage High V
Output Leakage Current I

POWER REQUIREMENTS

Analog Supply Voltage V
Digital Supply Voltage V

Analog Supply Current,
Normal Mode

Analog Supply Current,
Partial Power-Down Mode

Analog Supply Current,
Full Power-Down Mode

Digital Supply Current (Note 7)

Positive-Supply Rejection PSR VDD = 5V ±5%, full-scale input ±0.2 ±3.0 mV

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AIN+ - AIN-, MAX1076 0 V

IN

AIN+ - AIN-, MAX1078 -V

I

SOURCE

I

= 0 to 200µA 0.5

SINK

IL

OUT

OH
OL

DD

I

DD

I

DD

I

DD

For stated timing performance 30 pF
I

OL

L

= 5mA, VL ≥ 1.8V 0.4 V

SINK

I

SOURCE

Output high impedance ±0.2 ±10 µA

Static, f

SCLK

Static, no SCLK 5 7
Operational, 1.8Msps 10 13
f

= 28.8MHz 2

SCLK

No SCLK 2
f

= 28.8MHz 1

SCLK

No SCLK
Operational, full-scale input at 1.8Msps
Static, f

SCLK

Partial/full power-down mode,

= 28.8MHz

f

SCLK

Static, no SCLK (all modes)

= 0 to 2mA 0.3

= 1mA, VL ≥ 1.8V V L - 0.5V V

= 28.8MHz

= 28.8MHz

REF

/ 2 +V

REF

L

0.05 ±10 µA

4.75 5.25 V

1.8 V
811

0.3
1 2.5

0.4 1

0.2 0.5

0.1

/ 2

REF

DD

L

DD

1

1µA

mV/mA

V

V

V
V

V

mA

mA

µA

mA

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

4 _______________________________________________________________________________________

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset

error have been nulled.

Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-

ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.

Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: Digital supply current is measured with the V

IH

level equal to VL, and the VILlevel equal to GND.

TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL= VDD, f

SCLK

= 28.8MHz, 50% duty cycle, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.)

Figure 1. Detailed Serial-Interface Timing

Figure 2. Load Circuits for Enable/Disable Times

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLK Pulse-Width High t
SCLK Pulse-Width Low t

SCLK Rise to DOUT Transition t

DOUT Remains Valid After SCLK t
CNVST Fall to SCLK Fall t
CNVST Pulse Width t
Power-Up Time; Full Power-Down t
Restart Time; Partial Power-Down t

CH
CL

VL = 1.8V to V
VL = 1.8V to V
CL = 30pF, VL = 4.75V to V

DOUT

CL = 30pF, VL = 2.7V to V
CL = 30pF, VL = 1.8V to V

DHOLDVL

SETUP

CSW

PWR-UP

RCV

= 1.8V to V
VL = 1.8V to V
VL = 1.8V to V

DD
DD

DD
DD
DD

DD
DD
DD

15.6 ns

15.6 ns
14
17
24

4ns
10 ns
20 ns

2ms

16 Cycles

ns

CNVST

t

t

CL

t

CH

t

DHOLD

t

DOUT

SCLK

DOUT

t

SETUP

CSW

DOUT

6kΩ

a) HIGH-Z TO VOH, V
AND V

TO HIGH-Z

OH

GND

OL

TO VOH,

C

L

DOUT

b) HIGH-Z TO V
AND V

6kΩ

TO HIGH-Z

OL

V

L

C

L

GND

, V

TO VOL,

OL

OH

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(VDD= +5V, VL= VDD, f

SCLK

= 28.8MHz, f

SAMPLE

= 1.8Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1076)

MAX1076/78 toc01

DIGITAL OUTPUT CODE

INL (LSB)

756512256

-0.1

0

0.1

0.2

-0.2
0 1024

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1078)

MAX1076/78 toc02

DIGITAL OUTPUT CODE

INL (LSB)

2560-256

-0.1

0

0.1

0.2

-0.2

-512 512

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1076)

MAX1076/78 toc03

DIGITAL OUTPUT CODE

INL (LSB)

756512256

-0.1

0

0.1

0.2

-0.2
0 1024

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1078)

MAX1076/78 toc04

DIGITAL OUTPUT CODE

INL (LSB)

2560-256

-0.1

0

0.1

0.2

-0.2

-512 512

OFFSET ERROR

vs. TEMPERATURE (MAX1076)

MAX1076/78 toc05

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-0.25

0

0.25

0.50

-0.50

-40 85

OFFSET ERROR

vs. TEMPERATURE (MAX1078)

MAX1076/78 toc06

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-0.25

0

0.25

0.50

-0.50

-40 85

GAIN ERROR

vs. TEMPERATURE (MAX1076)

MAX1076/78 toc07

TEMPERATURE (°C)

GAIN ERROR (LSB)

6035-15 10

-0.75

-0.50

-0.25

0

0.25

0.50

0.75

1.00

-1.00

-40 85

GAIN ERROR

vs. TEMPERATURE (MAX1078)

MAX1076/78 toc08

TEMPERATURE (°C)

GAIN ERROR (LSB)

6035-15 10

-0.75

-0.50

-0.25

0

0.25

0.50

0.75

1.00

-1.00

-40 85

DYNAMIC PERFORMANCE

vs. INPUT FREQUENCY (MAX1076)

MAX1076/78 toc09

ANALOG INPUT FREQUENCY (kHz)

DYNAMIC PERFORMANCE (dB)

400300200

61.1

61.2

61.3

61.4

61.5

61.6

61.0
100 500

SNR

SINAD

VDD/VL FULL POWER-DOWN SUPPLY

CURRENT vs. TEMPERATURE

MAX1076/78 toc18

TEMPERATURE (°C)

V

DD

/V

L

SUPPLY CURRENT (µA)

603510-15

0.2

0.4

0.6

0.8

1.0

0

-40 85

VDD, f

SCLK

= 28.8MHz

VDD, NO SCLK

VL, NO SCLK

Typical Operating Characteristics (continued)

(VDD= +5V, VL= VDD, f

SCLK

= 28.8MHz, f

SAMPLE

= 1.8Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

6 _______________________________________________________________________________________

DYNAMIC PERFORMANCE

vs. INPUT FREQUENCY (MAX1078)

62.00

61.75

61.50

61.25

DYNAMIC PERFORMANCE (dB)

61.00
100 500

ANALOG FREQUENCY (kHz)

0

-20

-40

-60

-80

AMPLITUDE (dB)

-100

-120

FFT PLOT (MAX1076)

fIN = 500kHz
SINAD = 61.5dB
SNR = 61.4dB
THD = -88.5dB
SFDR = 87.0dB

SNR

SINAD

400300200

MAX1076/78 toc10

THD (dB)

MAX1076/78 toc13

AMPLITUDE (dB)

THD vs. INPUT FREQUENCY

-80

MAX1076

-82

-84

-86

-88

-90

-92

-94

-96

100 500

MAX1078

400300200

ANALOG INPUT FREQUENCY (kHz)

FFT PLOT (MAX1078)

0

fIN = 500kHz
SINAD = 61.4dB

-20

SNR = 61.5dB
THD = -93.8dB

-40

SFDR = 84.5dB

-60

-80

-100

-120

MAX1076/78 toc11

MAX1076/78 toc14

SFDR vs. INPUT FREQUENCY

90

88

86

SFDR (dB)

84

82

100 500

MAX1078

MAX1076

ANALOG INPUT FREQUENCY (kHz)

TOTAL HARMONIC DISTORTION

vs. SOURCE IMPEDANCE

-50

-60

fIN = 500kHz

-70

THD (dB)

-80

-90

fIN = 100kHz

MAX1076/78 toc12

400300200

MAX1076/78 toc15

-140
0 900

ANALOG FREQUENCY (kHz)

TWO-TONE IMD PLOT (MAX1076)

0

-20

-40

f

IN1

-60

-80

AMPLITUDE (dB)

-100

-120

-140
0 1000

ANALOG FREQUENCY (kHz)

-140

750600450300150

0 900

ANALOG FREQUENCY (kHz)

750600450300150

-100
10 1000

100

SOURCE IMPEDANCE (Ω)

TWO-TONE IMD PLOT (MAX1078)

f

= 2Msps

SAMPLE

= 250.039kHz

f

IN1

= 300.059kHz

f

IN2

IMD = -81.9dB

f

IN2

800600400200

MAX1076/78 toc16

0

-20

-40

f

IN1

-60

-80

AMPLITUDE (dB)

-100

-120

-140
0 1000

ANALOG FREQUENCY (kHz)

f

IN2

f

SAMPLE

f

IN1

f

IN2

IMD = 82.1dB

= 2Msps
= 250.039kHz
= 300.059kHz

800600400200

MAX1076/78 toc17

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(VDD= +5V, VL= VDD, f

SCLK

= 28.8MHz, f

SAMPLE

= 1.8Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

VL PARTIAL/FULL POWER-DOWN SUPPLY

CURRENT vs. TEMPERATURE

200

150

100

SUPPLY CURRENT (µA)

L

V

50

0

-40 85

VL = 5V, f

SCLK

VL = 3V, f

= 28.8MHz

SCLK

TEMPERATURE (°C)

VL SUPPLY CURRENT

vs. TEMPERATURE

1.0

0.8

0.6

CONVERSION, f

= 28.8MHz

603510-15

= 28.8MHz

SCLK

MAX1076/78 toc19

SUPPLY CURRENT (mA)
V

MAX1076/78 toc22

DD

VDD SUPPLY CURRENT

12

9

CONVERSION, f

6

3

0

-40 85

VL SUPPLY CURRENT

vs. CONVERSION RATE

1.0

0.8

0.6

vs. TEMPERATURE

= 28.8MHz

SCLK

PARTIAL POWER-DOWN

TEMPERATURE (°C)

VL = 5V

VDD SUPPLY CURRENT
vs. CONVERSION RATE

12

MAX1076/78 toc20

603510-15

9

6

SUPPLY CURRENT (mA)

DD

3

V

0

0 2000

f

(kHz)

SAMPLE

15001000500

REFERENCE VOLTAGE

vs. TEMPERATURE

4.12

MAX1076/78 toc23

4.10

MAX1076/78 toc21

MAX1076/78 toc24

0.4

FULL/PARTIAL POWER-DOWN, f

SUPPLY CURRENT (mA)

L

V

0.2

0

-40 85
TEMPERATURE (°C)

SCLK

vs. LOAD CURRENT (SOURCE)

4.10

4.09

4.08

REFERENCE VOLTAGE (V)

4.07

4.06
010

= 28.8MHz

603510-15

SUPPLY CURRENT (mA)

L

V

REFERENCE VOLTAGE

LOAD CURRENT (mA)

0.4

0.2

0

0 2000

f

SAMPLE

MAX1076/78 toc25

8642

VL = 3V

VL = 1.8V

15001000500

(kHz)

4.12

4.11

4.10

REFERENCE VOLTAGE (V)

4.09

4.08

4.08

REFERENCE VOLTAGE (V)

4.06

-40 85
TEMPERATURE (°C)

REFERENCE VOLTAGE

vs. LOAD CURRENT (SINK)

0 500

LOAD CURRENT (µA)

400300200100

603510-15

MAX1076/78 toc26

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

8 _______________________________________________________________________________________

Pin Description

Detailed Description

The MAX1076/MAX1078 use an input T/H and succes­sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 10-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1076/MAX1078.

True-Differential Analog Input T/H

The equivalent circuit of Figure 4 shows the input archi­tecture of the MAX1076/MAX1078, which is composed of
a T/H, a comparator, and a switched-capacitor digital-to­analog converter (DAC). The T/H enters its tracking mode
on the 14th SCLK rising edge of the previous conversion.
Upon power-up, the T/H enters its tracking mode immedi­ately. The positive input capacitor is connected to AIN+.
The negative input capacitor is connected to AIN-. The
T/H enters its hold mode on the falling edge of CNVST
and the difference between the sampled positive and
negative input voltages is converted. The time required
for the T/H to acquire an input signal is determined by
how quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens. The acquisition time, t

ACQ

, is the minimum

time needed for the signal to be acquired. It is calculated
by the following equation:

t

ACQ

≥ 8 × (RS + RIN) × 16pF

where RIN= 200Ω, and RS is the source impedance of
the input signal.

Note: t

ACQ

is never less than 104ns, and any source
impedance below 12Ω does not significantly affect the
ADC’s AC performance.

Input Bandwidth

The ADC’s input-tracking circuitry has a 20MHz small­signal bandwidth, making it possible to digitize high­speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre­quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes that clamp the analog input
to VDDand GND allow the analog input pins to swing
from GND - 0.3V to VDD+ 0.3V without damage. Both
inputs must not exceed VDDor be lower than GND for
accurate conversions.

PIN NAME FUNCTION

1 AIN- Negative Analog Input

2 REF

3 RGND Reference Ground. Connect RGND to GND.

4V

5, 11 N.C. No Connection

6 GND Ground. GND is internally connected to EP.

7V

8 DOUT Serial Data Output. Data is clocked out on the rising edge of SCLK.

9 CNVST

10 SCLK Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.
12 AIN+ Positive Analog Input
—EPExposed Paddle. EP is internally connected to GND.

DD

L

Reference Voltage Output. Internal 4.096V reference output. Bypass REF with a 0.01µF capacitor and
a 4.7µF capacitor to RGND.

Positive Analog Supply Voltage (+4.75V to +5.25V). Bypass VDD with a 0.01µF capacitor and a 10µF
capacitor to GND.

Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor
to GND.

Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the
falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 9

Serial Interface

Initialization After Power-Up

and Starting a Conversion

Upon initial power-up, the MAX1076/MAX1078 require a
complete conversion cycle to initialize the internal cali­bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.

To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a con­version is initiated. SCLK runs the conversion and the
data can then be shifted out serially on DOUT.

Timing and Control

Conversion-start and data-read operations are con­trolled by the CNVST and SCLK digital inputs. Figures
1 and 5 show timing diagrams, which outline the serial­interface operation.

A CNVST falling edge initiates a conversion sequence:
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance
to logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the con­version is determined.

SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t

DOUT

after each

SCLK’s rising edge and remains valid 4ns (t

DHOLD

)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 10 data bits, 2 sub-bits (S1 and S0), and 3
leading zeros, at least 16 rising clock edges are need-

ed to shift out these bits. For continuous operation, pull
CNVST high between the 14th and the 16th SCLK ris­ing edges. If CNVST stays low after the falling edge of
the 16th SCLK cycle, the DOUT line goes to a high­impedance state on either CNVST’s rising edge or the
next SCLK’s rising edge.

Partial Power-Down and

Full Power-Down Modes

Power consumption can be reduced significantly by
placing the MAX1076/MAX1078 in either partial power­down mode or full power-down mode. Partial power­down mode is ideal for infrequent data sampling and
fast wake-up time applications. Pull CNVST high after
the 3rd SCLK rising edge and before the 14th SCLK
rising edge to enter and stay in partial power-down
mode (see Figure 6). This reduces the supply current
to 2mA. While in partial power-down mode, the refer­ence remains enabled to allow valid conversions once
the IC is returned to normal mode. Drive CNVST low
and allow at least 14 SCLK cycles to elapse before dri­ving CNVST high to exit partial power-down mode.

Full power-down mode is ideal for infrequent data sam­pling and very low supply-current applications. The
MAX1076/MAX1078 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CNVST sequence described above to enter

Figure 3. Functional Diagram

Figure 4. Equivalent Input Circuit

OUTPUT
BUFFER

CONTROL

LOGIC AND

TIMING

GND

V

L

DOUT

CNVST

SCLK

REF

AIN+

AIN-

RGND

REF 4.096V

T/H

MAX1076
MAX1078

V

DD

10-BIT

SAR
ADC

C

IN+

R

AIN+

AIN-

AIN+

AIN-

IN+

V

AZ

R

IN-

C

IN-

C

IN+

C

IN-

ACQUISITION MODE

R

IN+

V

AZ

R

IN-

HOLD/CONVERSION MODE

COMP

COMP

CAPACITIVE

DAC

CONTROL

LOGIC

CAPACITIVE

DAC

CONTROL

LOGIC

MAX1076/MAX1078

partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure

7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power­down mode. While in full power-down mode, the refer­ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In

partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.

Transfer Function

Figure 8 shows the unipolar transfer function for the
MAX1076. Figure 9 shows the bipolar transfer function for
the MAX1078. The MAX1076 output is straight binary,
while the MAX1078 output is two’s complement.

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

Figure 6. SPI Interface—Partial Power-Down Mode

Figure 5. Interface-Timing Sequence

Figure 7. SPI Interface—Full Power-Down Mode

CNVST

t

SCLK

SETUP

POWER-MODE SELECTION WINDOW

41412 83 16

t

ACQUIRE

CONTINUOUS-CONVERSION
SELECTION WINDOW

HIGH IMPEDANCE

DOUT

CNVST

ONE 8-BIT TRANSFER

SCLK

1ST SCLK RISING EDGE

DOUT

MODE

REF

000D9D8D7D6 D5

NORMAL

CNVST

FIRST 8-BIT TRANSFER

SCLK

1ST SCLK RISING EDGE 1ST SCLK RISING EDGE

DOUT

000D9D8D7D6 D5

S1D2D4 D3D7 D6 D5D9 D8

S0D0D1

CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE

DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH

PPD

ENABLED (4.096V)

EXECUTE PARTIAL POWER-DOWN TWICE

SECOND 8-BIT TRANSFER

DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH

000000

0

0

MODE

REF

ENABLED (4.096V)

RECOVERYPPDNORMAL

FPD

DISABLED

Applications Information

Internal Reference

The MAX1076/MAX1078 have an on-chip voltage refer­ence trimmed to 4.096V. The internal reference output
is connected to REF and also drives the internal capac­itive DAC. The output can be used as a reference volt­age source for other components and can source up to
2mA. Bypass REF with a 0.01µF capacitor and a 4.7µF
capacitor to RGND.

The internal reference is continuously powered up dur­ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Be sure to allow at least 2ms recovery time after hard­ware power-up or exiting full power-down mode for the
reference to reach its intended value.

How to Start a Conversion

An analog-to-digital conversion is initiated by CNVST
and clocked by SCLK, and the resulting data is clocked
out on DOUT by SCLK. With SCLK idling high or low, a
falling edge on CNVST begins a conversion. This causes
the analog input stage to transition from track to hold
mode, and DOUT to transition from high impedance to
being actively driven low. A total of 16 SCLK cycles are
required to complete a normal conversion. If CNVST is
low during the 16th falling SCLK edge, DOUT returns to
high impedance on the next rising edge of CNVST or
SCLK, enabling the serial interface to be shared by multi­ple devices. If CNVST returns high after the 14th, but
before the 16th SCLK rising edge, DOUT remains active
so continuous conversions can be sustained. The high­est throughput is achieved when performing continuous
conversions. Figure 10 illustrates a conversion using a
typical serial interface.

Connection to

Standard Interfaces

The MAX1076/MAX1078 serial interface is fully compati­ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.

SPI and MICROWIRE

When using SPI or MICROWIRE, the MAX1076/MAX1078
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
10 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid t

DOUT

later and

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Figure 8. Unipolar Transfer Function (MAX1076 Only)

Figure 9. Bipolar Transfer Function (MAX1078 Only)

OUTPUT CODE

111...111

111...110

111...101

000...011

000...010

000...001

000...000
0

12 3

DIFFERENTIAL INPUT

OUTPUT CODE

V

REF

011...111

011...110

000...010

000...001

000...000

111...111

111...110

111...101

100...001

100...000

FS =

ZS = 0

- FS =

1 LSB =

2

-V

REF

2

V

REF

1024

DIFFERENTIAL INPUT

FULL-SCALE

TRANSITION

VOLTAGE (LSB)

VOLTAGE (LSB)

FS - 3/2 LSB

FULL-SCALE
TRANSITION

FS - 3/2 LSB

FS = V

ZS = 0

1 LSB =

FS

REF

V

REF

1024

FS0-FS

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

Figure 10. Continuous Conversion with Burst/Continuous Clock

Figure 11. Common Serial-Interface Connections to the MAX1076/MAX1078

CNVST

SCLK

DOUT

1

000D9D8D7D6D5D4D3D2D1D0S1S0 0

I/O

SCK

MISO

SS

A) SPI

CS

SCK

MISO

SS

+3V TO +5V

+3V TO +5V

CNVST
SCLK
DOUT

CNVST
SCLK
DOUT

MAX1076
MAX1078

MAX1076
MAX1078

1614

1

0

B) QSPI

I/O
SK

SI

CNVST
SCLK
DOUT

MAX1076
MAX1078

C) MICROWIRE

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 13

remains valid until t

DHOLD

after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1 or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini­mum number of clock cycles necessary to clock in the

data. The MAX1076/MAX1078 require 16 clock cycles
from the µP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.

DSP Interface to the TMS320C54_

The MAX1076/MAX1078 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1076/MAX1078 and

Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)

CNVST

8

D6

HIGH-Z

CNVST

1

D9

D8

D7

1

000D9D8D7D6D5D4D3D2D1D0S1S0 0

SCLK

DOUT

CNVST

SCLK

DOUT

916

S0

D5

D4

D2

D3

D1

S1

D0

14

HIGH-Z

16

1

0

SCLK

HIGH-Z

DOUT

2

D9

D8

D7

D4D5D6 D3 D2 D1 D0

16

S1

HIGH-Z

S0

the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.

For continuous conversion, set the serial port to trans­mit a clock, and pulse the frame sync signal for a clock
period before data transmission. The serial-port config­uration (SPC) register should be set up with internal
frame sync (TXM = 1), CLKX driven by an on-chip clock
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).

This setup allows continuous conversions provided that
the data-transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to execute conversions and
read the data without CPU intervention. Connect the V

L

pin to the TMS320C54_ supply voltage when the
MAX1076/MAX1078 are operating with an analog sup­ply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to imple­ment the power-down modes. The CNVST pin must idle
high to remain in either power-down state.

Another method of connecting the MAX1076/MAX1078
to the TMS320C54_ is to generate the clock signals
external to either device. This connection is shown in
Figure 16 where serial clock (CLOCK) drives the CLKR
and SCLK and the convert signal (CONVERT) drives
the FSR and CNVST.

The serial port must be set up to accept an external
receive-clock and external receive-frame sync.

The SPC register should be written as follows:
TXM = 0, external frame sync

MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that

the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
intervention. Connect the VL pin to the TMS320C54_
supply voltage when the MAX1076/MAX1078 are oper­ating with an analog supply voltage higher than the
DSP supply voltage.

The MAX1076/MAX1078 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).

DSP Interface to the ADSP21_ _ _

The MAX1076/MAX1078 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1076/MAX1078 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1076/MAX1078. For continuous conver­sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

14 ______________________________________________________________________________________

Figure 15. Interfacing to the TMS320C54_ Internal Clocks

Figure 16. Interfacing to the TMS320C54_ External Clocks

V

MAX1076
MAX1078

SCLK

CNVST

DOUT

L DV

V

L

DV

DD

TMS320C54_

CLKX

CLKR

FSX

FSR

DR

MAX1076
MAX1078

CONVERT

SCLK

CNVST

DOUT DR

CLOCK

DD

TMS320C54_

CLKR

FSR

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 15

can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver­sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis­ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the VL pin to the ADSP21_ _ _ supply voltage
when the MAX1076/MAX1078 are operating with a sup­ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).

Layout, Grounding, and Bypassing

For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat­ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.

Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for

noise-free operation.
High-frequency noise in the VDDpower supply can

affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1076/MAX1078 are mea­sured using the end-points method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.

Figure 17. DSP Interface—Continuous Conversion

Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock

CNVST

SCLK

DOUT

CNVST

SCLK

DOUT

1 1

000D9D8D7D6D5D4D3D2D1D0S1S0 0

1

000D9D8D7D6D5D4D3 D2D1D0S1S0 0

00S0

1

0 0

MAX1076/MAX1078

Aperture Delay

Aperture delay (tAD) is the time defined between the
falling edge of CNVST and the instant when an actual
sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam­ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The theoretical minimum analog-to-digital
noise is caused by quantization error, and results directly
from the ADC’s resolution (N bits):

SNR = (6.02 x N + 1.76)dB

In reality, there are other noise sources besides quantiza­tion noise, including thermal noise, reference noise, clock
jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first five
harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:

SINAD(dB) = 20 x log (Signal

RMS

/ Noise

RMS

)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantiza­tion noise only. With an input range equal to the full-scale
range of the ADC, calculate the ENOB as follows:

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:

where V

1

is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor­tion component.

Full-Power Bandwidth

Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.

THD x

V VVV

V

log=

+++



















20

2232425

2

1

ENOB

SINAD

( .)

.

=

− 176

602

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

16 ______________________________________________________________________________________

Figure 19. Interfacing to the ADSP21_ _ _

Figure 20. Power-Supply Grounding Condition

V

MAX1076
MAX1078

L

SCLK

CNVST

DOUT

VDDINT

TCLK

RCLK

TFS

RFS

DR

ADSP21_ _ _

SUPPLIES

V

DD

10µF

0.1µF

GND V

10µF

0.1µF

L

V

DD GND RGND

MAX1076
MAX1078

V

L

DGND V

DIGITAL

CIRCUITRY

L

Full-Linear Bandwidth

Full-linear bandwidth is the frequency at which the sig­nal-to-noise plus distortion (SINAD) is equal to 56dB.

Intermodulation Distortion

Any device with nonlinearities creates distortion prod­ucts when two sine waves at two different frequencies
(f1 and f2) are input into the device. Intermodulation
distortion (IMD) is the total power of the IM2 to IM5
intermodulation products to the Nyquist frequency rela­tive to the total input power of the two input tones, f1
and f2. The individual input tone levels are at -7dBFS.

The intermodulation products are as follows:

• 2nd-order intermodulation products (IM2): f

1

+ f2,

f2- f

1

• 3rd-order intermodulation products (IM3): 2f1- f2,

2f2- f1, 2f1+ f2, 2f2+ f

1

• 4th-order intermodulation products (IM4): 3f1- f2,

3f

2

- f1, 3f1+ f2, 3f2+ f

1

• 5th-order intermodulation products (IM5): 3f1- 2f2,

3f2- 2f1, 3f1+ 2f2, 3f2+ 2f

1

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True-

Differential, 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 17

Chip Information

TRANSISTOR COUNT: 13,016
PROCESS: BiCMOS

MAX1076/MAX1078

1.8Msps, Single-Supply, Low-Power, True­Differential, 10-Bit ADCs with Internal Reference

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages

.)

24L QFN THIN.EPS

PACKAGEOUTLINE
12,16,20,24LTHINQFN,4x4x0.8mm

21-0139

PACKAGEOUTLINE
12,16,20,24LTHINQFN,4x4x0.8mm

21-0139

1

C

2

2

C

2