For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1069 is a low-power, 14-bit successiveapproximation analog-to-digital converter (ADC). The
device features automatic power-down, an on-chip
4MHz clock, a +4.096V internal reference, and an
I2C™-compatible 2-wire serial interface capable of both
fast and high-speed modes.
The MAX1069 operates from a single supply and consumes 5mW at the maximum conversion rate of
58.6ksps. AutoShutdown™ powers down the device
between conversions, reducing supply current to less
than 50µA at a 1ksps throughput rate. The option of a
separate digital supply voltage allows direct interfacing
with +2.7V to +5.5V digital logic.
The MAX1069 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to AV
DD
.
The four address select inputs (ADD0–ADD3) allow up
to sixteen MAX1069 devices on the same bus.
The MAX1069 is packaged in a 14-pin TSSOP and
offers both commercial and extended temperature
ranges. Refer to the MAX1169 for a 16-bit device in a
pin-compatible package.
Applications
Hand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Receive Signal Strength Indicators
System Supervision
Features
♦ High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
♦ +4.75V to +5.25V Single Supply
♦ +2.7V to +5.5V Adjustable Logic Level
♦ Internal +4.096V Reference
♦ External Reference: 1V to AV
DD
♦ Internal 4MHz Conversion Clock
♦ 58.6ksps Sampling Rate
♦ AutoShutdown Between Conversions
♦ Low Power
5.0mW at 58.6ksps
4.2mW at 50ksps
2.0mW at 10ksps
0.23mW at 1ksps
3µW in Shutdown
♦ Small 14-Pin TSSOP Package
Ordering Information
(
)
Pin Configuration
I2C is a trademark of Philips Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
*Future product—contact factory for availability.
查询MAX1069供应商
PARTTEMP RANGE
MAX1069ACUD0°C to +70°C14 TSSOP±1
MAX1069BCUD0°C to +70°C14 TSSOP±2
MAX1069CCUD0°C to +70°C14 TSSOP±3
MAX1069AEUD* -40°C to +85°C14 TSSOP±1
MAX1069BEUD* -40°C to +85°C14 TSSOP±2
MAX1069CEUD* -40°C to +85°C14 TSSOP±3
PINPACKAGE
INL
LSB
TOP VIEW
DGND
SCL
SDA
ADD1
ADD0
DV
1
2
3
4
5
6
7
DD
ADD3
14
REF
13
REFADJ
12
AGNDSADD2
MAX1069
TSSOP
11
10
AIN
9
AGND
8
AV
DD
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD
to AGND .........................................................-0.3V to +6V
DV
DD
to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AV
DD
+ 0.3V)
SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
The MAX1069 analog-to-digital converter (ADC) uses
successive-approximation conversion (SAR) techniques and on-chip track-and-hold (T/H) circuitry to
capture and convert an analog signal to a serial 14-bit
digital output.
The MAX1069 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to AVDD.
The flexible 2-wire serial interface provides easy connection to microcontrollers (µCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified func-
tional diagram for the MAX1069 and Figure 4 shows the
typical application circuit.
Power Supply
To maintain a low-noise environment, the MAX1069
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900µA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with lowvoltage ASICs. The MAX1069 wakes up in shutdown
mode when power is applied irrespective of the AV
DD
and DVDDsequence.
Analog Input and Track/Hold
The MAX1069 analog input contains a track-and-hold
(T/H) capacitor, T/H switches, comparator, and a
switched capacitor digital-to-analog converter (DAC)
(Figure 5).
As shown in Figure 11c, the MAX1069 acquisition period is the two clock cycles prior to the conversion period. The T/H switches are normally in the hold position.
During the acquisition period the T/H switches are in
the track position and C
T/H
charges to the analog input
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on C
T/H
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 14-bit resolution. This is equivalent to transferring a charge of 35pF × (V
AIN
- V
AGNDS
)
from C
T/H
to the binary-weighted capacitive DAC,
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
7DVDDDigital Power Input. Bypass to DGND with a 0.1µF capacitor.
8AVDDAnalog Power Input. Bypass to AGND with a 0.1µF capacitor.
9AGNDAnalog Ground
10AINAnalog Input
11AGNDSAnalog Signal Ground. Negative reference for analog input. Connect to AGND.
12REFADJ
13REF
14ADD3Address Select Input 3
Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1µF capacitor.
Connect REFADJ to AV
Reference Buffer Output and External Reference Input. Bypass to AGND with a 10µF capacitor
when using the internal reference.
to disable the internal bandgap reference and reference-buffer amplifier.
DD
MAX1069
forming a digital representation of the analog input signal. During the conversion period, the MAX1069 holds
SCL low (clock stretching).
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
acquisition time by reducing f
SCL
. The MAX1069 pro-
vides two SCL cycles (t
ACQ
), in which the track-andhold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(R
SOURCE
) to allow the track-and-hold capacitance to
charge within the allotted time. R
SOURCE
should be
less than 12.9kΩ for f
SCL
= 400kHz and less than 2.4kΩ
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(>4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the Input Buffer section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for C
T/H
.
Analog Input Bandwidth
The MAX1069 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input bandwidth makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Analog Input Range and Protection
Internal ESD (electrostatic discharge) protection diodes
clamp AIN, REF, and REFADJ to AV
DD
and
AGNDS/AGND (Figure 6). These diodes allow the ana-
log inputs to swing from (AGND - 0.3V) to (AVDD+
0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than
50mV beyond their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
Internal Clock
The MAX1069 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
data when the conversion is in progress. When the
MAX1069 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
Digital Interface
The MAX1069 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the
MAX1069 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data transfer on the bus and generates SCL.
SDA and SCL require pullup resistors (500Ω or greater,
Figure 4). Optional resistors (24Ω) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1069. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the Bus Timing
section). Use a repeated START condition (Sr) in place
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
*MINIMIZE R
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (t
TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (C
SOURCE
) TO
T/H
ACQ
REFADJ
AGNDS
AGND
).
MAX1069
of a STOP condition to leave the bus active and in its
current timing mode (see the HS-Mode section).
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX1069 (slave) generate acknowledge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 8). To generate a not acknowledge, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
Slave Address
A master initiates communication with a slave device by
issuing a START condition followed by a slave address
byte. As shown in Figure 9, the slave address byte consists of 7 address bits and a read/write bit (R/W). When
idle, the MAX1069 continuously waits for a START condition followed by its slave address. When the
MAX1069 recognizes its slave address, it acquires the
analog input signal and prepares for conversion. The
first three bits (MSBs) of the slave address have been
factory programmed and are always 011. Connecting
ADD3–ADD0 to DVDDor DGND, programs the last four
bits (LSBs) of the slave address high or low.
Since the MAX1069 does not require setup or configuration, the least significant bit (LSB) of the address byte
(R/W) controls power-down. In external reference mode
(REFADJ = AVDD), R/W is a don’t care. In internal reference mode, setting R/W = 1 places the device in normal operation and setting R/W = 0 powers down the
internal reference following the conversion (see the
Internal Reference Shutdown section).
After receiving the address, the MAX1069 (slave)
issues an acknowledge by pulling SDA low for one
clock cycle.
Bus Timing
At power-up, the MAX1069 bus timing defaults to fast
mode (F/S-mode), allowing conversion rates up to
19ksps. The MAX1069 must operate in high-speed
mode (HS-mode) to achieve conversion rates up to
58.6ksps. Figure 1 shows the bus timing for the
MAX1069 2-wire interface.
HS-Mode
At power-up, the MAX1069 bus timing is set for F/Smode. The master selects HS-mode by addressing all
devices on the bus with the HS-mode master code 0000
1XXX (X = don’t care). After successfully receiving the
HS-mode master code, the MAX1069 issues a not
acknowledge allowing SDA to be pulled high for one
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
clock cycle (Figure 10). After the not acknowledge, the
MAX1069 is in HS-mode. The master must then send a
repeated START followed by a slave address to initiate
HS-mode communication. If the master generates a
STOP condition, the MAX1069 returns to F/S-mode.
Data Byte (Read Cycle)
Initiate a read cycle to begin a conversion. A read
cycle begins with the master issuing a START condition
followed by seven address bits and a read bit (R/W).
The standard I2C-compatible interface requires that
R/W = 1 to read from a device, however, since the
MAX1069 does not require setup or configuration, the
read mode is inherent and R/W controls power-down
(see the Internal Reference Shutdown section). If the
address byte is successfully received, the MAX1069
(slave) issues an acknowledge and begins conversion.
As seen in Figure 11, the MAX1069 holds SCL low during conversion. When the conversion is complete, SCL
is released and the master can clock data out of the
device. The most significant byte of the conversion is
available first and contains D13 to D6. The least significant byte contains D5 to D0 plus two trailing sub bits
S1 and S0. Data can be continuously converted as long
as the master acknowledges the conversion results.
Issuing a not acknowledge frees the bus allowing the
master to generate a STOP or repeated START.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1069 in shutdown. When the
internal reference is used, allow 12ms for the reference
to settle when C
REF
= 10µF and C
REFADJ
= 0.1µF.
Automatic Shutdown
The MAX1069 automatic shutdown reduces the supply
current to less than 0.6µA between conversions. The
MAX1069 I2C-compatible interface is always active.
When the MAX1069 receives a valid slave address the
device powers up. The device is then powered down
again when the conversion is complete. The automatic
shutdown function does not change with internal or
external reference. When the internal reference is chosen, the internal reference remains active between conversions unless internal reference shutdown is requested
(see the Internal Reference Shutdown section).
Internal Reference Shutdown
The R/W bit of the slave address controls the MAX1069
internal reference shutdown. In external reference
mode (REFADJ = AVDD), R/W is a don’t care. In internal
reference mode, setting R/W = 1 places the device in
normal operation and setting R/W = 0 prepares the
internal reference for shutdown.
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
If the internal reference is used and R/W = 0, shutdown
occurs when the master issues a not-acknowledge bit
while reading the conversion results. The internal reference and internal reference buffer are disabled during
shutdown, reducing the analog supply current to less
than 1µA.
A dummy conversion is required to power up the internal reference. The MAX1069 internal reference begins
powering up from shutdown on the 9th falling edge of a
valid address byte. Allow 12ms for the internal reference to settle before obtaining valid conversion results.
Reference Voltage
The MAX1069 provides an internal or accepts an external reference voltage. The ADC input range is from
V
AGNDS
to V
REF
(see the Transfer Function section).
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
The MAX1069 contains an internal 4.096V bandgap reference. This bandgap reference is connected to
REFADJ through a 5kΩ resistor. Bypass REFADJ with a
0.1µF capacitor to AGND. The MAX1069 reference
buffer has a unity gain to provide +4.096V at REF.
Bypass REF with a 10µF capacitor to AGND when the
internal reference is used (Figure 12).
The internal reference is adjustable to ±1.5% using the
Figure 13 circuit.
External Reference
For external reference operation, disable the internal
reference by connecting REFADJ to AVDD. During conversion, an external reference at REF must deliver up to
100µA of DC load current and have an output impedance of less than 10Ω.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1069’s equivalent input noise
(80µV
RMS
) when choosing a reference.
Transfer Function
The MAX1069 has a standard unipolar transfer function
with a valid analog input voltage range from V
AGNDS
to
V
REF
. Output data coding is binary with 1LSB =
(V
REF
/2N) where ‘N’ is the number of bits (14). Code
transitions occur halfway between successive-integer
LSB values. Figure 14 shows the MAX1069 input/output
(I/O) transfer function.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy. If the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step-change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output voltage change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output), causing some output disturbance.
Ensure that the sampled voltage has settled to within
the required limits before the end of the acquisition
time. If the frequency of interest is low, AIN can be
bypassed with a large enough capacitor to charge the
internal sampling capacitor with very little ripple.
However, for AC use, AIN must be driven by a wideband buffer (at least 4MHz), which must be stable with
the ADC’s capacitive load (in parallel with any AIN
bypass capacitor used) and also settle quickly. Refer to
Maxim’s website at www.maxim-ic.com for application
notes on how to choose the optimum buffer amplifier for
your ADC application.
Layout, Grounding, and Bypassing
Careful printed circuit (PC) layout is essential for the
best system performance. Boards should have separate analog and digital ground planes and ensure that
digital and analog signals are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the device package.
Figure 4 shows the recommended system ground con-
nections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest-noise operation, make the ground return to
the star ground’s power-supply low impedance and
make it as short as possible.
High-frequency noise in the AVDDpower supply
degrades the ADC’s high-speed comparator performance. Bypass AVDDto AGND with a 0.1µF ceramic
surface-mount capacitor. Make bypass capacitor connections as short as possible. If the power supply is
very noisy, connect a 10Ω resistor in series with AV
DD
and a 4.7µF capacitor from AVDDto AGND to create a
lowpass RC filter.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function
once offset and gain errors have been nullified. The
MAX1069 INL is measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples (Figure 11).
Aperture Delay
Aperture delay (tAD) is the time from the falling edge of
SCL to the instant when an actual sample is taken
(Figure 11).
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = ((6.02
✕
N) + 1.76)dB
In reality, noise sources besides quantization noise
exist, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the RMS sum ratio of
the input signal’s first five harmonics to the fundamental
itself, expressed as:
where V1is the fundamental amplitude, and V2through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Chip Information
TRANSISTOR COUNT: 18,269
PROCESS: BiCMOS
MAX1069
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
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