Maxim MAX104CHC Datasheet

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General Description

The MAX104 PECL-compatible, 1Gsps, 8-bit analog-to­digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX104 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.

The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (greater than 7.5 effective
bits) at the Nyquist frequency. A fully differential com­parator design and decoding circuitry reduce out-of­sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance
of one error per 1016clock cycles. Unlike other ADCs
that can have errors resulting in false full- or zero-scale
outputs, the MAX104 limits the error magnitude to
1LSB.

The analog input is designed for either differential or
single-ended use with a ±250mV input voltage range.
Dual, differential, PECL-compatible output data paths
ensure easy interfacing and include an 8:16 demulti­plexer feature that reduces output data rates to one-half
the sampling clock rate. The PECL outputs can be
operated from any supply between +3V to +5V for com­patibility with +3.3V or +5V referenced systems. Control
inputs are provided for interleaving additional MAX104
devices to increase the effective system sampling rate.

The MAX104 is packaged in a 25mm x 25mm, 192-con­tact Enhanced Super-Ball Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) tempera­ture range.

Applications

Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/Sonar/ECM Systems
ATE Systems

Features

♦ 1Gsps Conversion Rate
♦ 2.2GHz Full-Power Analog Input Bandwidth
♦ >7.5 Effective Bits at f

IN

= 500MHz (Nyquist

Frequency)

♦ ±0.25LSB INL and DNL
♦ 50Ω Differential Analog Inputs
♦ ±250mV Input Signal Range
♦ On-Chip, +2.5V Precision Bandgap Voltage

Reference

♦ Latched, Differential PECL Digital Outputs
♦ Low Error Rate: 10

-16

Metastable States at 1Gsps

♦ Selectable 8:16 Demultiplexer
♦ Internal Demux Reset Input with Reset Output
♦ 192-Contact ESBGA Package

MAX104

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

________________________________________________________________

Maxim Integrated Products

1

ESBGA

TOP VIEW

MAX104

19-1459; Rev 1; 5/99

PART

MAX104CHC 0°C to +70°C

TEMP. RANGE PIN-PACKAGE

192 ESBGA

EVALUATION KIT

AVAILABLE

Typical Operating Circuit appears at end of data sheet.

192-Contact ESBGA

Ball Assignment Matrix

Ordering Information

ESBGA is a trademark of Amkor/Anam.

MAX104

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VCCA to GNDA.........................................................-0.3V to +6V

V

CC

D to GNDD.........................................................-0.3V to +6V

V

CC

I to GNDI............................................................-0.3V to +6V

V

CC

O to GNDD........................................-0.3V to (VCCD + 0.3V)

AUXEN1, AUXEN2 to GND .....................-0.3V to (V

CC

D + 0.3V)

V

EE

to GNDI..............................................................-6V to +0.3V

Between GNDs......................................................-0.3V to +0.3V

V

CC

A to VCCD.......................................................-0.3V to +0.3V

V

CC

A to VCCI.........................................................-0.3V to +0.3V

PECL Digital Output Current...............................................50mA

REFIN to GNDR ........................................-0.3V to (V

CC

I + 0.3V)

REFOUT Current................................................+100µA to -5mA

ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V

TTL/CMOS Control Inputs (DEMUXEN,

DIVSELECT)..........................................-0.3V to (V

CC

D + 0.3V)

RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V)

VOSADJ Adjust Input................................-0.3V to (V

CC

I + 0.3V)

CLK+ to CLK- Voltage Difference..........................................±3V

CLK+, CLK-.....................................(V

EE

- 0.3V) to (GNDD + 1V)

CLKCOM.........................................(V

EE

- 0.3V) to (GNDD + 1V)

VIN+ to VIN- Voltage Difference............................................±2V

VIN+, VIN- to GNDI................................................................±2V

Continuous Power Dissipation (T

A

= +70°C)

192-Contact ESBGA (derate 61mW/°C above +70°C)......4.88W

(with heatsink and 200 LFM airflow,

derate 106mW/°C above +70°C) ........................................8.48W

Operating Temperature Range

MAX104CHC........................................................0°C to +70°C

Operating Junction Temperature.....................................+150°C

Storage Temperature Range.............................-65°C to +150°C

T

A

= +25°C

Referenced to GNDR

0 < I

SOURCE

< 2.5mA

Driving REFIN input only

VIN+ and VIN- to GNDI, TA= +25°C

VOSADJ = 0 to 2.5V

Signal + offset w.r.t. GNDI

Note 1

TA= +25°C
No missing codes guaranteed

CONDITIONS

kΩ45R

REF

Reference Input Resistance

mV5∆REFOUT

Reference Output Load
Regulation

V2.475 2.50 2.525REFOUTReference Output Voltage

LSB±4 ±5.5Input VOSAdjust Range

kΩ14 25R

VOS

Input Resistance (Note 2)

LSB-0.5 ±0.25 0.5INLIntegral Nonlinearity (Note 1)

Bits8RESResolution

ppm/°C150TC

R

Input Resistance Temperature
Coefficient

Ω49 50 51R

IN

Input Resistance

V±0.8V

CM

Common-Mode Input Range

mVp-p475 500 525V

FSR

Full-Scale Input Range

LSB-0.5 ±0.25 0.5DNLDifferential Nonlinearity (Note 1)

CodesNoneMissing Codes

UNITSMIN TYP MAXSYMBOLPARAMETER

ACCURACY

ANALOG INPUTS

VOS ADJUST CONTROL INPUT

REFERENCE INPUT AND OUTPUT

MAX104

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= T

MIN

to T

MAX

,

unless otherwise noted. Typical values are at T

A

= +25°C.)

CLK+ and CLK- to CLKCOM, TA= +25°C

VIH= 2.4V
VIL= 0

CONDITIONS

V-1.475V

IL

Digital Input Low Voltage

V-1.165V

IH

Digital Input High Voltage

µA-1 1I

IL

Low-Level Input Current

ppm/°C150TC

R

Input Resistance Temperature
Coefficient

Ω48 50 52R

CLK

Clock Input Resistance

µA50I

IH

High-Level Input Current

V0.8V

IL

Low-Level Input Voltage

V2.0V

IH

High-Level Input Voltage

UNITSMIN TYP MAXSYMBOLPARAMETER

V-1.810 -1.620V

OL

Digital Output Low Voltage

V-1.025 -0.880V

OH

Digital Output High Voltage

W5.25P

DISS

Power Dissipation (Note 6)

mA75 115ICCOOutput Supply Current (Note 6)

mA205 340ICCDDigital Supply Current

mA-290 -210I

EE

Negative Input Supply Current

mA108 150ICCIPositive Input Supply Current

mA480 780ICCAPositive Analog Supply Current

(Note 9)

VIN+ = VIN- = ±0.1V

dB40 73PSRR+

Positive Power-Supply Rejection
Ratio (Note 8)

dB40 68CMRR

Common-Mode Rejection Ratio
(Note 7)

(Note 10) dB40 68PSRR-

Negative Power-Supply
Rejection Ratio (Note 8)

CLOCK INPUTS (Note 3)

TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT)

DEMUX RESET INPUT (Note 4)

PECL DIGITAL OUTPUTS (Note 5)

POWER REQUIREMENTS

MAX104

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

f

IN1

= 124MHz, f

IN2

= 126MHz,

at -7dB below full-scale

fIN= 500MHz

fIN= 1000MHz

CONDITIONS

dB-57.7IMDTwo-Tone Intermodulation

7.40

ENOB

1000

GHz2.2BW

-3dB

Analog Input Full-Power
Bandwidth

V/V1.1:1VSWRAnalog Input VSWR

7.52

UNITSMIN TYP MAXSYMBOLPARAMETER

Differential
Single-ended

fIN= 500MHz

7.49

ENOB

500

7.2 7.55Differential

Single-ended

fIN= 1000MHz

46.4

SNR

1000

46.4

fIN= 125MHz

Differential
Single-ended

Bits

7.73

ENOB

125

Effective Number of Bits
(Note 11)

7.4 7.74Differential

Single-ended

fIN= 500MHz

47.1

SNR

500

43.5 47.0Differential

Single-ended

fIN= 125MHz

dB

47.4

SNR

125

Signal-to-Noise Ratio
(No Harmonics)

44.2 47.4Differential

Single-ended

fIN= 500MHz

fIN= 1000MHz

-49.6

THD

1000

-52.6

-51.3

THD

500

Differential
Single-ended

-50 -52.5Differential

Single-ended

fIN= 125MHz

dB

-67.4

THD

125

Total Harmonic Distortion
(Note 12)

-61 -66.2Differential

Single-ended

fIN= 500MHz

fIN= 1000MHz

52.5

SFDR

1000

52.8

52.3

SFDR

500

Differential
Single-ended

50 52.3Differential

Single-ended

fIN= 125MHz

dB

69.5

SFDR

125

Spurious-Free Dynamic Range

62 68.9Differential

Single-ended

fIN= 500MHz

fIN= 1000MHz

46.3

SINAD

1000

47.0

46.9

SINAD

500

Differential
Single-ended

45.1 47.2Differential

Single-ended

fIN= 125MHz

dB

48.3

SINAD

125

Signal-to-Noise Ratio and
Distortion (Note 11)

46.3 48.3Differential

Single-ended

VOSADJ control input open LSB-1.5 0 +1.5V

OS

Transfer Curve Offset

ANALOG INPUT

DYNAMIC SPECIFICATIONS

MAX104

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________ 5

Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale

range (FSR) is defined as 256

· slope of the line.

Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit

voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.

Note 3: The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings

on the CLK+ and CLK- inputs.

Note 4: Input logic levels are measured with respect to the V

CC

O power-supply voltage.

Note 5: All PECL digital outputs are loaded with 50Ω to V

CC

O - 2.0V. Measurements are made with respect to the VCCO power-

supply voltage.

Note 6: The current in the V

CC

O power supply does not include the current in the digital output’s emitter followers, which is a func-

tion of the load resistance and the V

TT

termination voltage.

Note 7: Common-Mode Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in

the common-mode voltage, expressed in dB.

Note 8: Power-Supply Rejection Ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in

power-supply voltage, expressed in dB.

Note 9: Measured with the positive supplies tied to the same potential; V

CC

A = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.

Note 10: V

EE

varies from -5.25V to -4.75V.

AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)

Figure 17

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

20% to 80%, CL= 3pF

Figure 15

Figure 4
Figure 4

CONDITIONS

Clock

Cycles

7.5

Primary Port Pipeline
Delay

ps180t

FDREADY

DREADY Fall Time

ps220t

RDREADY

DREADY Rise Time

ps360t

FDATA

DATA Fall Time

ns0.45t

PWL

Clock Pulse Width Low

Gsps1f

MAX

Maximum Sample Rate

ps420 t

RDATA

DATA Rise Time

ps0t

SU

Reset Input Data Setup Time
(Note 13)

ps100t

AD

Aperture Delay

ps<0.5t

AJ

Aperture Jitter

UNITSMIN TYP MAXSYMBOLPARAMETER

Figure 17 ns0.45 5t

PWH

Clock Pulse Width High

Figure 15 ps0t

HD

Reset Input Data Hold Time
(Note 13)

Figure 17 ns2.2t

PD1

CLK to DREADY Propagation
Delay

Figure 17 ps-50 150 350t

PD2

DREADY to DATA Propagation
Delay (Note 14)

8.5

Figures 6, 7, 8

Clock

Cycles

9.5

t

PDA

Auxiliary Port Pipeline
Delay

t

PDP

Figures 6, 7, 8

TIMING CHARACTERISTICS

DIV1, DIV2 modes
DIV4 mode 7.5
DIV1, DIV2 modes
DIV4 mode

MAX104

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, TA= +25°C, unless otherwise
noted.)

8.00

6.50
10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

6.75

7.00

7.25

7.50

7.75

MAX104toc01

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

-12dBFS

-6dBFS

-1dBFS

1250

8.00

6.50
10 100 1000

EFFECTIVE NUMBER OF BITS vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

6.75

7.00

7.25

7.50

7.75

MAX104toc02

ANALOG INPUT FREQUENCY (MHz)

ENOB (Bits)

-12dBFS

-6dBFS

-1dBFS

1250

49

43

10 100 1000

SIGNAL-TO-NOISE PLUS DISTORTION vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

44

45

46

48

47

MAX104toc04

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

-12dBFS

-6dBFS

-1dBFS

1250

49

43

10 100

1000

SIGNAL-TO-NOISE PLUS DISTORTION vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

44

45

46

47

48

MAX104toc03

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

-12dBFS

-6dBFS

-1dBFS

1250

50

30

10 100

1000

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

34

38

46

42

MAX104toc05

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

-12dBFS

-6dBFS

-1dBFS

1250

50

30

10 100 1000

1250

SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

34

38

46

42

MAX104toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

-12dBFS

-6dBFS

-1dBFS

Note 11: Effective Number of Bits (ENOB) and Signal-to-Noise Plus Distortion (SINAD) are computed from a curve fit referenced to

the theoretical full-scale range.

Note 12: Total Harmonic Distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse one clock period long or greater.
Note 14: The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when

the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the
middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which
gives maximum setup and hold time for latching external data latches.

MAX104

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________

7

80

30

10 100 1000

SPURIOUS-FREE DYNAMIC RANGE vs.

ANALOG INPUT FREQUENCY

(SINGLE-ENDED ANALOG INPUT DRIVE)

40

50

60

70

MAX104toc09

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

-1dBFS

-6dBFS

-12dBFS

1250

80

30

10 100 1000

SPURIOUS-FREE DYNAMIC RANGE vs.

ANALOG INPUT FREQUENCY

(DIFFERENTIAL ANALOG INPUT DRIVE)

40

50

60

70

MAX104toc10

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

-1dBFS

-6dBFS

-12dBFS

1250

6.50

7.25

7.00

6.75

7.50

7.75

8.00

4.50 4.904.70 5.10 5.30 5.50

EFFECTIVE NUMBER OF BITS

vs. V

CC

I = VCCA = VCCD

(f

IN

= 125MHz, -1dBFS)

MAX104-13

VCC (V)

ENOB (Bits)

8.00

6.50
100 1000

EFFECTIVE NUMBER OF BITS vs.

CLOCK FREQUENCY

(f

IN

= 125MHz, -1dBFS)

6.75

7.00

7.25

7.50

7.75

MAX104toc11

CLOCK FREQUENCY (MHz)

ENOB (Bits)

8.00

6.50

-12 -10

-6

-2 2 6-8 -4 0 4 108

EFFECTIVE NUMBER OF BITS vs.

CLOCK POWER

(f

IN

= 125MHz, -1dBFS)

6.75

7.00

7.25

7.50

7.75

MAX104toc12

CLOCK POWER (dBm) PER SIDE

ENOB (Bits)

SINGLE-ENDED CLOCK DRIVE

DIFFERENTIAL CLOCK DRIVE

6.50

7.25

7.00

6.75

7.50

7.75

8.00

-5.50 -5.10-5.30 -4.90 -4.70 -4.50

EFFECTIVE NUMBER OF BITS vs. V

EE

(fIN = 125MHz, -1dBFS)

MAX104-14

VEE (V)

ENOB (Bits)

55

59
57

65
63
61

67

69

73
71

75

-12 -10 -8 -6 -4 -2 0 2 4 8610

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK POWER

(f

IN

= 125MHz, -1dBFS)

MAX104toc15

CLOCK POWER (dBm) PER SIDE

SFDR (dB)

DIFFERENTIAL CLOCK DRIVE

SINGLE-ENDED CLOCK DRIVE

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, TA= +25°C, unless otherwise
noted.)

MAX104

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, TA= +25°C, unless otherwise
noted.)

65

67
66

69
68

71
70

72

74
73

75

4.50 4.70 4.90 5.10 5.30 5.50

SPURIOUS-FREE DYNAMIC RANGE

vs. V

CC

I = VCCA = VCCD

(f

IN

= 125MHz, -1dBFS)

MAX104-16

VCC (V)

SFDR (dB)

65

67
66

69
68

71
70

72

74
73

75

-5.50 -5.30 -5.10 -4.90 -4.70 -4.50

SPURIOUS-FREE DYNAMIC RANGE vs. V

EE

(fIN = 125MHz, -1dBFS)

MAX104-17

VEE (V)

SFDR (dB)

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 200100 300 400 500

FFT PLOT

(f

IN

= 125.8545MHz, RECORD LENGTH 8192)

MAX104toc18

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.75 BITS
SNR = 47.4dB
THD = -66.2dB
SFDR = 70.3dB

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 200100 300 400 500

FFT PLOT

(f

IN

= 494.5068MHz, RECORD LENGTH 8192)

MAX104toc19

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.51 BITS
SNR = 46.8dB
THD = -51.9dB
SFDR = 52.1dB

-5

-6

-7

-8

-9

-10
500 1500 2500

ANALOG INPUT BANDWIDTH

-6dB BELOW FULL-SCALE

MAX104toc22

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

SMALL-SIGNAL BANDWIDTH = 2.4GHz

-128.0

-102.4

-51.2

-76.8

-25.6

0

0 200100 300 400 500

FFT PLOT

(f

IN

= 1005.0049MHz, RECORD LENGTH 8192)

MAX104toc20

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

ENOB = 7.51 BITS
SNR = 46.3dB
THD = -52.8dB
SFDR = 53.7dB

-128.0

-76.8

-51.2

-102.4

-25.6

0

0 200100 300 400 500

TWO-TONE INTERMODULATION

FFT PLOT (f

IN1

= 124MHz, f

IN2

= 126MHz,

7dB BELOW FULL-SCALE, RECORD LENGTH 8192)

MAX104toc21

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

f

IN1

f

IN2

0

-1

-2

-3

-4

-5
500 1500 2500

ANALOG INPUT BANDWIDTH

FULL-POWER

MAX104toc23

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

FULL-POWER BANDWIDTH = 2.2GHz

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

INTEGRAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO LOOP DATA)

MAX104toc24

OUTPUT CODE

INL (LSB)

MAX104

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5V, VEE= -5V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 1Gsps, TA= +25°C, unless otherwise
noted.)

Pin Description

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 32 64 96 128 160 192 224 256

DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

(LOW-FREQUENCY SERVO LOOP DATA)

MAX104toc25

OUTPUT CODE

DNL (LSB)

-70

-68

-69

-66

-67

-64

-65

-63

-61

-62

-60

-5.50 -5.30 -5.10 -4.90 -4.70 -4.50

TOTAL HARMONIC DISTORTION vs. V

EE

(f

IN

= 125MHz, -1dBFS)

MAX104-28

V

EE

(V)

THD (dB)

-70

-68

-69

-66

-67

-64

-65

-63

-61

-62

-60

4.50 4.70 4.90 5.10 5.30 5.50

TOTAL HARMONIC DISTORTION

vs. V

CC

I = VCCA = VCCD

(f

IN

= 125MHz, -1dBFS)

MAX104-29

V

CC

(V)

THD (dB)

500ps/div

DREADY RISE/FALL TIME,

DATA OUTPUT RISE/FALL TIME

DREADY

(200mV/div)

DATA

(200mV/div)

MAX104toc26

1.0

1.1

1.2

1.3

1.4

1.5

0 1000500 1500 2000 2500

VSWR vs. ANALOG INPUT FREQUENCY

MAX104toc27

ANALOG INPUT FREQUENCY (MHz)

VSWR

Test Point. Do not connect.

TESTPOINT (T.P.)A10, E17, F2, P3, R17, R18

Digital GroundGNDD

A11, B11, B16, B17, C11, C16, U9, U17,

V9, V17, V18, W9

PECL Supply Voltage, +3V to +5VVCCO

A12–A19, B19, C19, D19, E19, F19,

G19, H19, J19, K19, L19, M19, N19,

P19, T19, U19, V19, W10-W19

Analog Supply Voltage, +5V. Supplies analog comparator array.VCCAA9, B9, C9, U7, V7, W7

Analog Ground. For comparator array.GNDAA8, B8, C8, U6, V6, W6

CONTACT

Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distri­bution, bandgap reference, and reference amplifier.

VCCIA5, B5, C5, H2, H3, M2, M3, U5, V5, W5

Analog Ground. For T/H amplifier, clock distribution, bandgap
reference, and reference amplifier.

GNDI

A1–A4, A6, A7, B1, B2, C1, C2, D1, D2,

D3, G1, H1, J2, J3, K1–K3, L2, L3, M1,

N1, T2, T3, U1, V1, V2, W1–W4

FUNCTIONNAME

MAX104

±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier

10 ______________________________________________________________________________________

Pin Description (continued)

CONTACT

Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribu­tion, bandgap reference, and reference amplifier.

V

EE

B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,

U2, U3, U4, V3, V4

FUNCTIONNAME

Reference Ground. Must be connected to GNDI.

GNDRB6, B7

Primary Output Data Bit 0 (LSB)P0+B12

Digital Supply Voltage, +5VVCCD

B10, B18, C10, C17, C18, T17, T18, U8,

U18, V8, W8

Primary Output Data Bit 1P1+B14

Reference InputREFINC6

Auxiliary Output Data Bit 1A1+B15

Auxiliary Output Data Bit 0 (LSB)A0+B13

Complementary Primary Output Data Bit 0 (LSB)P0-C12

Complementary Primary Output Data Bit 1P1-C14

Complementary Auxiliary Output Data Bit 0 (LSB)A0-C13

TTL/CMOS Demux Divide Selection Input
1: Decimation DIV4 mode
0: Demultiplexed DIV2 mode

DIVSELECTD17

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

ICONSTE1

Tie to VCCO to power the auxiliary port. Tie to GNDD to power
down.

AUXEN2D18

Complementary Auxiliary Output Data Bit 1A1-C15

Reference OutputREFOUTC7

Die Temperature Measurement Test Point. See

Die Temperature

Measurement

section.

IPTATE2

Offset Adjust InputVOSADJF1

TTL/CMOS Demux Enable Control
1: Enable Demux
0: Disable Demux

DEMUXENE18

Primary Output Data Bit 2P2+F18

Auxiliary Output Data Bit 2A2+G18

Complementary Auxiliary Output Data Bit 2A2-G17

Complementary Primary Output Data Bit 2P2-F17

Complementary Primary Output Data Bit 3P3-H17
Primary Output Data Bit 3P3+H18