MAXIM MAX1043, MAX1046, MAX1049 Technical data

General Description

The MAX1040–MAX1043/MAX1046–MAX1049 integrate a multichannel, 10-bit, analog-to-digital converter (ADC) and a quad, 10-bit, digital-to-analog converter (DAC) in a single IC. The devices also include a temperature sensor and configurable general-purpose I/O ports (GPIOs) with a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. The ADC is available in a 4 or an 8 inputchannel version. The four DAC outputs settle within 2.0µs, and the ADC has a 300ksps conversion rate.

All devices include an internal reference (2.5V or 4.096V) providing a well-regulated, low-noise reference for both the ADC and DAC. Programmable reference modes for the ADC and DAC allow the use of an internal reference, an external reference, or a combination of both. Features such as an internal ±1°C accurate temperature sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and AutoShutdown™ allow users to minimize both power consumption and processor requirements. The low glitch energy (4nV•s) and low digital feedthrough (0.5nV•s) of the integrated quad DACs make these devices ideal for digital control of fastresponse closed-loop systems.

The devices are guaranteed to operate with a supply voltage from +2.7V to +3.6V (MAX1041/MAX1043/MAX1047/ MAX1049) and from +4.75V to +5.25V (MAX1040/ MAX1042/MAX1046/MAX1048). These devices consume

2.5mA at 300ksps throughput, only 22µA at 1ksps throughput, and under 0.2µA in the shutdown mode. The MAX1042/MAX1043/MAX1048/MAX1049 offer four GPIOs that can be configured as inputs or outputs.

The MAX1040–MAX1043/MAX1046–MAX1049 are available in 36-pin thin QFN packages. All devices are specified over the -40°C to +85°C temperature range.

Applications

Closed-Loop Controls for Optical Components and Base Stations

System Supervision and Control Data-Acquisition Systems

Features

♦ 10-Bit, 300ksps ADC

Analog Multiplexer with True-Differential

Track/Hold (T/H)

8 Single-Ended Channels or 4 Differential

Channels (Unipolar or Bipolar)

4 Single-Ended Channels or 2 Differential

Channels (Unipolar or Bipolar)

Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB

DNL, No Missing Codes Over Temperature

♦ 10-Bit, Quad, 2µs Settling DAC

Ultra-Low-Glitch Energy (4nV•s) Power-Up Options from Zero Scale or Full Scale Excellent Accuracy: ±0.5 LSB INL

♦ Internal Reference or External Single-Ended/

Differential Reference

Internal Reference Voltage 2.5V or 4.096V

♦ Internal ±1°C Accurate Temperature Sensor ♦ On-Chip FIFO Capable of Storing 16 ADC

Conversion Results and One Temperature Result

♦ On-Chip Channel-Scan Mode and Internal

Data-Averaging Features

♦ Analog Single-Supply Operation

+2.7V to +3.6V or +4.75V to +5.25V

♦ 25MHz, SPI/QSPI/MICROWIRE Serial Interface ♦ AutoShutdown Between Conversions ♦ Low-Power ADC

2.5mA at 300ksps 22µA at 1ksps

0.2µA at Shutdown

♦ Low-Power DAC: 1.5µA ♦ Evaluation Kit Available (Order MAX1258EVKIT)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

________________________________________________________________ Maxim Integrated Products 1

Ordering Information/Selector Guide

19-3294; Rev 1; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information/Selector Guide continued on last page.

EVALUATION KIT

AVAILABLE

Pin Configurations appear at end of data sheet.

PART

TEMP RANGE

PIN-PACKAGE

REF

(V)

ANALOG

SUPPLY

RESOLUTION

BITS***

ADC

DAC

GPIOs

MAX1040BETX

4.096

10 8 4 0

MAX1041BETX*

2.5 2.7 to 3.6 10 8 4 0

MAX1042BETX

4.096

10 8 4 4

MAX1043BETX*

2.5 2.7 to 3.6 10 8 4 4

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc.

*Future product—contact factory for availability. **EP = Exposed pad. ***Number of resolution bits refers to both DAC and ADC.

查询MAX1047供应商

-40°C to +85°C 36 Thin QFN-EP**

VOLTAGE

VOLTAGE (V)

4.75 to 5.25

CHANNELS

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto AGND.........................................................-0.3V to +6V

DGND to AGND.....................................................-0.3V to +0.3V

to AVDD.......................................................-3.0V to +0.3V

Digital Inputs to DGND.............................................-0.3V to +6V

Digital Outputs to DGND .........................-0.3V to (DV

+ 0.3V)

Analog Inputs, Analog Outputs and REF_

to AGND...............................................-0.3V to (AV

+ 0.3V)

Maximum Current into Any Pin (except AGND, DGND, AV

, and OUT_) ...........................................................50mA

Maximum Current into OUT_.............................................100mA

Continuous Power Dissipation (TA= +70°C)

36-Pin Thin QFN (6mm x 6mm)

(derate 26.3mW/°C above +70°C)..........................2105.3mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-60°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s).................................+300°C

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

ADC

DC ACCURACY (Note 1)

Resolution 10 Bits Integral Nonlinearity INL ±0.5

LSB Differential Nonlinearity DNL ±0.5 ±1 LSB Offset Error

LSB Gain Error (Note 2)

LSB Gain Temperature Coefficient ±1.4

ppm/°C

Channel-to-Channel Offset ±0.1 LSB

DYNAMIC SPECIFICATIONS (10kHz sine wave input, VIN = 2.5V

P-P

(MAX1041/MAX1043/MAX1047/MAX1049), VIN = 4.096V

P-P

(MAX1040/MAX1042/MAX1046/MAX1048), 300ksps, f

SCLK

= 4.8MHz)

Signal-to-Noise Plus Distortion

61 dB

Total Harmonic Distortion (Up to the Fifth Harmonic)

THD -70 dBc

Spurious-Free Dynamic Range SFDR 66 dBc Intermodulation Distortion IMD f

IN1

= 9.9kHz, f

IN2

= 10.2kHz 72 dBc Full-Linear Bandwidth SINAD > 70dB 100 kHz Full-Power Bandwidth -3dB point 1 MHz

CONVERSION RATE (Note 3)

External reference 0.8 µs

Power-Up Time t

Internal reference (Note 4) 218

C onver si on

cl ock

cycl es

Note: If the package power dissipation is not exceeded, one output at a time can be shorted to AVDD, DVDD, AGND, or DGND

indefinitely.

±0.25 ±2.0

SINAD

±0.025 ±2.0

±1.0

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

Acquisition Time t

ACQ

(Note 5) 0.6 µs Internally clocked 3.5

Conversion Time t

CONV

Externally clocked 2.7

µs

Internal Clock Frequency Internally clocked conversion 4.3 MHz External Clock Frequency f

CLK

Externally clocked conversion (Note 5) 0.1 4.8 MHz Duty Cycle 40 60 % Aperture Delay 30 ns Aperture Jitter <50 ps

ANALOG INPUTS

Unipolar 0 Input Voltage Range (Note 6)

Bipolar

Input Leakage Current

±1 µA

Input Capacitance 24 pF

INTERNAL TEMPERATURE SENSOR

TA = +25°C ±0.7

Measurement Error (Notes 5, 7)

TA = T

MIN

to T

MAX

±1.0

°C

Temperature Resolution 1/8

°C/LSB

INTERNAL REFERENCE

2.50

REF1 Output Voltage

REF1 Voltage Temperature Coefficient

±30

ppm/°C

REF1 Output Impedance 6.5 kΩ

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049)

0.39

REF1 Short-Circuit Current

REF

= 4.096V (MAX1040/MAX1042/

MAX1046/MAX1048)

0.63

EXTERNAL REFERENCE

REF1 Input Voltage Range V

REF1

REF mode 11 (Note 4) 1

0.05

REF mode 01 1

0.05

REF2 Input Voltage Range (Note 4)

REF2

REF mode 11 0 1

MAX1041/MAX1043/MAX1047/MAX1049 2.482 MAX1040/MAX1042/MAX1046/MAX1048 4.066 4.096 4.126

REF

-V

/ 2 V

REF

±0.01

2.518

REF

±3.0

/ 2

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

REF

= 2.5V (MAX1041/MAX1043/

25 80

REF

= 4.096V (MAX1040/MAX1042/

40 80

REF1 Input Current (Note 9) I

REF1

Acquisition between conversions

±1

µA

REF

= 2.5V (MAX1041/MAX1043/

25 80

REF

= 4.096V (MAX1040/MAX1042/

40 80

REF2 Input Current I

REF2

Acquisition between conversions

±1

µA

DAC

DC ACCURACY (Note 10)

Resolution 10 Bits Integral Nonlinearity INL ±0.5 ±1 LSB Differential Nonlinearity DNL Guaranteed monotonic

LSB

Offset Error V

±3 ±10 mV

Offset-Error Drift ±10

ppm of

FS/°C

Gain Error GE

±10 LSB

Gain Temperature Coefficient ±8

ppm of

FS/°C

DAC OUTPUT

No load 0.02

0.02

Output Voltage Range

10kΩ load to either rail 0.1

0.1

DC Output Impedance 0.5 Ω Capacitive Load (Note 11) 1 nF

AVDD = 2.7V, V

REF

= 2.5V (MAX1041/ MAX1043/MAX1047/MAX1049), gain error < 1%

2000

Resistive Load to AGND

D D

= 4.75V , V

R E F

= 4.096V ( M AX 1040/ M AX 1042/M AX 1046/M AX 1048) , g ai n er r or < 2%

500

Ω

MAX1047/MAX1049), f

MAX1046/MAX1048), f

MAX1047/MAX1049), f

MAX1046/MAX1048), f

SAMPLE

= 300ksps

±0.01

±1.25

±0.5

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

From power-down mode, AVDD = 5V 25

Wake-Up Time (Note 12)

µs 1kΩ Output Termination Programmed in power-down mode 1 kΩ 100kΩ Output Termination

At wake-up or programmed in power-down mode

100 kΩ

DYNAMIC PERFORMANCE (Notes 5, 13)

Output-Voltage Slew Rate SR Positive and negative 3 V/µs Output-Voltage Settling Time t

To 1 LSB, 400 - C00 hex (Note 7) 2 5 µs

Digital Feedthrough

0.5 nV•s

Major Code Transition Glitch Impulse

Between codes 2047 and 2048 4 nV

•s

From V

REF

660

Output Noise (0.1Hz to 50MHz)

Using internal reference 720

µV

P-P

From V

REF

260

Output Noise (0.1Hz to 500kHz)

Using internal reference 320

µV

P-P

DAC-to-DAC Transition Crosstalk

0.5 nV

•s

INTERNAL REFERENCE

2.50

REF1 Output Voltage

REF1 Temperature Coefficient

ppm/°C

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049)

0.39

REF1 Short-Circuit Current

REF

= 4.096V (MAX1040/MAX1042/

MAX1046/MAX1048)

0.63

EXTERNAL REFERENCE INPUT

REF1 Input Voltage Range V

REF1

REF modes 01, 10, and 11 (Note 4) 0.7

REF1 Input Impedance R

REF1

70 100 130 kΩ

DIGITAL INTERFACE

DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)

= 2.7V to 5.25V 2.4

Input-Voltage High V

= 3.6V to 5.25V 2.0

= 2.7V to 3.6V 0.8

= 3V to 3.6V 0.6

Input-Voltage Low V

= 2.7V to 3V 0.5

Input Leakage Current I

0.01 ±10 µA

From power-down mode, AVDD = 2.7V

Code 0, all digital inputs from 0 to DV

MAX1041/MAX1043/MAX1047/MAX1049 2.482 MAX1040/MAX1042/MAX1046/MAX1048 4.066 4.096 4.126

REF

2.518

±30

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

Input Capacitance C

15 pF

DIGITAL OUTPUT (DOUT) (Note 14)

Output-Voltage Low V

SINK

= 2mA 0.4 V

Output-Voltage High V

OHISOURCE

= 2mA

0.5

Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C

OUT

15 pF

DIGITAL OUTPUT (EOC) (Note 14)

Output-Voltage Low V

SINK

= 2mA 0.4 V

Output-Voltage High V

OHISOURCE

= 2mA

0.5

Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C

OUT

15 pF

DIGITAL OUTPUTS (GPIO_) (Note 14)

SINK

= 2mA 0.4

GPIOC_ Output-Voltage Low

SINK

= 4mA 0.8

GPIOC_ Output-Voltage High I

SOURCE

= 2mA

0.5

GPIOA_ Output-Voltage Low I

SINK

= 15mA 0.8 V

GPIOA_ Output-Voltage High I

SOURCE

= 15mA

0.8

Tri-State Leakage Current ±10 µA Tri-State Output Capacitance C

OUT

15 pF

POWER REQUIREMENTS (Note 15)

Digital Positive-Supply Voltage DV

2.7

Idle, all blocks shut down 0.2 4 µA

Digital Positive-Supply Current DI

Only ADC on, external reference 1 mA

2.7 3.6

Analog Positive-Supply Voltage

4.75 5.25

Idle, all blocks shut down 0.2 2 µA

2.8 4.2

Only ADC on,

2.6

Analog Positive-Supply Current

IDD

1.5 4.0

AVDD = 2.7V (MAX1041/MAX1043/ MAX1047/MAX1049)

-77

REF1 Positive-Supply Rejection

PSRR

D D

= 4.75V ( M AX 1040/M AX 1042/

M AX 1046/M AX 1048)

-80

MAX1041/MAX1043/MAX1047/MAX1049 MAX1040/MAX1042/MAX1046/MAX1048

= 300ksps

external reference All DACs on, no load, internal reference

SAMPLE

= 100ksps

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

±0.1

DAC Positive-Supply Rejection PSRD

Output code =

M AX 1042/M AX 1046/M AX 1048)

±0.1

ADC Positive-Supply Rejection PSRA

Fullscale input

M AX 1042/M AX 1046/M AX 1048)

TIMING CHARACTERISTICS (Figures 6–13)

SCLK Clock Period t

40 ns

SCLK Pulse-Width High t

40/60 duty cycle 16 ns

SCLK Pulse-Width Low t

60/40 duty cycle 16 ns

GPIO Output Rise/Fall After CS Rise

GOD

LOAD

= 20pF 100 ns

GPIO Input Setup Before CS Fall

GSU

0ns

LDAC Pulse Width

20 ns

LOAD

= 20pF, SLOW = 0 1.8 12.0

SCLK Fall to DOUT Transition (Note 16)

DOT

LOAD

= 20pF, SLOW = 1 10 40

LOAD

= 20pF, SLOW = 0 1.8 12.0

SCLK Rise to DOUT Transition (Notes 16, 17)

DOT

LOAD

= 20pF, SLOW = 1 10 40

CS Fall to SCLK Fall Setup Time

CSS

10 ns

S C LK Fal l to CS Ri se S etup Ti m et

CSH

0ns

DIN to SCLK Fall Setup Time t

10 ns

DIN to SCLK Fall Hold Time t

0ns

CS Pulse-Width High

50 ns

CS Rise to DOUT Disable t

DOD

LOAD

= 20pF 25 ns

CS Fall to DOUT Enable t

DOE

LOAD

= 20pF 1.5 25.0 ns

EOC Fall to CS Fall t

RDS

30 ns

CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference on

CKSEL = 01 (temp sense) or CKSEL = 10 (temp sense), internal reference initially off

120

CKSEL = 01 (voltage conversion) 8 CKSEL = 10 (voltage conversion),

internal reference on

CS or CNVST Rise to EOC Fall t

DOV

CKSEL = 10 (voltage conversion), internal reference initially off

µs

AVDD = 2.7V to 3.6V (MAX1041/ MAX1043/MAX1047/MAX1049)

= 4.75V to 5.25V ( M AX 1040/

FFFhex

D D

AVDD = 2.7V to 3.6V (MAX1041/ MAX1043/MAX1047/MAX1049)

= 4.75V to 5.25V ( M AX 1040/

D D

±0.06 ±0.5

LDACPWL

CSPWH

±0.5

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

8 _______________________________________________________________________________________

Note 1: Tested at DVDD= AVDD= 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), DVDD= AVDD= 5.25V (MAX1040/MAX1042/

MAX1046/MAX1048).

Note 2: Offset nulled. Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the

clock period.

Note 4: See Table 5 for reference-mode details. Note 5: Not production tested. Guaranteed by design. Note 6: See the ADC/DAC References section. Note 7: Fast automated test, excludes self-heating effects. Note 8: Specified over the -40°C to +85°C temperature range. Note 9: REFSEL[1:0] = 00 or when DACs are not powered up. Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981. Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load. Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode. Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ. Note 14: Only one digital output (either DOUT,

EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.

Note 15: All digital inputs at either DV

or DGND. DVDDshould not exceed AVDD.

Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit. Note 17: Clock mode 11 only.

SHUTDOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc01

SUPPLY VOLTAGE (V)

SHUTDOWN CURRENT (µA)

5.155.054.954.85

0.05

0.10

0.15

0.20

0.25

0.30

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

SHUTDOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc02

SUPPLY VOLTAGE (V)

SHUTDOWN CURRENT (µA)

3.33.0

0.12

0.14

0.16

0.18

0.20

0.10

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX1040 toc03

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

603510-15

0.1

0.2

0.3

0.4

0.5

0.6

-40 85

Typical Operating Characteristics

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= 2.7V to 3.6V (MAX1041/MAX1043/MAX1047/MAX1049), external reference V

REF

= 2.5V (MAX1041/MAX1043/

MAX1047/MAX1049), AV

= DVDD= 4.75V to 5.25V (MAX1040/MAX1042/MAX1046/MAX1048), external reference V

REF

= 4.096V

(MAX1040/MAX1042/MAX1046/MAX1048), f

SCLK

= 4.8MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical

values are at AV

= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), AVDD= DVDD= 5V (MAX1040/MAX1042/

MAX1046/MAX1048), T

= +25°C. Outputs are unloaded, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS MIN TYP

MAX

UNITS

CKSEL = 00, CKSEL = 01 (temp sense) 40 ns

CNVST Pulse Width t

CSW

CKSEL = 01 (voltage conversion) 1.4 µs

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

_______________________________________________________________________________________ 9

INTERNAL OSCILLATOR FREQUENCY

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc04

SUPPLY VOLTAGE (V)

INTERNAL OSCILLATOR FREQUENCY (MHz)

5.155.054.954.85

4.1

4.2

4.3

4.4

4.5

4.0

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

INTERNAL OSCILLATOR FREQUENCY

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc05

SUPPLY VOLTAGE (V)

INTERNAL OSCILLATOR FREQUENCY (MHz)

3.33.0

4.65

4.70

4.75

4.80

4.85

4.90

4.60

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

INTERNAL OSCILLATOR FREQUENCY

vs. TEMPERATURE

MAX1040 toc06

TEMPERATURE (°C)

INTERNAL OSCILLATOR FREQUENCY (MHz)

603510-15

4.0

4.2

4.4

4.6

4.8

5.0

3.8

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

MAX1041/MAX1043/MAX1047/MAX1049

ADC INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc07

OUTPUT CODE

INTEGRAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 0 1024

MAX1040/MAX1042/MAX1046/MAX1048

ADC INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc08

OUTPUT CODE

INTEGRAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 0 1024

MAX1041/MAX1043/MAX1047/MAX1049

ADC DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc09

OUTPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 0 1024

MAX1040/MAX1042/MAX1046/MAX1048

ADC DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc10

OUTPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 01024

MAX1041/MAX1043/MAX1047/MAX1049

ADC OFFSET ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc11

SUPPLY VOLTAGE (V)

OFFSET ERROR (LSB)

5.155.054.954.85

-0.7

-0.6

-0.5

-0.4

-0.8

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

ADC OFFSET ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc10

SUPPLY VOLTAGE (V)

OFFSET ERROR (LSB)

3.33.0

-1.5

-1.0

-0.5

-2.0

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

10 ______________________________________________________________________________________

ADC OFFSET ERROR

vs. TEMPERATURE

MAX1040 toc13

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-1.5

-1.0

-0.5

-2.0

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

MAX1041/MAX1043/MAX1047/MAX1049

ADC GAIN ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc14

SUPPLY VOLTAGE (V)

GAIN ERROR (LSB)

5.155.054.954.85

-0.050

-0.025

0.025

0.050

-0.075

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

ADC GAIN ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc15

SUPPLY VOLTAGE (V)

GAIN ERROR (LSB)

3.33.0

0.25

0.30

0.35

0.40

0.45

0.50

0.20

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

ADC GAIN ERROR

vs. TEMPERATURE

MAX1040 toc16

TEMPERATURE (°C)

GAIN ERROR (LSB)

603510-15

-0.25

0.25

0.50

0.75

1.00

-0.50

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

MAX1041/MAX1043/MAX1047/MAX1049

ADC EXTERNAL REFERENCE

INPUT CURRENT vs. SAMPLING RATE

MAX1040 toc17

SAMPLING RATE (ksps)

ADC EXTERNAL REFERENCE INPUT CURRENT (µA)

25020015010050

0300

MAX1040/MAX1042/MAX1046/MAX1048

MAX1041/MAX1043/MAX1047/MAX1049

ANALOG SUPPLY CURRENT

vs. SAMPLING RATE

MAX1040 toc18

SAMPLING RATE (ksps)

ANALOG SUPPLY CURRENT (mA)

25020015010050

0.5

1.0

1.5

2.0

2.5

3.0

0300

MAX1040/MAX1042/MAX1046/MAX1048

MAX1041/MAX1043/MAX1047/MAX1049

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc19

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

5.155.054.954.85

2.4

2.5

2.6

2.7

2.8

2.2

2.3

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAx1040 toc20

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

3.33.0

2.1

2.2

2.3

2.4

2.5

2.6

1.9

2.0

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1040 toc21

TEMPERATURE (°C)

ANALOG SUPPLY CURRENT (mA)

603510-15

2.4

2.5

2.6

2.7

2.3

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 11

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1040 toc22

TEMPERATURE (°C)

ANALOG SUPPLY CURRENT (mA)

603510-15

2.13

2.12

2.11

2.14

2.15

2.16

2.10

-40 85

MAX1041/MAX1043/MAX1047/MAX1049

DAC INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc23

OUTPUT CODE

INTEGRAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 0 1024

MAX1040/MAX1042/MAX1046/MAX1048

DAC INTEGRAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc24

OUTPUT CODE

INTEGRAL NONLINEARITY (LSB)

768512256

-0.2

-0.1

0.1

0.2

0.3

-0.3 0 1024

MAX1041/MAX1043/MAX1047/MAX1049

DAC DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc25

OUTPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

1035103210291026

-0.05

0.05

0.10

-0.10 1023 1038

MAX1040/MAX1042/MAX1046/MAX1048

DAC DIFFERENTIAL NONLINEARITY

vs. OUTPUT CODE

MAX1040 toc26

OUTPUT CODE

DIFFERENTIAL NONLINEARITY (LSB)

1035103210291026

-0.05

0.05

0.10

-0.10 1023 1038

MAX1041/MAX1043/MAX1047/MAX1049

DAC FULL-SCALE ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc27

SUPPLY VOLTAGE (V)

DAC FULL-SCALE ERROR (LSB)

5.155.054.954.85

0.01

0.02

0.03

0.04

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

DAC FULL-SCALE ERROR

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc28

SUPPLY VOLTAGE (V)

DAC FULL-SCALE ERROR (LSB)

3.33.0

-0.65

-0.60

-0.55

-0.50

-0.70

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

DAC FULL-SCALE ERROR

vs. TEMPERATURE

MAX1040 toc29

TEMPERATURE (°C)

DAC FULL-SCALE ERROR (LSB)

603510-15

0.5

1.0

1.5

2.0

-1.0

-0.5

-40 85

INTERNAL REFERENCE

EXTERNAL REFERENCE = 4.096V

MAX1040/MAX1042/MAX1046/MAX1048

DAC FULL-SCALE ERROR

vs. TEMPERATURE

MAX1040 toc30

TEMPERATURE (°C)

DAC FULL-SCALE ERROR (LSB)

603510-15

-1.50

-1.25

-1.00

-0.75

-0.50

-0.25

-2.00

-1.75

-40 85

INTERNAL REFERENCE

EXTERNAL REFERENCE = 2.500V

MAX1041/MAX1043/MAX1047/MAX1049

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

12 ______________________________________________________________________________________

DAC FULL-SCALE ERROR

vs. REFERENCE VOLTAGE

MAX1040 toc31

REFERENCE VOLTAGE (V)

DAC FULL-SCALE ERROR (LSB)

431 2

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00 05

MAX1040/MAX1042/MAX1046/MAX1048

DAC FULL-SCALE ERROR

vs. REFERENCE VOLTAGE

MAX1040 toc32

REFERENCE VOLTAGE (V)

DAC FULL-SCALE ERROR (LSB)

2.0 2.51.50.5 1.0

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0 3.0

MAX1041/MAX1043/MAX1047/MAX1049

DAC FULL-SCALE ERROR

vs. LOAD CURRENT

MAX1040 toc33

LOAD CURRENT (mA)

DAC FULL-SCALE ERROR (LSB)

252015105

-2

-3

-1

-4 030

MAX1040/MAX1042/MAX1046/MAX1048

DAC FULL-SCALE ERROR

vs. LOAD CURRENT

MAX1040 toc34

LOAD CURRENT (mA)

DAC FULL-SCALE ERROR (LSB)

2.52.01.51.00.5

-2

-1

-4

-3

03.0

MAX1041/MAX1043/MAX1047/MAX1049

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1040 toc35

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

603510-15

4.09

4.10

4.11

4.12

4.08

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1040 toc36

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

603510-15

2.49

2.50

2.51

2.52

2.48

-40 85

MAX1041/MAX1043/MAX1047/MAX1049

ADC REFERENCE SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc37

SUPPLY VOLTAGE (V)

ADC REFERENCE SUPPLY CURRENT (µA)

5.155.054.954.85

42.2

42.4

42.6

42.8

43.0

42.0

4.75 5.25

MAX1040/MAX1042/MAX1046/MAX1048

ADC REFERENCE SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

MAX1040 toc38

SUPPLY VOLTAGE (V)

ADC REFERENCE SUPPLY CURRENT (µA)

3.33.0

25.5

25.6

25.7

25.8

25.4

2.7 3.6

MAX1041/MAX1043/MAX1047/MAX1049

ADC REFERENCE SUPPLY CURRENT

vs. TEMPERATURE

MAX1040 toc39

TEMPERATURE (°C)

ADC REFERENCE SUPPLY CURRENT (µA)

603510-15

-40 85

MAX1040/MAX1042/MAX1046/MAX1048

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 13

ADC REFERENCE SUPPLY CURRENT

vs. TEMPERATURE

MAX1040 toc40

TEMPERATURE (°C)

ADC REFERENCE SUPPLY CURRENT (µA)

6035-15 10

25.25

25.50

25.75

26.00

26.25

26.50

26.75

27.00

25.00

-40 85

MAX1041/MAX1043/MAX1047/MAX1049

ADC FFT PLOT

MAX1040 toc41

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

15010050

-140

-120

-100

-80

-60

-40

-20

-160 0200

SAMPLE

= 32.768kHz

ANALOG_)N

= 10.080kHz

CLK

= 5.24288MHz SINAD = 61.21dBc SNR = 61.21dBc THD = 73.32dBc SFDR = 81.25dBc

ADC IMD PLOT

MAX1040 toc42

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

15010050

-140

-120

-100

-80

-60

-40

-20

-160 0200

CLK

= 5.24288MHz

IN1

= 9.0kHz

IN2

= 11.0kHz

= -6dBFS

IMD = 78.0dBc

ADC CROSSTALK PLOT

MAX1040 toc43

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

15010050

-140

-120

-100

-80

-60

-40

-20

-160 0200

CLK

= 5.24288MHz

IN1

= 10.080kHz

IN2

= 8.0801kHz SNR = 61.11dBc THD = 73.32dBc ENOB = 9.86 BITS SFDR = 86.34dBc

DAC OUTPUT LOAD REGULATION

vs. OUTPUT CURRENT

MAX1040 toc44

OUTPUT CURRENT (mA)

DAC OUTPUT VOLTAGE (V)

60300

2.01

2.02

2.03

2.04

2.05

2.06

2.07

2.08

2.00

-30 90

DAC OUTPUT = MIDSCALE

SINKING

SOURCING

MAX1040/MAX1042/MAX1046/MAX1048

DAC OUTPUT LOAD REGULATION

vs. OUTPUT CURRENT

MAX1040 toc45

OUTPUT CURRENT (mA)

DAC OUTPUT VOLTAGE (V)

20100-20

-10

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.21

-30 30

DAC OUTPUT = MIDSCALE

SINKING

SOURCING

MAX1041/MAX1043/MAX1047/MAX1049

GPIO OUTPUT VOLTAGE

vs. SOURCE CURRENT

MAX1040 toc46

SOURCE CURRENT (mA)

GPIO OUTPUT VOLTAGE (V)

80604020

0100

GPIOA0–A3 OUTPUTS

GPIOB0–B3,

C0–C3 OUTPUTS

MAX1040/MAX1042/ MAX1046/MAX1048

GPIO OUTPUT VOLTAGE

vs. SOURCE CURRENT

MAX1040 toc47

SOURCE CURRENT (mA)

GPIO OUTPUT VOLTAGE (V)

80604020

0.5

1.0

1.5

2.0

2.5

3.0

0 100

GPIOA0–A3 OUTPUTS

GPIOB0–B3, C0–C3

OUTPUTS

MAX1041/MAX1043/MAX1047/MAX1049

GPIO OUTPUT VOLTAGE

vs. SINK CURRENT

MAX1040 toc48

SINK CURRENT (mA)

GPIO OUTPUT VOLTAGE (mV)

80604020

300

600

900

1200

1500

0100

GPIOA0–A3 OUTPUTS

GPIOB0–B3, C0–C3

OUTPUTS

MAX1040/MAX1042/MAX1046/MAX1048

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

14 ______________________________________________________________________________________

GPIO OUTPUT VOLTAGE

vs. SINK CURRENT

MAX1040 toc49

SINK CURRENT (mA)

GPIO OUTPUT VOLTAGE (mV)

40 50302010

300

600

900

1200

1500

060

GPIOA0–A3 OUTPUTS

GPIOB0–B3, C0–C3

OUTPUTS

MAX1041/MAX1043/MAX1047/MAX1049

TEMPERATURE SENSOR ERROR

vs. TEMPERATURE

MAX1040 toc50

TEMPERATURE (°C)

TEMPERATURE SENSOR ERROR (°C)

6035-15 10

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

-40 85

DAC-TO-DAC CROSSTALK

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc51

100µs

OUTA

1V/div

OUTB

10mV/div AC-COUPLED

MAX1041/MAX1043/MAX1047/MAX1049

DAC-TO-DAC CROSSTALK

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc52

100µs

OUTA

2V/div

OUTB

10mV/div AC-COUPLED

MAX1040/MAX1042/MAX1046/MAX1048

DYNAMIC RESPONSE RISE TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc53

1µs

OUT

1V/div

CS 1V/div

MAX1041/MAX1043/MAX1047/MAX1049

DYNAMIC RESPONSE RISE TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc54

1µs

OUT

2V/div

CS 2V/div

MAX1040/MAX1042/MAX1046/MAX1048

DYNAMIC RESPONSE FALL TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc55

1µs

OUT

1V/div

CS 1V/div

MAX1041/MAX1043/MAX1047/MAX1049

DYNAMIC RESPONSE FALL TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc56

1µs

OUT

2V/div

CS 2V/div

MAX1040/MAX1042/MAX1046/MAX1048

MAJOR CARRY TRANSITION

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc57

1µs

OUT

10mV/div AC-COUPLED

CS 1V/div

MAX1041/MAX1043/MAX1047/MAX1049

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 15

MAJOR CARRY TRANSITION

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc58

1µs

OUT

20mV/div AC-COUPLED

CS 2V/div

MAX1040/MAX1042/MAX1046/MAX1048

DAC DIGITAL FEEDTHROUGH R

LOAD

= 10kΩ,

LOAD

= 100pF, CS = HIGH, DIN = LOW

MAX1040 toc59

200ns

OUT

100mV/div AC-COUPLED

SCLK 1V/div

MAX1041/MAX1043/MAX1047/MAX1049

DAC DIGITAL FEEDTHROUGH R

LOAD

= 10kΩ,

LOAD

= 100pF, CS = HIGH, DIN = LOW

MAX1040 toc60

200ns

OUT

100mV/div AC-COUPLED

SCLK 2V/div

MAX1040/MAX1042/MAX1046/MAX1048

NEGATIVE FULL-SCALE SETTLING TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc61

1µs

OUT

1V/div

MAX1041/MAX1043/MAX1047/MAX1049

LDAC

1V/div

NEGATIVE FULL-SCALE SETTLING TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc62

2µs

OUT_

2V/div

MAX1040/MAX1042/MAX1046/MAX1048

LDAC

2V/div

POSITIVE FULL-SCALE SETTLING TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc63

1µs

OUT_

1V/div

MAX1041/MAX1043/MAX1047/MAX1049

LDAC

1V/div

POSITIVE FULL-SCALE SETTLING TIME

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc64

1µs

OUT_

2V/div

MAX1040/MAX1042/MAX1046/MAX1048

LDAC

2V/div

ADC REFERENCE FEEDTHROUGH

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc65

200µs

DAC-OUT

10mV/div AC-COUPLED

REF2

1V/div

ADC REFERENCE SWITCHING

MAX1041/MAX1043/MAX1047/MAX1049

ADC REFERENCE FEEDTHROUGH

LOAD

= 10kΩ, C

LOAD

= 100pF

MAX1040 toc66

200µs

DAC-OUT

2mV/div AC-COUPLED

REF2

2V/div

ADC REFERENCE SWITCHING

MAX1040/MAX1042/MAX1046/MAX1048

Typical Operating Characteristics (continued)

(AVDD= DVDD= 3V (MAX1041/MAX1043/MAX1047/MAX1049), external V

REF

= 2.5V (MAX1041/MAX1043/MAX1047/MAX1049),

AVDD= DVDD= 5V (MAX1040/MAX1042/MAX1046/MAX1048), external V

REF

= 4.096V (MAX1040/MAX1042/MAX1046/MAX1048),

CLK

= 4.8MHz (50% duty cycle), f

SAMPLE

= 300ksps, C

LOAD

= 50pF, 0.1µF capacitor at REF, TA= +25°C, unless otherwise noted.)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

16 ______________________________________________________________________________________

Pin Description

MAX1040

MAX1042

MAX1046

MAX1048

NAME FUNCTION

1, 2, 15–19,

23, 24, 25,

32, 33

15–19, 23,

32, 33

1, 2, 15–19,

23, 24, 25,

31–34

15–19, 23,

31–34

N.C. No Connection. Not internally connected.

3333EOC

Active-Low End-of-Conversion Output. Data is valid after the falling edge of EOC.

4444DV

Digital Positive Power Input. Bypass DVDD to DGND with a

0.1µF capacitor.

5 5 5 5 DGND Digital Ground. Connect DGND to AGND.

6 6 6 6 DOUT

Serial Data Output. Data is clocked out on the falling edge of the SCLK clock in clock modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock in clock mode 11. High impedance when CS is high.

7 7 7 7 SCLK

Serial Clock Input. Clocks data in and out of the serial interface. (Duty cycle must be 40% to 60%.) See Table 4 for details on programming the clock mode.

8888DIN

Serial Data Input. DIN data is latched into the serial interface on the falling edge of SCLK.

9–12 9–12 9–12 9–12

OUT0–

OUT3

DAC Outputs

13 13 13 13 AV

Positive Analog Power Input. Bypass AVDD to AGND with a

0.1µF capacitor.

14 14 14 14 AGND Analog Ground

20 20 20 20 LDAC

Active-Low Load DAC. LDAC is an asynchronous active-low input that updates the DAC outputs. Drive LDAC low to make the DAC registers transparent.

21 21 21 21 CS

Active-Low Chip-Select Input. When CS is low, the serial interface is enabled. When CS is high, DOUT is high impedance.

MAX1041

MAX1043

MAX1047

MAX1049

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 17

Pin Description (continued)

MAX1040

MAX1041

NAME FUNCTION

22 22 22 22

Reset Select. Selects DAC wake-up mode. Set RES_SEL low to wake up the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to wake up the DAC outputs with a 100kΩ resistor to V

REF

. Set RES_SEL high to power up the DAC input register to FFFh. Set RES_SEL low to power up the DAC input register to 000h.

26 26 26 26 REF1

Reference 1 Input. Reference voltage. Leave unconnected to use the internal reference (2.5V for the MAX1041/MAX1043/MAX1047/MAX1049 or 4.096V for the MAX1040/MAX1042/MAX1046/MAX1048). REF1 is the positive reference in ADC external differential mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section.

27–31, 34

——

Analog Inputs

35 35 — —

Refer ence 2 Inp ut/Anal og Inp ut C hannel 6. S ee Tab l e 5 for d etai l s on p r og r am m i ng the setup r eg i ster . RE F2 i s the neg ati ve r efer ence i n the AD C exter nal d i ffer enti al r efer ence m od e.

36 36 — —

CNVST/

AIN7

Active-Low Conversion Start Input/Analog Input 7. See Table 5 for details on programming the setup register.

— 1, 2 — 1, 2

GPIOA0,

General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and source 15mA.

— 24, 25 — 24, 25

GPIOC0,

General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA and source 2mA.

— — 27–30 27–30

Analog Inputs

— — 35 35 REF2

Reference 2 Input. See Table 5 for details on programming the setup register. RE F2 i s the neg ati ve r efer ence i n the AD C exter nal d i ffer enti al r efer ence m od e.

— — 36 36 CNVST

Active-Low Conversion Start Input. See Table 5 details on programming the setup register.

————EP

Exposed Paddle. Must be externally connected to AGND. Do not use as a ground connect.

MAX1042 MAX1043

27–31, 34

MAX1046 MAX1047

MAX1048 MAX1049

RES_SEL

AIN0–AIN5

REF2/AIN6

GPIOA1

GPIOC1

AIN0–AIN3

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

18 ______________________________________________________________________________________

Detailed Description

The MAX1040–MAX1043/MAX1046–MAX1049 integrate a multichannel 10-bit ADC and a quad 10-bit DAC in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI/QSPI-/MICROWIRE-compatible serial interface. The ADC is available in a 4 or an 8 input-channel version. The four DAC outputs settle within 2.0µs, and the ADC has a 300ksps conversion rate.

All devices include an internal reference (2.5V or

4.096V) providing a well-regulated, low-noise reference for both the ADC and DAC. Programmable reference modes for the ADC and DAC allow the use of an internal reference, an external reference, or a combination of both. Features such as an internal ±1°C accurate temperature sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and AutoShutdown allow users to minimize both power consumption and processor requirements. The low glitch energy (4nV•s) and low digital feedthrough (0.5nV•s) of the integrated quad DACs make these devices ideal for digital control of fast-response closed-loop systems.

The devices are guaranteed to operate with a supply voltage from +2.7V to +3.6V (MAX1041/MAX1043/ MAX1047/MAX1049) and from +4.5V to +5.5V (MAX1040/MAX1042/MAX1046/MAX1048). These devices consume 2.5mA at 300ksps throughput, only

0.22µA at 1ksps throughput, and under 0.2µA in the shutdown mode. The MAX1042/MAX1043/MAX1048/ MAX1049 offer four GPIOs that can be configured as inputs or outputs.

Figure 1 shows the MAX1042/MAX1043 functional diagram. The MAX1042/MAX1043/MAX1048/MAX1049 only include the GPIO A0, A1, GPIO C0, C1 blocks. The MAX1040/MAX1041/MAX1046/MAX1047 exclude the GPIOs. The output-conditioning circuitry takes the internal parallel data bus and converts it to a serial data format at DOUT, with the appropriate wake-up timing. The arithmetic logic unit (ALU) performs the averaging function.

SPI-Compatible Serial Interface

The MAX1040–MAX1043/MAX1046–MAX1049 feature a serial interface that is compatible with SPI and MICROWIRE devices. For SPI, ensure the SPI bus master (typically a microcontroller (µC)) runs in master mode so that it generates the serial clock signal. Select the SCLK frequency of 25MHz or less, and set the clock polarity (CPOL) and phase (CPHA) in the µC con-

trol registers to the same value. The MAX1040– MAX1043/MAX1046–MAX1049 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch any input data at DIN on the falling edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK in clock modes 00, 01, and 10. Output data at DOUT is updated on the rising edge of SCLK in clock mode 11. See Figures 6–11. Bipolar true-differential results and temperature-sensor results are available in two’s complement format, while all other results are in binary.

A high-to-low transition on CS initiates the data-input operation. Serial communications to the ADC always begin with an 8-bit command byte (MSB first) loaded from DIN. The command byte and the subsequent data bytes are clocked from DIN into the serial interface on the falling edge of SCLK. The serial-interface and fastinterface circuitry is common to the ADC, DAC, and GPIO sections. The content of the command byte determines whether the SPI port should expect 8, 16, or 24 bits and whether the data is intended for the ADC, DAC, or GPIOs (if applicable). See Table 1. Driving CS high resets the serial interface.

The conversion register controls ADC channel selection, ADC scan mode, and temperature-measurement requests. See Table 4 for information on writing to the conversion register. The setup register controls the clock mode, reference, and unipolar/bipolar ADC configuration. Use a second byte, following the first, to write to the unipolar-mode or bipolar-mode registers. See Table 5 for details of the setup register and see Tables 6, 7, and 8 for setting the unipolar- and bipolarmode registers. Hold CS low between the command byte and the second and third byte. The ADC averaging register is specific to the ADC. See Table 9 to address that register. Table 11 shows the details of the reset register.

Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of this command byte are don’t-care bits. Write another 2 bytes (holding CS low) to the DAC interface register following the command byte to select the appropriate DAC and the data to be written to it. See the DAC Serial Interface section and Tables 10, 17, and 18.

Write to the GPIOs (if applicable) by issuing a command byte to the appropriate register. Writing to the MAX1042/MAX1043/MAX1048/MAX1049 GPIOs requires 1 additional byte following the command byte.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 19

DOUT

EOC

ADDRESS

AIN0

AIN5

REF2/

AIN6

CNVST/

AIN7

REF1

DIN

SCLK

GPIOA0,

GPIOA1

GPIOC0,

GPIOC1

SPI

PORT

GPIO

CONTROL

INPUT

DAC

OUTPUT

CONDITIONING

10-BIT

DAC

BUFFER

USER-PROGRAMMABLE

I/O

OSCILLATOR

OUT0

OUT1

OUT2

MAX1042 MAX1043

10-BIT

SAR ADC

LOGIC

CONTROL

TEMPERATURE

SENSOR

FIFO AND

ALU

LDAC

RES_SEL

AGND

T/H

REF2

INPUT

DAC

OUTPUT

CONDITIONING

10-BIT

DAC

BUFFER

INPUT

DAC

OUTPUT

CONDITIONING

10-BIT

DAC

BUFFER

INPUT

DAC

OUTPUT

CONDITIONING

10-BIT

DAC

BUFFER

INTERNAL

REFERENCE

OUT3

DGND

CNVST

Figure 1. MAX1042/MAX1043 Functional Diagram

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

20 ______________________________________________________________________________________

Table 1. Command Byte (MSB First)

Conversion* 1 X

SCAN1 SCAN0 TEMP

Setup 0 1

DIFFSEL0

ADC Averaging 0 0 1 AVGON NAVG1 NAVG0

NSCAN0

DAC Select 0 0 0 1 XXXX Reset 0 0 0 0 1 RESET SLOW FBGON GPIO Configure** 0 0 000011 GPIO Write** 0 0 000010 GPIO Read** 0 0 000001 No Operation 0 0 000000

X = Don’t care. *CHESL2 bit is only valid on the MAX1040–MAX1043. Set CHSEL2 to 0 on the MAX1046–MAX1049. **Only applicable on the MAX1042/MAX1043/MAX1048/MAX1049.

See Tables 12–16 for details on GPIO configuration, writes, and reads. See the GPIO Command section. Command bytes written to the GPIOs on devices without GPIOs are ignored.

Power-Up Default State

The MAX1040–MAX1043/MAX1046–MAX1049 power up with all blocks in shutdown (including the reference). All registers power up in state 00000000, except for the setup register and the DAC input register. The setup register powers up at 0010 1000 with CKSEL1 = 1 and REFSEL1 = 1. The DAC input register powers up to FFFh when RES_SEL is high, and it powers up to 000h when RES_SEL is low.

10-Bit ADC

The MAX1040–MAX1043/MAX1046–MAX1049 ADCs use a fully differential successive-approximation register (SAR) conversion technique and on-chip track-andhold (T/H) circuitry to convert temperature and voltage signals into 10-bit digital results. The analog inputs accept both single-ended and differential input signals. Single-ended signals are converted using a unipolar transfer function, and differential signals are converted using a selectable bipolar or unipolar transfer function. See the ADC Transfer Functions section for more data.

ADC Clock Modes

When addressing the setup, register bits 5 and 4 of the command byte (CKSEL1 and CKSEL0, respectively) control the ADC clock modes. See Table 5. Choose between four different clock modes for various ways to start a conversion and determine whether the acquisitions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conver-

sion start and use it to request internally timed conversions, without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, thereby controlling the sampling speed without tying up the serial bus. Request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode,

10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 6–9 for timing specifications on how to begin a conversion.

These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the last requested operation and is waiting for the next command byte. EOC goes high when CS or CNVST go low. EOC is always high in clock mode 11.

Single-Ended or Differential Conversions

The MAX1040–MAX1043/MAX1046–MAX1049 use a fully differential ADC for all conversions. When a pair of inputs are connected as a differential pair, each input is connected to the ADC. When configured in singleended mode, the positive input is the single-ended channel and the negative input is referred to AGND. See Figure 2.

In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7. AIN0–AIN3 are available on all devices. AIN0–AIN7 are available on the MAX1040–MAX1043. See Tables 5–8 for more details on configuring the

CHSEL2 CHSEL1 CHSEL0 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1

NSCAN1

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 21

inputs. For the inputs that are configurable as CNVST, REF2, and an analog input, only one function can be used at a time.

Unipolar or Bipolar Conversions

Address the unipolar- and bipolar-mode registers through the setup register (bits 1 and 0). See Table 5 for the setup register. See Figures 3 and 4 for the transferfunction graphs. Program a pair of analog inputs for differential operation by writing a one to the appropriate bit of the bipolar- or unipolar-mode register. Unipolar mode sets the differential input range from 0 to V

REF1.

A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±V

REF1

/2. The digital output code is binary in unipolar mode and two’s complement in bipolar mode.

In single-ended mode, the MAX1040–MAX1043/ MAX1046–MAX1049 always operate in unipolar mode. The analog inputs are internally referenced to AGND with a full-scale input range from 0 to the selected reference voltage.

Analog Input (T/H)

The equivalent circuit of Figure 2 shows the ADC input architecture of the MAX1040–MAX1043/MAX1046– MAX1049. In track mode, a positive input capacitor is connected to AIN0–AIN7 in single-ended mode and AIN0, AIN2, AIN4, and AIN6 in differential mode. A negative input capacitor is connected to AGND in single-ended mode or AIN1, AIN3, AIN5, and AIN7 in

differential mode. For external T/H timing, use clock mode 01. After the T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted. The input capacitance charging rate determines the time required for the T/H to acquire an input signal. If the input signal’s source impedance is high, the required acquisition time lengthens.

Any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by lengthening t

ACQ

(only in clock mode 01) or by placing a 1µF capacitor between the positive and negative analog inputs. The combination of the analog-input source impedance and the capacitance at the analog input creates an RC filter that limits the analog input bandwidth.

Input Bandwidth

The ADC’s input-tracking circuitry has a 1MHz smallsignal bandwidth, making it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest.

Analog-Input Protection

Internal electrostatic-discharge (ESD) protection diodes clamp all analog inputs to AVDDand AGND, allowing the inputs to swing from (AGND - 0.3V) to (AVDD+

0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed AV

by more than 50mV or be lower than AGND by 50mV. If an analog input voltage exceeds the supplies, limit the input current to 2mA.

Internal FIFO

The MAX1040–MAX1043/MAX1046–MAX1049 contain a first-in/first-out (FIFO) buffer that holds up to 16 ADC results plus one temperature result. The internal FIFO allows the ADC to process and store multiple internally clocked conversions and a temperature measurement without being serviced by the serial bus.

If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each result contains 2 bytes, with the MSB preceded by four leading zeros. After each falling edge of CS, the oldest available pair of bytes of data is available at DOUT, MSB first. When the FIFO is empty, DOUT is zero.

The first 2 bytes of data read out after a temperature measurement always contain the 10-bit temperature result, preceded by four leading zeros, MSB first. The

AIN0–AIN7

(SINGLE-ENDED),

AIN0, AIN2, AIN4, AIN6

(DIFFERENTIAL)

COMPARATOR

HOLD

ACQ

HOLD

ACQ

HOLD

/ 2

REF1

AGND

CIN+

CIN-

DAC

AGND

(SINGLE-ENDED),

AIN1, AIN3,

AIN5, AIN7

(DIFFERENTIAL)

Figure 2. Equivalent Input Circuit

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

22 ______________________________________________________________________________________

LSB is followed by 2 sub-bits. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement), at a resolution of 8 LSB per degree. See the Temperature Measurements section for details on converting the digital code to a temperature.

10-Bit DAC

In addition to the 10-bit ADC, the MAX1040–MAX1043/ MAX1046–MAX1049 also include four voltage-output, 10-bit, monotonic DACs with less than 1 LSB integral nonlinearity error and less than 0.5 LSB differential nonlinearity error. Each DAC has a 2µs settling time and ultra-low glitch energy (4nV•s). The 10-bit DAC code is unipolar binary with 1 LSB = V

REF

/ 1024.

DAC Digital Interface

Figure 1 shows the functional diagram of the MAX1042/ MAX1043. The shift register converts a serial 16-bit word to parallel data for each input register operating with a clock rate up to 25MHz. The SPI-compatible digital interface to the shift register consists of CS, SCLK, DIN, and DOUT. Serial data at DIN is loaded on the falling edge of SCLK. Pull CS low to begin a write sequence. Begin a write to the DAC by writing 0001XXXX as a command byte. The last 4 bits of the DAC select register are don’t-care bits. See Table 10. Write another 2 bytes to the DAC interface register following the command byte to select the appropriate DAC and the data to be written to it. See Tables 17 and 18.

The four double-buffered DACs include an input and a DAC register. The input registers are directly connected to the shift register and hold the result of the most recent write operation. The four 10-bit DAC registers hold the current output code for the respective DAC. Data can be transferred from the input registers to the DAC registers by pulling LDAC low or by writing the appropriate DAC command sequence at DIN. See Table 17. The outputs of the DACs are buffered through four rail-to-railop amps.

The MAX1040–MAX1043/MAX1046–MAX1049 DAC output-voltage range is based on the internal reference or an external reference. Write to the setup register (see Table 5) to program the reference. If using an external voltage reference, bypass REF1 with a 0.1µF capacitor to AGND. The MAX1041/MAX1043/MAX1047/

MAX1049 internal reference is 2.5V. The MAX1040/ MAX1042/MAX1046/MAX1048 internal reference is

4.096V. When using an external reference on any of these devices, the voltage range is 0.7V to AVDD.

DAC Transfer Function

See Table 2 for various analog outputs from the DAC.

DAC Power-On Wake-Up Modes

The state of the RES_SEL input determines the wake-up state of the DAC outputs. Connect RES_SEL to AVDDor AGND upon power-up to be sure the DAC outputs wake up to a known state. Connect RES_SEL to AGND to wake up all DAC outputs at 000h. While RES_SEL is low, the 100kΩ internal resistor pulls the DAC outputs to AGND and the output buffers are powered down. Connect RES_SEL to AVDDto wake up all DAC outputs at FFFh. While RES_SEL is high, the 100kΩ pullup resistor pulls the DAC outputs to V

REF1

and the output

buffers are powered down.

DAC Power-Up Modes

See Table 18 for a description of the DAC power-up and power-down modes.

GPIOs

In addition to the internal ADC and DAC, the MAX1042/MAX1043/MAX1048/MAX1049 also provide four GPIO channels, GPIOA0, GPIOA1, GPIOC0, and GPIOC1.

DAC CONTENTS

MSB

ANALOG OUTPUT

0000

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

Table 2. DAC Output Code Table

LSB

1111 1111

0000 0001

0000 0000

0111 0111

0000 0001

⎛

⎞

REF

1023

REF

⎜

1024

⎝

⎛

1023

REF

⎜

1024

⎝

⎛

⎞ ⎟

⎠

⎜

1024

⎜

1024

511

⎛ ⎜

⎝

512

⎜

1024 2

⎝

REF

⎟ ⎠

⎞ ⎟

⎠

REF

⎟

⎞ ⎟

⎠

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 23

Read and write to the GPIOs as detailed in Table 1 and Tables 12–16. Also, see the GPIO Command section. See Figures 11 and 12 for GPIO timing.

Write to the GPIOs by writing a command byte to the GPIO command register. Write a single data byte to the MAX1042/MAX1043/MAX1048/MAX1049 following the command byte.

The GPIOs can sink and source current. The MAX1042/MAX1043/MAX1048/MAX1049 GPIOA0 and GPIOA1 can sink and source up to 15mA. GPIOC0 and GPIOC1 can sink 4mA and source 2mA. See Table 3.

Clock Modes

Internal Clock

The MAX1040–MAX1043/MAX1046–MAX1049 can operate from an internal oscillator. The internal oscillator is active in clock modes 00, 01, and 10. Figures 6, 7, and 8 show how to start an ADC conversion in the three internally timed conversion modes.

Read out the data at clock speeds up to 25MHz through the SPI interface.

External Clock

Set CKSEL1 and CKSEL0 in the setup register to 11 to set up the interface for external clock mode 11. See Table 5. Pulse SCLK at speeds from 0.1MHz to

4.8MHz. Write to SCLK with a 40% to 60% duty cycle. The SCLK frequency controls the conversion timing. See Figure 9 for clock mode 11 timing. See the ADC Conversions in Clock Mode 11 section.

ADC/DAC References

Address the reference through the setup register, bits 3 and 2. See Table 5. Following a wake-up delay, set REFSEL[1:0] = 00 to program both the ADC and DAC for internal reference use. Set REFSEL[1:0] = 10 to program the ADC for internal reference. Set REFSEL[1:0] = 10 to program the DAC for external reference, REF1. When using REF1 or REF2/AIN_ in external reference mode, connect a 0.1µF capacitor to AGND. Set REFSEL[1:0] = 01 to program the ADC and DAC for

external reference mode. The DAC uses REF1 as its external reference, while the ADC uses REF2 as its external reference. Set REFSEL[1:0] = 11 to program the ADC for external differential-reference mode. REF1 is the positive reference and REF2 is the negative reference in the ADC external differential mode.

When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as an analog input channel. When REFSEL[1:0] = 01 or 11, REF2/AIN_ functions as the device’s negative reference.

Temperature Measurements

Issue a command byte setting bit 0 of the conversion register to one to take a temperature measurement. See Table 4. The MAX1040–MAX1043/MAX1046– MAX1049 perform temperature measurements with an internal diode-connected transistor. The diode bias current changes from 68µA to 4µA to produce a temperature-dependent bias voltage difference. The second conversion result at 4µA is subtracted from the first at 68µA to calculate a digital value that is proportional to absolute temperature. The output data appearing at DOUT is the digital code above, minus an offset to adjust from Kelvin to Celsius.

The reference voltage used for the temperature measurements is always derived from the internal reference source to ensure that 1 LSB corresponds to 1/8th of a degree Celsius. On every scan where a temperature measurement is requested, the 12-bit temperature conversion is carried out first. The first 2 bytes of data read from the FIFO contain the result of the 12-bit temperature measurement. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement). See the Applications Information section for information on how to perform temperature measurements in each clock mode.

The MAX1040–MAX1043/MAX1046–MAX1049 communicate between the internal registers and the external circuitry through the SPI-compatible serial interface. Table 1 details the command byte, the registers, and the bit names. Tables 4–12 show the various functions within the conversion register, setup register, unipolarmode register, bipolar-mode register, ADC averaging register, DAC select register, reset register, and GPIO command register, respectively.

Conversion Register

Select active analog input channels, scan modes, and a single temperature measurement per scan by issuing

MAX1042/MAX1043/

MAX1048/MAX1049

CURRENT

GPIOC0, GPIOC1

SINK CURRENT

15mA 4mA

SOURCE CURRENT

15mA 2mA

Table 3. GPIO Maximum Sink/Source Current

GPIOA0, GPIOA1

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

24 ______________________________________________________________________________________

a command byte to the conversion register. Table 4 details channel selection, the four scan modes, and how to request a temperature measurement. Start a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. See Figures 6 and 7 for timing specifications for starting a scan with CNVST.

A conversion is not performed if it is requested on a channel or one of the channel pairs that has been configured as CNVST or REF2. For channels configured as differential pairs, the CHSEL0 bit is ignored and the two pins are treated as a single differential channel. For the MAX1046–MAX1049, the CHSEL2 bit must be zero. Channels 4–7 are invalid. Any scans or averages on these channles can cause corrupt data.

Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the selected scanning range (set by bits 2 and 1, SCAN1 and SCAN0), plus one temperature result if selected. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the ADC averaging register (Table 9). Select scan mode 11 to return only one result from a single channel.

Setup Register

Issue a command byte to the setup register to configure the clock, reference, power-down modes, and ADC single-ended/differential modes. Table 5 details the bits in the setup-register command byte. Bits 5 and 4 (CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3 and 2 (REFSEL1 and REFSEL0) set the device for either internal or external reference. Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the ADC unipolar-mode and bipolar-mode registers and configure the analog-input channels for differential operation.

The ADC reference is always on if any of the following conditions are true:

1)The FBGON bit is set to one in the reset register.

2)At least one DAC output is powered up and REFSEL[1:0] (in the setup register) = 00.

3)At least one DAC is powered down through the 100kΩ to V

REF

and REFSEL[1:0] = 00.

If any of the above conditions exist, the ADC reference is always on, but there is a 188 clock-cycle delay before temperature-sensor measurements begin, if requested.

Table 4. Conversion Register*

BIT

NAME

BIT FUNCTION

—

S et to one to sel ect conver si on r eg i ster .

X 6 Don’t care.

CHSEL2

Analog-input channel select. (MAX1040–MAX1043). Set to 0 on MAX1046–MAX1049

CHSEL1

4 Analog-input channel select.

CHSEL0

3 Analog-input channel select.

SCAN1

2 Scan-mode select.

SCAN0

1 Scan-mode select.

TEMP

Set to one to take a single temperature measurement. The first conversion result of a scan contains temperature information.

*See below for bit details.

**Channels 4–7 are invalid on the MAX1046–MAX1049. Set

CHSEL2 bit to 0 on those devices.

7 (MSB)

0 (LSB)

CHSEL2** CHSEL1 CHSEL0

0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7

SCAN1 SCAN0

0 0 Scans channels 0 through N. 01

11N o scan. C onver ts channel N once onl y.

(CHANNEL N IS SELECTED BY

BITS CHSEL2, CHSEL1, AND CHSEL0)

Scans channels N through the highest numbered channel.

Scans channel N repeatedly. The ADC averaging register sets the number of results.

SELEC T ED

C H AN N EL

( N )

SCAN MODE

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 25

Table 5. Setup Register*

BIT NAME BIT FUNCTION

— 7 (MSB) Set to zero to select setup register.

— 6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration.

REFSEL1 3 Reference-mode configuration.

REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode. DIFFSEL0 0 (LSB) Unipolar-/bipolar-mode register configuration for differential mode.

Table 5a. Clock Modes (see the Clock Modes section)

CONVERSION CLOCK ACQUISITION/SAMPLING CNVST CONFIGURATION

0 0 Internal Internally timed. CNVST 0 1 Internal Externally timed by CNVST. CNVST 1 0 Internal Internally timed. AIN7 1 1 External (4.8MHz max) Externally timed by SCLK. AIN7

Table 5b. Clock Modes 00, 01, and 10

REFSEL1

REFSEL0

VOLTAGE

OVERRIDE

AUTOSHUTDOWN

REF2

CONFIGURATION

AIN

Inter nal r efer ence tur ns off after scan i s com p l ete. If i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed d el ay of 218 i nter nal - conver si on cl ock cycl es.

Internal (DAC

and ADC)

Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up.

AIN6

AIN Internal reference not used.

External single-

ended (REF1

for DAC and

Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up.

REF2

AIN

Default reference mode. Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 internalconversion clock cycles.

Internal (ADC)

and external REF1 (DAC)

Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up.

AIN6

AIN Internal reference not used.

External

differential

(ADC), external

REF1 (DAC)

Internal reference required. There is a programmed delay of 244 internal-conversion clock cycles for the internal reference to settle after wake-up.

REF2

*See below for bit details.

CKSEL1 CKSEL0

REFERENCE

CONDITIONS

REF2 for ADC)

Temperature

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

26 ______________________________________________________________________________________

Table 5c. Clock Mode 11

REFSEL1

VOLTAGE

OVERRIDE

AUTOSHUTDOWN

REF2

CONFIGURATION

AIN

Inter nal r efer ence tur ns off after scan i s com p l ete. If i nter nal r efer ence i s tur ned off, ther e i s a p r og r am m ed d el ay of 218 exter nal conver si on cl ock cycl es.

Internal (DAC

and ADC)

Inter nal r efer ence r eq ui r ed . Ther e i s a p r og r am m ed d el ay of 244 exter nal conver si on cl ock cycl es for the i nter nal r efer ence. Tem p er atu r e- sensor outp ut ap p ear s at D OU T after 188 fur ther exter nal cl ock cycl es.

AIN6

AIN Internal reference not used.

External single-

ended (REF1

for DAC and

REF2

AIN

Default reference mode. Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 external conversion clock cycles.

Internal (ADC)

and external REF1 (DAC)

AIN6

AIN Internal reference not used.

External

differential

(ADC), external

REF1 (DAC)

REF2

Table 5d. Differential Select Modes

DIFFSEL1

FUNCTION

0 0 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. 0 1 No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged. 1 0 1 byte of data follows the command setup byte and is written to the unipolar-mode register. 1 1 1 byte of data follows the command setup byte and is written to the bipolar-mode register.

REFSEL0

REFERENCE

CONDITIONS

Temperature

REF2 for ADC)

DIFFSEL0

Tem p er atur e

Temperature

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 27

Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)

BIT NAME

BIT FUNCTION

UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion.

UCH4/5 5

Configure AIN4 and AIN5 for unipolar differential conversion (MAX1040–MAX1043). Set UCH4/5 to 0 on the MAX1046–MAX1049.

UCH6/7 4

Configure AIN6 and AIN7 for unipolar differential conversion (MAX1040–MAX1043). Set UCH6/7 to 0 on the MAX1046–MAX1049.

X 3 Don’t care. X 2 Don’t care. X 1 Don’t care. X 0 (LSB) Don’t care.

Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)

BIT NAME BIT FUNCTION

BCH0/1

Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar single-ended conversion.

BCH2/3 6

Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar single-ended conversion.

BCH4/5 5

Set to one to configure AIN4 and AIN5 for bipolar differential conversion (MAX1040–MAX1043). Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar single-ended conversion. Set BCH4/5 to 0 on the MAX1046–MAX1049.

BCH6/7 4

Set to one to configure AIN6 and AIN7 for bipolar differential conversion (MAX1040–MAX1043). Set the corresponding bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar single-ended conversion. Set BCH6/7 to 0 on the MAX1046–MAX1049.

X 3 Don’t care. X 2 Don’t care. X 1 Don’t care. X 0 (LSB) Don’t care.

7 (MSB)

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

28 ______________________________________________________________________________________

Unipolar/Bipolar Registers

The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register. Hold CS low and run 16 SCLK cycles before pulling CS high.

If the last 2 bits of the setup register are 00 or 01, neither the unipolar-mode register nor the bipolar-mode register is written. Any subsequent byte is recognized as a new command byte. See Tables 6, 7, and 8 to program the unipolar- and bipolar-mode registers.

Both registers power up at all zeros to set the inputs as eight unipolar single-ended channels. To configure a channel pair as single-ended unipolar, bipolar differential, or unipolar differential, see Table 8.

In unipolar mode, AIN+ can exceed AIN- by up to V

REF

. The output format in unipolar mode is binary. In bipolar mode, either input can exceed the other by up to V

REF

/2. The output format in bipolar mode is two’s

complement (see the ADC Transfer Functions section).

ADC Averaging Register

Write a command byte to the ADC averaging register to configure the ADC to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans.

Table 8. Unipolar/Bipolar Channel Function

UNIPOLAR-

MODE

BIPOLAR-MODE

CHANNEL PAIR

FUNCTION

Unipolar single ended

0 1 Bipolar differential 1 0 Unipolar differential 1 1 Unipolar differential

Table 9. ADC Averaging Register*

BIT NAME BIT FUNCTION

— 7 (MSB) Set to zero to select ADC averaging register. — 6 Set to zero to select ADC averaging register. — 5 Set to one to select ADC averaging register.

AVGON 4 Set to one to turn averaging on. Set to zero to turn averaging off.

NAVG1 3 Configures the number of conversions for single-channel scans.

NAVG0 2 Configures the number of conversions for single-channel scans. NSCAN1 1 Single-channel scan count. (Scan mode 10 only.) NSCAN0 0 (LSB) Single-channel scan count. (Scan mode 10 only.)

*See below for bit details.

AVGON NAVG1 NAVG0

0 X X Performs one conversion for each requested result. 1 0 0 Performs four conversions and returns the average for each requested result. 1 0 1 Performs eight conversions and returns the average for each requested result. 1 1 0 Performs 16 conversions and returns the average for each requested result. 1 1 1 Performs 32 conversions and returns the average for each requested result.

NSCAN1 NSCAN0 FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)

0 0 Scans channel N and returns four results. 0 1 Scans channel N and returns eight results. 1 0 Scans channel N and returns 12 results. 1 1 Scans channel N and returns 16 results.

FUNCTION

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 29

Table 9 details the four scan modes available in the ADC conversion register. All four scan modes allow averaging as long as the AVGON bit, bit 4 in the averaging register, is set to 1. Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. For example, if AVGON = 1, NAVG[1:0] = 00, NSCAN [1:0] = 11 and SCAN [1:0] = 10, 16 results are written to the FIFO, with each result being the average of four conversions of channel N.

DAC Select Register

Write a command byte 0001XXXX to the DAC select register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command byte controls the DAC serial interface. See Table 17 and the DAC Serial Interface section.

Reset Register

Write to the reset register (as shown in Table 11) to clear the FIFO or to reset all registers to their default states. Set the RESET bit to one to reset the FIFO. Set the RESET bit to zero to return the MAX1040–MAX1043/ MAX1046–MAX1049 to their default power-up state. All registers power up in state 00000000, except for the setup register that powers up in clock mode 10 (CKSEL1 = 1). Set the SLOW bit to one to add a 15ns delay in the DOUT signal path to provide a longer hold time. Writing a one to the SLOW bit also clears the contents of the FIFO. Set the FBGON bit to one to force the bias block and bandgap reference to power up regardless of the state of the DAC and activity of the ADC block. Setting the FBGON bit high also removes the programmed wake-up delay between conversions in clock modes 01 and 11. Setting the FBGON bit high also clears the FIFO.

GPIO Command

Write a command byte to the GPIO command register to configure, write, or read the GPIOs, as detailed in Table 12.

Write the command byte 00000011 to configure the GPIOs. The eight SCLK cycles following the command byte load data from DIN to the GPIO configuration register in the MAX1042/MAX1043/MAX1048/MAX1049.

Table 10. DAC Select Register

BIT

NAME

BIT FUNCTION

—

Set to zero to select DAC select register.

—6

Set to zero to select DAC select register.

—5

Set to zero to select DAC select register.

—4

Set to one to select DAC select register.

X 3 Don’t care. X 2 Don’t care. X 1 Don’t care. X 0 Don’t care.

Table 11. Reset Register

BIT

NAME

BIT FUNCTION

—

Set to zero to select ADC reset register. — 6 Set to zero to select ADC reset register. — 5 Set to zero to select ADC reset register. — 4 Set to zero to select ADC reset register. — 3 Set to one to select ADC reset register.

RESET

Set to zero to clear the FIFO only. Set to

one to set the device in its power-on

condition.

SLOW

1 Set to one to turn on slow mode.

FBGON

Set to one to force internal bias block and

bandgap reference to be always powered

up.

Table 12. GPIO Command Register

BIT NAME

BIT FUNCTION

—

Set to zero to select GPIO register.

—6

Set to zero to select GPIO register.

—5

Set to zero to select GPIO register.

—4

Set to zero to select GPIO register.

—3

Set to zero to select GPIO register.

—2

Set to zero to select GPIO register.

GPIOSEL1

1 GPIO configuration bit.

GPIOSEL2

0 (LSB) GPIO write bit.

7 (MSB)

0 (LSB)

7 (MSB)

GPIOSEL1 GPIOSEL2 FUNCTION

GPIO configuration; written data is

entered in the GPIO configuration register.

GPIO write; written data is entered in the GPIO write register.

GPIO read; the next 8 SCLK cycles transfer the state of all GPIO drivers into DOUT.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

30 ______________________________________________________________________________________

Table 13. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Configuration

DATA PIN GPIO COMMAND BYTE DATA BYTE

DIN

DOUT

0000

Table 14. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Write

DATA PIN

GPIO COMMAND BYTE DATA BYTE

DIN

DOUT

0000

See Tables 13 and 14. The register bits are updated after the last CS rising edge. All GPIOs default to inputs upon power-up.

The data in the register controls the function of each GPIO, as shown in Tables 13, 14, and 16.

GPIO Write

Write the command byte 00000010 to indicate a GPIO write operation. The eight SCLK cycles following the command byte load data from DIN into the GPIO write register in the MAX1042/MAX1043/MAX1048/MAX1049. See Tables 14 and 15. The register bits are updated after the last CS rising edge.

GPIO Read

Write the command byte 00000001 to indicate a GPIO read operation. The eight SCLK cycles following the command byte transfer the state of the GPIOs to DOUT in the MAX1042/MAX1043/MAX1048/MAX1049. See Table 16.

DAC Serial Interface

Write a command byte 0001XXXX to the DAC select register to indicate the word to follow is written to the DAC serial interface, as detailed in Tables 1, 10, 17, and

18. Write the next 16 bits to the DAC interface register, as shown in Tables 17 and 18. Following the high-to-low transition of CS, the data is shifted synchronously and latched into the input register on each falling edge of SCLK. Each word is 16 bits. The first 4 bits are the control bits, followed by 10 data bits (MSB first), followed by 2 sub-bits. See Figures 9–12 for DAC timing specifications.

If CS goes high prior to completing 16 SCLK cycles, the command is discarded. To initiate a new transfer, drive CS low again.

For example, writing the DAC serial interface word 1111 0000 and 0011 0100 disconnects DAC outputs 2 and 3 and forces them to a high-impedance state. DAC outputs 0 and 1 remain in their previous state.

Table 15. GPIO-Mode Control

CONFIGURATION

BIT

WRITE

BIT

OUTPUT

STATE

GPIO

FUNCTION

1 1 1 Output 1 0 0 Output 0 1 Tri-state Input

000

Pulldown

(open drain)

Table 16. MAX1042/MAX1043/MAX1048/MAX1049 GPIO Read

DATA PIN

GPIO COMMAND BYTE DATA BYTE

DIN

XXXX

DOUT

GPIOC1 GPIOC0 GPIOA1 GPIOA0

0 0 0 0 0 0 1 1 GPIOC1 GPIOC0 GPIOA1 GPIOA0 X X X 00000000

000

0 0 0 0 0 0 1 0 GPIOC1 GPIOC0 GPIOA1 GPIOA0 X X X 00000000

00000001X X X X 000000000 0 0 0

000

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 31

Table 17. DAC Serial-Interface Configuration

16-BIT SERIAL WORD

MSB

CONTROL

BITS

DATA BITS

FUNCTION

NOP No Operation.

RESET

Reset all internal registers to 000h and leave output buffers in their present state.

Pull-High

Preset all internal registers to FFFh and leave output buffers in their present state.

DAC0

D9–D0 to input register 0, DAC output unchanged.

DAC1

D9–D0 to input register 1, DAC output unchanged.

DAC2

D9–D0 to input register 2, DAC output unchanged.

DAC3

D9–D0 to input register 3, DAC output unchanged.

NOP No Operation.

D9–D0 to input registers 0–3 and DAC register 0–3. DAC outputs updated (write-through).

NOP No Operation.

D9–D0 to input registers 0–3 and DAC Register 0–3. DAC outputs updated (write-through).

D9–D0 to input registers 0–3. DAC outputs unchanged.

DAC3

DAC2

DAC1

DAC0

Input registers to DAC registers indicated by ones, DAC outputs updated, equivalent to software LDAC.

(No effect on DACs indicated by zeros.)

C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

000XXXXXXXXXXXX

0010XXXXXXXXXXX

0011XXXXXXXXXXX

0 1 0——————————X X

0 1 1——————————X X

1 0 0——————————X X

1 0 1——————————X X 110XXXXXXXXXXXX

111XXXXXXXXXXXX 000XXXXXXXXXXXX 001XXXXXXXXXXXX

0 1 0——————————X X DAC0–DAC3

011XXXXXXXXXXXX

1 0 0——————————X X DAC0–DAC3

1 0 1——————————X X DAC0–DAC3

110XXXX

LSB

DESCRIPTION

X X X X DAC0–DAC3

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

32 ______________________________________________________________________________________

Output-Data Format

Figures 6–9 illustrate the conversion timing for the MAX1040–MAX1043/MAX1046–MAX1049. All 10-bit conversion results are output in 2-byte format, MSB first, with four leading zeros and the LSB followed by 2 sub-bits. Data appears on DOUT on the falling edges of SCLK. Data is binary for unipolar mode and two’s complement for bipolar mode and temperature results. See Figures 3, 4, and 5 for input/output and temperature-transfer functions.

ADC Transfer Functions

Figure 3 shows the unipolar transfer function for singleended or differential inputs. Figure 4 shows the bipolar

transfer function for differential inputs. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = V

REF1

/ 1024 for unipolar and bipolar operation, and 1 LSB = +0.125°C for temperature measurements. Bipolar true-differential results and temperature-sensor results are available in two’s complement format, while all others are in binary. See Tables 6, 7, and 8 for details on which setting (unipolar or bipolar) takes precedence.

In unipolar mode, AIN+ can exceed AIN- by up to V

REF1

. In bipolar mode, either input can exceed the

other by up to V

REF1

/2.

Table 18. DAC Power-Up and Power-Down Commands

CONTROL

BITS

DATA BITS

DAC3

DAC2

DAC1

DAC0

DESCRIPTION

FUNCTION

Power-Up

Power up individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is connected and active. A zero does not affect the DAC’s present state.

Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is disconnected and high impedance. A zero does not affect the DAC’s present state.

Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is disconnected and pulled to AGND with a 1kΩ resistor. A zero does not affect the DAC’s present state.

Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is disconnected and pulled to AGND with a 100kΩ resistor. A zero does not affect the DAC’s present state.

Power down individual DAC buffers indicated by data in DAC0 through DAC3. A one indicates the DAC output is disconnected and pulled to REF1 with a 100kΩ resistor. A zero does not affect the DAC’s present state.

C2 C1 C0 X X X X

1 1 1 X X X X ————0 0 1 X

1 1 1 X X X X ————0 1 0 X Power-Down 1

1 1 1 X X X X ————1 0 0 X Power-Down 2

1 1 1 X X X X ————0 0 0 X Power-Down 3

1 1 1 X X X X ————1 1 1 X Power-Down 4

D3 D2 D1 D0

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 33

Partial Reads and Partial Writes

If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the remaining bits are lost for that byte. The next byte of data that is read out contains the next 8 bits. If the first byte of an entry in the FIFO is read out fully, but the second byte is read out partially, the rest of that byte is lost. The remaining data in the FIFO is unaffected and can be read out normally after taking CS low again, as long as the 4 leading bits (normally zeros) are ignored. If CS is pulled low before EOC goes low, a conversion may not be completed and the FIFO data may not be correct. Incorrect writes (pulling CS high before completing eight SCLK cycles) are ignored and the register remains unchanged.

Applications Information

Internally Timed Acquisitions and

Conversions Using

CNVST

ADC Conversions in Clock Mode 00

In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequence is initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 6 for clock mode 00 timing after a command byte is issued. See Table 5 for details on programming the clock mode in the setup register.

Initiate a scan by setting CNVST low for at least 40ns before pulling it high again. The MAX1040–MAX1043/

MAX1046–MAX1049 then wake up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. A temperature-conversion result, if requested, precedes all other FIFO results. Temperature results are available in 12-bit format.

FULL-SCALE TRANSITION

111....111

INPUT VOLTAGE (LSB)

FS = V

REF

111....110

111....101

OFFSET BINARY OUTPUT CODE (LSB)

000....011

000....010

000....001

000....000

213 FS

1 LSB = V

REF

/ 1024

FS - 3/2 LSB

Figure 3. Unipolar Transfer Function—Full Scale (FS) = V

REF

OUTPUT CODE

011....111

TEMPERATURE (°C)

011....110

000....001

111....101

100....001

100....000

111....111

111....110

000....000

000....010

-256 +255.5

Figure 5. Temperature Transfer Function

011....111

-FS

INPUT VOLTAGE (LSB)

FS = V

REF

/ 2 + V

COM

REF

= V

REF+

- V

REF-

-FS = -V

REF

/ 2

011....110

011....101

000....001

000....000

111....111

OFFSET BINARY OUTPUT CODE (LSB)

100....011

100....010

100....001

100....000

(COM)

-1 +1

+FS - 1 LSB

1 LSB = V

REF

/ 1024

ZS = COM

REF

(COM)

REF

Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±V

REF

/ 2

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

34 ______________________________________________________________________________________

Do not issue a second CNVST signal before EOC goes low; otherwise, the FIFO can be corrupted. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC signal-to-noise ratio (SNR).

Externally Timed Acquisitions and

Internally Timed Conversions with

CNVST

ADC Conversions in Clock Mode 01

In clock mode 01, conversions are requested one at a time using CNVST and performed automatically using the internal oscillator. See Figure 7 for clock mode 01 timing after a command byte is issued.

Setting CNVST low begins an acquisition, wakes up the ADC, and places it in track mode. Hold CNVST low for

at least 1.4µs to complete the acquisition. If reference mode 00 or 10 is selected, an additional 45µs is required for the internal reference to power up. If a temperature measurement is being requested, reference power-up and temperature measurement is internally timed. In this case, hold CNVST low for at least 40ns.

Set CNVST high to begin a conversion. Sampling is completed approximately 500ns after CNVST goes high. After the conversion is complete, the ADC shuts down and pulls EOC low. EOC stays low until CS or CNVST is pulled low again. Wait until EOC goes low before pulling CS or CNVST low. The number of CNVST signals must equal the number of conversions requested by the scan and averaging registers to correctly update the FIFO. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during con-

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

DOUT

MSB1

RDS

LSB1 MSB2

SCLK

CNVST

EOC

Figure 6. Clock Mode 00—After writing a command byte, set

CNVST

low for at least 40ns to begin a conversion.

(CONVERSION 2)

CSW

DOV

(ACQUISITION 2)

(ACQUISITION 1)

(CONVERSION 1)

DOUT

MSB1

LSB1 MSB2

SCLK

CNVST

EOC

Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting

CNVST

low for each conversion.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 35

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

MSB1

DOV

LSB1

MSB2

(CONVERSION BYTE)

DOUT

SCLK

DIN

EOC

Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (

CNVST

is not required).

version. However, coupled noise may result in degraded ADC SNR.

If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO. Once the proper number of conversions has been performed to generate an averaged FIFO result (as specified to the averaging register), the scan logic automatically switches the analog-input multiplexer to the next requested channel. If a temperature measurement is programmed, it is performed after the first rising edge of CNVST follow- ing the command byte written to the conversion register. The temperature-conversion result is available on DOUT once EOC has been pulled low. Temperature results are available in 12-bit format.

Internally Timed Acquisitions and

Conversions Using the Serial Interface

ADC Conversions in Clock Mode 10

In clock mode 10, the wake-up, acquisition, conversion, and shutdown sequence is initiated by writing a command byte to the conversion register, and is performed automatically using the internal oscillator. This is the default clock mode upon power-up. See Figure 8 for clock mode 10 timing.

Initiate a scan by writing a command byte to the conversion register. The MAX1040–MAX1043/MAX1046– MAX1049 then power up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. If a temperature measurement is requested, the temperature result precedes all other FIFO results. Temperature results are available in 12-bit format. EOC stays low until CS is pulled low again. Wait until all conversions are complete before reading the FIFO. SPI communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may result in degraded ADC SNR.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

36 ______________________________________________________________________________________

Externally Clocked Acquisitions and

Conversions Using the Serial Interface

ADC Conversions in Clock Mode 11

In clock mode 11, acquisitions and conversions are initiated by writing a command byte to the conversion register and are performed one at a time using the SCLK as the conversion clock. Scanning, averaging and the FIFO are disabled, and the conversion result is available at DOUT during the conversion. Output data is updated on the rising edge of SCLK in clock mode

11. See Figure 9 for clock mode 11 timing. Initiate a conversion by writing a command byte to the

conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100µs. To continuously convert at 16 cycles per conversion, alternate 1 byte of zeros (NOP byte) between each conversion byte. If 2 NOP bytes follow a conversion byte, the analog cells power down at the end of the second NOP. Set the FBGON bit to one in the reset register to keep the internal bias block powered.

If reference mode 00 is requested, or if an external reference is selected but a temperature measurement is being requested, wait 45µs with CS high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. To perform a temperature measurement, write 24 bytes (192 cycles) of zeros after the conversion byte. The temperature result appears on DOUT during the last 2 bytes of the 192 cycles. Temperature results are available in 12-bit format.

Conversion-Time Calculations

The conversion time for each scan is based on a number of different factors: conversion time per sample, samples per result, results per scan, if a temperature measurement is requested, and if the external reference is in use. Use the following formula to calculate the total conversion time for an internally timed conversion in clock mode 00 and 10 (see the Electrical Characteristics, as applicable):

Total conversion time =

CNV

x n

AVG

x n

SCAN

+ tTS+ t

INT-REF,SU

where: t

CNV

= t

DOV

(where t

DOV

is dependent on clock mode

and reference mode selected). n

AVG

= samples per result (amount of averaging)

SCAN

= number of times each channel is scanned; set

to one unless [SCAN1, SCAN0] = 10 t

= time required for temperature measurement (53.1µs); set to zero if temperature measurement is not requested

INT-REF,SU

= tWU(external-reference wake-up); if a

conversion using the external reference is requested In clock mode 01, the total conversion time depends on

how long CNVST is held low or high. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. In clock mode 01, the total conversion time does not include the time required to turn on the internal reference.

SCLK

DOUT

MSB1 LSB1 MSB2

(ACQUISITION1)

(ACQUISITION2)

(CONVERSION1)

DIN

(CONVERSION BYTE)

EOC

Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without

CNVST

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 37

CSH

SCLK

DIN

DOUT

1234

32 16

D15

D14

D13 D12 D11

D15

D14

D13

D12

DOD

DOT

CSS

CSPWH

DOE

Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)

DAC/GPIO Timing

Figures 10–13 detail the timing diagrams for writing to the DAC and GPIOs. Figure 10 shows the timing specifications for clock modes 00, 01, and 10. Figure 11 shows the timing specifications for clock mode 11. Figure 12 details the timing specifications for the DAC input select register and 2 bytes to follow. Output data

is updated on the rising edge of SCLK in clock mode

11. Figure 13 shows the GPIO timing. Figure 14 shows the timing details of a hardware LDAC command DACregister update. For a software-command DAC-register update, tSis valid from the rising edge of CS, which follows the last data bit in the software command word.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

38 ______________________________________________________________________________________

SCLK

DIN

DOUT

1234

CSPWH

CSS

DOE

DOT

CSH

DOD

32 16

D15 D14 D13 D12 D11

D15

D14

D13

D12

D1 D0

Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)

SCLK

DIN

DOUT

1289

BIT 7 (MSB)

BIT 6

BIT 0 (LSB)

THE COMMAND BYTE

INITIALIZES THE DAC SELECT

THE NEXT 16 BITS SELECT THE DAC

AND THE DATA WRITTEN TO IT

BIT 15 BIT 14

BIT 0BIT 1

Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 39

GPIO INPUT/OUTPUT

GSU

GOD

Figure 13. GPIO Timing

LDAC

LDACPWL

OUT_

±1 LSB

Figure 14.

LDAC

Functionality

LDAC

Functionality

Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently low to make the DAC register transparent. The DAC output typically settles from zero to full scale within ±1 LSB after 2µs. See Figure 14.

Layout, Grounding, and Bypassing

For best performance, use PC boards. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital signals parallel to one another (especially clock signals) or do not run digital lines underneath the MAX1040–MAX1043/ MAX1046–MAX1049 package. High-frequency noise in the AVDDpower supply may affect performance. Bypass the AVDDsupply with a 0.1µF capacitor to AGND, close to the AV

pin. Bypass the DVDDsupply

with a 0.1µF capacitor to DGND, close to the DV

pin. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10Ω resistor in series with the supply to improve powersupply filtering.

The MAX1040–MAX1043/MAX1046–MAX1049 thin QFN packages contain an exposed pad on the underside of the device. Connect this exposed pad to AGND. Refer to the MAX1258EVKIT for an example of proper layout.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1040–MAX1043/MAX1046–MAX1049 is measured using the end-point method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

40 ______________________________________________________________________________________

Unipolar ADC Offset Error

For an ideal converter, the first transition occurs at 0.5 LSB, above zero. Offset error is the amount of deviation between the measured first transition point and the ideal first transition point.

Bipolar ADC Offset Error

While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value.

ADC Gain Error

Gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed and with a full-scale analog input voltage applied to the ADC, resulting in all ones at DOUT.

DAC Offset Error

DAC offset error is determined by loading a code of all zeros into the DAC and measuring the analog output voltage.

DAC Gain Error

DAC gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function, with the offset error removed, when loading a code of all ones into the DAC.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):

SNR = (6.02 x N + 1.76)dB

In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals:

SINAD(dB) = 20 x log (Signal

RMS

/ Noise

RMS

)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V6are the amplitudes of the first five harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.

ADC Channel-to-Channel Crosstalk

Bias the ON channel to midscale. Apply a full-scale sine wave test tone to all OFF channels. Perform an FFT on the ON channel. ADC channel-to-channel crosstalk is expressed in dB as the amplitude of the FFT spur at the frequency associated with the OFF channel test tone.

Intermodulation Distortion (IMD)

IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ± f1). The individual input tone levels are at -7dB FS.

Small-Signal Bandwidth

A small -20dB FS analog input signal is applied to an ADC so the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the T/H performance is usually the limiting factor for the smallsignal input bandwidth.

THD x VVVVVV= ++++

()

⎡ ⎣

⎢

⎤ ⎦

⎥

621

log /

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 41

Full-Power Bandwidth

A large -0.5dB FS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.

DAC Digital Feedthrough

DAC digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.

ADC Power-Supply Rejection

ADC power-supply rejection (PSR) is defined as the shift in offset error when the power-supply is moved from the minimum operating voltage to the maximum operating voltage.

DAC Power-Supply Rejection

DAC PSR is the amount of change in the converter’s value at full-scale as the power-supply voltage changes from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the powersupply voltage.

Chip Information

TRANSISTOR COUNT: 58,141 PROCESS: BiCMOS

Ordering Information/Selector Guide

PART

TEMP RANGE

PIN-PACKAGE

REF

(V)

ANALOG

SUPPLY

RESOLUTION

BITS***

ADC

DAC

GPIOs

MAX1046BETX

4.096

10 4 4 0

MAX1047BETX*

2.5 2.7 to 3.6 10 4 4 0

MAX1048BETX

4.096

10 4 4 4

MAX1049BETX*

2.5 2.7 to 3.6 10 4 4 4

*Future product—contact factory for availability. **EP = Exposed pad. ***Number of resolution bits refers to both DAC and ADC.

VOLTAGE

-40°C to +85°C 36 Thin QFN-EP**

VOLTAGE (V)

4.75 to 5.25

CHANNELS

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

42 ______________________________________________________________________________________

Pin Configurations

N.C. 1 N.C.

2 3

DGND

DOUT

SCLK

DIN

OUT0

EOC

AIN027 REF1

26 25

N.C.

RES_SEL

22 21 20

N.C.

OUT110OUT2

11 12

AGND

N.C.15N.C.16N.C.17N.C.

OUT3

REF2/AIN6

35 34

N.C.33N.C.32AIN431AIN330AIN229AIN1

AIN5

LDAC

CNVST/AIN7

MAX1040 MAX1041

TOP VIEW

6mm x 6mm x 0.8mm

THIN QFN

GPIOA0 1 GPIOA1

2 3

DGND

DOUT

SCLK

DIN

OUT0

EOC

AIN027 REF1

26 25

GPIOC0

N.C.

RES_SEL

22 21 20

N.C.

GPIOC1

OUT110OUT2

11 12

AGND

N.C.15N.C.16N.C.17N.C.

OUT3

REF2/AIN6

35 34

N.C.33N.C.32AIN431AIN330AIN229AIN1

AIN5

LDAC

CNVST/AIN7

MAX1042 MAX1043

TOP VIEW

6mm x 6mm x 0.8mm

THIN QFN

N.C. 1 N.C.

2 3

DGND

DOUT

SCLK

DIN

OUT0

EOC

AIN027 REF1

26 25

N.C.

RES_SEL

22 21 20

N.C.

OUT110OUT2

11 12

AGND

N.C.15N.C.16N.C.17N.C.

OUT3

REF2

35 34

N.C.33N.C.32N.C.31AIN330AIN229AIN1

N.C.

LDAC

CNVST

MAX1046 MAX1047

TOP VIEW

6mm x 6mm x 0.8mm

THIN QFN

GPIOA0 1 GPIOA1

2 3

DGND

DOUT

SCLK

DIN

OUT0

EOC

AIN027 REF1

26 25

GPIOC0

N.C.

RES_SEL

22 21 20

N.C.

GPIOC1

OUT110OUT2

11 12

AGND

N.C.15N.C.16N.C.17N.C.

OUT3

REF2

35 34

N.C.33N.C.32N.C.31AIN330AIN229AIN1

N.C.

LDAC

CNVST

MAX1048 MAX1049

TOP VIEW

6mm x 6mm x 0.8mm

THIN QFN

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________ 43

QFN THIN 6x6x0.8.EPS

e e

A1 A2

E/2

D/2

E2/2

(NE-1) X e

(ND-1) X e

D2/2

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

MAX1040–MAX1043/MAX1046–MAX1049

10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

3. N IS THE TOTAL NUMBER OF TERMINALS.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

21-0141

PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm

MAXIM MAX1043, MAX1046, MAX1049 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual