MAXIM MAX1036, MAX1039 Technical data

General Description

The MAX1036–MAX1039 low-power, 8-bit, multichannel,
analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto­Shutdown™ powers down the devices between conver­sions reducing supply current to less than 1µA at low
throughput rates. The MAX1036/MAX1037 have four ana­log input channels each, while the MAX1038/MAX1039
have twelve analog input channels. The analog inputs are
software configurable for unipolar or bipolar and single­ended or pseudo-differential operation.

The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1037/
MAX1039 feature a 2.048V internal reference and the
MAX1036/MAX1038 feature a 4.096V internal reference.

The MAX1036/MAX1037 are available in 8-pin SOT23
packages. The MAX1038/MAX1039 are available in 16­pin QSOP packages. The MAX1036–MAX1039 are guar­anteed over the extended industrial temperature range
(-40°C to +85°C). Refer to MAX1136–MAX1139 for 10-bit
devices and to the MAX1236–MAX1239 for 12-bit
devices.

Applications

Hand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision

Features

♦ High-Speed I2C-Compatible Serial Interface

400kHz Fast Mode

1.7MHz High-Speed Mode

♦ Single Supply

2.7V to 3.6V (MAX1037/MAX1039)

4.5V to 5.5V (MAX1036/MAX1038)

♦ Internal Reference

2.048V (MAX1037/MAX1039)

4.096V (MAX1036/MAX1038)

♦ External Reference: 1V to V

DD

♦ Internal Clock

♦ 4-Channel Single-Ended or 2-Channel Pseudo-

Differential (MAX1036/MAX1037)

♦ 12-Channel Single-Ended or 6-Channel Pseudo-

Differential (MAX1038/MAX1039)

♦ Internal FIFO with Channel-Scan Mode

♦ Low Power

350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode

♦ Software Configurable Unipolar/Bipolar

♦ Small Packages

8-Pin SOT23 (MAX1036/MAX1037)
16-Pin QSOP (MAX1038/MAX1039)

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2442; Rev 1; 10/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE

TUE

(LSB)

INPUT

INTERNAL

TOP

MARK

MAX1036EKA-T

8 SOT23-8 ±2 4 4.096 AAJE

MAX1037EKA-T

8 SOT23-8 ±2 4 2.048 AAJG

MAX1038AEEE

16 QSOP ±1 12 4.096 —

MAX1039AEEE

16 QSOP ±1 12 2.048 —

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

Pin Configurations and Typical Operating Circuit appear
at end of data sheet.

查询MAX1035供应商

PIN-PACKAGE

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

CHANNELS

REFERENCE (V)

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= 2.7V to 3.6V (MAX1037/MAX1039), VDD= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V

REF

= 2.048V

(MAX1037/MAX1039), V

REF

= 4.096V (MAX1036/MAX1038). External clock, f

SCL

= 1.7MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto GND..............................................................-0.3V to +6V

AIN0–AIN11, REF to

GND ......................-0.3V to the lower of (V

DD

+ 0.3V) and +6V

SDA, SCL to GND.....................................................-0.3V to +6V

Maximum Current Into Any Pin .........................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW

16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY (Note 1)

Resolution 8 Bits
Relative Accuracy INL (Note 2) ±1

LSB

Differential Nonlinearity DNL No missing codes over temperature ±1

LSB

Offset Error

LSB

Offset Error Temperature
Coefficient

3

ppm/°C

Gain Error (Note 3) ±1

LSB

Gain Temperature Coefficient ±1

ppm/°C

MAX1036/MAX1037

±2

Total Unadjusted Error TUE

MAX1038A/MAX1039A

±1

LSB

Channel-to-Channel Offset
Matching

LSB

Channel-to-Channel Gain
Matching

LSB

Input Common-Mode Rejection
Ratio

Pseudo-differential input mode 75 dB

DYNAMIC PERFORMANCE (f

IN(sine wave)

= 25kHz, VIN = V

REF(P-P)

, f

SAMPLE

= 188ksps, RIN = 100Ω)

Signal-to-Noise Plus Distortion

49 dB

Total Harmonic Distortion THD Up to the 5th harmonic -69 dB

Spurious-Free Dynamic Range SFDR 69 dB

Channel-to-Channel Crosstalk (Note 4) 75 dB

Full-Power Bandwidth -3dB point 2.0

MHz

Full-Linear Bandwidth SINAD > 49dB

kHz

CONVERSION RATE

Internal clock 6.1

Conversion Time (Note 5)

External clock 4.7

µs

CMRR

SINAD

t

CONV

±0.5
±0.5

±0.1

±0.5

200

±1.5

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX1037/MAX1039), VDD= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V

REF

= 2.048V

(MAX1037/MAX1039), V

REF

= 4.096V (MAX1036/MAX1038). External clock, f

SCL

= 1.7MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Internal clock, SCAN[1:0] = 01
(MAX1036/MAX1037)

76

Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX1038/MAX1039)

77

Throughput Rate

External clock 188

ksps

Track/Hold Acquisition Time

ns

Internal Clock Frequency

MHz

External clock, fast mode 45

Aperture Delay t

AD

External clock, high-speed mode 30

ns

ANALOG INPUT (AIN0–AIN11)

Unipolar 0

Input Voltage Range, Single
Ended and Differential (Note 6)

Bipolar

V

Input Multiplexer Leakage Current

On/off-leakage current, V

AIN

_= 0 or V

DD,

no clock, f

SCL

= 0

±1µA

Input Capacitance C

IN

18 pF

INTERNAL REFERENCE (Note 7)

MAX1037/MAX1039

Reference Voltage V

REF

TA = +25°C

MAX1036/MAX1038

V

Reference Temperature
Coefficient

ppm/°C

Reference Short-Circuit Current 10 mA

Reference Source Impedance (Note 8)

Ω

EXTERNAL REFERENCE

Reference Input Voltage Range V

REF

(Note 9) 1.0

V

REF Input Current I

REF

f

SAMPLE

= 188ksps 14 30 µA

DIGITAL INPUTS/OUTPUTS (SCL, SDA)

Input High Voltage V

IH

V

Input Low Voltage V

IL

V

Input Hysteresis

V

Input Current I

IN

VIN = 0 to V

DD

±10 µA

Input Capacitance C

IN

15 pF

Output Low Voltage V

OL

I

SINK

= 3mA 0.4 V

f

SAMPLE

TC

REF

V

HYST

588

1.925 2.048 2.171

3.850 4.096 4.342

0.7 x V

DD

0.1 x V

DD

2.25

±V

±0.01

120

675

0.3 x V

V

REF

V

REF

DD

/ 2

DD

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX1037/MAX1039), VDD= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V

REF

= 2.048V

(MAX1037/MAX1039), V

REF

= 4.096V (MAX1036/MAX1038). External clock, f

SCL

= 1.7MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER REQUIREMENTS

MAX1037/MAX1039 2.7 3.6

Supply Voltage (Note 10) V

DD

MAX1036/MAX1038 4.5 5.5

V

650

f

SAMPLE

=

188ksps

f

SAMPLE

=

75ksps

8

f

SAMPLE

=

10ksps

10

2

f

SAMPLE

=

1ksps

2.5

Supply Current I

DD

Power-down 1 10

µA

Power-Supply Rejection Ratio PSRR (Note 11)

±1

LSB/V

TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2)

Serial Clock Frequency f

SCL

400 kHz

Bus Free Time Between a STOP
and a START Condition

t

BUF

1.3 µs

Hold Time for Start Condition

,

0.6 µs

Low Period of the SCL Clock t

LOW

1.3 µs

High Period of the SCL Clock t

HIGH

0.6 µs

Setup Time for a Repeated START
Condition (Sr)

,

0.6 µs

Data Hold Time

,

(Note 12) 0 150 ns

Data Setup Time

,

ns

Rise Time of Both SDA and SCL
Signals, Receiving

t

R

(Note 13)

300 ns

Fall Time of SDA Transmitting t

F

(Note 13)

300 ns

Setup Time for STOP Condition

,

0.6 µs

Capacitive Load for Each Bus Line

C

B

400 pF

Pulse Width of Spike Suppressed

t

SP

50 ns

TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2)

Serial Clock Frequency f

SCLH

(Note 14) 1.7

MHz

Hold Time (Repeated) Start
Condition

,

ns

Low Period of the SCL Clock t

LOW

ns

High Period of the SCL Clock t

HIGH

ns

t

HD

STA

t

SU

STA

t

HD

DAT

t

SU

DAT

t

SU

STO

t

HD

STA

Internal REF, external clock 350

External REF, external clock 250

External REF, external clock 110

External REF, internal clock 150

External REF, external clock

External REF, internal clock

External REF, external clock

External REF, internal clock

100

20 + 0.1C

20 + 0.1C

160

320

120

±0.25

B

B

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX1037/MAX1039), VDD= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V

REF

= 2.048V

(MAX1037/MAX1039), V

REF

= 4.096V (MAX1036/MAX1038). External clock, f

SCL

= 1.7MHz, TA= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Setup Time for a Repeated START
Condition (Sr)

ns

Data Hold Time

(Note 12) 0 150 ns

Data Setup Time

10 ns

Rise Time of SCL Signal
(Current Source Enabled)

t

RCL

(Note 13) 20 80 ns

Rise Time of SCL Signal After
Acknowledge Bit

t

RCL1

(Note 13) 20 160 ns

Fall Time of SCL Signal t

FCL

(Note 13) 20 80 ns

Rise Time of SDA Signal t

RDA

(Note 13) 20 160 ns

Fall Time of SDA Signal t

FDA

(Note 13) 20 160 ns

Setup Time for STOP Condition

ns

Capacitive Load for Each Bus Line

C

B

400 pF

Pulse Width of Spike Suppressed

t

SP

010ns

Note 1: The MAX1036/MAX1038 are tested at VDD= 5V and the MAX1037/MAX1039 are tested at VDD= 3V. All devices are config-

ured for unipolar, single-ended inputs.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and

offsets have been calibrated.

Note 3: Offset nulled.
Note 4: Ground ON channel; sine wave applied to all OFF channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not

include acquisition time. SCL is the conversion clock in the external clock mode.

Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V

DD

.

Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV

P-P

.

Note 10: Electrical characteristics are guaranteed from V

DD(min)

to V

DD(max)

. For operation beyond this range, see the Typical

Operating Characteristics.

Note 11: Power-supply rejection ratio is measured as:

, for the MAX1037/MAX1039 where N is the number of bits (8) and V

REF

= 2.048V.

Power-supply rejection ratio is measured as:

, for the MAX1036/MAX1038 where N is the number of bits (8) and V

REF

= 2.048V.

Note 12: A master device must provide a data hold time for SDA (referred to V

IL

of SCL) in order to bridge the undefined region of

SCL’s falling edge (Figure 1).

Note 13: C

B

= total capacitance of one bus line in pF. tRand tFmeasured between 0.3VDDand 0.7VDD. Minimum specification is

tested at +25°C with C

B

= 400pF.

Note 14: f

SCLH

must meet the minimum clock low time plus the rise/fall times.

VVVV

V

VV

FS FS

N

REF

55 45

2

55 45

..

..

()−()

[]

×

−

VVVV

V

VV

FS FS

N

REF

33 27

2

33 27

..

..

()−()

[]

×

−

tSU,

STA

tHD,

DAT

tSU,

DAT

tSU,

STO

160

160

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= 3.3V (MAX1037/MAX1039), VDD= 5V (MAX1036/MAX1038), f

SCL

= 1.7MHz, external clock (33% duty cycle), f

SAMPLE

= 188ksps,

single ended, unipolar, TA= +25°C, unless otherwise noted.)

150

250

200

350

300

400

450

SUPPLY CURRENT

vs. VOLTAGE

MAX1036 toc01

VDD (V)

I

DD

(µA)

2.5 3.5 4.03.0 4.5 5.0 5.5

A) INTERNAL 4.096V

REF

B) INTERNAL 2.048V

REF

C) EXTERNAL 4.096V

REF

D) EXTERNAL 2.048V

REF

A

C

B

D

150

250

200

350

300

400

450

-40 85

SUPPLY CURRENT
vs. TEMPERATURE

MAX1036 toc02

TEMPERATURE (°C)

I

DD

(µA)

10-15 35 60

INTERNAL 4.096V

REF

INTERNAL 2.048V

REF

EXTERNAL 4.096V

REF

EXTERNAL 2.048V

REF

0

1

3

2

4

5

2.5 3.53.0 4.0 4.5 5.0 5.5

SHUTDOWN SUPPLY CURRENT

vs.

SUPPLY VOLTAGE

MAX1036 toc03

VDD (V)

I

DD

(µA)

SDA = SCL = V

DD

0

1

3

2

4

5

-40 10-15 35 60 85

SHUTDOWN SUPPLY CURRENT

vs.

TEMPERATURE

MAX1036 toc04

TEMPERATURE (°C)

I

DD

(µA)

SDA = SCL = V

DD

V

DD

= 5V

V

DD

= 3.3V

0

100

50

200

150

300

250

350

0203010 40 50 60

AVERAGE SUPPLY CURRENT vs.

CONVERSION RATE (INTERNAL CLOCK)

MAX1036 toc05

CONVERSION RATE (ksps)

AVERAGE I

DD

(µA)

A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF

A

C

B

INTERNAL CLOCK MODE

f

SCL

= 1.7MHz

0

150

100

50

300

250

200

450

400

350

500

0 10050 150 200

AVERAGE SUPPLY CURRENT VS.

CONVERSION RATE (EXTERNAL CLOCK)

MAX1036 toc06

CONVERSION RATE (ksps)

AVERAGE I

DD

(µA)

A

C

B

A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF

EXTERNAL CLOCK MODE

f

SCL

= 1.7MHz

0.9900

0.9925

0.9950

0.9975

1.0000

1.0025

1.0050

1.0075

1.0100

4.00 4.504.25 4.75 5.00 5.25 5.50

NORMALIZED 4.096V REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1036 toc7

VDD (V)

V

REF

NORMALIZED

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

-40 -15 10 35 60 85

INTERNAL 4.096V REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1036 toc08

TEMPERATURE (°C)

V

REF

NORMALIZED

0.9900

0.9925

0.9950

0.9975

1.0000

1.0025

1.0050

1.0075

1.0100

2.5 3.53.0 4.0 4.5 5.0 5.5

INTERNAL 2.048V REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1036 toc09

VDD (V)

V

REF

NORMALIZED

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

_______________________________________________________________________________________ 7

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

-40 -15 10 35 60 85

INTERNAL 2.048V REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1036 toc10

TEMPERATURE (°C)

V

REF

NORMALIZED

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 10050 150 200 250 300

DIFFERENTIAL NONLINEARITY

vs. DIGITAL CODE

MAX1036 toc11

DIGITAL OUTPUT CODE

DNL (LSB)

-0.5

-0.2

-0.3

-0.4

-0.1

0

0.1

0.2

0.3

0.4

0.5

0 10050 150 200 250 300

INTEGRAL NONLINEARITY

vs. DIGITAL CODE

MAX1036 toc12

DIGITAL OUTPUT CODE

INL (LSB)

-120

-80

-100

-40

-60

-20

0

0 100k

FFT PLOT

MAX1036 toc13

FREQUENCY (Hz)

AMPLITUDE (dBc)

40k20k 60k 80k

f

SAMPLE = 188ksps

f

IN = 25kHz

0

0.3

0.2

0.1

0.4

0.5

0.6

0.7

0.8

0.9

1.0

2.5 3.53.0 4.0 4.5 5.0 5.5

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX1036 toc14

VDD (V)

OFFSET ERROR (LSB)

V

REF

= 2.048V

0

0.3

0.2

0.1

0.4

0.5

0.6

0.7

0.8

0.9

1.0

-40 10-15 35 60 85

OFFSET ERROR vs. TEMPERATURE

MAX1036 toc15

TEMPERATURE (°C)

OFFSET ERROR (LSB)

VDD = 3.3V
V

REF

= 2.048V

-0.1

-0.07

-0.08

-0.09

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0

2.5 3.53.0 4.0 4.5 5.0 5.5

GAIN ERROR vs. SUPPLY VOLTAGE

MAX1036 toc16

VDD (V)

GAIN ERROR (LSB)

V

REF

= 2.048V

Typical Operating Characteristics (continued)

(VDD= 3.3V (MAX1037/MAX1039), VDD= 5V (MAX1036/MAX1038), f

SCL

= 1.7MHz, external clock (33% duty cycle), f

SAMPLE

= 188ksps,

single ended, unipolar, TA= +25°C, unless otherwise noted.)

MAX1036–MAX1039

Detailed Description

The MAX1036–MAX1039 ADCs use successive­approximation conversion techniques and input T/H cir­cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX1036/MAX1037 are
4-channel ADCs, and the MAX1038/MAX1039 are 12­channel ADCs. These devices feature a high-speed 2­wire serial interface supporting data rates up to

1.7MHz. Figure 3 shows the simplified functional dia­gram for the MAX1038/MAX1039.

Power Supply

The MAX1036–MAX1039 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX1037/MAX1039 feature a 2.048V internal
reference and the MAX1036/MAX1038 feature a 4.096V
internal reference. All devices can be configured for
use with an external reference from 1V to VDD.

Analog Input and Track/Hold

The MAX1036–MAX1039 analog input architecture con-
tains an analog input multiplexer (MUX), a T/H capaci­tor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).

In single-ended mode, the analog input multiplexer con­nects C

T/H

to the analog input selected by CS[3:0] (see
the Configuration/Setup Bytes (Write Cycle) section). The
charge on C

T/H

is referenced to GND when converted. In
pseudo-differential mode, the analog input multiplexer
connects C

T/H

to the ‘+ ’ analog input selected by

CS[3:0]. The charge on C

T/H

is referenced to the ‘-’ ana-

log input when converted.

The MAX1036–MAX1039 input configuration is pseudo­differential in that only the signal at the ‘+’ analog input
is sampled with the T/H circuitry. The ‘-’ analog input
signal must remain stable within ±0.5LSB (±0.1LSB for
best results) with respect to GND during a conversion.
To accomplish this, connect a 0.1µF capacitor from ‘-’
analog input to GND. See the Single-Ended/Pseudo-
Differential Input section.

During the acquisition interval, the T/H switches are in
the track position and C

T/H

charges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C

T/H

as a sample of the input signal.

During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva­lent to transferring a charge of 18pF ✕ (VIN+ - VIN-)
from C

T/H

to the binary weighted capacitive DAC form-

ing a digital representation of the analog input signal.

Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped­ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.

When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

8 _______________________________________________________________________________________

PIN

MAX1036/

MAX1037

MAX1038/

MAX1039

NAME FUNCTION

1, 2, 3 8, 7, 6 AIN0–AIN2

— 5, 4, 3, 2, 1 AIN3–AIN7

— 16, 15, 14 AIN8–AIN10

Analog Inputs

4 — AIN3/REF

Analog Input 3/Reference Input or Output. Selected in the setup
register.

— 13 AIN11/REF

Analog Input 11/Reference Input or Output. Selected in the setup
register.

5 9 SCL Clock Input

6 10 SDA Data Input/Output

7 11 GND Ground

812VDDPositive Supply. Bypass to GND with a 0.1µF capacitor.

Pin Description

of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or series of conversions are
then internally clocked (eight clock cycles per conver­sion) and the MAX1036–MAX1039 hold SCL low. When
operating in external clock mode, the T/H circuitry
enters track mode on the seventh falling edge of a valid
slave address byte. Hold mode is then entered on the
falling edge of the eighth clock cycle. The conversion is
performed during the next eight clock cycles.

The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (t

ACQ

) is the
minimum time needed for the signal to be acquired. It
is calculated by:

t

ACQ

≥ 6.25 ✕ (R

SOURCE

+ RIN) ✕ C

IN

where R

SOURCE

is the analog input source impedance,

RIN= 2.5kΩ, and CIN= 18pF. t

ACQ

is 1/f

SCL

for external

clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select R

SOURCE

,

allow 625ns for t

ACQ

in internal clock mode to account

for clock frequency variations.

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

_______________________________________________________________________________________ 9

t

HD.STA

t

SU.DAT

t

HIGH

t

R

t

F

t

HD.DAT

t

HD.STA

S

Sr

A

SCL

SDA

t

SU.STA

t

LOW

t

BUF

t

SU.STO

PS

t

HD.STA

t

SU.DAT

t

HIGH

t

FCL

t

HD.DAT

t

HD.STA

S Sr A

SCL

SDA

t

SU.STA

t

LOW

t

BUF

t

SU.STO

S

t

RCL

t

RCL1

HS-MODE F/S-MODE

A. F/S-MODE I

2

C SERIAL INTERFACE TIMING

B. HS-MODE I

2

C SERIAL INTERFACE TIMING

t

FDA

t

RDA

t

t

R

t

F

Figure 1. I2C Serial Interface Timing

V

DD

I

OL

= 3mA

I

OH

= 0mA

V

OUT

400pF

SDA

Figure 2. Load Circuit

MAX1036–MAX1039

Analog Input Bandwidth

The MAX1036–MAX1039 feature input tracking circuitry
with a 2MHz small signal-bandwidth. The 2MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre­quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.

Analog Input Range and Protection

Internal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
swing from (GND - 0.3V) to (VDD+ 0.3V) without caus­ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD. If the analog input exceeds VDDby more
than 50mV, the input current should be limited to 2mA.

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

10 ______________________________________________________________________________________

ANALOG

INPUT

MUX

AIN1

AIN11/REF

AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9

AIN10

AIN0

SCL

SDA

INPUT SHIFT REGISTER

SETUP REGISTER

CONFIGURATION REGISTER

CONTROL

LOGIC

REFERENCE

4.096V (MAX1038)

2.048V (MAX1039)

INTERNAL

OSCILLATOR

OUTPUT SHIFT
REGISTER AND

12-BYTE RAM

REF

T/H

8-BIT

ADC

V

DD

GND

MAX1038
MAX1039

Figure 3. MAX1038/MAX1039 Simplified Functional Diagram

TRACK

HOLD

C

T/H

TRACK

HOLD

DIFFERENTIAL

SINGLE ENDED

AIN0

AIN1

AIN2

AIN3/REF

GND

ANALOG INPUT MUX

CAPACITIVE
DAC

REF

MAX1036
MAX1037

Figure 4. Equivalent Input Circuit

Single-Ended/Pseudo-Differential Input

The SGL/DIF bit of the configuration byte configures the

MAX1036–MAX1039 analog input circuitry for single­ended or pseudo-differential inputs (Table 2). In single­ended mode (SGL/DIF = 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF = 0), the digital conversion results are the differ­ence between the ‘+’ and the ‘-’ analog inputs selected
by CS[3:0] (Table 4). The ‘-’ analog input signal must
remain stable within ±0.5LSB (±0.1LSB for best results)
with respect to GND during a conversion.

Unipolar/Bipolar

When operating in pseudo-differential mode, the BIP/
UNI bit of the setup byte (Table 1) selects unipolar or
bipolar operation. Unipolar mode sets the differential
analog input range from zero to V

REF

. A negative differ­ential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to ±V

REF

/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).

In single-ended mode, the MAX1036–MAX1039 always
operate in unipolar mode regardless of the BIP/UNI
setting, and the analog inputs are internally referenced
to GND with a full-scale input range from zero to V

REF

.

Digital Interface

The MAX1036–MAX1039 feature a 2-wire interface con­sisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate bidirectional communica­tion between the MAX1036–MAX1039 and the master
at rates up to 1.7MHz. The MAX1036–MAX1039 are
slaves that transmit and receive data. The master (typi­cally a microcontroller) initiates data transfer on the bus
and generates SCL to permit that transfer.

SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ω or greater) (see
Typical Operating Circuit). Series resistors (RS) are
optional. They protect the input architecture of the
MAX1036–MAX1039 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.

Bit Transfer

One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX1036–MAX1039. The data on
SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are
control signals (see the START and STOP Conditions
section). Both SDA and SCL idle high when the bus is
not busy.

START and STOP Conditions

The master initiates a transmission with a START condi­tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 11

BIT 7

(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

BIT 0

(LSB)

REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X

BIT NAME DESCRIPTION

7 REG Register bit. 1 = Setup Byte, 0 = Configuration Byte (Table 2).

6 SEL2

5 SEL1

4 SEL0

Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at
power-up.

3 CLK 1 = External clock, 0 = Internal clock. Defaulted to zero at power-up.
2 BIP/UNI 1 = Bipolar, 0 = Unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).

1 RST

1 = No action, 0 = Resets the configuration register to default. Setup register remains
unchanged.

0 X Don’t care, can be set to 1 or 0.

Table 1. Setup Byte Format

MAX1036–MAX1039

SCL is high (Figure 5). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the HS-
Mode section).

Acknowledge Bits

Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX1036–MAX1039 (slave) generate
acknowledge bits. To generate an “acknowledge,” the
receiving device must pull SDA low before the rising
edge of the acknowledge related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a “not acknowledge,” the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge related clock pulse and leaves
it high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc­cessful data transfer, the bus master should reattempt
communication at a later time.

Slave Address

A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX1036–MAX1039 con­tinuously wait for a START condition followed by their
slave address. When the MAX1036–MAX1039 recog­nize their slave address, they are ready to accept or
send data. The slave address has been factory pro­grammed and is always 1100100 for the MAX1036/
MAX1037, and 1100101 for MAX1038/ MAX1039
(Figure 7). The least significant bit (LSB) of the address
byte (R/W) determines whether the master is writing to
or reading from the MAX1036–MAX1039 (R/W = zero
selects a write condition. R/W = 1 selects a read condi­tion). After receiving the address, the MAX1036–
MAX1039 (slave) issue an acknowledge by pulling SDA
low for one clock cycle.

Bus Timing

At power-up, the MAX1036–MAX1039 bus timing
defaults to fast mode (F/S-mode) allowing conversion
rates up to 44ksps. The MAX1036–MAX1039 must
operate in high-speed mode (HS-mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX1036–MAX1039’s 2-wire interface.

HS-Mode

At power-up, the MAX1036–MAX1039 bus timing is set
for F/S-mode. The master selects HS-mode by address­ing all devices on the bus with the HS-mode master

code 0000 1XXX (X = Don’t care). After successfully
receiving the HS-mode master code, the MAX1036–
MAX1039 issues a not acknowledge, allowing SDA to be
pulled high for one clock cycle (Figure 8). After the not
acknowledge, the MAX1036–MAX1039 are in HS-mode.
The master must then send a repeated START followed
by a slave address to initiate HS-mode communication. If
the master generates a STOP condition, the
MAX1036–MAX1039 return to F/S-mode.

Configuration/Setup Bytes (Write Cycle)

Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W = zero). If the address byte is successful­ly received, the MAX1036–MAX1039 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the con­figuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowl­edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS-mode, a STOP condition returns the
bus to F/S-mode (see the HS-Mode section).

Data Byte (Read Cycle)

A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

12 ______________________________________________________________________________________

SCL

SDA

SP

Sr

Figure 5. START and STOP Conditions

SCL

SDA

S

NOT ACKNOWLEDGE

ACKNOWLEDGE

12 89

Figure 6. Acknowledge Bits

a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX1036–MAX1039 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX1036–MAX1039 receive a not acknowledge, they
release SDA allowing the master to generate a STOP
or repeated START. See the Clock Mode and Scan
Mode sections for detailed information on how data is
obtained and converted.

Clock Mode

The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table

1). At power-up, the MAX1036–MAX1039 default to
internal clock mode (CLK = zero).

Internal Clock

When configured for internal clock mode (CLK = zero),
the MAX1036–MAX1039 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX1036–MAX1039 begin tracking analog input on the
ninth falling clock edge of a valid slave address byte.
Two internal clock cycles later, the analog signal is
acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX1036–MAX1039 hold SCL low (clock stretching).
After the conversion completes, the results are stored

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 13

110 10 0 0 R/W A

SLAVE ADDRESS

S

SCL

SDA

123456789

DEVICE SLAVE ADDRESS

1100100

1100101

MAX1036/MAX1037

MAX1038/MAX1039

Figure 7. MAX1036/MAX1037 Slave Address Byte

000 10XXXA

HS-MODE MASTER CODE

SCL

SDA

S Sr

F/S-MODE HS-MODE

Figure 8. F/S-Mode to HS-Mode Transfer

MAX1036–MAX1039

in random access memory (RAM). If the scan mode is
set for multiple conversions, they all happen in succes­sion with each additional result being stored in RAM.
The MAX1036/MAX1037 contain 8 bytes of RAM, and
the MAX1038/MAX1039 contain 12 bytes of RAM. Once
all conversions are complete, the MAX1036–MAX1039
release SCL, allowing it to be pulled high. The master
can now clock the results out of the output shift register
at a clock rate of up to 1.7MHz. SCL is stretched for a
maximum acquisition and conversion time of 7.6µs per
channel (Figure 10).

The device RAM contains all of the conversion results
when the MAX1036–MAX1039 release SCL. The con­verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. RAM contents can be read contin­uously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.

The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con­version. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.

External Clock

When configured for external clock mode (CLK = 1),
the MAX1036–MAX1039 use SCL as the conversion
clock. In external clock mode, the MAX1036–MAX1039
begin tracking the analog input on the seventh falling
clock edge of a valid slave address byte. One SCL
clock cycle later, the analog signal is acquired and the
conversion begins. Unlike internal clock mode, convert­ed data is available immediately after the slave-address
acknowledge bit. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (Figure 11).

The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.

The MAX1036–MAX1039 must operate in external clock
mode for conversion rates up to 188ksps.

Scan Mode

SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan.

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

14 ______________________________________________________________________________________

B. 2-BYTE WRITE CYCLE

SLAVE TO MASTER

MASTER TO SLAVE

S

1

SLAVE ADDRESS A

711

W

SETUP OR

CONFIGURATION BYTE

SETUP OR

CONFIGURATION BYTE

8

P OR Sr

1A1

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

S

1

SLAVE ADDRESS A

711

W

SETUP OR

CONFIGURATION BYTE

8

P OR Sr

1

A

1

MSB DETERMINES WHETHER

SETUP OR CONFIGURATION BYTE

A

1

8

A. 1-BYTE WRITE CYCLE

NUMBER OF BITS

NUMBER OF BITS

Figure 9. Write Cycle

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 15

Applications Information

Power-On Reset

The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con­version on AIN0 using the internal clock with VDDas the
reference and AIN_/REF configured as an analog input.
The RAM contents are unknown after power-up.

Automatic Shutdown

SEL[2:0] of the setup byte (Tables 1 and 6) controls the
state of the reference and AIN_/REF. If automatic shut­down is selected (SEL[2:0] = 100), shutdown occurs
between conversions when the MAX1036–MAX1039 are
idle. When operating in external clock mode, a STOP
condition must be issued to place the devices in idle
mode and benefit from automatic shutdown. A STOP
condition is not necessary in internal clock mode to ben­efit from automatic shutdown because power-down
occurs once all contents are written to memory (Figure

10). All analog circuitry is inactive in shutdown and sup­ply current is less than 1µA. The digital conversion
results are maintained in RAM during shutdown and are
available for access through the serial interface at any
time prior to a STOP or repeated START condition.

When idle, the MAX1036–MAX1039 wait for a START
condition followed by their slave address (see the
Slave Address section). Upon reading a valid address
byte, the MAX1036–MAX1039 power up. The analog
circuits do not require any wakeup time from shutdown,
whether using external or internal reference.

Automatic shutdown results in dramatic power savings,
particularly at slow conversion rates. For example, at a
conversion rate of 10ksps, the average supply current
for the MAX1036 is 8µA and drops to 2µA at 1ksps.
At 0.1ksps the average supply current is just 1µA (see
Average Supply Current vs. Conversion Rate in the
Typical Operating Characteristics section).

Reference Voltage

SEL[2:0] of the setup byte (Table 1) controls the refer­ence and the AIN_/REF configuration (Table 6). When
AIN_/REF is configured to be a reference input or refer­ence output (SEL1 = 1), conversions on AIN_/REF
appear as if AIN_/REF is connected to GND (see Note
2 of Tables 3 and 4).

Internal Reference

The internal reference is 4.096V for the MAX1036/
MAX1038 and 2.048V for the MAX1037/MAX1039. SEL1
of the setup byte controls whether AIN_/REF is used for
an analog input or a reference (Table 6). When
AIN_/REF is configured to be an internal reference out­put (SEL[2:1] = 11), decouple AIN_/REF to GND with a

0.01µF capacitor. Due to the decoupling capacitor and
the 675Ω reference source impedance, allow 80µs for
the reference to stabilize during initial power-up. Once
powered up, the reference always remains on until
reconfigured. The reference should not be used to sup­ply current for external circuitry.

BIT 7

(MSB)

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

BIT 0

(LSB)

REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF

BIT NAME DESCRIPTION

7 REG Register bit. 1 = Setup Byte (Table 1), 0 = Configuration Byte.

6 SCAN1

5 SCAN0

Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at
power-up.

4 CS3

3 CS2

2 CS1

1 CS0

Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3, 4). Default to 0000 at power-up. For MAX1036/MAX1037, CS3 and CS2 are internally
set to 0.

0 SGL/DIF

1 = single-ended, 0 = pseudo-differential (Tables 3, 4). Default to 1 at power-up (see the Single-
Ended/Pseudo-Differential Input section).

Table 2. Configuration Byte Format

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

16 ______________________________________________________________________________________

B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK

NOTE: t

ACQ

+ t

CONV

≤ 7.6µs PER CHANNEL.

S

1

SLAVE ADDRESS A

711

R

CLOCK STRETCH

NUMBER OF BITS

P or Sr

1

8

RESULT

A

1

A. SINGLE CONVERSION WITH INTERNAL CLOCK

S

1

SLAVE ADDRESS

711

R

CLOCK STRETCH

A

NUMBER OF BITS

P OR Sr

1

8

RESULT 1

A

1

A

8

RESULT 2

A

8

RESULT N

SLAVE TO MASTER

MASTER TO SLAVE

t

CONV1

CLOCK STRETCH

t

ACQ1

t

CONV2

t

ACQ2

t

CONVN

t

ACQN

t

CONV

t

ACQ

1

1

Figure 10. Internal Clock Mode Read Cycles

SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N

t

CONV1

t

ACQ1

t

CONV2

t

ACQ2

t

CONVN

t

ACQN

t

CONV

t

ACQ

NUMBER OF BITS

NUMBER OF BITS

18

A

1

S

1

A

711

R

S

1

A

711

R P OR Sr

1

8

A

1

A

8

A

8

B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK

11

SLAVE ADDRESS P OR SrRESULT

A. SINGLE CONVERSION WITH EXTERNAL CLOCK

SLAVE TO MASTER

MASTER TO SLAVE

Figure 11. External Clock Mode Read Cycles

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 17

CS31CS21CS1

CS0

AIN0

AIN1

AIN2

AIN32AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

2

GN D

0000+ -

0001 + -

0010 + -

0011 + -

0100 + -

0101 + -

0110 + -

0111 + -

1000 + -

1001 +-

1010 +-

1011 +-

1 1 0 0 RESERVED

1 1 0 1 RESERVED

1 1 1 0 RESERVED

1 1 1 1 RESERVED

Table 3. Channel Selection in Single-Ended Mode (SGL / DIF = 1)

Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero.
Note 2: When SEL1 = 1, a single-ended read of AIN3/REF (MAX1036/MAX1037) or AIN11/REF (MAX1038/MAX1039) returns GND.

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

18 ______________________________________________________________________________________

CS3

1

0000+-

0001- +

0010 +-

0011 - +

0100 +-

0101 -+

0110 +-

0111 -+

1000 +-

1001 -+

1010 +-

1011 -+

1 1 0 0 RESERVED

1 1 0 1 RESERVED

1 1 1 0 RESERVED

1 1 1 1 RESERVED

Table 4. Channel Selection in Pseudo-Differential Mode (SGL / DIF = 0)

Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero.
Note 2: When SEL1 =1, a pseudo-differential read between AIN2 and AIN3/REF (MAX1036/MAX1037) or AIN10 and AIN11/REF

(MAX1038/MAX1039) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of
1011 returns the negative difference between AIN10 and GND.

Note 3: When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned,

while CS0 = 1 causes the odd-numbered channel-select bits to be scanned. For example, if the MAX1038/MAX1039
SCAN[1:0] = 00 and CS[3:0] = 1010, a differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7,
AIN8–AIN9, and AIN10–AIN11. If the MAX1038/MAX1039 SCAN[1:0] = 00 and CS[3:0] = 1011, a differential read returns
AIN1–AIN0, AIN3–AIN2, AIN5–AIN4, AIN7–AIN6, AIN9–8, and AIN11–AIN10.

CS21CS1 CS0 AIN0 AIN1 AIN2 AIN32AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11

2

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 19

External Reference

The external reference can range from 1.0V to VDD. For
maximum conversion accuracy, the reference must be
able to deliver up to 30µA and have an output imped­ance of 1kΩ or less. If the reference has a higher output
impedance or is noisy, bypass it to GND as close to
AIN_/REF as possible with a 0.1µF capacitor.

Transfer Functions

Output data coding for the MAX1036–MAX1039 is binary
in unipolar mode and two’s complement binary in bipolar
mode with 1LSB = (V

REF

/2N) where N is the number of
bits (8). Code transitions occur halfway between succes­sive-integer LSB values. Figures 12 and 13 show the
input/output (I/O) transfer functions for unipolar and bi­polar operations, respectively.

Layout, Grounding, and Bypassing

For best performance, use PC boards. Wire-wrap config­urations are not recommended since the layout should
ensure proper separation of analog and digital traces. Do
not run analog and digital lines parallel to each other, and
do not lay out digital signal paths underneath the ADC
package. Use separate analog and digital PC board
ground sections with only one star point (Figure 14) con-

necting the two ground systems (analog and digital). For
lowest noise operation, ensure the ground return to the
star ground’s power supply is low impedance and as
short as possible. Route digital signals far away from sen­sitive analog and reference inputs.

High-frequency noise in the power supply (V

DD

) could
influence the proper operation of the ADC’s fast
comparator. Bypass V

DD

to the star ground with a

0.1µF capacitor located as close as possible to the
MAX1036–MAX1039 power-supply pin. Minimize
capacitor lead length for best supply-noise rejection,
and add an attenuation resistor (5Ω) if the power sup­ply is extremely noisy.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The INL
is measured using the endpoint method.

SCAN1 SCAN0 SCANNING CONFIGURATION

0 0 Scans up from AIN0 to the input selected by CS3–CS0 (default setting).

0 1 Converts the input selected by CS3–CS0 eight times.*

Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for
AIN0–AIN2, the scanning stops at AIN2 (MAX1036/MAX1037).

10

Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6
scanning stops at AIN6 (MAX1038/MAX1039).

1 1 Converts the channel selected by CS3–CS0.*

Table 5. Scanning Configuration

*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues
until a not acknowledge occurs.

SEL2

SEL1

SEL0

REFERENCE VOLTAGE AIN_/REF

INTERNAL REFERENCE

STATE

00XV

DD

Analog input Always Off

0 1 X External reference Reference input Always Off

1 0 0 Internal reference Analog input Auto Shutdown

1 0 1 Internal reference Analog input Always On

1 1 X Internal reference Reference output Always On

Table 6. Reference Voltage and AIN_/REF Format

X = Don’t care.

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

20 ______________________________________________________________________________________

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam­ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog­to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):

SNR = (6.02

✕

N + 1.76)dB

INPUT VOLTAGE (LSB)

OUTPUT CODE

1...111

1...110

1...101

1...100

0...000

0...001

0...010

0...011

23

256

V

REF

1LSB =

1 253 255254

REF

2560 252

Figure 12. Unipolar Transfer Function

INPUT VOLTAGE (LSB)

OUTPUT CODE

(TWO'S COMPLEMENT)

0...111

0...110

0...101

0...100

1...000

1...001

1...010

1...011

-1-126 -125

256

V

REF

1LSB =

0+1-127 +125 +127+126

0...000

0...001

1...111

REF

+128-128 +124

'-' INPUT

Figure 13. Bipolar Transfer Function

3V/5V

V

LOGIC

= 3V/5V

GND

SUPPLIES

DGND3V/5V

GND

0.1µF

V

DD

DIGITAL

CIRCUITRY

MAX1036
MAX1037
MAX1038
MAX1039

R* = 5Ω

*OPTIONAL

Figure 14. Power-Supply and Grounding Connections

In reality, there are other noise sources besides quanti­zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen­tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.

SINAD (dB) = 20 ✕log (Signal

RMS

/ Noise

RMS

)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti­zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:

ENOB = (SINAD - 1.76) / 6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun­damental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo­nent) to the RMS value of the next-largest distortion
component.

Chip Information

MAX1036/MAX1037 TRANSISTOR COUNT: 6283

MAX1038/MAX1039 TRANSISTOR COUNT: 7257

PROCESS: BiCMOS

THD VVVV V=

×

+++

























20

2

2

3

2

4

2

5

2

1

log /

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

______________________________________________________________________________________ 21

SDA

SCLAIN3/REF

1

2

87V

DD

GNDAIN1

AIN2

AIN0

SOT23

TOP VIEW

3

4

6

5

MAX1036
MAX1037

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

AIN7 AIN8

AIN9

AIN10

AIN11/REF

V

DD

GND

SDA

SCL

MAX1038
MAX1039

QSOP

AIN6

AIN5

AIN2

AIN4

AIN3

AIN1

AIN0

Pin Configurations

*OPTIONAL

*R

S

*R

S

ANALOG

INPUTS

µC

SDA

SCL

GND

V

DD

SDA

SCL

AIN0
AIN1
AIN2
AIN3/REF

5V

5V

R

P

R

P

5V

MAX1036
MAX1037
MAX1038
MAX1039

Typical Operating Circuit

MAX1036–MAX1039

2.7V to 5.5V, Low-Power, 4-/12-Channel
2-Wire Serial 8-Bit ADCs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

SOT23, 8L.EPS

QSOP.EPS