MAXIM MAX101 Technical data

查询MAX101CFR供应商

19-0296; Rev 0; 8/94

EVALUATION KIT MANUAL

AVAILABLE

500Msps, 8-Bit ADC with Track/Hold

_______________General Description

The MAX101 ECL-compatible, 500Msps, 8-bit analog­to-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequen­cy). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time inter­leaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101 contains a high-perfor­mance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.

The innovative design of the internal T/H assures an
exceptionally wide 1.2GHz input bandwidth and aper­ture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 1015clock cycles. And, unlike
other ADCs that can have errors resulting in false full­scale or zero-scale outputs, the MAX101 keeps the error
magnitude to less than 1LSB.

The analog input is designed for either differential or
single-ended use with a ±270mV range. Sense pins for
the reference input allow full-scale calibration of the

____________________________Features

♦ 500Msps Conversion Rate
♦ 7.0 Effective Bits Typical at 250MHz
♦ 1.2GHz Analog Input Bandwidth
♦ Less than ±1/2LSB INL
♦ 50Ω Differential or Single-Ended Inputs
♦ ±270mV Input Signal Range
♦ Ratiometric Reference Inputs
♦ Dual Latched Output Data Paths

-15

♦ Low Error Rate, Less than 10

Metastable States

♦ 84-Pin Ceramic Flat Pack

________________________Applications

High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications

input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative

sampling of the converter halves for optimizing convert­er performance. Input clock phasing is also available
for interleaving several MAX101s for higher effective
sampling rates.

______________Ordering Information

PART

MAX101CFR* 0°C to +70°C

*Contact factory for 84-pin ceramic flat pack without heatsink.

TEMP. RANGE PIN-PACKAGE

84 Ceramic Flat Pack
(with heatsink)

_________________________________________________________Functional Diagram

MAX101

VA

RTVARTS VA

MAX101

AIN+
AIN-

CLK
CLK

TRK1

TRACK

AND

HOLD

PH

VB

TRK1

ADJ

________________________________________________________________

VB

RT

RTS

FLASH CONVERTER

(8 -BIT)

FLASH CONVERTER

(8 -BIT)

Call toll free 1-800-998-8800 for free literature.

VA

RBS

RB

STROBESTROBE

VB

VB

RB

RBS

Maxim Integrated Products

L
A
T
C
H

8 8

E
S

B
U
F
F
E
R



8 8

L
A
T
C
H
E
S

ADATA

DCLK
DCLK

BDATA

1

500Msps, 8-Bit ADC with Track/Hold

ABSOLUTE MAXIMUM RATINGS

Supply Voltages

...........................................................................0V to +7V

V

CC

.............................................................................-7V to 0V

V

EE

- VEE.........................................................................+12V

V

CC

Analog Input Voltage.............................................................±2V

Reference Voltage (VA
Reference Voltage (VA

MAX101

Clock Input Voltage (V

, VBRT)...........................-0.3V to +1.5V

RT

, VBRB)..........................-1.5V to +0.3V

RB

, VIL).....................................-2.3V to 0V

IH

Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage

may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.

Note 2: Typical thermal resistance, junction-to-case R

=12°C/W, if 200 lineal ft/min airflow is provided. See

R

θJA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

= 5°C/W and thermal resistance, junction to ambient (MAX101CFR)

θJC

ELECTRICAL CHARACTERISTICS

(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.

to T

T

MIN

ACCURACY

DYNAMIC SPECIFICATIONS

Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
Aperture Jitter

ANALOG INPUT

Input Voltage Range
Input Offset Voltage

Least Significant Bit Size
Input Resistance
Input Resistance

Temperature Coefficient

= 0°C to +70°C. Note 3)

MAX

AData, BData

INLIntegral Nonlinearity (Note 4)

AData, BData,

DNLDifferential Nonlinearity

no missing codes

f

= 500MHz,

CLK

ENOBEffective Bits

VIN= 95% full scale
(Note 5)

f

= 125MHz, f

AIN

VIN= 95% full scale (Note 6)
(Note 7)

CLK

3dB

Figure 4

AW

Figure 4

AJ

AIN+ to AIN-, Table 2,

V

IN

TA= T
AIN+, AIN-, TA= T

IO

TA= T
AIN+, AIN-, to GND

I

MIN

MIN

to T

to T

DIV10 Input Voltage (VIH, VIL).......................................VEEto 0V

Output Current, (I

<100°C.......................................................................14mA

T

J

100°C < T

Operating Temperature Range...............................0°C to +70°C

max)

O

<125°C.........................................................12mA

J

Operating Junction Temperature (Note 2)............0°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+250°C

Package Information.

CONDITIONS

TA= T

MIN

to T

MAX

TA= +25°C

CLK

MAX

MAX

TA= T

f

AIN

f

AIN

f

AIN

= 500MHz,

Full scale
Zero scale

to T

MIN

MIN

= 10MHz
= 125MHz
= 250MHz

MAX

to T

MAX

7.6

6.7 7.0

230 315

-305 -215

UNITSMIN TYP MAXSYMBOLPARAMETER

±0.50TA= +25°C
±0.75
±0.75
±0.85

Bits8Resolution

LSB

LSB

Bits7.1

dB44.5SNRSignal-to-Noise Ratio

Msps500f

GHz1.2BW

ps270t
ps2t

mV
mV-17 32V

mV1.8 2.5LSB

Ω49 51R

Ω/°C0.008

2 _______________________________________________________________________________________

500Msps, 8-Bit ADC with Track/Hold

ELECTRICAL CHARACTERISTICS (continued)

(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.

to T

T

MIN

REFERENCE INPUT

Reference String Resistance
Reference String Resistance

Temperature Coefficient

LOGIC INPUTS

Digital Input Low Voltage

Digital Input High Voltage

Digital Input High Current

Input Bias Current I

Clock Input Bias Current I

LOGIC OUTPUTS (Note 8)

Digital Output Low Voltage
Digital Output Low Voltage

Digital Output High Voltage

Digital Output Voltage

POWER REQUIREMENTS

Positive Supply Current

Negative Supply Current

Power-Supply Rejection Ratio PSRR

= 0°C to +70°C. Note 3)

MAX

OH

CLK

V

V

I

VCC

I

VEE

REF

IL

IH

I

IH

B

OL

OH

- V

OL

CONDITIONS

VARTto VA

RB

CLK, CLK

CLK, CLK V-1.1V

DIV10 = 0V

PH

= 0V

ADJ

CLK, CLK = -0.8V
(no termination)

AData, BData

DCLK, DCLK

AData, BData,
DCLK, DCLK

DCLK, DCLK mV275 445V

VCC= 5.0V

VEE= -5.2V
V

= ±0.5V TA= T

INCM

VCC(nom) = ±0.25V
VEE(nom) = ±0.25V

TA= T

MIN

TA= T

MIN

TA= T

MIN

TA= T

MIN

TA= T

MIN

TA= T

MIN

TA= T

MIN

TA= +25°C
TA= T

MIN

TA= T

MIN

TA= +25°C
TA= T

MIN

TA= +25°C
TA= T

MIN
MIN

TA= T

MIN

to T

to T

to T

to T

to T

to T

to T

to T
to T

to T

to T
to T

to T

MAX

MAX

MAX

MAX

MAX

MAX

MAX

MAX

MAX

MAX

MAX
MAX

MAX

1.1 3.1

40

50

-1.95 -1.60TA= +25°C

-1.95 -1.50

-1.3 -1.00TA= +25°C

-1.4 -0.9

-1.02 -0.70

-1.10 -0.60

550 765 1065

1130

-935 -750 -525

-975

40
40

MAX101

UNITSMIN TYP MAXSYMBOLPARAMETER

Ω100 175R

Ω/°C0.02

V-1.50V

mA

µA

µA

V

V

mA

mA

dBCMRRCommon-Mode Rejection Ratio 35
dB

_______________________________________________________________________________________ 3

500Msps, 8-Bit ADC with Track/Hold

TIMING CHARACTERISTICS

(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)

CONDITIONS

Clock Pulse Width Low
Clock Pulse Width High
CLK to DCLK

Propagation Delay

MAX101

DCLK to A/BData
Propagation Delay

Rise Time

Fall Time
Pipeline Delay

(Latency)

Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for T
Note 4: Deviation from best-fit straight line. See
Note 5: See the

Signal-to-Noise Ratio and Effective Bits

Note 6: SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Note 7: Clock pulse width minimum requirements t
Note 8: Outputs terminated through 100Ω to -2.0V.

__________________________________________Typical Operating Characteristics

(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY 

0.75

0.50

0.25

vs. OUTPUT CODE

CLK, CLK

PWL

CLK, CLK

PWH

DIV10 = 0, Figures 1, 2

PD1

DIV10 = 0, Figures 1, 2

PD2

20% to 80%

t

R

20% to 80% ps

t

F

See Figures 2, 3

t

NPD

and Table 1

Integral Nonlinearity

section in the

and t

PWL

DCLK
DATA
DCLK
DATA

Divide-by-1 mode

section.

Detailed Description of Specifications

must be observed to achieve stated performance.

PWH

0.7 1.3 1.8t
400

850
400
700

15 15

= T

to T

A

MIN

DIFFERENTIAL NONLINEARITY 

vs. OUTPUT CODE

MAX101 TOC1

0.75

0.50

0.25

as specified.

MAX

.

UNITSMIN TYP MAXSYMBOLPARAMETER

ns0.9 2.5t
ns0.9 2.5t

ns1.2 2.3 3.4t

ns

ps

Clock

Cycles

MAX101 TOC2

0

INL (LSBs)

-0.25

-0.50

-0.75
0 256

64 192128

OUTPUT CODE

0

DNL (LSBs)

-0.25

-0.50

-0.75
0 256

64 192128

OUTPUT CODE

4 _______________________________________________________________________________________

500Msps, 8-Bit ADC with Track/Hold

____________________________Typical Operating Characteristics (continued)

(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)

FFT PLOT

(f

= 251.4462MHz)

0

-10

-20

-30

-40

-50

(dB)

-60

-70

-80

-90

-100
0 50 75 100 125

AIN

f

= 500MHz,

CLK

SER = -44.5dB,
NOISE FLOOR = -67.3dB,
SPURIOUS = -58.2dB

25

(MHz)

EFFECTIVE BITS vs. ANALOG INPUT

8

7

EFFECTIVE BITS

FREQUENCY (f

(f

= 500MHz, VIN = 95% FS)

CLK

AIN

0

MAX101 TOC3

-10

-20

-30

-40

-50

(dB)

-60

-70

-80

-90

-100
0 25 37.5 50 62.5

12.5

) 

(f

8

MAX110 TOC5



7

EFFECTIVE BITS

FFT PLOT

(f

= 10.4462MHz)

AIN

f

= 250MHz,

CLK

SER = -47.2dB,
NOISE FLOOR = -70.5dB,
SPURIOUS = -61.8dB

(MHz)

EFFECTIVE BITS vs. CLOCK

FREQUENCY (f

= 500MHz, VIN = 95% FS)

AIN

CLK

)

MAX101 TOC4

MAX110 TOC6

MAX101

6

100 150 200 250 300

500

f

(MHz)

AIN

_______________________________________________________________________________________

6

200 300 400 500 600

1000

f

(MHz)

CLK

5