查询MAX101CFR供应商
19-0296; Rev 0; 8/94
EVALUATION KIT MANUAL
AVAILABLE
500Msps, 8-Bit ADC with Track/Hold
_______________General Description
The MAX101 ECL-compatible, 500Msps, 8-bit analogto-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequency). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time interleaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101 contains a high-performance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
The innovative design of the internal T/H assures an
exceptionally wide 1.2GHz input bandwidth and aperture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 1015clock cycles. And, unlike
other ADCs that can have errors resulting in false fullscale or zero-scale outputs, the MAX101 keeps the error
magnitude to less than 1LSB.
The analog input is designed for either differential or
single-ended use with a ±270mV range. Sense pins for
the reference input allow full-scale calibration of the
____________________________Features
♦ 500Msps Conversion Rate
♦ 7.0 Effective Bits Typical at 250MHz
♦ 1.2GHz Analog Input Bandwidth
♦ Less than ±1/2LSB INL
♦ 50Ω Differential or Single-Ended Inputs
♦ ±270mV Input Signal Range
♦ Ratiometric Reference Inputs
♦ Dual Latched Output Data Paths
-15
♦ Low Error Rate, Less than 10
Metastable States
♦ 84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications
input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing converter performance. Input clock phasing is also available
for interleaving several MAX101s for higher effective
sampling rates.
______________Ordering Information
PART
MAX101CFR* 0°C to +70°C
*Contact factory for 84-pin ceramic flat pack without heatsink.
TEMP. RANGE PIN-PACKAGE
84 Ceramic Flat Pack
(with heatsink)
_________________________________________________________Functional Diagram
MAX101
VA
RTVARTS VA
MAX101
AIN+
AIN-
CLK
CLK
TRK1
TRACK
AND
HOLD
PH
VB
TRK1
ADJ
________________________________________________________________
VB
RT
RTS
FLASH CONVERTER
(8 -BIT)
FLASH CONVERTER
(8 -BIT)
Call toll free 1-800-998-8800 for free literature.
VA
RBS
RB
STROBESTROBE
VB
VB
RB
RBS
Maxim Integrated Products
L
A
T
C
H
8 8
E
S
B
U
F
F
E
R
8 8
L
A
T
C
H
E
S
ADATA
DCLK
DCLK
BDATA
1
500Msps, 8-Bit ADC with Track/Hold
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
...........................................................................0V to +7V
V
CC
.............................................................................-7V to 0V
V
EE
- VEE.........................................................................+12V
V
CC
Analog Input Voltage.............................................................±2V
Reference Voltage (VA
Reference Voltage (VA
MAX101
Clock Input Voltage (V
, VBRT)...........................-0.3V to +1.5V
RT
, VBRB)..........................-1.5V to +0.3V
RB
, VIL).....................................-2.3V to 0V
IH
Note 1: The digital control inputs are diode protected. However, limited protection is provided on other pins. Permanent damage
may occur on unconnected units under high-energy electrostatic fields. Keep unused units in supplied conductive carrier or
shunt the terminals together.
Note 2: Typical thermal resistance, junction-to-case R
=12°C/W, if 200 lineal ft/min airflow is provided. See
R
θJA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
= 5°C/W and thermal resistance, junction to ambient (MAX101CFR)
θJC
ELECTRICAL CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.
to T
T
MIN
ACCURACY
DYNAMIC SPECIFICATIONS
Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Offset Voltage
Least Significant Bit Size
Input Resistance
Input Resistance
Temperature Coefficient
= 0°C to +70°C. Note 3)
MAX
AData, BData
INLIntegral Nonlinearity (Note 4)
AData, BData,
DNLDifferential Nonlinearity
no missing codes
f
= 500MHz,
CLK
ENOBEffective Bits
VIN= 95% full scale
(Note 5)
f
= 125MHz, f
AIN
VIN= 95% full scale (Note 6)
(Note 7)
CLK
3dB
Figure 4
AW
Figure 4
AJ
AIN+ to AIN-, Table 2,
V
IN
TA= T
AIN+, AIN-, TA= T
IO
TA= T
AIN+, AIN-, to GND
I
MIN
MIN
to T
to T
DIV10 Input Voltage (VIH, VIL).......................................VEEto 0V
Output Current, (I
<100°C.......................................................................14mA
T
J
100°C < T
Operating Temperature Range...............................0°C to +70°C
max)
O
<125°C.........................................................12mA
J
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+250°C
Package Information.
CONDITIONS
TA= T
MIN
to T
MAX
TA= +25°C
CLK
MAX
MAX
TA= T
f
AIN
f
AIN
f
AIN
= 500MHz,
Full scale
Zero scale
to T
MIN
MIN
= 10MHz
= 125MHz
= 250MHz
MAX
to T
MAX
7.6
6.7 7.0
230 315
-305 -215
UNITSMIN TYP MAXSYMBOLPARAMETER
±0.50TA= +25°C
±0.75
±0.75
±0.85
Bits8Resolution
LSB
LSB
Bits7.1
dB44.5SNRSignal-to-Noise Ratio
Msps500f
GHz1.2BW
ps270t
ps2t
mV
mV-17 32V
mV1.8 2.5LSB
Ω49 51R
Ω/°C0.008
2 _______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
ELECTRICAL CHARACTERISTICS (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.
to T
T
MIN
REFERENCE INPUT
Reference String Resistance
Reference String Resistance
Temperature Coefficient
LOGIC INPUTS
Digital Input Low Voltage
Digital Input High Voltage
Digital Input High Current
Input Bias Current I
Clock Input Bias Current I
LOGIC OUTPUTS (Note 8)
Digital Output Low Voltage
Digital Output Low Voltage
Digital Output High Voltage
Digital Output Voltage
POWER REQUIREMENTS
Positive Supply Current
Negative Supply Current
Power-Supply Rejection Ratio PSRR
= 0°C to +70°C. Note 3)
MAX
OH
CLK
V
V
I
VCC
I
VEE
REF
IL
IH
I
IH
B
OL
OH
- V
OL
CONDITIONS
VARTto VA
RB
CLK, CLK
CLK, CLK V-1.1V
DIV10 = 0V
PH
= 0V
ADJ
CLK, CLK = -0.8V
(no termination)
AData, BData
DCLK, DCLK
AData, BData,
DCLK, DCLK
DCLK, DCLK mV275 445V
VCC= 5.0V
VEE= -5.2V
V
= ±0.5V TA= T
INCM
VCC(nom) = ±0.25V
VEE(nom) = ±0.25V
TA= T
MIN
TA= T
MIN
TA= T
MIN
TA= T
MIN
TA= T
MIN
TA= T
MIN
TA= T
MIN
TA= +25°C
TA= T
MIN
TA= T
MIN
TA= +25°C
TA= T
MIN
TA= +25°C
TA= T
MIN
MIN
TA= T
MIN
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
to T
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
1.1 3.1
40
50
-1.95 -1.60TA= +25°C
-1.95 -1.50
-1.3 -1.00TA= +25°C
-1.4 -0.9
-1.02 -0.70
-1.10 -0.60
550 765 1065
1130
-935 -750 -525
-975
40
40
MAX101
UNITSMIN TYP MAXSYMBOLPARAMETER
Ω100 175R
Ω/°C0.02
V-1.50V
mA
µA
µA
V
V
mA
mA
dBCMRRCommon-Mode Rejection Ratio 35
dB
_______________________________________________________________________________________ 3
500Msps, 8-Bit ADC with Track/Hold
TIMING CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)
CONDITIONS
Clock Pulse Width Low
Clock Pulse Width High
CLK to DCLK
Propagation Delay
MAX101
DCLK to A/BData
Propagation Delay
Rise Time
Fall Time
Pipeline Delay
(Latency)
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for T
Note 4: Deviation from best-fit straight line. See
Note 5: See the
Signal-to-Noise Ratio and Effective Bits
Note 6: SNR calculated from effective bits performance using the following equation: SNR(dB) = 1.76 + 6.02 x effective bits.
Note 7: Clock pulse width minimum requirements t
Note 8: Outputs terminated through 100Ω to -2.0V.
__________________________________________Typical Operating Characteristics
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
0.75
0.50
0.25
vs. OUTPUT CODE
CLK, CLK
PWL
CLK, CLK
PWH
DIV10 = 0, Figures 1, 2
PD1
DIV10 = 0, Figures 1, 2
PD2
20% to 80%
t
R
20% to 80% ps
t
F
See Figures 2, 3
t
NPD
and Table 1
Integral Nonlinearity
section in the
and t
PWL
DCLK
DATA
DCLK
DATA
Divide-by-1 mode
section.
Detailed Description of Specifications
must be observed to achieve stated performance.
PWH
0.7 1.3 1.8t
400
850
400
700
15 15
= T
to T
A
MIN
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX101 TOC1
0.75
0.50
0.25
as specified.
MAX
.
UNITSMIN TYP MAXSYMBOLPARAMETER
ns0.9 2.5t
ns0.9 2.5t
ns1.2 2.3 3.4t
ns
ps
Clock
Cycles
MAX101 TOC2
0
INL (LSBs)
-0.25
-0.50
-0.75
0 256
64 192128
OUTPUT CODE
0
DNL (LSBs)
-0.25
-0.50
-0.75
0 256
64 192128
OUTPUT CODE
4 _______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)
FFT PLOT
(f
= 251.4462MHz)
0
-10
-20
-30
-40
-50
(dB)
-60
-70
-80
-90
-100
0 50 75 100 125
AIN
f
= 500MHz,
CLK
SER = -44.5dB,
NOISE FLOOR = -67.3dB,
SPURIOUS = -58.2dB
25
(MHz)
EFFECTIVE BITS vs. ANALOG INPUT
8
7
EFFECTIVE BITS
FREQUENCY (f
(f
= 500MHz, VIN = 95% FS)
CLK
AIN
0
MAX101 TOC3
-10
-20
-30
-40
-50
(dB)
-60
-70
-80
-90
-100
0 25 37.5 50 62.5
12.5
)
(f
8
MAX110 TOC5
7
EFFECTIVE BITS
FFT PLOT
(f
= 10.4462MHz)
AIN
f
= 250MHz,
CLK
SER = -47.2dB,
NOISE FLOOR = -70.5dB,
SPURIOUS = -61.8dB
(MHz)
EFFECTIVE BITS vs. CLOCK
FREQUENCY (f
= 500MHz, VIN = 95% FS)
AIN
CLK
)
MAX101 TOC4
MAX110 TOC6
MAX101
6
100 150 200 250 300
500
f
(MHz)
AIN
_______________________________________________________________________________________
6
200 300 400 500 600
1000
f
(MHz)
CLK
5
500Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(VEE= -5.2V, VCC= +5V, RL= 100Ω to -2V, VART, VBRT= 1.02V, VARB, VBRB= -1.02V, TA= +25°C, unless otherwise noted.)
MAX101
-550mV
100mV/div
-1.55V
-825mV
100mV/div
DATA CLOCK (DCLK)
RISE TIME (526ps), DIV10 = OPEN
-4.18ns 5.2ns
BDATA RISE TIME (855ps),
DIV10 = OPEN
MAX101 TOC7
MAX101 TOC9
DATA CLOCK (DCLK) FALL TIME
(352ps), DIV10 = OPEN
-550mV
MAX101 TOC8
100mV/div
-1.55V
-4.18ns 5.2ns
BDATA FALL TIME (714ps),
DIV10 = OPEN
-825mV
MAX101 TOC10
100mV/div
-1.825V
-4.98ns 5.02ns
-1.825V
-4.98ns 5.02ns
6 _______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
______________________________________________________________Pin Description
PIN
1 PAD Internal connection, leave open.
2, 62 CLK
3, 61 CLK
4, 7, 15, 18,
24, 27, 30,
34, 37, 40,
46, 49, 57,
60, 64, 67,
68, 70, 71,
74, 77, 78,
79, 82, 84
5, 59 TRK1
6, 58 TRK1
8, 21, 43,
56, 81
9 VB
10 VB
11 TP4 Internal connection, leave pin open.
12 TP3
13 VB
14 VB
16, 48, 63 N.C.
29 SUB
31 DCLK
33 DCLK
32, 69, 80 VEE
35
36, 38, 39,
41, 42, 44,
45, 47
28, 26, 25,
23, 22, 20,
19, 17
NAME FUNCTION
Complementary Differential Clock Inputs. Can be driven from standard 10KH ECL with the following
considerations: Internally, pins 2, 62 and 3, 61 are the ends of a 50Ω transmission line. Either end
can be driven with the other end terminated with 50Ω to -2V. See
GND Power-Supply Ground
Phasing inputs (normally left open). See
VCC Positive Power Supply, +5V ±5% nominal
“B” side negative reference voltage input (Note 9)
RB
“B” side negative reference voltage sense (Note 9)
RBS
Internal connection, leave pin open.
“B” side positive reference voltage sense (Note 9)
RTS
“B” side positive reference voltage input (Note 9)
RT
No Connect—no internal connection to these pins.
Circuit Substrate contact. This pin must be connected to VEE.
Complementary Differential Clock Outputs. Used to synchronize following circuitry: Outputs A0–A7
are valid after DCLK’s rising edge. B0–B7 output data are valid after DCLK’s falling edge (see Figure 1
for output timing information).
Negative Power Supply, -5.2V ±5% nominal
DIV10 Divide by 10 mode. Leave open for normal operation. Selects test mode when grounded.
A7–A0
B7–B0
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to ECL logic swings and drive 100Ω transmission lines. Terminate with 100Ω to -2V
(120Ω for Tj > +100°C). See Figures 1–3.
Applications Information
Typical Operating Circuit
section.
.
MAX101
_______________________________________________________________________________________ 7
500Msps, 8-Bit ADC with Track/Hold
_________________________________________________Pin Description (continued)
NAME FUNCTIONPIN
50 VA
51 VA
MAX101
52 TP1 Internal connection, leave pin open.
53 TP2 Internal connection, leave pin open.
54 VA
55 VA
65 TP5 Internal connection, leave pin open.
66 TP6 Internal connection, leave pin open.
72, 73 AIN+
75, 76 AIN-
83 PH
Note 9: VART, VARB, VBRT, and VBRBshould be adjusted separately from a well bypassed reference circuit to ensure proper
amplitude and offset matching. The sense connections to each of these terminals allows precision setting of the reference
voltage. The reference ladder is similar for both converter halves (check electrical section for values). Any noise on these
terminals will severely reduce overall performance.
Note 10: Good results are obtained by connecting the PH
±1.25V to this input. The time that the “A” T/H bridge samples relative to the time that the “B” T/H bridge samples can be
varied through a ±18ps range.
“A” side positive reference voltage input (Note 9)
RT
“A” side positive reference voltage sense (Note 9)
RTS
“A” side negative reference voltage sense (Note 9)
RBS
“A” side negative reference voltage input (Note 9)
RB
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Phase adjustment for T/H. Normally connected to ground. A phase adjustment of approximately ±18ps
ADJ
can be made by varying this pin’s bias point to optimize interleaving between sides A and B (Note 10).
input to ground. Improve performance by applying a voltage between
ADJ
CLK
CLK
DCLK
DCLK
ADATA
BDATA
t
PD2
t
t
PWH
t
PD1
t
PWL
PD2
Figure 1. Output Timing, Normal Mode, DIV10 = OPEN
8 _______________________________________________________________________________________
CLK
DCLK
500Msps, 8-Bit ADC with Track/Hold
N–1
N
N+2 +14 +15 +16 +17
N+1
01 7 8
MAX101
ADATA
BDATA
t
PD2
t
PD2
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE
INPUT CLOCK PHASING
Figure 2. Output Timing, Clock to Data, Normal Mode DIV10 = OPEN
CLK
DCLK
ADATA
BDATA
N
N+2 N+3 +15 +16 +17
N+1
N-1 N+3
N-2 N N+2
.
N+1
N
N+5
NOTE: DATA ARBITRARY ON START-UP FOR SIDE A OR B, SEE
Figure 3. Output Timing, Test Mode (DIV10 = GND)
_______________________________________________________________________________________ 9
INPUT CLOCK PHASING
.
500Msps, 8-Bit ADC with Track/Hold
______Definitions of Specifications
Signal-to Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency to the
RMS amplitude of all other analog-to-digital (A/D) output signals. The theoretical minimum A/D noise is
caused by quantization error and is a direct result of
MAX101
the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N
is the number of effective bits of resolution. Therefore, a
perfect 8-bit ADC can do no better than 50dB. The FFT
plots in the
Typical Operating Characteristics
output level in various spectral bands.
Effective bits is calculated from a digital record taken
from the ADC under test. The quantization error of the
ideal converter equals the total error of the device. In
addition to ideal quantization error, other sources of
error include all DC and AC nonlinearities, clock and
aperture jitter, missing output codes, and noise. Noise
on references and supplies also degrades effective bits
performance.
The ADC’s input is a sine wave filtered with an antialiasing filter to remove any harmonic content. The digital record taken from this signal is compared against a
mathematically generated sine wave. DC offsets,
phase, and amplitudes of the mathematical model are
adjusted until a best-fit sine wave is found. After subtracting this sine wave from the digital record, the residual error remains. The rms value of the error is applied
in the following equation to yield the ADC’s effective
bits.
Effective bits = N - log2—————————-
measured rms error
ideal rms error
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the converter’s maximum clock rate with the analog input near
the Nyquist rate (one-half the input clock rate).
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 4).
Error Rates
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
show the
CLK
CLK
ANALOG
INPUT
t
AD
SAMPLED
DATA (T/H)
TRACK
T/H
Figure 4. T/H Aperture Timing
typical converters can be incorrect, including false fullor zero-scale output. The MAX101’s unique design
reduces the magnitude of this type of error to 1LSB,
and reduces the probability of the error occurring to
less than one in every 10
were operated at 500MHz, 24 hours a day, this would
translate to less than one metastable state error every
46 days.
Integral nonlinearity is the deviation of the transfer function from a reference line measured in fractions of 1LSB
using a “best straight line” determined by a least
square curve fit.
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
DNL(LSB) = ——————————————-
where V
MEAS - 1
is the measured value of the previous
code.
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
t
AW
t
AJ
TRACKHOLD
APERTURE DELAY (t
APERTURE WIDTH (tAW)
APERTURE JITTER (tAJ)
15
AD)
clock cycles. If the MAX101
Integral Nonlinearity
Differential Nonlinearity
[V
MEAS
- (V
MEAS - 1
)] - LSB
LSB
10 ______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
_______________Detailed Description
Converter Operation
The parallel or “flash” architecture used by the MAX101
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash, as
with all other ADC architectures, is the comparator, which
has a positive input, a negative input, and an output. If
the voltage at the positive input is higher than the negative input (connected to a reference), the output will be
high. If the positive input voltage is lower than the reference, the output will be low. A typical n-bit flash consists
of 2n - 1 comparators with negative inputs evenly spaced
at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there are 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1 and all comparators
with negative inputs above the input voltage will have
outputs of 0. Decode logic is provided to convert this
information into a parallel n-bit digital word (the output)
corresponding to the number of LSBs (minus 1) that the
input voltage is above the bottom of the ladder.
The comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described previously when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
The MAX101 uses a monolithic dual interleaved parallel
quantizer chip with two separate 8-bit converters.
These converters deliver results to the A and B output
latches on alternate negative edges of the input clock.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will decrease. The MAX101 has an internal
track/hold (T/H) that increases attainable effective bits
performance and allows more accurate capture of analog data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX101:
1) Its nominal voltage gain of 4 reduces the input driving signal to ±270mV differential (assuming a
±1.02V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX101.
Table 1. Output Mode Control
DCLK*
DIV10
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In
(MHz)
OPEN 250
GND 50
all modes, the output clock DCLK will be a 50% duty cycle signal.
MODE
Normal
Divide
by 2
Test
Divide
by 10
DESCRIPTION
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall).
AData and BData valid on opposite DCLK edges (AData on rise,
BData on fall). Data sampled at
input CLK rate but 4 out of every
5 samples discarded.
Data Flow
The MAX101’s internal T/H amplifier samples the analog
input voltage for the ADC to convert. The T/H is split into
two sections that operate on alternate negative clock
edges. The input clock, CLK, is conditioned by the T/H
and fed to the A/D section. The output clock, DCLK,
used for output data timing, will be divided by 2 or 10
from the input clock, CLK (Table 1). This would result in
an output data rate of 250Mbps on each output port in
normal mode and 50Mbps in test mode. The differential
inputs, AIN+ and AIN-, are tracked continuously
between data samples. When a negative strobe edge is
sensed, one-half of the T/H goes into the hold mode
(Figure 4). When the strobe is low, the just-acquired
sample is presented to the ADC’s input comparators.
Internal processing of the sampled data takes an additional 15 clock cycles before it is available at the outputs, AData and BData. See Figures 1–3 for timing.
__________Applications Information
Although the normal operating range is ±270mV, the
MAX101 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain full-scale digital output with differential
input drive, a nominal +270mV must be applied
between AIN+ and AIN-. That is, AIN+ = +135mV and
AIN- = -135mV (with no DC offset). Mid-scale digital
output code occurs when there is no voltage difference
across the analog inputs. Zero-scale digital output
code, with differential -270mV drive, occurs when AIN+
= -135mV and AIN- = +135mV. Table 2 shows how the
output of the converter stays at all ones (full scale)
when over-ranged or all zeros (zero scale) when underranged.
Analog Input Ranges
MAX101
______________________________________________________________________________________ 11
500Msps, 8-Bit ADC with Track/Hold
Table 2. Input Voltage Range
INPUT
Differential 0 0 1 0 0 0 0 0 0 0 mid scale
MAX101
Single
Ended
* An offset VIO, as specified in the DC electrical paramters, will be
present at the input. Compensate for this offset by adjusting the
reference voltage. Offsets may be different between side A and
side B.
AIN+
(mV)
+135 -135 1 1 1 1 1 1 1 1 full scale
-135 +135 0 0 0 0 0 0 0 0 zero scale
+270 0 1 1 1 1 1 1 1 1 full scale
-270 0 0 0 0 0 0 0 0 0 zero scale
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are terminated internally with 50Ω to analog ground.)
2) Drive the other input with a ±270mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
The ADC’s reference resistor is a Kelvin-sensed, resistor string that sets the ADC’s LSB size and dynamic
operating range. Normally, the top and bottom of this
string are driven with an external buffer amplifier. It will
need to supply approximately 21mA due to the 100Ω
minimum resistor string impedance. A ±1.02V reference voltage is normally applied to inputs VART, VBRT,
VARB, and VBRB. This reference voltage can be adjusted up to ±1.2V to accommodate extended input
requirements (accuracy specifications are guaranteed
with ±1.02V references). The reference inputs VA
VA
, VB
RTS
, and VB
RBS
applied voltages to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the buffer output that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the buffer’s output
(see
Typical Operating Circuit
capacitor combination should be located within 0.5
inches of the MAX101 package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective bits performance.
AIN-
(mV)
0 0 1 0 0 0 0 0 0 0 mid scale
OUTPUT
CODE
MSB to
LSB
Reference
allow Kelvin sensing of the
RBS
RTS
). This resistor and
VA
VA
RTS
,
VA
RBS
VA
Figure 5. Reference Ladder
RT
RB
POSITIVE
REFERENCE
NEGATIVE
REFERENCE
PARASITIC
RESISTANCE
R
TO
COMPARATORS
R
R
R
R
PARASITIC
RESISTANCE
12 ______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing signals for the MAX101. CLK (pins 2, 62) and CLK (pins 3,
61) are fed to the internal circuitry through an internal
50Ω transmission line. One set of CLK, CLK inputs
should be driven and the other pair terminated by 50Ω
to -2V. Either set of inputs can be used as the driven
inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (t
CLK and CLK (Figures 1–3).
For best performance and consistent results, use a lowphase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
converter’s effective bits performance and causes
inconsistent results. The clock supplied to the MAX101
is internally divided by two, reshaped, and buffered.
This divided clock becomes the internal signal used as
strobes for the converters.
DCLK and DCLK are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. (AData is valid after the rising edge of DCLK and BData is valid after the falling
edge.) They are fixed at one-half the rate of the input
clocks in normal mode (Table 1). The MAX101 is characterized to work with 500MHz maximum input clock
frequencies. See
Typical Operating Circuit
) is required for
PWL
.
Output Mode Control (DIV10)
When DIV10 is grounded, it enables the test mode,
where the input incoming clock is divided by ten. This
reduces the output data and clock rates by a factor of
5, allowing the output clock duty cycle to remain at
50%. The clock to output phasing remains the same
and four out of every five sampled input values are discarded.
When left open, this input (DIV10) is pulled low by internal circuitry and the converter functions in its normal
mode.
CLK and DCLK
Layout, Grounding, and Power Supplies
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEE and VCC
supply pins to GND with high-quality 0.1µF and 0.001µF
ceramic capacitors located as close to the package as
possible. Connect all ground pins to a ground plane to
optimize noise immunity and highest device accuracy.
Phase Adjust
This control pin affects the point in time that one-half of
the converter samples the input signal relative to the
other half. PH
but can be adjusted over a ±1.25V range that typically
provides a ±18ps adjustment between the “A” side T/H
bridge strobe and the “B” side T/H bridge strobe.
is normally connected to ground (0V),
ADJ
Input Clock Phasing (TRK1, TRK1)
At power-up, the clock edge from which AData and
BData are synchronized is undetermined. The converter can work from a specific input clock edge, as
described in the following paragraph.
TRK1 and TRK1 are differential inputs that are used in
addition to the normal input clock (CLK) to set data
phasing. A signal at one-half the input clock rate with
the proper setup and hold times (setup and hold typically 300ps) is applied to these inputs. Choose AData
by applying a logic “1” to TRK1 (“0” to TRK1) before
CLK’s negative transition. Choose BData by applying a
logic “0” at CLK’s negative edge (“1” to TRK1). In this
manner, several MAX101s can be interleaved to obtain
faster effective sampling rates. Voltages at the TRK1
input between ±50mV are interpreted as logic “1” and
voltages between -350mV and -500mV are interpreted
as logic “0”.
MAX101
______________________________________________________________________________________ 13
500Msps, 8-Bit ADC with Track/Hold
___________________________________________________Typical Operating Circuit
0.01µF
+5V
V
CC
MAX101
SUB VEE
0.1µF
0.001µF
ADATA
DCLK
DCLK
BDATA
PH
ADJ
29 32, 69, 80
-5.2V
33
31
83
0.001µF
MC100E151
D>Q
8
8
+1.25V
-1.25V
D>Q
MC100E151
D>Q
D>Q
PHASE
0.1µF
1
+VS
2
MAX101
VOUT
GND
MX580LH
WATKINS-JOHNSON
SMRA 89-1 (2x)
3
0.01µF
500Ω
1.5k
500Ω
1.2k
500Ω
1.5k
500Ω
1.2k
MC100E116
1.5k
1.2k
1.5k
1.2k
2.5V
1
/2 MAX412
0.47µF
0.01µF
0.01µF
20k
10k
0.01µF
0.01µF
20k
10k
50Ω
20k
1
/2 MAX412
0.47µF
1
/2 MAX412
0.47µF
50Ω
20k
1
/2 MAX412
0.47µF
-2V
-2V
4, 7, 15, 18, 24, 27, 30, 34,
37, 40, 46, 49, 57, 60, 64, 67, 68,
70, 71, 74, 77, 78, 79, 82, 84
33Ω20Ω
CMPSH-3
50Ω
33Ω20Ω
CMPSH-3
72, 73
75, 76
33Ω20Ω
CMPSH-3
50Ω
33Ω20Ω
CMPSH-3
50Ω
50Ω
8, 21, 43, 56, 81
50
VA
RT
51
VA
RTS
54
VA
RBS
55
VA
RB
AIN+
AIN-
14
VB
RT
13
VB
RTS
10
VB
RBS
9
VB
RB
62
CLK
2
61
CLK
3
GND
Q
Q
Q
Q
14 ______________________________________________________________________________________
500Msps, 8-Bit ADC with Track/Hold
____________________________________________________________Pin Configuration
TOP VIEW
GND
TRK1
TRK1
VB
VB
VB
VB
GND
GND
PAD
CLK
CLK
GND
VCC
TP4
TP3
N.C.
VCC
ADJ
VCC
GND
GND
PH
84838281807978
1
2
3
4
5
6
7
8
9
RB
10
RBS
11
12
13
RTS
14
RT
15
16
17
B0
18
19
B1
20
B2
21
VEE
GND
GND
77
GND
76
AIN-
AIN-
75
MAX101
74
GND
GND
VEE
GND
GND
AIN+
AIN+
69
70
71
72
73
686766
GND
TP6
TP5
GND
65
64
63
N.C.
62
CLK
61
CLK
60
GND
59
TRK1
58
TRK1
57
GND
56
VCC
55
VA
RB
54
VA
RBS
53
TP2
52
TP1
51
VA
RTS
50
VA
RT
49
GND
48
N.C.
47
A0
46
GND
45
A1
44
A2
43
VCC
MAX101
22
23
B4
B3
2425262728
B6
B5
GND
GND
29
B7
SUB
30
GND
31
DCLK
32
VEE
33
DCLK
34
GND
35
DIV10
38
37
36
A7
GND
39
A6
A5
40
GND
42
41
A4
A3
Ceramic Flat Pack
______________________________________________________________________________________ 15
500Msps, 8-Bit ADC with Track/Hold
________________________________________________________Package Information
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
23
MAX101
21
19
17
15
(°C/W)
JA
θ
13
11
45° Angle*
9
7
0 100 200 300 400 500
*DIRECTION OF AIRFLOW ACROSS HEATSINK
0° Angle*
VELOCITY (ft /min)
MAX100-insertB
E1
E
E2
e
PIN #1
C
5°–6°
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
S
0.060±.005(7x)
D1
D
D2
b
A2 A1
A
D3
0.075±.020(6x)
EQUAL SPACES
84-PIN CERAMIC FLAT
PACK WITH HEAT SINK
E3
0.060±.005
MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
A
17.272
A1
A2
b
C
D
D1
D2
D3
e
E
E1
E2
E3
S
18.288
1.041
1.270
3.048
3.302
0.406
0.508
0.228
0.279
29.184
29.794
44.196
44.704
25.298
25.502
28.448
28.829
1.270 BSC 0.050 BSC
29.184
29.794
44.196
44.704
25.298
25.502
28.194
28.702
1.930
2.184
0.680
0.041
0.120
0.016
0.009
1.149
1.740
0.996
1.120
1.149
1.740
0.996
1.110
0.076
0.720
0.050
0.130
0.020
0.011
1.173
1.760
1.004
1.135
1.173
1.760
1.004
1.130
0.086
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