_______________General Description
The MAX100 ECL-compatible, 250Msps, 8-bit analog-todigital converter (ADC) allows accurate digitizing of analog signals from DC to 125MHz (Nyquist frequency).
Designed with Maxim’s proprietary advanced bipolar
processes, the MAX100 contains a high-performance
track/hold (T/H) amplifier and a quantizer in a single
ceramic strip-line package.
The innovative design of the internal T/H assures an
exceptionally wide input bandwidth of 1.2GHz and aperture delay uncertainty of less than 2ps, resulting in a high
6.8 effective bits performance. Special comparator output
design and decoding circuitry reduce out-of-sequence
code errors. The probability of erroneous codes occurring
due to metastable states is reduced to less than 1 error
per 1015clock cycles. Unlike other ADCs, which can
have errors that result in false full-scale or zero-scale outputs, the MAX100 keeps the magnitude to less than 1LSB.
The analog input is designed for either differential or singleended use with a ±270mV range. Sense pins for the reference input allow full-scale calibration of the input range or
facilitate ratiometric use. Midpoint tap for the reference
string is available for applications that need to modify the
output coding for a user-defined bilinear response. Use of
separate high-current and low-current ground pins provides better noise immunity and highest device accuracy.
Dual output data paths provide several data output modes
for easy interfacing. These modes can be configured as
either one or two identical latched ECL outputs. An 8:16
demultiplexer mode that reduces the output data rates to
one-half the clock rate is also available.
For applications that require faster data rates, refer to
Maxim’s MAX101, which allows conversion rates up to
500Msps.
____________________________Features
♦ 250Msps Conversion Rate
♦ 6.8 Effective Bits at 125MHz
♦ Less than ±1/2LSB INL
♦ 50Ω Differential or Single-Ended Inputs
♦ ±270mV Input Signal Range
♦ Reference Sense Inputs
♦ Ratiometric Reference Inputs
♦ Configurable Dual-Output Data Paths
♦ Latched, ECL-Compatible Outputs
♦ Low Error Rate, Less than 10
-15
Metastable States
♦ Selectable On-Chip 8:16 Demultiplexer
♦ 84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Sonar
High-Energy Physics
Communications
______________Ordering Information
MAX100
________________________________________________________________
Maxim Integrated Products
1
DCLK
DCLK
A=B
DIVMOD
BData
(B0–B7)
AData
(A0–A7)
AIN+
AIN-
CLK
CLK
VA
RTVARTS
VA
RB
VA
RBS
VA
CT
VA
CTS
L
A
T
C
H
E
S
B
U
F
F
E
R
L
A
T
C
H
E
S
MODE
CONTROL
TRACK/
HOLD
FLASH CONVERTER
8 8
8
_________________________________________________________Functional Diagram
Call toll free 1-800-998-8800 for free literature.
PART
MAX100CFR* 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
84 Ceramic Flat Pack (with heatsink)
19-0282; Rev 0; 7/94
EVALUATION KIT
AVAILABLE
*Contact factory for 84-Pin Ceramic Flat Pack without heatsink.
250Msps, 8-Bit ADC with Track/Hold
MAX100
250Msps, 8-Bit ADC with Track/Hold
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS (Note 1)
ELECTRICAL CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 50Ω to -2V, VART= 1.02V, VARB= -1.02V, T
MIN
to T
MAX
= 0°C to +70°C, TA= +25°C, unless
otherwise noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under high-
energy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conductive foam to the destination socket before insertion.
Note 2: Typical thermal resistance, junction-to-case R
θJC
= 5°C/W and thermal resistance, junction to ambient (MAX100CA) R
θJA
=
12°C/W, providing 200 lineal ft/min airflow with heatsink. See
Package Information.
Supply Voltages
V
CC
.............................................................................0V to +7V
V
EE
...............................................................................-7V to 0V
V
CC - VEE
............................................................................+12V
Analog Input Voltage.............................................................±2V
Digital Input Voltage.................................................-2.3V to +0V
Reference Voltage (VA
RT
).....................................-0.3V to +1.5V
Reference Voltage (VA
RB
).....................................-1.5V to +0.3V
Data Output Current ..........................................................-33mA
DCLK Output Current ........................................................-43mA
Operating Temperature Range...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+250°C
AData, BData
CONDITIONS
±0.5
Bits8Resolution
LSB
±0.6
INLIntegral Nonlinearity (Note 4)
UNITSMIN TYP MAXSYMBOLPARAMETER
f
CLK
= 250MHz,
VIN= 95% full scale
(Note 5)
Bits7.1
7.4
6.8
ENOBEffective Bits
Figure 5
Figure 5
(Note 7)
f
AIN
= 50MHz, f
CLK
= 250MHz, VIN= 95%
full scale (Note 6)
ps2t
AJ
ps270t
AW
Aperture Width
Aperture Jitter
230 315
Msps250f
CLK
Maximum Conversion Rate
dB44.5SNRSignal-to-Noise Ratio
GHz1.2BW
3dB
Analog Input Bandwidth
AIN+ to AIN-, Table 2,
TA= T
MIN
to T
MAX
mV
-305 -215
V
IN
Input Voltage Range
AIN+ and AIN- with respect to GND
TA= T
MIN
to T
MAX
AIN+, AIN-, TA= T
MIN
to T
MAX
Ω/°C0.008
Input Resistance
Temperature Coefficient
Ω49 51R
I
Input Resistance
mV1.8 2.5LSB
mV-17 +32V
IO
Input Offset Voltage
Least-Significant-Bit Size
TA= +25°C
TA= T
MIN
to T
MAX
AData, BData,
no missing codes
±0.75TA= +25°C
TA= T
MIN
to T
MAX
LSB
±0.85
DNLDifferential Nonlinearity
f
AIN
= 10MHz
f
AIN
= 50MHz
f
AIN
= 125MHz
Full scale
Zero scale
ACCURACY
DYNAMIC SPECIFICATIONS
ANALOG INPUT
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VEE= -5.2V, VCC= +5V, RL= 50Ω to -2V, VART= 1.02V, VARB= -1.02V, T
MIN
to T
MAX
= 0°C to +70°C, TA= +25°C, unless
otherwise noted.) (Note 3)
VARTto VA
RB
-5 20
-1.95 -1.60
CONDITIONS
VCC= 5.0V
AData, BData,
DCLK, DCLK
mA
710
I
CC
Positive Supply Current
V
-1.95 -1.50
V
OL
Digital Output Low Voltage
464 670
Ω116 175R
REF
Reference String Resistance
Ω/°C0.02
Reference String Resistance
Temperature Coefficient
UNITSMIN TYP MAXSYMBOLPARAMETER
DIV, MOD, A=B, CLK, CLK,
TA= T
MIN
to T
MAX
V-1.5V
IL
Digital Input Low Voltage
(Note 8)
DIV, MOD, A=B, CLK, CLK,
TA= T
MIN
to T
MAX
V-1.07V
IH
Digital Input High Voltage
(Note 8)
DIV, MOD, A=B = -1.8V, TA= T
MIN
to T
MAX
µA
080
I
IL
CLK, CLK, VIL= -1.8V (no termination),
TA= T
MIN
to T
MAX
Digital Input Low Current
-5 20DIV, MOD, A=B = -0.8V, TA= T
MIN
to T
MAX
µA
080
I
IH
CLK, CLK, VIH= -0.8V (no termination),
TA= T
MIN
to T
MAX
Digital Input High Current
TA= +25°C
TA= T
MIN
to T
MAX
-1.02 -0.70TA= +25°C
TA= T
MIN
to T
MAX
AData, BData,
DCLK, DCLK
V
-1.10 -0.70
V
OH
Digital Output High Voltage
TA= +25°C
TA= T
MIN
to T
MAX
VEE= -5.2V
TA= +25°C
mA
-780
I
EE
Negative Supply Current
TA= T
MIN
to T
MAX
-750 -560
V
INCM
= ±0.5V TA= T
MIN
to T
MAX
dBCMRRCommon-Mode Rejection Ratio 35
dB
40VCC(nom) = ±0.25V
Power-Supply Rejection Ratio PSRR TA= T
MIN
to T
MAX
REFERENCE INPUT
LOGIC INPUTS
LOGIC OUTPUTS (Note 9)
POWER REQUIREMENTS
VEE(nom) = ±0.25V 40
OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.25
0
-0.25
0 64 128 192 256
-0.50
-0.75
INL (LSBs)
OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.50
0.25
0
-0.25
0
DNL (LSBs)
64 128 192 256
-0.50
-0.75
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX100
250Msps, 8-Bit ADC with Track/Hold
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VEE= -5.2V, VCC= +5V, RL= 50Ω to -2V, VART= 1.02V, VARB= -1.02V, TA= +25°C, unless otherwise noted.)
DIV = 0, Figure 1
DIV = 1, Figure 2
CLK, CLK, Figures 1 and 2
0.8 2.4
CLK, CLK, Figures 1 and 2
ns
1.9 5.7
t
PD1
CLK to DCLK
Propagation Delay
CONDITIONS
See Figures 3 and 4
and Table 1 (delay
depends on output
mode)
20% to 80%
Clock
Cycles
8 1/2 8 1/2
t
NPD
7 1/2 7 1/2
Pipeline Delay
(Latency)
7 1/2 7 1/2
ps
700
t
R
500
Rise Time
ns1.9t
PWH
ns1.9 5.0t
PWL
Clock Pulse Width Low
Clock Pulse Width High
UNITSMIN TYP MAXSYMBOLPARAMETER
DIV = 0, Figure 1
DIV = 1, Figure 2
0.5 2.2
ns
-1.4 -0.1
t
PD2
DCLK to A/BData
Propagation Delay
DCLK
DATA
DCLK
DATA
20% to 80% ps
550
t
F
600
Fall Time
Divide-by-1 mode
Divide-by-
2 mode
BData
AData
Note 3: All devices are 100% production tested at +25°C and are guaranteed by design for TA= T
MIN
to T
MAX
as specified.
Note 4: Deviation from best-fit straight line. See
Integral Nonlinearity
section.
Note 5: See the
Signal-to-Noise Ratio and Effective Bits
section in the
Definitions of Specifications.
Note 6: SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits).
Note 7: Clock pulse width minimum requirements t
PWL
and t
PWH
must be observed to achieve stated performance.
Note 8: Functionality guaranteed for -1.07 ≤ V
IH
≤ -0.7 and -2.0 ≤ VIL≤ -1.5.
Note 9: Outputs terminated through 50Ω to -2.0V.
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________
5
f
CLK
= 250MHz, f
AIN
= 120.4462MHz
SER = -42.3dB, NOISE FLOOR = -65.4dB
FREQUENCY (MHz)
FFT PLOT (f
AIN
= 120.4462MHz)
0
-10
-20
-30
-40
SIGNAL AMPLITUDE (dB)
-50
-60
-70
-80
-90
-100
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5125
f
CLK
= 250MHz, f
AIN
= 10.4462MHz
SER = -45.87dB, NOISE FLOOR = -68.5dB
FFT PLOT (f
AIN
= 10.4462MHz)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0 12.5
25
37.5 50
62.5
0
SIGNAL AMPLITUDE (dB)
FREQUENCY (MHz)
0
050
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
MAX100-10
f
AIN
(MHz)
EFFECTIVE BITS
100 150
200
250 300
1
2
3
4
5
6
7
8
f
CLK
= 250MHz,
V
IN
= 95% FS
050100 150 200 250
0
MAX100-12
f
AIN
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
T
CASE
= +80°C,
f
CLK
= 250MHz,
V
IN
= 95% FS
300
50
100 150 200 250
0
0
EFFECTIVE BITS
vs. CLOCK FREQUENCY
MAX100-11
f
CLK
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
f
AIN
= 10.4MHz,
V
IN
= 95% FS
050
100 150 200 250
0
MAX100-13
f
AIN
(MHz)
EFFECTIVE BITS
1
2
3
4
5
6
7
8
T
CASE
= -15°C,
f
CLK
= 250MHz
V
IN
= 95% FS
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX100
250Msps, 8-Bit ADC with Track/Hold
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
A = CLK, 200mV/div
B = DCLK, 200mV/div
A
B
CLOCK RELATIONSHIP
(DIVIDE-BY-1 MODE)
TIMEBASE = 1ns/div,
f
CLK
= 250MHz
A = CLK, 500mV/div
B = DCLK, 500mV/div
C = AData, 500mV/div
A
B
C
CLOCK/DATA
(DIVIDE-BY-1 MODE)
TIMEBASE = 2ns/div,
f
CLK
= 250MHz
A = CLK, 500mV/div
B = DCLK, 500mV/div
C = AData, 500mV/div
CLOCK/DATA
(DIVIDE-BY-2 MODE)
A
B
C
TIMEBASE = 2ns/div,
f
CLK
= 250MHz
TIMEBASE = 1ns/div, tf = 596ps
DATA OUTPUT
(NEGATIVE EDGE)
100mV/div
AData
OUTPUT
A = DCLK, 200mV/div
B = AData, 200mV/div
CLOCK/DATA DETAIL
(DIVIDE-BY-5 MODE)
TIMEBASE = 5ns/div,
f
CLK
= 250MHz
A
B
TIMEBASE = 1ns/div, tr = 580ps
DIGITAL CLOCK
(POSITIVE EDGE)
DCLK
100mV/div
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________
7
______________________________________________________________Pin Description
12 MOD Modulus. MOD and DIV select the output modes. See Table 1.
5, 6, 9, 10,
31, 33, 35,
48, 58, 59,
63, 81, 83
N.C. No Connect—there is no internal connection to these pins.
8, 21, 43, 56 VCC Positive power supply, +5V ±5% nominal
13 DCLK
Complementary Differential Clock Outputs. Used to synchronize following circuitry: AData and BData
outputs are valid t
PD2
after the rising edge of DCLK. See Figures 1–4.
16 A=B Sets AData equal to BData when asserted (A=B = 1). See Table 1.
11 DIV Divide Enable Input. DIV and MOD select the output modes. See Table 1.
3, 61 CLK
Complementary Differential Clock Inputs. Can be driven from standard 10K ECL with the following
considerations: Internally, pins 2 & 62 and 3 & 61 are the ends of a 50Ω transmission line. Either end
can be driven, with the other end terminated with 50Ω to -2V. See
Typical Operating Circuit.
4, 7, 15, 49,
57, 60, 64,
67, 70, 71,
74, 77, 78,
79, 82, 84
GND Power-Supply Ground. Connect GND and DGND pins (Note 10).
2, 62 CLK
NAME FUNCTION
1 PAD Internal connection, leave open.
PIN
17, 20, 23,
26, 36, 39,
42, 45
A7–A0
19, 22, 25,
28, 38, 41,
44, 47
B7–B0
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to standard 10K ECL logic swings and drive 50Ω transmission lines. Terminate with
50Ω to -2V. See Figures 1–4.
18, 24, 27,
30, 34, 37,
40, 46
DGND Power-Supply Ground. Connect all ground (GND, DGND) pins together, as described in Note 10.
29 SUB
Circuit Substrate Contact. This pin must be connected to VEE.
32, 69, 80 VEE Negative Power Supply, -5.2V ±5% nominal
50 VA
RT
Positive Reference Voltage Input (Note 11)
51 VA
RTS
Positive Reference Voltage Sense (Note 11)
14 DCLK
MAX100
250Msps, 8-Bit ADC with Track/Hold
8 _______________________________________________________________________________________
_________________________________________________Pin Description (continued)
72, 73 AIN+
75, 76 AIN-
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
54 VA
RBS
Negative Reference Voltage Sense (Note 11)
55 VA
RB
Negative Reference Voltage Input (Note 11)
65 TP3 Internal node. Do not connect.
66 TP2 Internal node. Do not connect.
68 TP1
Internal connection. This pin must be connected to GND.
52 VA
CTS
Reference Bias Resistor Center-Tap Sense (Note 12)
53 VA
CT
Reference Bias Resistor Center Tap (Note 12)
NAME FUNCTIONPIN
Note 10: Use a multilayer board with a separate layer dedicated to ground. Connect GND and DGND in separate areas in the
ground plane (separated by at least 1/4 inch) and at only one location on the board (see
Typical Operating Circuit
).
Note 11: Reference bias supply. Use a separate high-quality supply for these pins. Carefully bypassing these pins to achieve
noise-free operation of the reference supplies contributes directly to high ADC accuracy.
Note 12: The center-tap connection of the MAX100 is normally left open. It can be driven with a bias voltage, but should be
bypassed carefully (refer to Note 11).
CLK
AData
BData
CLK
DCLK
DCLK
t
pd1
t
pd2
t
pwh
t
pwl
Figure 1. Output Timing: Divide-by-1 Mode (DIV = 0)
MAX100
250Msps, 8-Bit ADC with Track/Hold
_______________________________________________________________________________________ 9
CLK
AData
BData
CLK
DCLK
DCLK
t
pd1
t
pd2
t
pwh
t
pwl
Figure 2. Output Timing: Divide-by-2 or Divide-by-5 Mode (DIV = 1)
AData
BData
CLK
DCLK
t
pd1
t
pd2
t
NPD
12345678
N - 1 N N + 1
N - 1 N N + 1
N - 1 N N + 1
Figure 3. Output Timing: Clock to Data, Divide-by-1 Mode (fast mode, DIV = 0)
AData
BData
CLK
DCLK
t
pd2
t
NPD
N - 1 N + 3
N - 2 N N + 2
N - 1 N N + 1
N + 2N - 2
12345
N + 1
Figure 4. Output Timing: Divide-by-2 Mode (DIV = 1)
MAX100
250Msps, 8-Bit ADC with Track/Hold
10 ______________________________________________________________________________________
______Definitions of Specifications
Signal-to-Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the
RMS amplitude of all other analog-to-digital (A/D) output
signals. The theoretical minimum A/D noise is caused by
quantization error and is a direct result of the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number
of effective bits of resolution. Therefore, a perfect 8-bit
ADC can do no better than 50dB. The FFT plots in the
Typical Operating Characteristics
show the output level in
various spectral bands.
Effective bits is calculated from a digital record taken from
the ADC under test. The quantization error of the ideal
converter equals the total error of the device. In addition
to ideal quantization error, other sources of error include
all DC and AC nonlinearities, clock and aperture jitter,
missing output codes, and noise. Noise on references
and supplies also degrades effective bits performance.
The ADC’s input is a sine wave filtered with an anti-aliasing filter to remove any harmonic content. The digital
record taken from this signal is compared against a
mathematically generated sine wave. DC offsets, phase,
and amplitudes of the mathematical model are adjusted
until a best-fit sine wave is found. After subtracting this
sine wave from the digital record, the residual error
remains. The rms value of the error is applied in the following equation to yield the ADC’s effective bits.
measured rms error
Effective bits = N - log
2
(
—————————
)
ideal rms error
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the converter’s maximum clock rate with the analog input near
the Nyquist rate (1/2 the input clock rate).
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 5).
Error Rates
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
typical converters can be incorrect, including false fullor zero-scale output. The MAX100’s unique design
reduces the magnitude of this type of error to 1LSB,
and reduces the probability of the error occurring to
less than one in every 10
15
clock cycles. If the
MAX100 were operated at 250MHz, 24 hours a day,
this would translate to less than one metastable-state
error every 46 days.
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the transfer
function from a reference line measured in fractions of
1LSB using a “best straight line” determined by a least
square curve fit.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
[V
MEAS
- (V
MEAS-1
)] - LSB
DNL(LSB) = —————————————
LSB
where V
MEAS-1
is the measured value of the previous
code.
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
SAMPLED
DATA (T/H)
T/H
CLK
CLK
ANALOG
INPUT
t
AD
TRACK
t
AJ
t
AW
TRACKHOLD
APERTURE DELAY (t
AD)
APERTURE WIDTH (tAW)
APERTURE JITTER (tAJ)
Figure 5. T/H Aperture Timing
MAX100
250Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 11
_______________Detailed Description
Converter Operation
The parallel or “flash” architecture used by the MAX100
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash
(as with all other ADC architectures) is the comparator,
which has a positive input, a negative input, and an
output. If the voltage at the positive input is higher than
the negative input (connected to a reference), the output will be high. If the positive input voltage is lower
than the reference, the output will be low. A typical nbit flash consists of 2n-1 comparators with negative
inputs evenly spaced at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there
will be 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1, and all comparators with negative inputs above the input voltage will
have outputs of 0. Decode logic is provided to convert
this information into a parallel n-bit digital word (the output) corresponding to the number of LSBs (minus 1)
that the input voltage is above the level set at the bottom of the ladder.
Finally, the comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described above when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will decrease. The MAX100 has an internal
track/hold (T/H) that increases attainable effective-bits
performance and allows more accurate capture of analog data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX100:
1) Its nominal voltage gain of 4 reduces the input driving signal to ±270mV differential (assuming a
±1.02V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX100.
Data Flow
The MAX100 contains an internal T/H amplifier that
stores the analog input voltage for the ADC to convert.
The differential inputs AIN+ and AIN- are tracked continuously between data samples. When a negative CLK
edge is applied, the T/H enters hold mode (Figure 5).
When CLK goes low, the most recent sample is presented to the ADC’s input comparators. Internal processing of the sampled data is delayed for several
clock cycles before it is available at outputs AData or
BData. All output data is timed with respect to DCLK
and DCLK
(Figures 1–4).
__________Applications Information
Analog Input Ranges
Although the normal operating range is ±270mV, the
MAX100 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain a full-scale digital output with differential input
drive, a nominal +270mV must be applied between
AIN+ and AIN-. That is, AIN+ = +135mV and AIN- =
-135mV (with no DC offset). Mid-scale digital output
code occurs when there is no voltage difference across
the analog inputs. Zero-scale digital output code, with
differential -270mV drive, occurs when AIN+ = -135mV
and AIN- = +135mV. Table 2 shows how the output of
the converter stays at all ones (full scale) when over
ranged or all zeros (zero scale) when under ranged.
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are terminated internally with 50Ω to analog ground.)
2) Drive the other input with a ±270mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Table 1. Input Voltage Range
**An offset VIO, as specified in the DC electrical parameters, may
be present at the input. Compensate for this offset by either
adjusting the reference voltage (VARTor VARB), or introducing an
offset voltage in one of the input terminals AIN + or AIN-.
+135 -135
0 0
AIN+**
(mV)
AIN-**
(mV)
INPUT
11111111
10000000
OUTPUT
CODE
full scale
mid scale
MSB to LSB
-135 +135
+270 0
00000000
11111111
zero scale
full scale
0 0
-270 0
10000000
00000000
mid scale
zero scale
Single
Ended
Differential
MAX100
250Msps, 8-Bit ADC with Track/Hold
12 ______________________________________________________________________________________
Table 2. Output Mode Control
0 X 0
0 X 1
MOD A=BDIV
250
250
DCLK*
(MHz)
Data appears on
AData only, BData
port inactive
(Figure 3).
AData identical to
BData (Figure 3).
DESCRIPTION
1251 0 0
8:16 demultiplexer
mode. AData
and BData ports
are active. BData
carries older
sample and
AData carries
most recent sample (Figure 4).
1251 0 1
AData and BData
ports are active,
both carry identical sampled data.
Alternate samples
are taken but discarded.
501 1 0
AData port
updates data on
5th input CLK.
BData port inactive. Other 4 sampled data points
are discarded.
501 1 1
AData and BData
ports are both
active with identical data. Data is
updated on output ports every
5th input clock
(CLK). The other
4 samples are
discarded.
R
R
R
R
PARASITIC
RESISTANCE
TO
COMPARATORS
POSITIVE
REFERENCE
CENTER TAP
NEGATIVE
REFERENCE
R
/
2
R
/
2
VA
CTS
VA
CT
VA
RBS
VA
RB
VA
RT
VA
RTS
PARASITIC
RESISTANCE
Figure 6. Reference Ladder String
*Input clocks (CLK, –C—L—K–) = 250MHz for all above combinations.
In divide-by-2 or divide-by-5 mode the output clock DCLK will
always be a 50% duty-cycle signal. In divide-by-1 mode DCLK
will have the same duty cycle as CLK.
Divide
by 1
Divide
by 1
MODE
Divide
by 2
Divide
by 2
Divide
by 5
Divide
by 5
MAX100
250Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 13
Reference
The ADC’s reference resistor is a Kelvin-sensed, centertapped resistor string that sets the ADC’s LSB size and
dynamic operating range. Normally, the top and bottom of
this string are driven with an op amp, and the center tap is
left open. However, driving the center tap is an effective
way to modify the output coding to provide a user-defined
bilinear response. The buffer amplifier used to drive the
top and bottom inputs will need to supply approximately
18mA due to the resistor string impedance of 116Ω minimum. A reference voltage of ±1.02V is normally applied to
inputs VARTand VARB. This reference voltage can be
adjusted up to ±1.4V to accommodate extended input
requirements (accuracy specifications are guaranteed with
±1.02V references). The reference input VA
RTS
, VA
RBS
,
and VA
CTS
allow Kelvin sensing of the applied voltages
to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the op amp output that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the op amp’s output
(see
Typical Operating Circuit
). This resistor and
capacitor combination should be located within 0.5
inches of the MAX100 package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective-bits performance.
CLK and DCLK
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing signals for the MAX100. CLK and CLK are fed to the internal circuitry from pins 2 & 3 or pins 62 & 61 through an
internal 50Ω transmission line. One pair of CLK/CLK
inputs should be driven and the other pair terminated
by 50Ω to -2V. Either pair can be used as the driven
inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (t
PWL
) is required for
CLK and CLK (Figures 1–4).
For best performance and consistent results, use a low
phase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
converter’s effective-bits performance and causes
inconsistent results.
DCLK and DCLK
are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. The MAX100 is characterized to work with maximum input clock frequencies of
250MHz (Table 1). See
Typical Operating Circuit.
Output Mode Control
DIV, MOD, and A=B are input pins that determine the
operating mode of the two output data paths. Six
options are available (Table 1). A typical operating configuration (8:16 demultiplexer mode) is set by 1 on DIV,
0 on MOD, and 0 on A=B. This will give the most
recent sample at AData with the older data on BData.
Both outputs are synchronous and are at half the input
clock rate. To terminate the control inputs, use a resistor to -2V or the equivalent circuit resistor combination
from DGND to -5.2V up to 1kΩ. When using a diode
pull-up to tie an input high, bias the diode “on” with a
pull-down resistor to avoid input voltage excursions
close to ground. The control inputs are compatible with
standard ECL 10K logic levels over temperature.
Layout, Grounding, and Power Supplies
The MAX100 is designed with separate analog and digital ground connections to isolate high-current digital
noise spikes. The high-current digital ground, DGND,
is connected to the collectors of the output emitter follower transistors. The low-current ground connection is
GND, which is a combination of the analog ground and
the ground of the low-current digital decode section.
The DGND and GND connections should be at the
same DC level, and should be connected at only one
location on the board. This will provide better noise
immunity and highest device accuracy. A ground
plane is recommended.
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEE and
VCC supply pins to GND with high-quality 0.1µF and
0.001µF ceramic capacitors located as close to the
package as possible. An evaluation kit with a suggested layout is available.
MAX100
250Msps, 8-Bit ADC with Track/Hold
14 ______________________________________________________________________________________
MAX100
1/2 MAX412
1/2 MAX412
D>Q
Q
D>Q
Q
8
D>Q
Q
D>Q
Q
8
14
13
16
11
12
DCLK
DCLK
A=B
DIV
MOD
1k
1k
1k
50Ω
50Ω
50Ω
-2V
-2V
-2V
-2V
CLOCK
BData
AData
+5V
0.1µF
0.001µF
20Ω
50
8, 21, 43, 56
51
55
72. 73
54
75, 76
2
62
3
61
AIN+
AIN-
CLK
DGND GND SUB VEE
29 32, 69, 80
*
-2V
-2V
CLK
*PINS 68, 4, 7, 15, 49, 57, 60, 64
67, 70, 71, 74, 77, 78, 79,
82, 84, 18, 24, 27, 30, 34,
37, 40, 46
-5.2V
0.1µF
0.001µF
10µF
0.47µF
VA
RT
V
CC
VA
RTS
VA
RB
VA
RBS
120Ω
50Ω
1.02V
0.01µF
0.01µF
2.5V
MX580LH
1
3
2
+V
S
VOUT
GND
51Ω
20k
CMPSH-3
0.22µF
CMPSH-3
0.22µF
51Ω
20Ω 33Ω
20k
50k
70k
10k
VA
CT
VA
CTS
MC100E151
MC100E151
WATKINS-JOHNSON
SMRA 89-1
MC100E116
150Ω
50Ω
___________________________________________________Typical Operating Circuit
MAX100
250Msps, 8-Bit ADC with Track/Hold
______________________________________________________________________________________ 15
____________________________________________________________Pin Configuration
GND
CLK
CLK
N.C.
63
62
61
60
59
58
57
56
55
54
53
52
50
49
48
47
46
45
44
43
51
TOP VIEW
MAX100
VCC
GND
N.C.
N.C.
VA
RBS
VA
RB
VA
RT
VA
RTS
VA
CTS
VA
CT
DGND
B0
N.C.
GND
B1
A0
VCC
GND
CLK
CLK
PAD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VCC
GND
N.C.
N.C.
N.C.
N.C.
DCLK
DCLK
MOD
DIV
DGND
A7
A = B
GND
A6
B7
VCC
84838281807978
77
N.C.
GND
N.C.
GND
GND
GND
GND
VEE
AIN-
AIN-
74
75
76
69
70
71
72
73
686766
65
GND
AIN+
AIN+
GND
GND
TP1
VEE
GND
TP3
TP2
64
GND
2425262728
29
B5
DGND
A5
B6
SUB
B4
DGND
A4
N.C.
DGND
34
35
33
32
31
30
39
38
37
36
N.C.
DGND
N.C.
VEE
A2
B3
DGND
A3
B2
DGND
22
23
42
41
40
A1
Ceramic Flat Pack
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX100
250Msps, 8-Bit ADC with Track/Hold
________________________________________________________Package Information
0 100 200 300 400 500
7
MAX100-insertB
VELOCITY (ft /min)
θ
JA
(°C/W)
12
11
13
15
17
19
21
23
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
45 Degrees*
*DIRECTION OF AIRFLOW ACROSS HEATSINK
0 Degrees*
0.060±.005(7x)
D3
0.075±.020(6x)
EQUAL SPACES
D2
D
D1
c
PIN #1
e
S
E2
E
E1
b
A2 A1
A
0.060±.005
E3
5–6°
84 LEAD CERAMIC FLAT
PACK WITH HEAT SINK
MILLIMETERS INCHES
A
A1
A2
b
C
D
D1
D2
D3
e
E
E1
E2
E3
S
DIM
MIN MAX MIN MAX
17.272
1.041
3.048
0.406
0.228
29.184
44.196
25.298
28.448
29.184
44.196
25.298
28.194
1.930
18.288
1.270
3.302
0.508
0.279
29.794
44.704
25.502
28.829
29.794
44.704
25.502
28.702
2.184
0.680
0.041
0.120
0.016
0.009
1.149
1.740
0.996
1.120
1.149
1.740
0.996
1.110
0.076
0.720
0.050
0.130
0.020
0.011
1.173
1.760
1.004
1.135
1.173
1.760
1.004
1.130
0.086
1.270 BSC 0.050 BSC
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