For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
_______________General Description
The MAX1005 is a combined digitizer and reconstruction integrated circuit designed to work in systems that
demodulate and modulate communications signals. It
integrates IF undersampling and signal synthesis functions into a single, low-power circuit. Its analog-todigital converter (ADC) is used to directly sample or
undersample a downconverted RF signal, while its
digital-to-analog converter (DAC) recreates the IF subcarrier and transmission data. The MAX1005’s ADC is
ideal for undersampling applications, due to the analog
input amplifier’s wide (15MHz) bandwidth. The DAC
has very low glitch energy, which minimizes the transmission of unwanted spurious signals. An on-chip
reference provides for low-noise ADC and DAC conversions.
The MAX1005 provides a high level of signal integrity
from a low power budget. It operates from a single
power supply, or from separate analog and digital supplies with independent voltages ranging from +2.7V to
+5.5V. The MAX1005 can operate with an unregulated
analog supply of 5.5V and a regulated digital supply
down to 2.7V. This flexible power-supply operation
saves additional power in complex digital systems.
The MAX1005 has three operating modes: transmit
(DAC active), receive (ADC active), and shutdown
(ADC and DAC inactive). In shutdown mode, the total
supply current drops below 1µA. The device requires
only 2.4µs to wake up from shutdown mode. The
MAX1005 is ideal for hand-held, as well as base-station
applications. It is available in a tiny 16-pin QSOP package specified for operation over both the commercial
and extended temperature ranges.
________________________Applications
PWT1900
PHS/P
Wireless Loops
PCS/N
____________________________Features
♦ Differential-Input, 5-Bit ADC
♦ Differential-Output, 7-Bit DAC
♦ 15Msps Min Conversion Rate
♦ 25MHz -1dB Full-Power Bandwidth
♦ 44dB SFDR for ADC
39dB at 10.7MHz SFDR (Imaged) for DAC
♦ Internal Voltage Reference
♦ Parallel Logic Interface
♦ Single-Supply Operation (+2.7V to +5.5V)
♦ 0.1µA Low-Power Shutdown Mode
MAX1005
IF Undersampler
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VCCD CLK
D0
D1
D2
D3
D4
D5
D6
TOP VIEW
MAX1005
QSOP
DGND
RXEN
TXEN
AIO+
AIO-
AGND
VCCA
__________________Pin Configuration
19-1291; Rev 0; 9/97
PART
MAX1005CEE
MAX1005EEE -40°C to +85°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 QSOP
16 QSOP
______________Ordering Information
Functional Diagram appears at end of data sheet.
查询MAX1005供应商
MAX1005
IF Undersampler
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, RL= ∞, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCA to AGND ........................................................-0.3V, +6.0V
VCCD to DGND........................................................-0.3V, +6.0V
VCCA to VCCD...................................................................±6.3V
Digital I/O Pins (D0–D6, CLK, RXEN, TXEN)
to DGND.................................-0.3V to (VCCD + 0.3V) or 6.0V
(whichever is smaller)
Analog I/O Pins (AIO+, AIO-)
to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V)
AGND to DGND........................................................-0.3V, +0.3V
Power Dissipation (T
A
= +70°C)
QSOP (derate 5.90mW/°C above 70°C)......................470mW
Operating Temperature Ranges
MAX1005CEE .....................................................0°C to +70°C
MAX1005EEE...................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
(Notes 9, 10)
AIO+ = AIO-
(Note 4)
(Notes 6, 7)
(Note 3)
(Note 5)
CONDITIONS
-42
dB
-42 -24
THDTotal Harmonic Distortion
mV368 400 432V
IN
Full-Scale Input Range
LSB±2Offset Error
LSB±0.2DNLDifferential Nonlinearity
LSB±0.2INLIntegral Nonlinearity
Bits5NResolution
dB67PSRPower-Supply Rejection
CLK
period
0.5DAC Latency
dBc-50Clock Feedthrough
µs0.7 2.4t
WAKE
Wakeup Time Exiting Shutdown
LSB±0.2 ±1INLIntegral Nonlinearity
Bits7NResolution
-28 dBcTHD+N
Total Harmonic Distortion plus
Noise
39
dBc
28 39
SFDRSpurious-Free Dynamic Range
LSB±0.2 ±1DNLDifferential Nonlinearity
LSB±1Offset Error
mVp-p736 800 864V
OUT
Transmit Full-Scale Output Voltage
UNITSMIN TYP MAXSYMBOLPARAMETER
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 3.0V
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
(Note 9)
(Note 9)
4.9
Bits
4.5 4.9
ENOBEffective Number of Bits
44
dB
24 44
SFDRSpurious-Free Dynamic Range
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
TRANSMIT DAC DC ACCURACY (Note 1)
TRANSMIT DAC DYNAMIC PERFORMANCE (TA= +25°C) (Note 2)
TRANSMIT ADC DC ACCURACY (Note 8)
RECEIVE ADC DYNAMIC PERFORMANCE (TA= +25°C) (Note 8)
MAX1005
IF Undersampler
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, RL= ∞, TA= T
MIN
to T
MAX
, unless otherwise noted.)
VCCD = 2.7V
to 5.5V
VCCD = 2.7V
to 5.5V
D0–D4, VCCD = 2.7V to 5.5V, I
SINK
= 50µA
D0–D4, VCCD = 2.7V to 5.5V,
I
SOURCE
= 200µA
VCCA = VCCD = 3.0V, CL≤ 12.5pF,
RXEN = TXEN
VCCA = VCCD
= 3.0V,
CL≤ 12.5pF
AIO+ or AIO- to GND
Differential between AIO+ and AIO-
VCCA = VCCD
= 3.0V,
CL≤ 12.5pF
CONDITIONS
-0.1 0.5
V
0.3VCCD
V
IL
Input Low Voltage
VCCD - VCCD +
0.5 0.1
V
0.7VCCD
V
IH
Input High Voltage
V0 0.5V
OL
Output Low Voltage
VVCCD - 1.0 VCCDV
OH
Output High Voltage
µA<0.1 5
ICCA +
ICD
Shutdown Supply Current
3.0 5.6
mA
4.0 6.4
ICCDDigital Supply Current
2.5 3.8
mA
9.0 14.8
ICCAAnalog Supply Current
µs0.6 2.4t
WAKE
Wakeup Time Exiting Shutdown
Mode
Msps15
MHz15 25
Input Full-Power Bandwidth
(-1dB)
Conversion Rate
V2.7 5.5
VCCA,
VCCD
Supply Voltage
pF
4
C
IN
Input Capacitance (Note 6)
LSB<0.1PSRPower-Supply Rejection
kΩ1.56 2.00 2.44R
IN
Input Resistance
ppm/°C-2000TCR
IN
Input Resistance Temperature
Coefficient
UNITSMIN TYP MAXSYMBOLPARAMETER
RXEN, TXEN
D0–D6, CLK
RXEN, TXEN
D0–D6, CLK
VIN= 90% of full scale
RXEN = 0, TXEN = 1,
ADC off, DAC on
RXEN = 1, TXEN = 0,
ADC on, DAC off
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
TA= +25°C, differential between AIO+ and
AIO-
RXEN = 0, TXEN = 1,
ADC off, DAC on
RXEN = 1, TXEN = 0,
ADC on, DAC off
4
DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK) (Note 12)
POWER REQUIREMENTS
ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11)
CONDITIONS
MAX1005
IF Undersampler
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
CLK
= 15MHz, RL= ∞, TA= T
MIN
to T
MAX
, unless otherwise noted.)
RXEN, TXEN;
VCCD = 2.7V
to 3.6V
D0–D6, CLK; VCCD = 2.7V to 5.5V
CL≤ 12.5pF
TA= +25°C (Note 6)
TA= +25°C (Note 6)
RXEN, TXEN;
VCCD = 3.6V
to 5.5V
D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)
CONDITIONS
±2
±1
µA
-1 7
I
IN
Input Current
ns13 20t
DO
ADC CLK to Output Data Valid
%45 55CLK Duty Cycle
ns5 0.3t
HOLD
DAC Data Hold Time
ns5 0.6t
DS
DAC Data Setup Time
±1
±4
pF8C
IN
Input Capacitance
UNITSMIN TYP MAXSYMBOLPARAMETER
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
TXEN = RXEN
TXEN = RXEN
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
Note 1: TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-
Point Linearity method.
Note 2: f
IN
= 4.3MHz digital sine wave applied to DAC data inputs; f
CLK
= 15MHz. The reference frequency (f
REF
) is defined to be
10.7MHz (f
CLK
- fIN). All frequency components present in the DAC output waveform except for f
REF
and fINare consid-
ered spurious.
Note 3: For DAC SFDR measurements, the amplitude of f
REF
(10.7MHz) is compared to the amplitudes of all frequency compo-
nents of the output waveform except for f
IN
(4.3MHz).
Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of
all harmonic and noise components of the output waveform (except for f
IN
and f
REF
) to the RMS amplitude of the f
REF
com-
ponent.
Note 5: Clock feedthrough is defined as the difference in amplitude between the f
REF
component and the f
CLK
component when
measured differentially from AIO+ to AIO-.
Note 6: Guaranteed by design. Not production tested.
Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to
propagate through to the DAC switches.
Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-
entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.
Note 9: f
IN
= 10.7MHz, f
CLK
= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (f
REF
) is defined to be 4.3MHz
(f
CLK
- fIN). All components except for f
REF
and fINare considered spurious.
Note 10: Receive ADC THD measurements include the first five harmonics.
Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause
latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are
required, then bypass these pins only to VCCA.
Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are
measured to V
OH(AC)
for rising output signals and to V
OL(AC)
for falling output signals. The values for V
OH(AC)
and V
OL(AC)
as a function of the VCCD supply are shown in the following table:
VCCD (V)
V
OH(AC)
(V) V
OL(AC)
(V)
2.7 to 3.3 VCCD - 1.1 0.5
3.3 to 5.5 2/3 x VCCD 0.5
TIMING CHARACTERISTICS (Data Outputs: RL= 1MΩ, CL= 15pF, TA= T
MIN
to T
MAX
, unless otherwise noted.) (Note 12)
MAX1005
IF Undersampler
_______________________________________________________________________________________
5
-0.50
-0.30
-0.40
-0.10
-0.20
0.10
0.00
0.20
0.40
0.30
0.50
-15 -9 -6 -3-12 0 3 6 129 15
RECEIVE ADC
INTEGRAL NONLINEARITY
MAX1005-01
CODE
INL (LSB)
-0.50
-0.30
-0.40
-0.10
-0.20
0.10
0.00
0.20
0.40
0.30
0.50
-15 -9 -6 -3-12 0 3 6 129 15
RECEIVE ADC
DIFFERENTIAL NONLINEARITY
MAX1005-02
CODE
DNL (LSB)
-0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
-64 -32 -16-48 0 16 32 48 64
TRANSMIT DAC
INTEGRAL NONLINEARITY
MAX1005-03
CODE
INL (LSB)
-0.5
-0.3
-0.4
-0.1
-0.2
0.1
0
0.2
0.4
0.3
0.5
-64 -32 -16-48 0 16 32 48 64
TRANSMIT DAC
DIFFERENTIAL NONLINEARITY
MAX1005-04
CODE
DNL (LSB)
-70
-40
-50
-60
-30
-20
-10
0
10
20
30
0 2.9301.465 4.395 5.860 7.325
RECEIVE ADC FFT PLOT
MAX1005-05
FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 10.7MHz
f
CLK
= 15MHz
256 POINTS
-7
-6
-5
1 10 100
FULL POWER ANALOG
INPUT BANDWIDTH
MAX1005-06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
-4
-3
-2
-1
0
VIN = 90% OF FULL SCALE
__________________________________________Typical Operating Characteristics
(VCCA = VCCD = 3.0V, TA = +25°C, unless otherwise noted.)
MAX1005
_______________Detailed Description
The MAX1005 is designed to operate with the Maxim
PWT1900 (TAG-6) wireless transceiver chipset consisting
of the MAX2411 RF transceiver, the MAX2511 IF transceiver, and the MAX1007 power-control/diversity IC. The
MAX1005 integrates all the functions of an IF undersampler into a single low-power integrated circuit. It is also
well suited for other time-division duplex (TDD) communications systems. This device includes a 7-bit transmit
DAC, a 5-bit receive ADC, two internal bandgap references, clock drivers, and all necessary interface and
control logic.
Transmit DAC
The low-side alias frequency (f
CLK
- f
OUT
= 10.7MHz)
generated by the MAX1005’s 7-bit DAC is used to recreate the IF sub-carrier and transmission data in TDD and
other communications systems. The DAC accepts CMOS
input data in the twos-complement format and outputs a
corresponding analog voltage differentially between
AIO+ and AIO-. The full-scale output voltage range is typically ±400mV. The DAC code table is shown in Table 1.
Table 1. Transmit DAC Code Table
Receive ADC
The 5-bit receive ADC is used to directly sample or
undersample a downconverted RF signal. The ADC
converts an analog input signal to a 5-bit digital output
code in the twos-complement format. Figure 1 shows
the ADC transfer function.
Analog input signals are applied differentially between
AIO+ and AIO-, with a full-scale range of ±200mV. An
internal amplifier buffers the input signal and drives the
comparator array, minimizing loading on the external
signal source. The input amplifier has a full-power -1dB
bandwidth of at least 15MHz, making this device ideally
suited for undersampling applications.
IF Undersampler
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
Two MSBs for DAC input data. D6 is the MSB.D6, D59, 10
Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4–D0 function as the five lower bits of DAC input
data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4–D0 function as the five data outputs for the
ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0–D4 should
not be externally held high, to prevent excessive input leakage currents.
D4–D011–15
Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling
edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is
active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is
updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down
(TXEN = RXEN).
CLK16
Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin.
AIO-5
Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN
enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its lowpower shutdown mode.
TXEN6
Analog Ground. Connect to analog ground plane.AGND7
Analog Supply Voltage, +2.7V to +5.5VVCCA8
Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin.
AIO+4
Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables
the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shutdown mode.
RXEN3
PIN
Digital Ground. Connect to digital ground plane.DGND2
Digital Supply Voltage, +2.7V to +5.5VVCCD
1
FUNCTIONNAME
DAC INPUT DATA ANALOG OUTPUT
011 1111 +FS
000 0000 0
100 0000 -FS
Digital Interface
The DAC has a 7-bit parallel digital interface. Figure 2
shows the timing diagram for the transmit DAC. Digital
data is latched into the DAC input register on the falling
edge of CLK. On the next rising edge of CLK the data
is transferred to the DAC register and the DAC output
voltage is updated.
The ADC is enabled by setting TXEN = 0 and RXEN =
1. Figure 3 shows the ADC timing diagram. Input data
is sampled on the falling edge of CLK, while output
data changes state on the rising edge of CLK. This
minimizes digital feedthrough and noise while the analog input is being sampled. The ADC output data is
applied to the 5-bit parallel output pins (D0–D4), with
the MSB at D4.
Operating Modes
The MAX1005 has three operating modes: transmit,
receive, and shutdown. The operating mode is selected
by the RXEN and TXEN inputs, as shown in Table 2.
In transmit mode, the DAC is active and the ADC is
inactive. Power consumption is typically 16.5mW with a
3V supply voltage. In receive mode, the ADC is active
and the DAC is inactive. Power consumption in this
mode is typically 39mW with a 3V supply voltage.
The third mode is shutdown, in which both the DAC
and the ADC are inactive. Select this mode by setting
RXEN = TXEN at any voltage from DGND to VCCD. In
shutdown mode, the CLK input can continue to run
without damaging the device and with no significant
increase in the typical shutdown supply current specification of 0.1µA. When exiting shutdown, the MAX1005
is guaranteed to be operational within 2.4µs after TXEN
or RXEN is asserted, as shown in Table 2.
To prevent supply-current drain due to leakage currents from entering the ADC output bits, the ADC outputs (D0–D4) should not be held high in low-power
shutdown mode.
Table 2. Operating Mode Selection
MAX1005
IF Undersampler
_______________________________________________________________________________________ 7
01111
01110
00010
00001
00000
11111
11110
11101
10001
10000
- FS
COM
INPUT VOLTAGE (LSB)
OUTPUT CODE
+FS
Figure 1. Receive ADC Transfer Function
CLK
DAC
OUTPUT
DAC
INPUT
DATA
(D0–D6)
n - 1 n n + 1 n + 2
n - 1 n n + 1
t
DS
t
HOLD
Figure 2. Transmit DAC Timing Diagram
ANALOG
INPUT
D0–D4
CLK
n - 1 n
SAMPLE
n
SAMPLE
n + 1
SAMPLE
n + 2
n + 1
t
DO
Figure 3. Receive ADC Timing Diagram
RXEN TXEN OPERATING MODE
0 0
Low-power shutdown: ADC and DAC
disabled
0 1 Transmit mode: DAC active, ADC disabled
1 0 Receive mode: ADC active, DAC disabled
1 1
Low-power shutdown: ADC and DAC
disabled
MAX1005
IF Undersampler
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8
_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Power-Supply Bypassing and Grounding
The MAX1005 has separate analog (VCCA) and digital
(VCCD) power-supply connections, as well as separate
analog and digital ground connections to minimize coupling of noisy digital signals into the circuit’s analog portion. The device will operate with both of these power
supplies connected to any voltage between +2.7V and
+5.5V. This feature allows the digital circuitry to operate
from a regulated logic power supply; this reduces power
consumption and maintains compatibility with external
logic, while allowing the analog circuitry to operate from
an unregulated supply.
The analog ground (AGND) and digital ground (DGND)
should be tied together close to the device. At no time
should the voltage between AGND and DGND exceed
±0.3V.
The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto board. 10µF electrolytic capacitors with low equivalent-series-resistance (ESR) ratings are recommended.
For best effective bits performance, minimize capacitive
loading at the digital outputs. Keep the digital output
traces as short as possible. Bypass each of the VCC_
supply pins to its respective GND with high-quality
ceramic capacitors located as close to the package as
possible.
___________________Chip Information
TRANSISTOR COUNT: 2377
SUBSTRATE CONNECTED TO AGND
5-BIT
FLASH ADC
VCCA
5
7
DAC
BANDGAP
REFERENCE
ADC
BANDGAP
REFERENCE
DIGITAL
INTERFACE
TXEN RXEN
ADC
CLOCK
DRIVER
1k 1k
AIO+
AIO-
7-BIT DAC
MAX1005
VCCA AGND VCCD DGND
CLK
DAC
CLOCK
DRIVER
D6–D0
7
________________Functional Diagram
________________________________________________________Package Information
QSOP.EPS
Loading...