MAXIM DS87C520, DS83C520 Technical data
s
www.maxim-ic.com
DS87C520/DS83C520
EPROM/ROM High-Speed Microcontroller
FEATURES
80C52 Compatible
8051 Pin- and Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory
16kB Program Memory
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Feature
Selects Internal ROM Size from 0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM/Peripherals
Power Management Mode
Programmable Clock Source to Save Power
CPU Runs from (crystal/64) or (crystal/1024)
Provides Automatic Hardware and Software Exit
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes:
Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
13 Interrupt Sources with Six External
Available in 40-pin PDIP, 44-Pin PLCC, 44-Pin
TQFP, and 40-Pin Windowed CERDIP
Factory Mask DS83C520 or EPROM (OTP)
DS87C520
PIN CONFIGURATIONS
TOP VIEW
The High-Speed Microcontroller User’s Guide must be used in
conjunction with this data sheet. Download it at:
www.maxim-ic.com/microcontrollers.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 022207
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
ORDERING INFORMATION
PART TEMP RANGE
MAX CLOCK
SPEED (MHz)
DS87C520-MCL 0˚C to +70˚C 33 40 Plastic DIP
DS87C520-MCL+ 0˚C to +70˚C 33 40 Plastic DIP
DS87C520-QCL 0˚C to +70˚C 33 44 PLCC
DS87C520-QCL+ 0˚C to +70˚C 33 44 PLCC
DS87C520-ECL 0˚C to +70˚C 33 44 TQFP
DS87C520-ECL+ 0˚C to +70˚C 33 44 TQFP
DS87C520-MNL -40˚C to +85˚C 33 40 Plastic DIP
DS87C520-MNL+ -40˚C to +85˚C 33 40 Plastic DIP
DS87C520-QNL -40˚C to +85˚C 33 44 PLCC
DS87C520-QNL+ -40˚C to +85˚C 33 44 PLCC
DS87C520-ENL -40˚C to +85˚C 33 44 TQFP
DS87C520-ENL+ -40˚C to +85˚C 33 44 TQFP
DS87C520-WCL* 0˚C to +70˚C 33 40 Windowed CERDIP
DS83C520-MCL 0˚C to +70˚C 33 40 Plastic DIP
DS83C520-MCL+ 0˚C to +70˚C 33 40 Plastic DIP
DS83C520-QCL 0˚C to +70˚C 33 44 PLCC
DS83C520-QCL+ 0˚C to +70˚C 33 44 PLCC
DS83C520-ECL 0˚C to +70˚C 33 44 TQFP
DS83C520-ECL+ 0˚C to +70˚C 33 44 TQFP
DS83C520-MNL -40˚C to +85˚C 33 40 Plastic DIP
DS83C520-MNL+ -40˚C to +85˚C 33 40 Plastic DIP
DS83C520-QNL -40˚C to +85˚C 33 44 PLCC
DS83C520-QNL+ -40˚C to +85˚C 33 44 PLCC
DS83C520-ENL -40˚C to +85˚C 33 44 TQFP
DS83C520-ENL+ -40˚C to +85˚C 33 44 TQFP
PIN-PACKAGE
+ Denotes a Pb-free/RoHS-compliant device.
* The windowed ceramic DIP package is intrinsically Pb free.
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
DESCRIPTION
The DS87C520/DS83C520 EPROM/ROM high-speed microcontrollers are fast 8051-compatible
microcontrollers. They feature a redesigned processor core without wasted clock and memory cycles. As
a result, the devices execute every 8051 instruction between 1.5 and 3 times faster than the original for
the same crystal speed. Typical applications will see a speed improvement of 2.5 times using the same
code and the same crystal. The DS87C520/DS83C520 offer a maximum crystal speed of 33MHz,
resulting in apparent execution speeds of 82.5MHz (approximately 2.5X).
The DS87C520/DS83C520 are pin compatible with all three packages of the standard 8051, and include
standard resources such as three timer/counters, serial port, and four 8-bit I/O ports. They feature 16kB of
EPROM or mask ROM with an extra 1kB of data RAM. Both OTP and windowed packages are
available.
Besides greater speed, the microcontroller includes a second full hardware serial port, seven additional
interrupts, programmable Watchdog Timer, Brownout Monitor, and Power-Fail Reset. The device also
provides dual data pointers (DPTRs) to speed block data memory moves. It also can adjust the speed of
MOVX data memory access from two to nine machine cycles for flexibility in selecting external memory
and peripherals.
A new Power Management Mode (PMM) is useful for portable applications. This feature allows software
to select a lower speed clock as the main time base. While normal operation has a machine cycle rate of 4
clocks per cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. For example, at 12MHz,
standard operation has a machine cycle rate of 3MHz. In Power Management Mode, software can select
either 187.5kHz or 11.7kHz machine cycle rate. There is a corresponding reduction in power
consumption when the processor runs slower.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C520 is a factory mask ROM version of the DS87C520 designed for high-volume, costsensitive applications. It is identical in all respects to the DS87C520, except that the 16kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C520 will apply to
the DS83C520, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
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Figure 1. Block Diagram
DS87C520/
DS83C520
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
PIN DESCRIPTION
PIN
DIP PLCC TQFP
40 44 38 V
20 1, 22, 23 16, 17, 39 GND
9 10 4 RST
18 20 14 XTAL2
19 21 15 XTAL1
29 32 26 PSEN
NAME FUNCTION
CC
Positive Supply Voltage. +5V
Digital Circuit Ground
Reset Input. The RST input pin contains a Schmitt voltage input
to recognize external active high Reset inputs. The pin also
employs an internal pulldown resistor to allow for a combination
of wired OR external reset sources. An RC is not required for
power-up, as the device provides this function internally.
Crystal Oscillator Pins. XTAL1 and XTAL2 provide support for
parallel-resonant, AT-cut crystals. XTAL1 acts also as an input if
there is an external clock source in place of a crystal. XTAL2
serves as the output of the crystal amplifier.
Program Store-Enable Output. This active-low signal is
commonly connected to optional external ROM memory as a chip
enable. PSEN provides an active-low pulse and is driven high
when external ROM is not being accessed.
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PIN DESCRIPTION (continued)
PIN
DIP PLCC TQFP
30 33 27 ALE
39 43 37 P0.0 (AD0)
38 42 36 P0.1 (AD1)
37 41 35 P0.2 (AD2)
36 40 34 P0.3 (AD3)
35 39 33 P0.4 (AD4)
34 38 32 P0.5 (AD5)
33 37 31 P0.6 (AD6)
32 36 30 P0.7 (AD7)
NAME FUNCTION
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
Address Latch Enable Output. The ALE functions as a clock to
latch the external address LSB from the multiplexed address/data bus
on Port 0. This signal is commonly connected to the latch enable of an
external 373 family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced
high when the DS87C520/DS83C520 are in a reset condition. ALE
can also be disabled and forced high by writing ALEOFF = 1
(PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
Port 0 (AD0–7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O
port. As an alternate function Port 0 can function as the multiplexed
address/data bus to access off-chip memory. During the time when
ALE is high, the LSB of a memory address is presented. When ALE
falls to a logic 0, the port transitions to a bidirectional data bus. This
bus is used to read external ROM and read/write external RAM
memory or peripherals. When used as a memory bus, the port
provides active high drivers. The reset condition of Port 0 is tri-state.
Pullup resistors are required when using Port 0 as an I/O port.
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PIN DESCRIPTION (continued)
PIN
DIP PLCC TQFP
NAME FUNCTION
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
21 24 18 P2.0 (A8)
22 25 19 P2.1 (A9)
23 26 20 P2.2 (A10)
24 27 21 P2.3 (A11)
25 28 22 P2.4 (A12)
26 29 23 P2.5 (A13)
27 30 24 P2.6 (A14)
28 31 25 P2.7 (A15)
10 11 5 P3.0
11 13 7 P3.1
12 14 8 P3.2
13 15 9 P3.3
Port 2 (A8–15), I/O. Port 2 is a bidirectional I/O port. The reset
condition of Port 2 is logic high. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since
any external circuit that writes to the port will overcome the weak
pullup. When software writes a 0 to any port pin, the
DS87C520/DS83C520 will activate a strong pulldown that
remains on until either a 1 is written or a reset occurs. Writing a 1
after the port has been at 0 will cause a strong transition driver to
turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes both the
output high and input state. As an alternate function Port 2 can
function as MSB of the external address bus. This bus can be used
to read external ROM and read/write external RAM memory or
peripherals.
Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O
port and an alternate functional interface for External Interrupts,
Serial Port 0, Timer 0 and 1 Inputs, and RD and WR strobes. The
reset condition of Port 3 is with all bits at a logic 1. In this state, a
weak pullup holds the port high. This condition also serves as an
input mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to any port
pin, the DS87C520/DS83C520 will activate a strong pulldown that
remains on until either a 1 is written or a reset occurs. Writing a 1
after the port has been at 0 will cause a strong transition driver to
14 16 10 P3.4
15 17 11 P3.5
16 18 12 P3.6
17 19 13 P3.7
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
COMPATIBILITY
The DS87C520/DS83C520 are fully static CMOS 8051-compatible microcontrollers designed for high
performance. In most cases, the DS87C520/DS83C520 can drop into an existing socket for the 8xc51
family to improve the operation significantly. While remaining familiar to 8051 family users, the devices
have many new features. In general, software written for existing 8051-based systems works without
modification on the DS87C520/DS83C520. The exception is critical timing since the high-speed
microcontrollers performs instructions much faster than the original for any given crystal selection. The
DS87C520/DS83C520 run the standard 8051 family instruction set and are pin compatible with DIP,
PLCC, or TQFP packages.
The DS87C520/DS83C520 provide three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of
direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051
product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with
original 8051 family systems. However, timers are individually programmable to run at the new four
clocks per cycle if desired. The PCA is not supported.
The DS87C520/DS83C520 provide several new hardware features implemented by new special function
registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C520/DS83C520 feature a high-speed 8051-compatible core. Higher speed comes not just from
increasing the clock frequency but also from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the
DS87C520/DS83C520, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine
cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions.
The majority of instructions on the DS87C520/DS83C520 will see the full 3-to-1 speed improvement.
Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the
original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements
produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user
to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and
other status functions is identical. However, the timing of each instruction is different. This applies both
in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the
High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks
per increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
The relative time of two instructions might be different in the new architecture than it was previously. For
example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”
instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of
time. In the DS87C520/DS83C520, the MOVX instruction takes as little as two machine cycles or eight
oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While
both are faster than their original counterparts, they now have different execution times. This is because
the DS87C520/DS83C520 usually use one instruction cycle for each instruction byte. The user concerned
with precise program timing should examine the timing of each instruction for familiarity with the
changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some require five. In the original architecture, all were one
or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for
details and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C520/DS83C520. This
allows the DS87C520/DS83C520 to have many new features but use the same instruction set as the 8051.
When writing software to use a new feature, an equate statement defines the SFR to an assembler or
compiler. This is the only change needed to access the new function. The DS87C520/DS83C520
duplicate the SFRs contained in the standard 80C52. Table 1 shows the register addresses and bit
locations. The High-Speed Microcontroller User’s Guide describes all SFRs.
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
Table 1. Special Function Register Locations
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
PORT1
EXIF
SCON0
SBUF0
P2
IE
SADDR0
SADDR1
P3
IP
SADEN0
SADEN1
SCON1
SBUF1
ROMSIZE
PMR
STATUS
TA
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
PSW
WDCON
ACC
EIE
B
EIP
Note: New functions are in bold.
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 80h
81h
82h
83h
84h
85h
0 0 0 0 0 0 0 SEL
SMOD_0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h
GATE
8Ah
8Bh
8Ch
8Dh
WD1 WD0 T2M T1M T0M MD2 MD1 MD0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 90h
IE5 IE4 IE3 IE
SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h
99h
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 A0h
EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h
A9h
AAh
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 B0h
— PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h
B9h
BAh
SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 R1_1
SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
— — — — —
CD1 CD0 SWB — XTOFF ALEOFF DME1 DME0
PIP HIP LIP XTUP SPTA1 SPTA1 SPTA0 SPRA0
TF2 EXF2 RCLK TCLK EXEN2 TR2
— — — — — — T2OE DCEN C9h
CAh
CBh
CCh
CDh
CY AC F0 RS1 RS0 OV FL P D0h
SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT
E0h
— — —
F0h
— — —
SMOD0
C/T
— — GF1 GF0 STOP IDLE 87h
M1 M0 GATE
XT/RG
EWDI EX5 EX4 EX3 EX2
PWDI PX5 PX4 PX3 PX2
C/T
RGMD RGSL BGS
RMS2 RMS1 RMS0
M1 M0 89h
C/T2 C/RL2
86h
8Eh
91h
C0h
C1h
C2h
C4h
C5h
C7h
C8h
D8h
E8h
F8h
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
MEMORY RESOURCES
Like the 8051, the DS87C520/DS83C520 use three memory areas. The total memory configuration of the
DS87C520/DS83C520 is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM.
The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is
reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes
of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap
among the 256 bytes and the 1kB as they use different addressing modes and separate instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CERDIP should be covered without regard to the
programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC
parameters listed in the data sheet.
PROGRAM MEMORY ACCESS
On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the
maximum address of on-chip ROM will cause the device to access off-chip memory. However, the
maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can
cause the DS87C520/DS83C520 to behave like a device with less on-chip memory. This is beneficial
when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically
variable. Thus a portion of memory can be removed from the memory map to access off-chip memory,
and then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the
memory map allowing the full 64kB memory space to be addressed from off-chip memory. ROM
addresses that are larger than the selected maximum are automatically fetched from outside the part via
Ports 0 and 2. A depiction of the ROM memory map is shown in Figure 2.
The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2,
RMS1, RMS0 have the following effect.
RMS2 RMS1 RMS0 MAXIMUM ON-CHIP ROM ADDRESS
0 0 0 0kB
0 0 1 1kB/03FFh
0 1 0 2kB/07FFh
0 1 1 4kB/0FFFh
1 0 0 8kB/1FFFh
1 0 1 16kB (default)/3FFFh
1 1 0 Invalid—reserved
1 1 1 Invalid—reserved
The reset default condition is a maximum on-chip ROM address of 16kB. Thus no action is required if
this feature is not used. When accessing external program memory, the first 16kB would be inaccessible.
To select a smaller effective ROM size, software must alter bits RMS2–RMS0. Altering these bits
requires a Timed-Access procedure as explained later.
Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For
example, assume that the DS87C520/DS83C520 are executing instructions from internal program
memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a
16kB internal program space. If software reconfigures the ROMSIZE register to 4kB (0000h–0FFFh) in
the current state, the device will immediately jump to external program execution because program code
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
from 4kB to 16kB (1000h–3FFFh) is no longer located on-chip. This could result in code misalignment
and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register
from a location in memory that will be internal (or external) both before and after the operation. In the
above example, the instruction which modifies the ROMSIZE register should be located below the 4kB
(1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should
be applied if the internal program memory size is modified while executing from external program
memory.
Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051
method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA
overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable
when Ports 0 and 2 fetch from external ROM.
Figure 2. ROM Memory Map
ROM SIZE ADJUSTABLE
DEFAULT = 16kB
ROM SIZE IGNORED
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C520/DS83C520 contain on-chip data memory. They also
contain the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The
MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this
area as though it was located off-chip. The 1kB of SRAM is between address 0000h and 03FFh.
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 03FFh automatically go to external memory through
Ports 0 and 2.
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default
condition. This default allows the DS87C520/DS83C520 to drop into an existing system that uses these
addresses for other hardware and still have full compatibility.
The on-chip data area is software selectable using 2 bits in the Power Management Register at location
C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to
reach off-chip devices at the same addresses. Th
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
setting. When desiring maximum speed, software should select a Stretch value of 0. When using very
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0.
This results in a wider read/write strobe and relaxed interface timing, allowing more time for
memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical
Specifications section. Table 3 shows the resulting strobe widths for each Stretch value. The memory
Stretch uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is
selected using bits CKCON.2–0. In the table, these bits are referred to as M2 through M0. The first
Stretch (default) allows the use of common 120ns RAMs without dramatically lengthening the memory
access.
Table 3. Data Memory Cycle Stretch Values
CKCON.2-0
MEMORY CYCLES
M2 M1 M0
0 0 0 2 (forced internal) 2 60
0 0 1 3 (default external) 4 121
0 1 0 4 8 242
0 1 1 5 12 364
1 0 0 6 16 485
1 0 1 7 20 606
1 1 0 8 24 727
1 1 1 9 28 848
RD OR WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH
TIME at 33MHz (ns)
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard
8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS87C520/DS83C520, this data pointer is called DPTR0, located at SFR addresses 82h and 83h. These
are the original locations. Using DPTR requires no modification of standard code. The new DPTR at SFR
84h and 85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location is the
lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user switches
between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest
way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity.
Therefore it takes only one instruction to switch from a source to a destination address. Using the Dual
Data Pointer saves code from needing to save source and destination addresses when doing a block move.
The software simply switches between DPTR0 and 1 once software loads them. The relevant register
locations are as follows:
DPL 82h Low byte original DPTR
DPH 83h High byte original DPTR
DPL1 84h Low byte new DPTR
DPH1 85h High byte new DPTR
DPS 86h DPTR Select (lsb)
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DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
POWER MANAGEMENT
Along with the standard Idle and power down (Stop) modes of the standard 80C52, the
DS87C520/DS83C520 provide a new Power Management Mode. This mode allows the processor to
continue functioning, yet to save power compared with full operation. The DS87C520/DS83C520 also
feature several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU
to run software but to use substantially less power. During default operation, the DS87C520/DS83C520
use four clocks per machine cycle. Thus the instruction cycle rate is Clock/4. At 33MHz crystal speed,
the instruction cycle speed is 8.25MHz (33/4). In PMM, the microcontroller continues to operate but uses
an internally divided version of the clock source. This creates a lower power state without external
components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed
below). The speeds are (Clock/64) and (Clock/1024).
Software is the only mechanism to invoke the PMM. Table 4 illustrates the instruction cycle rate in PMM
for several common crystal frequencies. Since power consumption is a direct function of operating speed,
PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing.
PMM 2 runs very slow and provides the lowest power consumption without stopping the CPU. This is
illustrated in Table 5.
Note that PMM provides a lower power condition than Idle mode. This is because in Idle mode, all
clocked functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast
as or faster than from Idle, and PMM allows the CPU to operate (even if doing NOPs), there is little
reason to use Idle mode in new designs.
Table 4. Machine Cycle Rate
CRYSTAL SPEED
(MHz)
11.0592 2.765 172.8 10.8
16 4.00 250.0 15.6
25 6.25 390.6 24.4
33 8.25 515.6 32.2
FULL OPERATION
(4 CLOCKS)
(MHz)
Table 5. Typical Operating Current in PMM
CRYSTAL SPEED
(MHz)
11.0592 13.1 5.3 4.8
16 17.2 6.4 5.6
25 25.7 8.1 7.0
33 32.8 9.8 8.2
FULL OPERATION
(4 CLOCKS)
(mA)
14 of 45
PMM1
(64 CLOCKS)
(kHz)
PMM1
(64 CLOCKS)
(mA)
PMM2
(1024 CLOCKS)
(kHz)
PMM2
(1024 CLOCKS)
(mA)
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