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GENERAL DESCRIPTION
The DS80C400 network microcontroller offers the highest
integration available in an 8051 device. Peripherals include
a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B
controller, 1-Wire
To enable access to the network, a full applicationaccessible TCP IPv4/6 network stack and OS are provided
in ROM. The network stack supports up to 32 simultaneous
TCP connections and can transfer up to 5Mbps through the
Ethernet MAC. Its maximum system-clock frequency of
75MHz results in a minimum instruction cycle time of 54ns.
Access to large program or data memory areas is
simplified with a 24-bit addressing scheme that supports up
to 16MB of contiguous memory.
To accelerate data transfers between the microcontroller
and memory, the DS80C400 provides four data pointers,
each of which can be configured to automatically increment
or decrement upon execution of certain data pointer-related
instructions. The DS80C400’s hardware math accelerator
further increases the speed of 32-bit and 16-bit multiply
and divide operations as well as high-speed shift,
normalization, and accumulate functions.
The High-Speed Microcontroller User’s Guide and the High-Speed
Microcontroller User’s Guide: DS80C400 Supplement should be
used in conjunction with this data sheet. Download both at:
www.maxim-ic.com/microcontrollers
®
Master, and 64 I/O pins.
.
APPLICATIONS
Industrial Control/Automation
Environmental Monitoring
Network Sensors Remote Data Collection
Vending
Home/Office Automation
Data Converters (Serial-to-
Ethernet, CAN-toEthernet)
Equipment
Transaction/Payment
Terminals
ORDERING INFORMATION
PART TEMP RANGE
DS80C400-FNY -40°C to +85°C 75MHz 100 LQFP
1-Wire is a registered trademark of Dallas Semiconductor.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
MAX CLOCK
SPEED
PINPACKAGE
DS80C400
Network Microcontrolle
FEATURES
§ High-Performance Architecture
Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate
Flat 16MB Address Space
Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement
16/32-Bit Math Accelerator
§ Multitiered Networking and I/O
10/100 Ethernet Media Access Controller (MAC)
CAN 2.0B Controller
1-Wire Net Controller
Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O
Pins)
§ Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP
and TFTP
Full, Application-Accessible TCP/IP Network Stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler
MAC Address can Optionally be Acquired from IEEE-
Registered DS2502-E48
§ 10/100 Ethernet Mac
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC
(10Mbps) Interfaces Allow Selection of PHY
Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet
and Wake-Up Frame Detection
8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU
Half- or Full-Duplex Operation with Flow Control
Multicast/Broadcast Address Filtering with VLAN
Support
§ Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet
Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
§ Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
Features continued on page 32.
Pin Configuration appears at end of data sheet.
™
™
, SDS, and
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1 of 96
REV: 102103
.
DS80C400 Network Microcontroller
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input Pin Relative to Ground -0.5V to +5.5V
Voltage Range on Any Output Pin Relative to Ground -0.5V to (V
Voltage Range on V
Voltage Range on V
Relative to Ground -0.5V to +3.6V
CC3
Relative to Ground -0.3V to +2.0V
CC1
+ 0.5)V
CC3
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C max
Storage Temperature Range -55°C to +160°C
Soldering Temperature See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 1)
(V
= 3.0V to 3.6V, V
CC3
Supply Voltage (V
Power-Fail Warning (V
Power-Fail Reset Voltage (V
Active Mode Current (V
VCC3
Idle Mode Current (V
Stop Mode Current (V
Stop Mode Current, Bandgap Enabled (V
Supply Voltage (V
Power-Fail Warning (V
Power-Fail Reset Voltage (V
Active Mode Current (V
VCC1
Idle Mode Current (V
Stop Mode Current (V
Stop Mode Current, Bandgap Enabled (V
Input Low Level V
Input Low Level for XTAL1, RST, OW V
Input High Level V
Input High Level for XTAL1, RST, OW V
Output Low Current for Port 1, 3–7 at VOL = 0.4V I
Output Low Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,
RSTOL, ALE, PSEN, and Ports 3–7 (when used as any of the following:
A21–A0, WR, RD, CE0-7, PCE0-3) at V
Output Low Current for OW, OWSTP at VOL= 0.4V
Output High Current for Port 1, 3–7 at VOH = V
Output High Current for Port 1, 3–7 at VOH= V
Output High Current for Port 0, 2, TX_EN, TXD[3:0], MDC, MDIO,
RSTOL, ALE, PSEN, and Ports 3–7 (when used as any of the following:
A21–A0, WR, RD, CE0-7, PCE0-3) at V
Input Low Current for Port 1–7 at 0.4V (Note 10) IIL -50 -20 -10
Logic 1-to-0 Transition Current for Port 1, 3–7 (Note 11) ITL -650 -400
Input Leakage Current, Port 0 Bus Mode, VIL = 0.8V (Note 12) I
Input Leakage Current, Port 0 Bus Mode, VIH = 2.0V (Note 12) I
Input Leakage Current, Input Mode (Note 13) IL -15 0 15
RST Pulldown Resistance R
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: The user should note that this part is tested and guaranteed to operate down to V
thresholds for those supplies, V
supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum operating
point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower than the
guaranteed minimum operating voltage, there exists a range of voltages for either supply, (V
3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not be an issue in
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
PARAMETER SYMBOL MIN TYP MAX UNITS
) (Note 2) V
CC3
) (Note 3) V
CC3
) (Note 3) V
CC3
) (Note 4) I
CC3
) (Note 4) I
CC3
) (Not 4) I
CC3
) (Note 4) I
CC3
) (Note 2) V
CC1
) (Note 5) V
CC1
) (Note 5) V
CC1
) (Note 4) I
CC1
) (Note 4) I
CC1
) (Note 4) I
CC1
) (Note 4) I
CC1
= 0.4V (Note 6)
OL
- 0.4V (Note 7) I
CC3
- 0.4V (Note 8) I
CC3
= V
OH
- 0.4V (Notes 6, 9)
CC3
3.0 3.3 3.6 V
CC3
2.85 3.00 3.15 V
PFW3
2.76 2.90 3.05 V
RST3
16 35 mA
CC3
7 15 mA
IDLE3
1 10
STOP3
100 150
SPBG3
1.62 1.8 1.98 V
CC1
1.52 1.60 1.68 V
PFW1
1.47 1.55 1.63 V
RST1
27 50 mA
CC1
20 40 mA
IDLE1
0.2 10 mA
STOP1
0.2 10 mA
SPBG1
0.8 V
IL1
1.0 V
IL2
2.0 V
IH1
2.4 V
IH2
6 10 mA
OL1
12 20 mA
I
OL2
10 16 mA
I
OL3
-75 -50
OH1
-8 -4 mA
OH2
I
-16 -8 mA
OH3
mA
mA
mA
mA
mA
20 50 200
TH0
-200 -50 -20
TL0
mA
mA
mA
RST3
and V
50 100 200
RST
= 3.0V and V
respectively, may be above or below those points. When the reset threshold for a given
RST1
CC3
RST3
< V
= 1.62V, while the reset
CC1
< 1.62V) or (V
CC3
RST1
< V
kW
CC1
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<
DS80C400 Network Microcontroller
most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be
desirable to use a more accurate external reset.
Note 3: While the specifications for V
PFW3
and V
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
RST3
given, there is a guaranteed separation between these two voltages.
Note 4: Current measured with 75MHz clock source on XTAL1, V
= 3.6V, V
CC3
= 2.0V, EA and RST = 0V, Port0 = V
CC1
, all other pins
CC3
disconnected.
Note 5: While the specifications for V
PFW1
and V
overlap, the design of the hardware makes it such that this is not possible. Within the ranges
RST1
given, there will be a guaranteed separation between these two voltages.
Note 6: Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-6.5
(CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
Note 7: This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V
pin state can be achieved by applying RST = V
CC3.
). This I/O
OH2
Note 8: The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (V
) remains in effect following the strong two-clock cycle
OH1
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Note 9: Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition of
either WR or RD from a 0 to a 1.
Note 10: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to
1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Note 11: Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port
0 pin is driven by an external memory source.
Note 13: The OW pin (when configured to output a 1) at V
CRS, COL, MDIO) at V
= 3.6V.
IN
= 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
IN
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL
External Crystal Frequency 4 40
Clock Multiplier 4X Mode
External Clock Oscillator Frequency DC 75
Clock Mutliplier 2X Mode 16 37.5
Clock Multiplier 4X Mode
ALE Pulse Width 15.0 t
Port 0 Instruction Address Valid to ALE Low t
Address Hold After ALE Low t
ALE Low to Valid Instruction In t
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instruction In t
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
PSEN Low to Address Float
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t
Note 4: The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5: All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following signals,
Note 6: For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid bus
Note 7: References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
, t
CLCH
, t
CHCL
CLCL
External Clock Oscillator (XTAL1) Characteristics table.
when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 ( PCE0-3),
Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
contention.
determing absolute signal timing with respect to the external clock.
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
75MHz VARIABLE CLOCK
MIN MAX MIN MAX
1 / t
CLK
16 37.5 Clock Mutliplier 2X Mode
11 18.75
1 / t
CLK
11 18.75
+ t
CLCL
1.7 t
LHLL
4.7 t
AVLL
14.3 2t
LLAX
3.7 t
t
LLIV
21.7 2t
t
LLPL
9.7 2t
t
PLPH
0 0 ns
t
PLIV
8.3 t
t
PXIX
21.0 3t
AVIV0
27.7 3t
t
AVIV2
0 0 ns
t
PLAZ
CHCL
CLCH
CLCH
- 5 ns
CHCL
- 5 ns
- 2 ns
+ t
CLCL
- 3 ns
- 5 ns
CLCL
CLCL
CLCL
CLCL
+ t
CLCL
are time periods associated with the internal system clock and are related to the external clock (t
3 of 96
UNITS
MHz
MHz
- 19 ns
CLCH
-17 ns
- 5 ns
- 19 ns
- 19 ns
CLCH
) as defined in the
CLK
DS80C400 Network Microcontroller
EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS
PARAMETER SYMBOL MIN MAX UNITS
Clock Oscillator Period t
Clock Symmetry at 0.5 x V
t
CC3
CLK
0.45 t
CH
See External Clock
Oscillator Frequency
0.55 t
CLK
ns
CLK
Clock Rise Time tCR 3 ns
Clock Fall Time tCF 3 ns
EXTERNAL CLOCK DRIVE
t
CF
tCR
XTAL1
t
CH
tCL
t
CLK
SYSTEM CLOCK TIME PERIODS (t
SYSTEM CLOCK SELECTION
4X/2X
CD1 CD0
1 0 0 t
0 0 0 t
X 1 0 t
X 1 1 256 t
Note 1: Figure 20 shows a detailed description and illustration of the system clock selection.
Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the
minimum/maximum system clock high (t
SYSTEM CLOCK
PERIOD t
/ 4 0.45 (t
CLK
/ 2 0.45 (t
CLK
0.45 t
CLK
CLK
) and system clock low (t
CHCL
CLCL
, t
CHCL
, t
CLCH
SYSTEM CLOCK HIGH (t
CLCL
SYSTEM CLOCK LOW (t
MIN MAX
0.45 (256 t
) periods are directly related to clock oscillator duty cycle.
CLCH
)
/ 4) 0.55 (t
CLK
/ 2) 0.55 (t
CLK
0.55 t
CLK
0.55 (256 t
CLK)
CHCL
) AND
CLCH
CLK
CLK
)
CLK
/ 4)
/ 2)
CLK)
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL MIN MAX UNITS
MOVX ALE Pulse Width t
Port 0 MOVX Address Valid
to ALE Low
Port 0 MOVX Address Hold
after ALE Low
RD Pulse Width (P3.7 or
PSEN)
WR Pulse Width (P3.6)
RD (P3.7 or PSEN) Low to
Valid Data In
Data Hold After RD (P3.7 or
PSEN) High
= 1.8V ±10%, TA = -40 °C to +85°C.)
CC1
t
+ t
CLCL
LHLL2
2t
6t
t
CHCL
t
AVLL2
t
CLCL
5t
t
5t
2t
(4 x C
2t
(4 x C
CLCH
t
CLCL
t
LLAX2
and t
LLAX3
t
RLRH
t
WLWH
t
RLDV
-2 ns
t
RHDX
- 5 CST = 0
CHCL
- 5
CLCL
- 5
CLCL
- 5 CST = 0
- 6
- 6
CLCL
- 2 CST = 0
- 2
- 2
CLCL
- 5 CST = 0
CLCL
) t
ST
CLCL
ST
- 3
CLCL
- 5 CST = 0
) t
- 3
CLCL
2t
(4 x C
STRETCH VALUES
C
ns
1£ C
4 £ C
ns
1£ C
4 £ C
ns
1£ C
4 £ C
ns
ns
- 17 CST = 0
CLCL
ST
) t
CLCL
- 17
ns
1 £ C
1 £ C
1 £ C
(MD2:0)
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
£ 3
£ 7
£ 3
£ 7
£3
£ 7
£ 7
£ 7
£ 7
4 of 96
DS80C400 Network Microcontroller
PARAMETER SYMBOL MIN MAX UNITS
Data Float After RD (P3.7 or
PSEN) High
t
RHDZ
t
2t
6t
2t
ALE Low to Valid Data In t
LLDV
(4 x CST + 1) t
(4 x CST + 5) t
Port 0 Address to Valid Data
In
t
AVDV0
3t
(4 x CST + 2)t
(4 x CST + 10)t
3t
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
t
AVDV2
Data In
ALE Low to (RD or PSEN) or
WR Low
Port 0 Address to (RD or
PSEN) or WR Low
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
(RD or PSEN) or WR High to
ALE
t
LLWL
t
AVWL0
t
t
AVWL2
2t
10t
0 ns
t
QVWX
t
WHQX
(Note 2)
t
RLAZ
t
WHLH
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
t
WHLH2
t
5t
t
- 3 t
CLCH
t
- 3 t
CLCL
5t
- 3 5t
CLCL
t
- 5 CST = 0
CLCL
2t
- 6
CLCL
10t
- 6
CLCL
+ t
CLCL
CLCL
CLCL
2
6t
t
CLCL
- 5 CST = 0
CLCH
+ t
- 5
CLCH
+ t
- 5
CLCH
- 4 CST = 0
- 7
CLCL
- 7
CLCL
0 7 CST = 0
t
- 3 t
CLCL
5t
- 3 5t
CLCL
t
-5 t
CHCL
+ t
+ t
CHCL
CHCL
- 5 t
- 5 5t
CLCL
CLCL
(4 x C
(4 x C
ST
CLCL
CLCL
- 5 CST = 0
CLCL
- 5
CLCL
- 5
CLCL
+ t
CLCL
CLCL
ST
+ 2)t
- 19 CST = 0
CLCH
- 19
CLCL
- 19
CLCL
- 19 CST = 0
CLCL
- 19
CLCL
- 19
CLCL
+ t
- 19 CST = 0
CLCH
+ t
CLCL
CLCH
19
+ 10)t
CLCL
+ t
CLCH
ns
ns
ns
ns
-
20
+ 6 CST = 0
CLCH
CLCL
CLCL
+ 6
+ 6
ns
ns
ns
ns
+ 4
CLCL
+ 4
CLCL
+ 13 CST = 0
CHCL
+ t
+ 13
CHCL
+ t
+ 13
CHCL
ns
ns
STRETCH VALUES
(MD2:0)
C
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
1£ CST £ 3
4 £ CST £ 7
£ 3
1 £ C
ST
£ 7
4 £ C
ST
£ 3
1 £ C
ST
£ 7
4 £ C
ST
£ 3
1 £ C
ST
£ 7
4 £ C
ST
£ 3
1 £ C
ST
£ 7
4 £ C
ST
£ 7
0£ C
ST
£ 3
1 £ C
ST
£ 7
4 £ C
ST
£ 3
1 £ C
ST
£ 7
4 £ C
ST
, t
, t
CLCL
CLCH
are time
CHCL
5 of 96
DS80C400 Network Microcontroller
6 of 96
DS80C400 Network Microcontroller
7 of 96
MULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
DS80C400 Network Microcontroller
PORT 4/6 ADDRESS
A16 -A21
-
A16 -A21 A16 -A21
MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21
A16 -A21 A16 -A21
A16 -A21
8 of 96
DS80C400 Network Microcontroller
MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21
A16 -A21
A16 -A21
MULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
A16 -A21
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21
A16 -A21
A16 -A21 A16 -A21
9 of 96
MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21 A16 -A21
A16 -A21
MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE
DS80C400 Network Microcontroller
A16 -A21
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
-
-
10 of 96
-
A16 -A21
DS80C400 Network Microcontroller
MULTIPLEXED, 9-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21 A16 -A21 A16 -A21
MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
A16 -A21
PORT 4/6
ADDRESS
A16 -A21 A16 -A21 A16 -A21
A16 -A21
11 of 96
MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
DS80C400 Network Microcontroller
PORT 4/6
ADDRESS
A16 -A21
A16 -A21 A16 -A21
A16 -A21
12 of 96
DS80C400 Network Microcontroller
ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL
External Crystal Frequency 4 40
Clock Mutliplier 2X Mode 16 37.5
Clock Multiplier 4X Mode
External Oscillator Frequency DC 75
Clock Mutliplier 2X Mode 16 37.5
Clock Multiplier 4X Mode
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 7 Address to Valid Instruction In t
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: t
Note 4: The precalculated 75MHz min/max timing specifications assume an exact 50% duty cycle.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
, t
CLCL
the System Clock Time Periods table.
, t
CLCH
CHCL
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
determing absolute signal timing with respect to the external clock.
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
75MHz VARIABLE CLOCK
MIN MAX MIN MAX
1 / t
CLK
11 18.75
1 / t
CLK
11 18.75
21.7 2t
t
PLPH
9.7 2t
t
PLIV
0 0 ns
t
PXIX
t
PXIZ
21.0 3t
AVIV1
27.7 3t
t
AVIV2
are time periods associated with the internal system clock and are related to the external clock (t
- 5 ns
CLCL
CLCL
See MOVX
Characteristics
CLCL
+ t
CLCL
CLCH
UNITS
MHz
MHz
- 17 ns
ns
- 19 ns
- 19 ns
) as defined in the
CLK
13 of 96
DS80C400 Network Microcontroller
MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL MIN MAX UNITS
Input Instruction Float After PSEN
PSEN High to Data Address, Port 4 CE,
Port 5 PCE Valid
RD Pulse Width (P3.7 or PSEN)
WR Pulse Width (P3.6)
RD (P3.7 or PSEN) Low to Valid Data In
Data Hold After RD (P3.7 or PSEN) High
Data Float After RD (P3.7 or PSEN) High
PSEN High to WR Low
PSEN High to (RD or PSEN) Low
Port 7 Address to Valid Data In t
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to Valid Data In
Port 7 Address to (RD or PSEN) or WR
Low
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to (RD or PSEN) or WR Low
Data Valid to WR Transition
Data Hold After WR High
(RD or PSEN) or WR High to Port 4 CE
or Port 5 PCE High
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. t
Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing
associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0–A7).
absolute signal timing with respect to the external clock.
= 1.8V +±10%, TA = -40°C to +85°C.)
CC1
t
PXIZ
t
t
PHAV
t
RLRH
t
WLWH
t
RLDV
-2 ns
t
RHDX
t
RHDZ
2t
(4 x C
2t
(4 x C
2t
t
PHWL
3t
11t
2t
t
PHRL
3t
11t
AVDV1
t
AVDV2
t
t
AVWL1
2t
10t
t
CLCL
2t
t
AVWL2
0 ns
t
QVWX
10t
CLCL
CLCL
t
t
WHQX
2
6t
t
t
WHCEH
t
5t
CLCL
CLCL
14 of 96
CST (MD2:0)
2t
3t
11t
- 3 ns
CHCL
- 5 CST =0
CLCL
) t
ST
CLCL
ST)tCLCL
- 3
CLCL
- 5 CST =0
- 3
2t
(4 x C
t
2t
6t
- 3 CST = 0
CLCL
- 3
CLCL
- 3
CLCL
- 3 CST = 0
CLCL
- 3
CLCL
- 3
CLCL
3t
(4 x CST + 2)t
3t
- 5 CST = 0
CLCL
- 5
CLCL
- 5
CLCL
+ t
- 5 CST = 0
CLCH
+ t
- 5
CLCH
+ t
- 5
CLCH
- 4 CST = 0
CLCL
- 7
CLCL
- 7
CLCL
- 5 t
CHCL
+ t
- 5 t
CHCL
+ t
-5 5t
CHCL
(4 x C
CLCL
(4 x C
(4 x C
CLCL
CLCL
- 5 CST = 0
CLCL
CLCL
CLCL
- 5
- 5
ns
ns
ns
- 17 CST = 0
CLCL
- 17
ST)tCLCL
- 5 CST = 0
CLCL
- 5
CLCL
- 5
CLCL
ns
ns
ns
ns
- 19 CST = 0
CLCL
- 19
+ 10)t
ST
CLCL
CLCL
-
ns
19
+ t
- 19 CST = 0
CLCH
ST
t
CLCH
ST
t
CLCH
+ 2)t
+ 10)t
- 19
- 19
CLCL
CLCL
+
ns
+
ns
ns
ns
+ 13 CST = 0
CHCL
CLCL
ns
, t
, t
CLCH
are time periods
CHCL
+ t
+ t
CHCL
CHCL
+12
+12
STRETCH
VALUES
£ 3
1£ C
ST
£ 7
4 £ C
ST
£ 7
1 £ C
ST
1 £ C
£ 7
ST
1 £ C
£ 7
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
£ 3
1£ C
ST
4 £ C
£ 7
ST
£ 3
1£ C
ST
£ 7
4 £ C
ST
1£ CST £ 3
£ 7
4 £ C
ST
£ 3
1 £ C
ST
4 £ C
£ 7
ST
£ 3
1 £ C
ST
4 £ C
£ 7
ST
£ 3
1 £ C
ST
4 £ C
£ 7
ST
£ 3
1 £ C
ST
4 £ C
£ 7
ST
DS80C400 Network Microcontroller
15 of 96
DS80C400 Network Microcontroller
l
16 of 96
DS80C400 Network Microcontroller
NONMULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
-
A16 -A21
A16 -A21 A16 -A21
NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21
PORT 7
A16 -A21
A16 -A21 A16 -A21
17 of 96
NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
DS80C400 Network Microcontroller
PORT 4/6 ADDRESS
PORT 7
A16 -A21
A16 -A21 A16 -A21
NONMULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
A16 -A21
PORT 4/6 ADDRESS
PORT 7
A16 -A21
A16 -A21
18 of 96
A16 -A21
A16 -A21
NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
A16 -A21
A16 -A21 A16 -A21
DS80C400 Network Microcontroller
A16 -A21
PORT 7
NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
PORT 7
A16 -A21 A16 -A21 A16 -A21 A16 -A21
19 of 96
DS80C400 Network Microcontroller
7
NONMULTIPLEXED, 9-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
PORT 4/6 ADDRESS
PORT
A16 -A21
A16 -A21
-
NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
-
PORT 4/6 ADDRESS
PORT 7
A16 -A21
A16 -A21 A16 -A21
A16 -A21
20 of 96
NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE
PORT 4 – 3CE0 -
PORT 6 – 7-CE4
DS80C400 Network Microcontroller
PORT 4/6 ADDRESS
PORT 7
A16 -A21 A16 -A21
A16 -A21 A16 -A21
OW PIN TIMING CHARACTERISTICS (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL
Transmit Reset Pulse Low Time
(Note 2)
Transmit Reset Pulse High Time
(Note 2)
Wait Time for Transmit of Presence
Pulse (Notes 2, 3)
Wait Time for Absence of Presence
Pulse (Notes 2, 4)
Presence Pulse Width (Note 2) t
Presence Pulse Sampling Time
(Note 2)
Read/Write Data Time Slot t
Low Time for Write 1 t
Low Time for Write 0 t
Write Data Sampling Time t
Read Data Sampling Time t
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: In PMM mode, the master pulls the line low after the first 15ms for the remainder of the standard speed 1-Wire routine.
Note 3: This parameter quantifies the wait time for the slave devices to respond to the reset pulse and is dependent on the slave device timing.
Note 4: This parameter quantifies the wait time for the case when no presence pulse detected.
Note 5: The maximum timing figures shown apply only when an exact 1-Wire clock frequency can be achieved from the microcontroller input
.
clock
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
STANDARD OVERDRIVE LONGLINE
MIN MAX MIN MAX MIN MAX
500.8 626 50.4 63 500.8 626
t
RSTL
t
508.8 636 59.2 74 508.8 636
RSTH
15 60 2 6 15 60
t
PDH
60 75 6.4 8 60 75
t
PDHCNT
60 240 8 24 60 240
PDL
24 31 2.4 4 30.4 38
t
PDS
68.8 86 12 15 68.8 86
SLOT
4.8 6 0.8 1 7.2 9
LOW1
62.4 78 8 10 62.4 78
LOW0
15 60 2 6 25 60
WDV
12 15 1.6 2 20 25
RDV
UNITS
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
21 of 96
OW PIN TIMING
DS80C400 Network Microcontroller
22 of 96
DS80C400 Network Microcontroller
OWSTP PIN TIMING CHARACTERISTICS (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL
Active Time for Presence Detect t
Active Time for Presence Detect Recovery t
Active Time for Write 1 Recovery (Notes 2, 3) t
Active Time for Write 0 Recovery (Notes 2, 3) t
Delay Time for Presence Detect t
Delay Time for Presence Detect Recovery (Note 4) t
Delay Time for Write 1/Write 0 Recovery t
Turn-Off Time for 1-Wire Reset t
Turn-Off Time for Write 1/Write 0 (Note 5) t
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: There is no OWSTP timing difference for sending out and receiving bits within a byte. The difference comes when the last bit of the byte
Note 3: When performing a read versus a write time slot, the master provides the same active time for write 1 and write 0. However, the
Note 4: This parameter is the time delay until the master begins to monitor the OW pin level. If the line is already high, then OWSTP is enabled.
Note 5: The very first bit in a byte has an extended turn-off time of 4ms because of the order of states that the 1-Wire master state machine
has been completely sent. At this point, the signal is either enabled continuously until the next reset or time slot begins, or enabled only
for active time write 1 or write 0.
Schmitt-triggered input from the OW line is sensed every 1ms for a high value. If OW is high, the OWSTP signal is enabled. If the OW
line is low, the OWSTP signal remains disabled until a high state is sensed. In all write time slots, a high is sensed immediately.
If not, it waits to enable OWSTP until the next state machine clock (1ms or 50ns) after the OW line recovers.
must go through.
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
ON1
ON2
ON3
ON4
DLY1
DLY2
DLY3
OFF1
OFF2
STANDARD OVERDRIVE
MIN MAX MIN MAX
6.4 8 0.8 1
8 10 8 10
51.2 64 7.2 9
6.4 8 0.8 1
0.8 1 0.8 1
399.2 499 31.2 39
0.8 1 0.8 1
1.6 2 1.6 2
0.8 1 0.8 1
UNITS
ms
ms
ms
ms
ms
ms
ms
ms
ms
OWSTP PIN TIMING
23 of 96
DS80C400 Network Microcontroller
ETHERNET MII INTERFACE TIMING CHARACTERISTICS (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL
TXClk Duty Cycle t
TXD, TX_EN Data Setup to TXClk t
TXD, TX_EN Data Hold from TXClk t
RXClk Pulse Width t
RXClk to RXD, RX_DV, RX_ER Valid t
MDC Period t
MDC to Input Data Valid t
MDIO Output Data Setup to MDC t
MDIO Output Data Hold from MDC t
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
MII INTERFACE TIMING
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
14 26 140 260 ns
TDC
10 25 ns
TSU
2 2 ns
THD
14 26 140 260 ns
RDC
10 30 190 210 ns
RDV
400 400 ns
MCLCL
300 300 ns
MDV
10 10 ns
MOS
10 10 ns
MOH
100Mbps 10Mbps
MIN MAX MIN MAX
UNITS
24 of 96
DS80C400 Network Microcontroller
SERIAL PORT MODE 0 TIMING CHARACTERISTICS (Note 1)
(V
= 3.0V to 3.6V, V
CC3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
= 1.8V ±10%, TA = -40°C to +85°C.)
CC1
SM2 = 0:12 clocks per cycle 12 t
Serial Port Clock Cycle Time t
XLXL
SM2 = 1:4 clocks per cycle 4 t
Output Data Setup to Clock
Rising
Output Data Hold from Clock
Rising
t
QVXH
t
XHQX
SM2 = 0:12 clocks per cycle
SM2 = 1:4 clocks per cycle
SM2 = 0:12 clocks per cycle
SM2 = 1:4 clocks per cycle
Input Data Hold After Clock
Rising
t
XHDX
SM2 = 0:12 clocks per cycle 0
SM2 = 1:4 clocks per cycle 0
SM2 = 0:12 clocks per cycle
t
Data Valid
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
XHDV
SM2 = 1:4 clocks per cycle
10 t
3 t
CLCL
10
CLCL
10
CLCL
ns
CLCL
-
-
-
2 t
CLCL
10
-
t
CLCL
ns
ns
10
ns
-
11 t
CLCL
3 t
20 Clock Rising Edge to Input
CLCL
-
ns
20
25 of 96
SERIAL PORT 0 (SYNCHRONOUS MODE)
DS80C400 Network Microcontroller
HIGH-SPEED OPERATION, TXD CLK = SYSCLK/4 (SM2 = 1)
TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 0)
26 of 96
DS80C400 Network Microcontroller
POWER CYCLE TIMING CHARACTERISTICS
PARAMETER SYMBOL MIN TYP MAX UNITS
Crystal Startup Time (Note 1) t
Power-On Reset Delay (Note 2) t
Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox
Note 2: Reset delay is a synchronous counter of crystal oscillations during crystal startup. Counting begins when the level on the XTAL1 input
Electronics.
meets the V
criteria. At 40MHz, this time is approximately 1.64ms.
IH2
POWER CYCLE TIMING
1.8 ms
CSU
65,536 t
POR
CLCK
27 of 96
X
A
MANAGEMENT
I/O
BLOCK DIAGRAM
DS80C400 Network Microcontroller
OW
OWSTP
P1.0–P1.7
P0.0–P0.7
MDC MDIO
MII I/O (15)
P3.0–P3.7
1-WIRE
CONTROLLER
MII
MII
BUFFER CONTROL UNIT
PORT 3
PORT LATCH
PORT LATCH
SRAM
9kk x 8
B
ACCUMULATOR
DATA BUS
PORT 1
ONE’S COMP.
PSW
SERIAL
PORT 0
PORT 1
TIMER 2
PORT 7
PORT LATCH
STACK
MATH
ADDER
ACCELERATOR
POINTER
256 x 8
SFRs/ SRAM
ROM
BOOT
TIMED
ACCESS
LOGIC
INTERRUPT
64k x 8
ADDRESS BUS
PORT LATCH
SERIAL
PORT 2
PORT 2
P2.0–P2.7 P7.0–P7.7
SERIAL
PORT 0
TIMER 0
TIMER 1
CAN
SRAM
TIMER 3
PORT LATCH
PORT 5
P5.0–P5.7
256 x 8
DPTR0
DPTR1
DPTR2
DPTR3
CAN 0
COUNTER
PROGRAM
CONTROLLER
(1)
CC1
V
POWER
CC
V
(4)
CC3
V
OSCILLATOR-
FAIL DETECT
RESET
MONITOR
(4)
SS
V
CONTROL
RST
RSTOL
WATCHDOG
REGISTER
INTRUCTION
MEMORY
CONTROL
CLOCK AND
E
MU
ALE
PSEN
OSCILLATOR
XTAL1
XTAL2
PORT 6
PORT LATCH
PORT 4
PORT LATCH
P6.0–P6.7
P4.0– 4.7
28 of 96
PIN DESCRIPTION
PIN NAME FUNCTION
70 V
12, 36, 62,
87
13, 39, 63,
88
CC1
V
CC3
V
SS
68 ALE
67
69
40
PSEN
EA
MUX
97 RST
98
RSTOL
37 XTAL2
38 XTAL1
86 AD0/D0
85 AD1/D1
84 AD2/D2
83 AD3/D3
82 AD4/D4
81 AD5/D5
80 AD6/D6
79 AD7/D7
89 P1.0
90 P1.1
91 P1.2
92 P1.3
93 P1.4
94 P1.5
95 P1.6
96 P1.7
66
A8
65 A9
64 A10
61 A11
60 A12
+1.8V Core Supply Voltage
+3.3V I/O Supply Voltage
Digital Circuit Ground
Address Latch Enable, Output. When the MUX pin is low, this pin outputs a clock to latch the external address
LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of
an external transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles.
When the MUX pin is high, the pin toggles continuously if the ALEOFF bit is cleared. ALE is forced high when
the device is in a reset condition or if the ALEOFF bit is set while the MUX pin is high.
Program Store Enable, Output. This signal is the chip enable for external program or merged program/data
memory. PSEN provides an active-low pulse and is driven high when external memory is not being accessed.
External Access Enable, Input. Connect to GND to use external program memory. Connect to V
internal ROM.
Multiplex/Demultiplex Select, Input. This pin selects if the address/data bus operates in multiplexed (MUX =
0) or demultiplexed (MUX = 1) mode. The MUX pin is sampled only on a power-on reset.
Reset, Input. The RST input pin contains a Schmitt voltage input to recognize external active-high reset inputs.
The pin also employs an internal pulldown resistor to allow for a combination of wired-OR external-reset
sources. An RC circuit is not required for power-up, as the device provides this function internally.
Reset Output Low, Output. This active-low signal is asserted when the microcontroller has entered reset
through the RST pin; during crystal warm-up period following power-on or stop mode; during a watchdog timer
reset; during an oscillator failure (if OFDE = 1); whenever V
DS80C400 to an external PHY, do not connect the RSTOL to the reset of the PHY. Doing so may disable the
Ethernet transmit.
XTAL1, XTAL2. Crystal oscillator pins support fundamental mode, parallel resonant, AT cut crystals. XTAL1 is
the input if an external clock source is used in place of a crystal. XTAL2 is the output of the crystal amplifier.
AD0–7 (Port 0), I/O. When the MUX pin is connected low, Port 0 is the multiplexed address/data bus. While
ALE is high, the LSB of a memory address is presented. While ALE falls, the port transitions to a bidirectional
data bus. When the MUX pin is connected high, Port 0 functions as the bidirectional data bus. Port 0 cannot be
modified by software. The reset condition of Port 0 pins is high. No pullup resistors are needed.
Port Alternate Function
P0.0 AD0/D0 (Address)/Data 0
P0.1 AD1/D1 (Address)/Data 1
P0.2 AD2/D2 (Address)/Data 2
P0.3 AD3/D3 (Address)/Data 3
P0.4 AD4/D4 (Address)/Data 4
P0.5 AD5/D5 (Address)/Data 5
P0.6 AD6/D6 (Address)/Data 6
P0.7 AD7/D7 (Address)/Data 7
Port 1, I/O. Port 1 can function as either an 8-bit, bidirectional I/O port or as an alternate interface for internal
resources. The reset condition of Port 1 is all bits at logic 1 through a weak pullup. The logic 1 state also serves
as an input mode, since external circuits writing to the port can override the weak pullup. When software clears
any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written to the port pin or a
reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and
input) high state.
Port Alternate Function
P1.0 T2 External I/O for Timer/Counter 2
P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger
P1.2 RXD1 Serial Port 1 Receive
P1.3 TXD1 Serial Port 1 Transmit
P1.4 INT2 External Interrupt 2 (Positive Edge Detect)
P1.5 INT3 External Interrupt 3 (Negative Edge Detect)
P1.6 INT4 External Interrupt 4 (Positive Edge Detect)
P1.7 INT5 External Interrupt 5 (Negative Edge Detect)
A15–A8 (Port 2), Output. Port 2 serves as the MSB for external addressing. The port automatically asserts the
address MSB during external ROM and RAM access. Although the Port 2 SFR exists, the SFR value never
appears on the pins (due to memory access). Therefore, accessing the Port 2 SFR is only useful for MOVX A,
@Ri or MOVX @Ri, A instructions, which use the Port 2 SFR as the external address MSB.
Port Alternate Function
P2.0 A8 Program/Data Memory Address 8
P2.1 A9 Program/Data Memory Address 9
CC1
DS80C400 Network Microcontroller
CC
£ V
or V
£ V
RST1
CC3
. When connecting the
RST3
to use
29 of 96
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