MAXIM DS4510 User Manual

General Description

The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile (NV) I/O pins. It is configured with an industry-standard I

C interface using either fast-mode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose I2Cto-parallel I/O expander with unlimited read/write capability. EEPROM registers allow the power-on value of the I/O pins to be adjusted to keep track of the system’s state through power cycles, and the CPU supervisor’s timer can be adjusted between 125ms and 1000ms to meet most any application need.

Applications

RAM-Based FPGA Bank Switching for Multiple Profiles

Industrial Controls

Cellular Telephones

PC Peripherals

PDAs

Features

♦ Accurate 5%, 10%, or 15% 5V Power-Supply

Monitoring

♦ Programmable Reset Timer Maintains Reset After

Returns to an In-Tolerance Condition

♦ Four Programmable, NV, Digital I/O Pins with

Selectable Internal Pullup Resistor

♦ 64 Bytes of User EEPROM

♦ Reduces Need for Discrete Components

♦ I

C-Compatible Serial Interface

♦ 10-Pin µSOP Package

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

______________________________________________ Maxim Integrated Products 1

I/O

SCL

SDA

TOP VIEW

I/O

GND

SOP

DS4510

RST

Pin Configuration

Ordering Information

DS4510

SDA

SCL

I/O

GND

FPGA

2.7V TO 5.5V

GND

RESET

CONFIG0

CONFIG1

CONFIG2

CONFIG3

FROM

SYSTEM

CONTROLLER

4.7kΩ 4.7kΩ

4.7kΩ

RST

Typical Operating Circuit

Rev 2; 8/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

TRIP

PIN-

PACKAGE

DS4510U-5 5%

10 µSOP

DS4510U-10 10%

10 µSOP

DS4510U-15 15%

10 µSOP

DS4510U-5/T&R 5%

10 µSOP

DS4510U-10/T&R 10%

10 µSOP

DS4510U-15/T&R 15%

10 µSOP

POINT

TEMP RANGE

-40°C to +85°C

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

2 _____________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

(TA= -40°C to +85°C)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on VCC, SDA, and SCL

Pins Relative to Ground.....................................-0.5V to +6.0V

Voltage Range on A

, I/O0, I/O1, I/O2, I/O3Relative

to Ground ..............-0.5V to V

+ 0.5V, not to exceed +6.0V.

Operating Temperature Range ...........................-40°C to +85°C

EEPROM Programming Temperature.....................0°C to +70°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature .......................................See IPC/JEDEC

J-STD-020A Specification

PARAMETER

CONDITIONS

UNITS

Supply Voltage V

(Notes 1) 2.7 5.5 V

Input Logic 1 V

(Note 2)

Input Logic 0 V

DC ELECTRICAL CHARACTERISTICS

(VCC= 2.7V to 5.5V, TA= -40°C to +85°C.)

PARAMETER

CONDITIONS

UNITS

DS4510U-5 4.5

DS4510U-10

VCC Trip Point V

CCTP

DS4510U-15 4.0

Standby Current I

STBY

VCC = 5.0V (Note 3) 50 75 µA

Input Leakage I

µA

3mA sink current 0.4

SDA Low-Level Output Voltage V

6mA sink current 0.6

I/OX Low-Level Output Voltage V

OLIOX

4mA sink current 0.4 V

RST Pin Low-Level Output

10mA sink current (Note 4) 0.4 V

I/OX Pullup Resistors R

4.0 5.0 6.5 kΩ

I/O Capacitance C

I/O

(Note 5) 10 pF

SYMBOL

MIN TYP MAX

SYMBOL

OLRST

0.7 x V

-0.3 +0.3 x V

MIN TYP MAX

4.25 4.375 4.49

-1.0 +1.0

4.625 4.75

4.125 4.24

+ 0.3

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

_____________________________________________________________________ 3

CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See Figure 1)

(VCC= 2.7V to 5.5V, TA= -40°C to +85°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TD1= 0, TD0 = 0

138

TD1= 0, TD0 = 1

275

TD1= 1, TD0 = 0

550

RST Active Time t

RST

TD1= 1, TD0 = 1

TD1= 0, TD0 = 0

138

TD1= 0, TD0 = 1

275

TD1= 1, TD0 = 0

550

VCC Detect to RST t

RPU

TD1= 1, TD0 = 1

VCC Fail to RST t

RPD

410µs

AC ELECTRICAL CHARACTERISTICS (See Figure 5)

(VCC= 2.7V to 5.5V, TA= -40°C to +85°C, timing referenced to V

IL(MAX)

and

IH(MIN)

PARAMETER

CONDITIONS

UNITS

SCL Clock Frequency f

SCL

(Note 6) 0

kHz

Bus Free Time Between Stop and Start Conditions

BUF

1.3 µs

Hold Time (Repeated) Start Condition

0.6 µs

Low Period of SCL t

LOW

1.3 µs

High Period of SCL t

HIGH

0.6 µs

Data Hold Time

0 0.9 µs

Data Setup Time

Start Setup time t

SU:STA

0.6 µs

SDA and SCL Rise Time t

(Note 7)

SDA and SCL Fall Time t

(Note 7)

Stop Setup Time

0.6 µs

SDA and SCL Capacitive Loading

(Note 7)

EEPROM Write Time t

(Note 7) 10 20 ms

112 125

225 250

450 500

900 1000 1100

112 125

225 250

450 500

900 1000 1100

SYMBOL

MIN TYP MAX

400

HD:STA

HD:DAT

SU:DAT

SU:STO

100

20 + 0.1C

300

400

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

4 _____________________________________________________________________

Note 1: All voltages referenced to ground. Note 2: The DS4510 does not obstruct the SDA and SCL lines if V

is switched off, as long as the voltages applied to these

inputs do not violate their min and max input voltage levels.

Note 3: I

STBY

specified with V

equal to 5.0V, and control port-logic pins are driven to ground or VCCfor the corresponding

inactive state (SDA = SCL = V

), does not include pullup resistor current.

Note 4: See Typical Operating Characteristics for the RST output voltage vs. supply voltage. Note 5: This parameter is guaranteed by design.

Note 6: I

C interface timing shown for is for fast-mode (400kHz) operation. This device is also backward compatible with I2C

standard-mode timing.

Note 7: CB—total capacitance of one bus line in picofarads. Note 8: EEPROM write time applies to all the EEPROM memory and SEEPROM memory when SEE = 0. The EEPROM write time

begins at the occurrence of a stop condition.

NONVOLATILE MEMORY CHARACTERISTICS

(VCC= 2.7V to 5.5V, TA= 0°C to +70°C.)

PARAMETER

CONDITIONS

UNITS

Writes +70°C (Note 5)

Typical Operating Characteristics

(VCC= +5.0V, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

DS4510 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

4.54.03.5

3.0 5.0

VCC (10%) TRIP POINT

SDA = SCL = V

I/O CONTROL BITS = 0 I/O PULLUPS DISABLED

SUPPLY CURRENT vs. TEMPERATURE

DS4510 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

6040200-20

-40 80

SDA = SCL = V

SUPPLY CURRENT vs. SCL FREQUENCY

DS4510 toc03

SCL FREQUENCY (kHz)

SUPPLY CURRENT (µA)

300200100

0 400

SDA = V

SYMBOL

MIN TYP MAX

50,000

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

_____________________________________________________________________ 5

Typical Operating Characteristics (continued)

(VCC= +5.0V, TA = +25°C, unless otherwise noted.)

VCC TRIP POINT vs. TEMPERATURE

DS4510 toc04

TEMPERATURE (°C)

TRIP POINT (V)

6040200-20

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

4.0

-40 80

RST OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

DS4510 toc05

SUPPLY VOLTAGE (V)

RESET TRIP VOLTAGE (V)

5.04.53.5 4.01.0 1.5 2.0 2.5 3.00.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0 5.5

5.6kΩ PULLUP RESISTOR ON RST SDA = SCL = V

I/O PULLUP RESISTANCE vs. TEMPERATURE

DS4510 toc06

TEMPERATURE (°C)

I/O PULLUP RESISTANCE (kΩ)

6040200-20

4.80

4.85

4.90

4.95

5.00

5.05

5.10

5.15

5.20

5.25

4.75

-40 80

Pin Description

PIN NAME FUNCTION

I2C Address Input. This input pin determines the chip address of the device. A0 = 0 sets the slave address to 1010000b, A

= 1 sets the slave address to 1010001b.

2 SDA Serial Data Input/Output. Bidirectional I2C data pin.

3 SCL Serial Clock Input. I2C clock input.

4VCCPower Input

5 GND Ground

6 I/O3 Input/Output 3. I2C accessible bidirectional I/O pin.

7 I/O2 Input/Output 2. I2C accessible bidirectional I/O pin.

8 I/O1 Input/Output 1. I2C accessible bidirectional I/O pin.

9 I/O0 Input/Output 0. I2C accessible bidirectional I/O pin.

10 RST Active-Low Reset Output. Open-drain CPU supervisor reset output.

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

6 _____________________________________________________________________

Detailed Description

The DS4510 contains a CPU supervisor, four programmable I/O pins, and a 64-byte EEPROM memory. All functions are configurable or controllable through an industry-standard I2C-compatible bus. DS4510 NV registers that are likely to require frequent modification are implemented using SRAM-shadowed EEPROM (SEEPROM) memory. This memory is configurable to act as volatile SRAM or NV EEPROM by adjusting the SEE bit in the Config register. Configuring the SEEPROM as SRAM eliminates the EEPROM write time and allows infinite write cycles to these registers. Configuring the registers as EEPROM allows the application to change the power-on values that are recalled during power-up.

Programmable CPU Supervisor

The timeout period is adjusted by writing the reset delay register (SEEPROM). The delay for each setting is shown in the CPU Supervisor AC Electrical Characteristics. If the SEE bit is set, changes are writ- ten to SRAM. On power-up the last value written to the EEPROM is recalled. The I2C bus is also used to activate the RST by setting the SWRST bit in the Config register. This bit automatically returns to zero after the timeout period. The Config register also contains the ready, trip point, and reset status bits. The ready bit

determines if the power-on reset level of the DS4510 is surpassed by VCC. The trip point bit determines if V

is above V

CCTP

, and the reset status bit is set if RST is

in its active state. Note: The RST pin is an open-drain output, therefore an

external pullup resistor must be used to realize high logic levels.

Programmable NV Digital I/O Pins

Each programmable I/OXpin contains an input, opencollector output, and a selectable internal pullup resistor. The DS4510 stores changes to the I/OXpin in SEEPROM memory. Using the SEEPROM as SRAM is conducive to applications such as I/O expansion that generally require fast access times and frequent modification of the I/OXpin. Configuring the SEEPROM to behave as EEPROM allows the modification of the power-on state of the I/OXpin. During power-up the I/OXpins are high impedance until VCCexceeds 2.0V (typically), which is when the last value programmed is recalled from EEPROM. On power-down, the I/OXstate is maintained until VCCdrops below 1.9V (typically).

The internal pullups for each I/OXpin are controlled by the pullup-enable register (F0h). Similarly, the individual I/OXcontrol registers (F4h to F7h) adjust the pulldown

INTERNAL

VOLTAGE

REFERENCE

2-WIRE

INTERFACE

EEPROM

64 BYTES

USER

MEMORY

PROGRAMMABLE

RESET TIMER

SCL

SDA

GND

4 NV I/O PINS

4 BIDIRECTIONAL

NONVOLATILE I/O LATCHES

PULLUP ENABLE (F0h)

I/O

CONTROL (F4h-F7h)

I/O STATUS (F8h)

RST

DS4510

Functional Diagram

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

_____________________________________________________________________ 7

transistors. Read the I/O status register (F8h) to determine the logic levels present at the I/O pins.

User Memory

Three types of memory are present in the DS4510 (EEPROM, SEEPROM, and SRAM). The main user memory is 64 bytes of EEPROM starting at address 00h. This memory is not SRAM shadowed, so all writes to these locations result in EEPROM write cycles regardless of the state of the SEE bit. Additional memory for storing application data includes 6 bytes of SRAM (FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer to the register memory map (Figure 3) for register addresses and memory types. Figure 4 shows the bit names for the memory-mapped I/O bytes and their factory default values.

The higher-order bits of the I/O registers that are not used, such as the four most significant bits of the pullup-enable byte (address F0h), can be used as additional memory. It is the responsibility of the application to ensure that writes to these bytes do not adversely affect bits controlling special functions of the DS4510.

I/O STATUS

SRAMF8

Figure 2. How to Read the Memory Map

RPU

RPD

CCTP (MAX)

CCTP (MIN)

CCTP

Figure 1. CPU Supervisor Power-Up and Power-Down Timing

00 01 02 03 04 05 06 07

0D0C0B0A0908 0E 0F

10 11 12 13 14 15 16 17

1D1C1B1A1918 1E 1F

20 21 22 23 24 25 26 27

2D2C2B2A2928 2E 2F

30 31 32 33 34 35 36 37

3D3C3B3A3938 3E 3F

40 41 42 43 44 45 46 47

E8 E9 EA EB EC ED EE EF

PULLUP ENABLE

SEEF0

RESET DELAY

SEE

USER BYTE

SEEF2

USER BYTE

SEEF3

I/O

CONTROL

SEEF4

I/O2 CONTROL

SEEF5

I/O1 CONTROL

SEEF6

I/O0 CONTROL

SEEF7

I/O STATUS

F9SRAMF8 CONFIG USER BYTE

USER BYTE

FB FC

USER BYTE

FFSRAM SRAM SRAM SRAM SRAM SRAM SRAM

USER BYTE

RESERVED

USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE

USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE

USER BYTE

USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE

USER BYTE USER BYTE User byte USER BYTE USER BYTE USER BYTE USER BYTE USER BYTE

*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.

Figure 3. Register Memory Map

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

8 _____________________________________________________________________

I2C Definitions

The following terminology is commonly used to describe I2C data transfers.

Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start, and stop conditions.

Slave Devices: Slave devices send and receive data at the master’s request.

Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices.

Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing.

Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high generates a stop condition. See the I2C Timing Diagram for applicable timing.

Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the I2C Timing Diagram for applicable timing.

Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL (see

Figure 5) plus the setup and hold-time requirements.

Data is shifted into the device during the rising edge of the SCL.

Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup

NAME

LOCATION

(HEX)

Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FACTORY OR

POWER-ON

DEFAULT

(BIN)

User

EEPROM

00-3F EE EE EE EE EE EE EE EE 00000000

Reserved

40-EF n/a n/a n/a n/a n/a n/a n/a n/a n/a

Pullup

Enable

F0 SEE SEE SEE SEE

I/O3

I/O2

I/O1

I/O0

00000000

RST Delay

F1 SEE SEE SEE SEE SEE SEE TD1 TD0 00000011

User SEE

F2 SEE SEE SEE SEE SEE SEE SEE SEE 00000000

User SEE

F3 SEE SEE SEE SEE SEE SEE SEE SEE 00000000

I/O3

Control

F4 SEE SEE SEE SEE SEE SEE SEE I/O3 00000001

I/O2

Control

F5 SEE SEE SEE SEE SEE SEE SEE I/O2 00000001

I/O1

Control

F6 SEE SEE SEE SEE SEE SEE SEE I/O1 00000001

I/O0

Control

F7 SEE SEE SEE SEE SEE SEE SEE I/O0 00000001

I/O Status

F8 0 0 00

I/O3

I/O2

I/O1

I/O0

n/a

Config F9

reset

SEE

000XXX00000

User SRAM

FA-FF

00000000

Figure 4. Register Bit Names

pullup

Status

ready trip point

SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM

status

SWRST

Status

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

_____________________________________________________________________ 9

time (see Figure 5) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave.

Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 5) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data.

Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the

slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition.

Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master.

Slave Address and the R/W Bit: Each slave on the I2C

bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte contains the slave address and the R/W bit. The slave address (see Figure 6) is the most significant 7 bits and

the R/W bit is the least significant bit.

The DS4510’s slave address is 101000A0 (binary), where A

is the value of the A0address pin. The

LOCATION (HEX)

NAME

FUNCTION

00 to 3F User EEPROM 64 bytes of EEPROM memory.

40 to EF Reserved These memory locations are reserved for future products.

F0 Pullup Enable

The four least significant bits of this register each enable/disable one of the internal pullup resistors. Set the bit to enable the pullup, clear it to disable the pullup.

F1 RST Delay

The two LSBs of this register (TD1 and TD0) select the reset delay (t

RST

) as shown in the

CPU Supervisor AC Timing Characteristics.

F2 to F3

SRAM Shadowed EEPROM user byte.

F4 to F7 I/OX Control

Clearing the LSB of the register enables the I/O

pulldown transistor; setting the bit disables

the pulldown transistor.

F8 I/O Status

This register reflects the logic level of the I/O

pins. The upper four bits of this register

always read zero.

F9 Config This register contains 5 bits that read and control the behavior of the part as follows:

Bit Name Bit Function

ready Reads zero when VCC is above the DS4510's power-on reset voltage.

Trip Point Reads one when VCC below V

CCTP

Reset Status Reads one when the RST pin is active.

SEE

When zero, writes to the SEEPROM registers behave like EEPROM. When one, writes to the SEEPROM registers behave like SRAM.

SWRST

Setting this bit activates the RST output. This bit automatically returns to zero during the RST active time.

FA to FF User SRAM 6 bytes of SRAM memory

Table 1. Register Definitions

User SEEPROM

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

10 ____________________________________________________________________

address pin allows for the DS4510 to respond to one of two slave addresses (1010000X, or 1010001X). If the R/W bit is zero, the master writes data to the slave. If the R/W is one, the master reads data from the slave.

Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte (R/W = 0).

I2C Communications

Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address (R/W= 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations.

Writing a Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a start condition, writes the slave address (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition.

The DS4510 can write 1 to 8 bytes (one page or row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory table, see Figure 3). Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row.

Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three “consecutive” addresses. The result would be addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h.

To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. The master may then generate a new start con-

HD:STA

SU:STA

SU:DAT

HD:DAT

HIGH

HD:STA

STARTSTOP

NOTE: TIMING IS REFERENCE TO V

IL(MAX)

AND V

IH(MIN)

LOW

BUF

SDA

SCL

REPEATED

START

SU:STO

Figure 5. I2C Timing Diagram

7-BIT SLAVE ADDRESS

MOST

SIGNIFICANT BIT

101 000

R/W

A0 PIN VALUE

DETERMINES

READ OR WRITE

Figure 6. DS4510’s Slave Address and the R/WBit

DS4510

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

____________________________________________________________________ 11

dition, write the slave address (R/W = 0), and the first memory address of the next page before continuing to write data.

Acknowledge Polling: Any time an EEPROM page is written, the DS4510 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the DS4510 does not acknowledge its slave address because it is busy. It is possible to take advantage of that phenomenon by repeated addressing the DS4510, which allows the next page to be written as soon as the DS4510 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tWto elapse before attempting to write again to the DS4510.

EEPROM Write Cycles: When EEPROM writes occur, the DS4510 writes the whole EEPROM memory page even if only a single byte on the page was modified. Writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. Because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Writing a page one byte at a time wears the EEPROM out eight times faster than writing the entire page at once. The DS4510’s EEPROM memory is guaranteed to handle 50,000 write cycles at +70°C. Writing to SEEPROM memory with SEE = 1 does not count as an EEPROM write cycle when evaluating the EEPROM’s estimated lifetime.

Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave the master generates a start condition, writes the slave address with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition.

Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition.

See Figure 7 for a read example using the repeated start condition dummy write cycle.

Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter’s location before the read cycle. The DS4510 does not wrap on page boundaries during read operations, but the counter rolls from its upper-most memory address FFh to 00h if the last memory location is read during the read transaction.

Example: The entire memory contents of the DS4510 can be read with a single transfer starting at address F0h that reads 80 bytes of data. Addresses F0h to FFh are read sequentially, the address counter rolls to 00h, and then addresses 00h to 3Fh can be read sequentially. This allows the entire memory contents to be read in a single operation without reading the undefined contents of the reserved area of the memory.

Application Information

Advantages of Using the

SEE

Bit to Disable

EEPROM Writes

The SEE bit allows EEPROM writes to be disabled for the SRAM-shadowed EEPROM bytes, allowing the SRAM of SEE registers to change without writing the EEPROM to the same value. This prevents write operations from changing the power-on value of the I/O pins, reduces the number of EEPROM write cycles, and speeds up I/O operations because the DS4510 does not require an internally timed EEPROM write cycle to complete the operation.

Power-Supply Decoupling

To achieve the best results when using the DS4510, decouple the power supply with a 0.01µF or a 0.1µF capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCCand GND pins of the DS4510 to minimize lead inductance.

SDA and SCL Pullup Resistors

SDA is an open-collector output on the DS4510 that requires a pullup resistor to realize high logic levels. Because the DS4510 does not utilize clock cycle stretching, a master using either an open-collector output with a pullup resistor or a normal output driver can be utilized for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics are within specification.

DS4510

CPU Supervisor with Nonvolatile Memory and Programmable I/O

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

is a registered trademark of Dallas Semiconductor Corporation.

Chip Topology

TRANSISTOR COUNT: 16559

SUBSTRATE CONNECTED TO GROUND

Package Information

For the latest package outline information, go to

www.maxim-ic.com/DallasPackInfo.

START

8-BITS ADDRESS OR DATA

REPEATED START

STOP

ACK

NOT ACK

WHITE BOXES INDICATED THE MASTER IS CONTROLLING SDA

SHADED BOXES INDICATED THE SLAVE IS CONTROLLING SDA

WRITE A SINGLE BYTE

WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION

READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER

READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER

COMMUNICATIONS KEY

XX XX XX XX

101000A00

MEMORY ADDRESS

DATA

A P

101000A00

MEMORY ADDRESS

DATA

A P

101000A00

MEMORY ADDRESS

A Sr

10 1 0 0 0A01

DATA

N P

101000A00

MEMORY ADDRESS

A Sr

10 1 0 0 0A01

DATA

N P

NOTES:

1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.

2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.

Figure 7. I2C Communications Examples

MAXIM DS4510 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual