MAXIM DS4420 User Manual

Page 1

General Description

The DS4420 is a fully differential, programmable-gain amplifier for audio applications. It features a -35dB to +25dB gain range controlled by an I

C interface and it is optimized to drive loads as low as 50Ω. The gain is adjustable in 3dB increments across the entire range. Three address inputs, used to select the I

C slave

address, enable up to eight devices on a common bus.

The product operates from a single 5V supply over a

-20°C to +70°C temperature range. It is offered in a 3mm x 3mm TDFN package.

Applications

Telephone Headsets

Audio Volume Control

Microphone Gain Control

Features

 Differential Inputs and Outputs

 -35dB to +25dB Adjustable Gain

 Low Output Noise

 Low-Distortion Driving into a 50Ω Load

 3dB Gain Steps Programmed through I

C Interface

 5V Single Supply

 20kHz Bandwidth for All Gain Settings

 Small 3mm x 3mm x 0.8mm TDFN Package

 Up to Eight DS4420s can be Placed on the Same

C Bus

DS4420

I2C Programmable-Gain Amplifier

for Audio Applications

______________________________________________

Maxim Integrated Products

Rev 0; 9/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

Denotes lead-free package.

EP = Exposed paddle.

DS4420

-35dB TO +25dB GAIN

A2 A1 A0

SDA SCL

IN+

OUT+

OUT-

IN-

GND

AGND

AUDIO

AMPLIFIER

AUDIO

SOURCE

MICROPR0CESSOR-

CONTROLLED GAIN

C INTERFACE

Typical Operating Circuit

TDFN

(3mm x 3mm x 0.8mm)

TOP VIEW

OUT+

AGND

N.C.

SCL

SDA

OUT-

IN-V

IN+GND

DS4420

Pin Configuration

PART TEMP RANGE PIN-PACKAGE

DS4420+ -20°C to +70°C 14 TDFN-EP*

Page 2

DS4420

I2C Programmable-Gain Amplifier for Audio Applications

2 _____________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

(TA= -20°C to +70°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage on VCC, SDA, and SCL

Relative to GND.................................................-0.5V to +6.0V

Voltage on A0, A1, and A2

Relative to GND......................................-0.5V to (V

+ 0.5V;

not to exceed 6.0V)

Voltage on IN+, IN-, OUT-, and OUT+

Relative to AGND .................................-0.5V to (AV

+ 0.5V;

not to exceed 6.0V)

Voltage on AV

Relative to VCC..........................-0.3V to +0.3V

Voltage on AGND Relative to GND .......................-0.3V to +0.3V

Output Current ..................................................................150mA

Operating Temperature Range ...........................-20°C to +70°C

Storage Temperature .....................See J-STD-020 Specification

ELECTRICAL CHARACTERISTICS

= +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.)

Digital Supply Voltage V

Analog Supply Voltage AV

Analog Ground AGND (See Figure 5) GND V

Input Logic 1 (SCL, SDA, A0, A1, A2) V

Input Logic 0 (SCL, SDA, A0, A1, A2) V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

(Note 1) +4.5 +5.5 V

2.0

-0.3 +0.8 V

+ 0.3

Supply Current I

Standby Current I

Input Leakage (SDA, SCL, A2, A1, A0) I

Output Leakage (SDA) I

Output-Current Low (SDA) I

Input Voltage Range V

Max Peak-to-Peak Input Level V

Input Resistance R

Input Common-Mode Voltage V

Output Voltage V

Output Peak-to-Peak Signal Swing V

Output Common-Mode Voltage V

Output Offset Voltage V

Amplifier Output Current (Sourcing)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STBY

INP-P

IN:CM

OP-P

O:CM

O:OSAV

OS1

VCC = 5.5V, RL = ∞, VIN = 0V differential (Note 9)

VCC = 5.5V (Notes 2, 9) 140 µA

VCC = 5.5V 1 µA

VOL = 0.4V 3

VOL = 0.6V 6

Differential -19 +1 dBV

Differential 3.2 V

Differential, active mode (Note 3) 29 49 60 kΩ

0.45 x V

RL = 50Ω differential 6 dBV

Differential 5.6 V

0.45 x V

= +25dB -20 +20 mV

= GND 95

OUT

= VCC - 0.75V 64

OUT

1.7 3 mA

1µA

0.55 x V

0.5 x V

0.55 x V

Page 3

DS4420

I2C Programmable-Gain Amplifier

for Audio Applications

_____________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

= +4.5V to +5.5V, TA = -20°C to +70°C, unless otherwise noted.)

I2C AC ELECTRICAL CHARACTERISTICS (See Figure 3)

(VCC= +4.5V to +5.5V, TA= -20°C to +70°C, timing referenced to V

IL(MAX)

and V

IH(MIN)

, unless otherwise noted.)

Amplifier Output Current (Sinking)

Resistive Load Range R

Capacitive Load C

Closed-Loop Bandwidth All gain settings (Note 5) 20 20k Hz

Passband Flatness 20Hz to 20kHz (Notes 2, 5) -1 +1 dB

Output Noise (Note 5) N

Total Harmonic Distortion (Note 5) THD

Gain Range A -35 +25 dB

Gain Step Size A

Gain Accuracy A

Mute and Standby Mode Gain A

S tand b y M od e E xi t Ti m et

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OS2

ERR1

MUTE

= V

OUT

Differential 50 50k Ω

Cap to GND (Note 4) 100 pF

A = -35dB, 300Hz to 3.4kHz -123

A = +25dB, 300Hz to 3.4kHz -88

RL = 50Ω, VO ≤ +6dBV, f = 1kHz, A = ±16dB

f = 1kHz, A = ±16dB

(Note 10) -2.5 +2.5 dB

(Note 5) -90 dB

(Note 6) 10 µs

= 0.75V 64

= 1kΩ, V

≤ +6dBV,

0.03 1.0

0.01

2.0 3.0 4.0 dB

dBV

SCL Clock Frequency f

Bus Free Time Between STOP and START Conditions

Hold Time (Repeated) START Condition

Low Period of SCL t

High Period of SCL t

Data Hold Time t

Data Setup Time t

Start Setup Time t

SDA and SCL Rise Time t

SDA and SCL Fall Time t

STOP Setup Time t

SDA and SCL Capacitive Loading C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL

BUF

HD:STA

LOW

HIGH

HD:DAT

SU:DAT

SU:STA

SU:STO

(Note 7) 0 400 kHz

(Note 8)

(Note 8) 400 pF

1.3 µs

0.6 µs

1.3 µs

0.6 µs

0 0.9 µs

100 ns

0.6 µs

20 +

0.1C

20 +

0.1C

0.6 µs

300 ns

Page 4

DS4420

I2C Programmable-Gain Amplifier for Audio Applications

4 _____________________________________________________________________

Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Note 2: Standby supply current specified with SDA = SCL = V

, the output disconnected, and A0, A1, and A2 driven to within

100mV of V

or GND.

Note 3: Input resistance during mute and power-down is approximately one-half of the active-mode resistance. Note 4: Each output is capable of driving a 100nF capacitive load to ground using an external 10Ω series resistor. However, output

capacitance should be minimal for optimal distortion performance.

Note 5: Guaranteed by design. Note 6: This is the time it takes for the output to become active after exiting standby mode. Note 7: I

C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-

mode timing.

Note 8: C

= total capacitance of one bus line in picofarads.

Note 9: The current specified is the sum of V

and AVCCsupply currents.

Note 10: Gain accuracy specified assuming the output impedance of signal source driving of the DS4420 is ≤ 2.5kΩ.

Typical Operating Characteristics

(TA= +25°C, V

= AVCC= 5.0V, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

(STANDBY MODE ENABLED)

DS4420 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (μA)

4.50 4.75 5.00 5.25 5.50

VCC = AVCC = SDA = SCL NO LOAD IN+ AND IN- SHORTED TOGETHER

+25°C

+70°C

-20°C

1.8

1.7

1.6

1.5

1.4

4.50 5.004.75 5.25 5.50

SUPPLY CURRENT vs. SUPPLY VOLTAGE

(SETTING AT -11dB)

DS4420 toc02

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

VCC = AVCC = SDA = SCL NO LOAD IN+ AND IN- SHORTED TOGETHER

+25°C

-20°C

+70°C

0.6

0.4

0.2

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 5 10 15 20

SUPPLY CURRENT vs. GAIN SETTING

DS4420 toc03

GAIN SETTING

SUPPLY CURRENT (mA)

IN+ AND IN- SHORTED TOGETHER NO LOAD

Page 5

DS4420

I2C Programmable-Gain Amplifier

for Audio Applications

_____________________________________________________________________

Typical Operating Characteristics (continued)

(TA= +25°C, V

= AVCC= 5.0V, unless otherwise noted.)

POWER-SUPPLY REJECTION RATIO

120

100

PSRR (dB)

01051520

IN+ AND IN- SHORTED TOGETHER ACROSS -20°C TO +70°C

WITH 50Ω LOAD, 1kΩ LOAD, AND NO LOAD

-10

GAIN (dB)

-20

-30

-40 0 5 10 15 20

vs. GAIN SETTING

1kHz

50Ω LOAD

20kHz

50Ω LOAD

GAIN SETTING

GAIN vs. SETTING

GAIN SETTING

DS4420 toc04

DS4420 toc07

CMRR (dB)

CCITT NOISE (dBV)

-100

-120

-140

COMMON-MODE FREQUENCY RESPONSE

SWEEP AT -11dB

NO LOAD

-10

-20

-30

-40

-50

-60

-70

-80 1000 10,000 100,000

FREQUENCY (Hz)

CCITT NOISE vs. GAIN SETTING

NO LOAD

-20

-40

-60

-80

0 5 10 15 20

GAIN SETTING

DS4420 toc05

DS4420 toc08

GAIN vs. FREQUENCY RESPONSE

-10

GAIN (dB)

-20

-30

-40 1000 100,000 1,000,000

+25dB SETTING

-2dB SETTING

-35dB SETTING

10,000

FREQUENCY (Hz)

TOTAL HARMONIC DISTORTION

vs. FREQUENCY

0.018 WITH 50Ω LOAD

AND 1kΩ LOAD

0.016

0.014

0.012

0.010

0.008

THD+N (%)

0.006

0.004

0.002

0.000

INPUT

RMS

-11dB SETTING

10 1000100 10,000 100,000

FREQUENCY (Hz)

50Ω LOAD

DS4420 toc06

DS4420 toc09

TOTAL HARMONIC DISTORTION

vs. FREQUENCY

0.09 WITH 50Ω LOAD

AND 1kΩ LOAD

0.08

0.07

0.06

0.05

0.04

THD+N (%)

0.03

0.02

0.01

0.00

INPUT

RMS

+10dB SETTING

10 1000100 10,000 100,000

FREQUENCY (Hz)

DS4420 toc10

TOTAL HARMONIC DISTORTION vs. V

50Ω LOAD

1kHz 2V

RMS

INPUT

-5

-10

(dB)

-15

OUT

-20

-25

-30

-35

-40 2 4 6 8 10 12 14 16 18 20

THD+N

GAIN SETTING

VOUT

DS4420 toc11

OUT

0.020

0.018

0.016

0.014

0.012

0.010

0.008

0.006

0.004

0.002

0.000

THD+N (%)

Page 6

DS4420

I2C Programmable-Gain Amplifier for Audio Applications

6 _____________________________________________________________________

Detailed Description

The key features of the DS4420 are illustrated in the

Block Diagram

Controlling the DS4420

The DS4420 is controlled through the I2C serial interface. Gain, mute, and standby settings all reside in one control register located at memory address F8h (see Figure 1). Writes to other memory addresses are invalid.

Programmable Gain

The gain is adjustable from -35dB to +25dB in 3dB increments. The gain is determined by the five LSBs of the control register as shown in Figure 1. Gain settings greater than 14h are invalid.

Mute Mode

The DS4420 is placed in mute mode by setting the mute bit located in the control register (see Figure 1). When in this mode, the output of the amplifier is muted and is independent of the gain setting. The input-to-output attenuation is specified in the

Electrical Characteristics

table as A

MUTE

Standby Mode

Standby mode is entered by setting the standby control bit (see Figure 1). Setting the standby control bit mutes the output of the amplifier and places the DS4420 into a

low-current (I

STBY

) consumption state. Unlike mute mode, however, standby mode is intended for use when no input signal is present. While in standby mode, the DS4420 maintains input and output common-mode bias voltages. The device produces no audible clicks or pops when entering or exiting the standby state. The time required for the output to become active when exiting standby mode is specified as tPU.

Pin Description

PIN NAME FUNCTION

1A2

2A1

3A0

Address Select Inputs—Determine I

C Slave Address. Device address is 1010A2A1A0.

4 SCL I2C Serial Clock—Input for I2C Clock

5 SDA I2C Serial Data—Input/Output for I2C Data

6VCCDigital Power-Supply Terminal

7 GND Ground

8 IN+

9 IN-

Differential Audio Input Signal

10 N.C. No Connection

11 AGND Analog Ground (Must be Connected to GND)

12 OUT-

13 OUT+

Differential Audio Output Signal

14 AV

Analog Power Supply (Must be Connected to VCC)

EP EP Exposed Paddle. Connect to GND and AGND.

Block Diagram

DS4420

3dB GAIN STEPS

AGNDGND

A2A1A0

SDA

SCL

IN+

IN-

OUT+

OUT-

I2C INTERFACE

-35dB TO +25dB GAIN

Page 7

DS4420

I2C Programmable-Gain Amplifier

for Audio Applications

_____________________________________________________________________ 7

Slave Address Byte and Address Pins

The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 2). The DS4420’s slave address is determined by the state of the A0, A1, and A2 address pins. These pins allow up to eight DS4420s to reside on the same I2C bus. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCCresult in a ‘1’ in the corresponding bit positions. For example, the DS4420’s slave address byte is A0h when A0, A1, and A2 pins are grounded. I

C communication is described in detail in

the

I2C Serial Interface Description

section.

Figure 1. Control Register Description

Figure 2. DS4420 Slave Address Byte

Control Register (F8h)

Power-Up Default: 1000 0000 b

F8h Standby x Mute Gain Setting[4:0]

bit 7 bit 4 bit 3 bit 2 bit 1 bit 0

Standby: Places the DS4420 in standby mode.

bit 7

bit 6 Don’t care.

bit 5

bit 4:0 Gain Setting: Five-bit gain setting. The power-up default is setting 00h.

0 = Normal operation. 1 = Places the DS4420 in standby mode. (Power-up default.)

Mute: Mutes the amplifier output, regardless of the current gain setting. 0 = Normal operation. (Power-up default.) 1 = Mutes the amplifier output.

GAIN

SETTING

(hex)

00h -35 0Bh -2

01h -32 0Ch +1

02h -29 0Dh +4

03h -26 0Eh +7

04h -23 0Fh +10

05h -20 10h +13

06h -17 11h +16

07h -14 12h +19

08h -11 13h +22

09h -8 14h +25

0Ah -5 15h to 1Fh Illegal

GAIN

(dB)

GAIN

SETTING

(hex)

GAIN

(dB)

MSB

010A2A1 A0

SLAVE

ADDRESS*

*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.

LSB

R/W

READ/WRITE

BIT

Page 8

DS4420

I2C Programmable-Gain Amplifier for Audio Applications

8 _____________________________________________________________________

I2C Serial Interface Description

I2C Definitions

The following terminology is commonly used to describe I2C data transfers. See the timing diagram (Figure 3) and the

I2C AC Electrical Characteristics

table for additional information.

Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions.

Slave Devices: Slave devices send and receive data at the master’s request.

Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states.

Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition.

Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition.

Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition.

Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL.

Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave.

Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one (done by releasing SDA) during the 9th bit. Timing (Figure 3) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data.

Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition.

Figure 3. I2C Timing Diagram

SDA

BUF

SCL

STOP START

LOW

HD:STA

HD:DAT

HIGH

SU:DAT

REPEATED

START

SU:STA

HD:STA

SU:STO

NOTE: TIMING IS REFERENCE TO V

IL(MAX)

AND V

IH(MIN)

Page 9

DS4420

I2C Programmable-Gain Amplifier

for Audio Applications

_____________________________________________________________________ 9

Byte Read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master.

Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit.

The DS4420’s slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure

2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to V

result in a

‘1’ in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indi-

cating it will write data to the slave. If R/W is set to a 1, (A1h in this case), the master is indicating it wants to read from the slave.

If an incorrect (nonmatching) slave address is written, the DS4420 will assume the master is communicating with another I

C device and ignore the communication

until the next start condition is sent.

Memory Address: During an I2C write operation to the DS4420, the master must transmit a memory address to identify the memory location where the slave is to store

the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.

I2C Communication

Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. The master must read the slave’s acknowledgement during all byte write operations.

Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. A dummy write cycle can be used to force the address pointer to a desired location. To do this, the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition.

See Figure 4 for I2C communication examples.

Applications Information

Power-Supply Decoupling

The DS4420 has separate supply voltages for its analog and digital circuitry. For best noise and distortion performance, place a 0.1µF or 0.01µF capacitor from VCCto GND and from AVCCto AGND. These capacitors should be placed as close as possible to the supply and ground pins of the device.

Figure 4. I2C Communication Examples

COMMUNICATIONS KEY

START ACK

STOP

REPEATED

START

WRITE THE GAIN SETTING F8h

101 0 A

READ THE GAIN SETTING F8h

101 0 A00A1A

NOT ACK

XXXXXXXX

00A1A2

WHITE BOXES INDICATE THE MASTER IS CONTROLLING SDA

SHADED BOXES INDICATE THE SLAVE IS CONTROLLING SDA

8-BITS ADDRESS OR DATA

111 1 0 001

ASr

NOTE 1: ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.

NOTE 2: THE FIRST BYTE SENT AFTER A START CONDITION IS

ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT.

101 0 A

Page 10

Exposed Paddle

The DS4420 exposed paddle is not electrically isolated. It must be soldered to ground for proper operation.

Input-Coupling Capacitors

The DS4420 is designed to be operated with an ACcoupled input signal. The input resistance, RIN, is sufficiently large to allow the use of small and inexpensive external capacitors. The input resistance combined with the AC-coupling capacitor will create a highpass filter. The -3dB cutoff frequency of the highpass, fC, is given by:

where C

is the external coupling capacitor and RINis

the internal input resistance.

At the cutoff frequency, the input signal will be attenuated 3dB, with less attenuation as the signal’s frequency increases beyond the cutoff frequency. To guarantee passband flatness, the cutoff frequency of the filter should be designed using the specified minimum input resistance, and placed well below the desired flat band of the circuit. The typical input resistance should only be used to estimate typical performance.

Internal Ground Connections

The DS4420’s ground pins, GND and AGND, must be connected together externally. Internally, they are connected as shown in Figure 5.

Chip Topology

TRANSISTOR COUNT: 5347

SUBSTRATE CONNECTED TO: Ground

Package Information

For the latest package outline information, go to www.maxim-

ic.com/DallasPackInfo.

Figure 5. Internal Ground Connections

Springer

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

is a registered trademark of Dallas Semiconductor Corporation.

I2C Programmable-Gain Amplifier for Audio Applications

DS4420

2=××π

IN IN

13Ω

TYPICAL

GND AGND