___________________________________ 概述
DS4302 是一款5位数模转换器 (DAC),提供三路可编程数
字输出。DS4302通过2线、SMBusTM兼容的串行接口进行
通信。微型8引脚µSOP封装,使其适合空间受限的应用。
___________________________________ 应用
CCFL背光亮度控制
电源校准
___________________________________ 特性
♦ SO封装可直接替换MPS1251和MPS1252
♦ 单路5位DAC (32级)
♦ 0V至2V和0V 至1.9V两种版本
♦ 三路可编程数字输出
♦ SMBus兼容的串行接口
♦ 电源电压范围:4.5V至5.5V
♦ 8引脚SO封装及8引脚µSOP封装
♦ 工业级温度范围: -40°C至+85°C
DS4302
2线、5位DAC,提供三路数字输出
______________________________________________ Maxim Integrated Products 1
_______________________________ 引脚配置
_______________________________ 定购信息
Rev 1; 6/04
若需卷带包装请加注“/T&R”。
*
供货信息请与厂商联系。
SMBus是 Intel Corp.的商标。
_______________________________ 引脚说明
本文是Maxim 正式英文资料的译文,Maxim不对翻译中存在的差异或由此产生的错误负责。请注意译文中可能存在文字组织或
翻译错误,如需确认任何词语的准确性,请参考 Maxim提供的英文版资料。
索取免费样品和最新版的数据资料,请访问Maxim的主页:www.maxim-ic.com.cn。
引脚
名称 功能
串行时钟输入。2线时钟输入。
串行数据输入/输出。双向、2线数据
引脚。
DAC输出电压
地
可编程数字输出
电源输入
V
PART
DS4302Z-020 0V to 2.0V 4302B 8 SO
DS4302Z-019* 0V to 1.9V 4302A 8 SO
DS4302U-020 0V to 2.0V 4302B 8 µSOP
DS4302U-019* 0V to 1.9V 4302A 8 µSOP
OUT
RANGE
TOP
BRAND
PINPACKAGE
PIN NAME FUNCTION
1 SCL Serial Clock Input. 2-wire clock input.
2 SDA
3V
4 GND Ground
5P2
6P1
7P0
8VCCPower-Supply Input
Serial Data Input/Output. Bidirectional,
2-wire data pin.
DAC Output Voltage
OUT
Programmable Digital Output
TOP VIEW
V
SCL
OUT
1
2
3
4
DS4302
SO/µSOP
87V
6
5
CC
P0SDA
P1
P2GND
DS4302
2线、5位DAC,提供三路数字输出
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(TA= -40°C to +85°C)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC, SDA, and SCL Pins
Relative to Ground.............................................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature ....See IPC/JEDEC J-STD-020A Specification
DC ELECTRICAL CHARACTERISTICS
(VCC= +4.5V to 5.5V, TA= -40°C to +85°C.)
X = Don’t care.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
Input Logic 1 (SDA, SCL) V
Input Logic 0 (SDA, SCL) V
CC
(Note 1) 4.5 5.5 V
IH
IL
2.0 V
GND - 0.3 0.8 V
+ 0.3 V
CC
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Standby Current I
Input Leakage I
SDA Low-Level Output Voltage V
P0, P1, P2 Low-Level Output
Voltage
P0, P1, P2 High-Level Output
Voltage
V
Maximum Level (-020) VCC = 5.0V, Data = 00000XXX (Note 3) 1.925 2.0 2.075 V
OUT
V
Minimum Level (-020) VCC = 5.0V, Data = 11111XXX 0.0 0.05 0.1 V
OUT
V
Maximum Level (-019) VCC = 5.0V, Data = 00000XXX (Note 3) 1.825 1.9 1.975 V
OUT
V
Minimum Level (-019) VCC = 5.0V, Data = 11111XXX 0.0 0.05 0.1 V
OUT
Power-On Reset 1.7 V
Settling Time 10 µs
D/A Output Levels 32 steps
STBY
OL1
V
OL2
V
OH
(Notes 2, 3) 200 300 µA
(Note 4) -1.0 +1.0 µA
L
3mA sink current 0.0 0.4
6mA sink current 0.0 0.6
(Note 1)
4mA sink
(Note 1)
4mA source
- 0.4V V
V
CC
+0.4V V
V
DS4302
2线、5位DAC,提供三路数字输出
_____________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS (Figure 3)
(VCC= +4.5V to 5.5V, TA= -40°C to +85°C, timing referenced to V
IL(MAX)
and V
IH(MIN)
.)
Note 1: All voltages referenced to ground.
Note 2: I
STBY
specified for the inactive state measured with SDA = SCL = VCCand with V
OUT
, P0, P1, and P2 floating.
Note 3: No load on V
OUT
.
Note 4: The DS4302 will not obstruct the SDA and SCL lines if V
CC
is switched off as long as the voltages applied to these inputs
does not violate their min and max input-voltage levels.
Note 5: C
B
—total capacitance of one bus line in picofarads.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
Bus Free Time Between STOP
and START Conditions
Low Period of SCL t
High Period of SCL t
Data Hold Time t
Data Setup Time t
Start Setup Time t
SDA and SCL Rise Time t
SDA and SCL Fall Time t
Stop Setup Time t
SDA and SCL Capacitive
Loading
SCL
t
BUF
LOW
HIGH
HD:DAT
SU:DAT
SU:STA
R
F
SU:STO
C
B
(Note 5) 20 + 0.1C
(Note 5) 20 + 0.1C
(Note 5) 400 pF
0 400 kHz
1.3 µs
1.3 µs
0.6 µs
00.9µs
100 ns
0.6 µs
0.6 µs
B
B
300 ns
300 ns