MAXIM DS33Z44DK User Manual

www.maxim-ic.com.cn

概述

DS33Z44 开发板是使用方便的评估板，用于评估以太
网在串行链路上的传输器件 DS33Z44。DS33Z44DK
的串行链路由子卡提供。串行子卡包括接口、变压器
以及网络接口。Dallas 的 ChipView 软件随开发板一起
提供，可在基于 Windows®的 PC 上访问配置寄存器
和状态寄存器。板载 LED 用于指示接收信号丢失、队
列溢出、以太网链路、Tx/Rx 和中断状态。

Windows是Microsoft Corp.

的注册商标。

定购信息

PART DESCRIPTION

DS33Z44DK

DS33Z44 demo card, T3/E3, T1/E1
transceiver resource card included

DS33Z44DK

以太网传输开发套件

特性

 演示 DS33Z44 以太网传输芯片组的主要功能
 包括两块子卡：一块 DS21458 T1/E1 SCT 和一块

DS3174 T3/E3 SCT，提供变压器、BNC 和 RJ48
网络连接器以及终端匹配

 提供硬件和软件模式支持
 板载 MMC2107 处理器和 ChipView 软件允许访

问 DS33Z44 的寄存器组

 所有 DS33Z44 接口引脚便于与外部数据源/接收

器连接

 LED 指示信号丢失、队列溢出、以太网链路、

Tx/Rx 以及中断状态

 丝网印制标记清晰标识与所有连接器、跳线和

LED 相关的信号

开发套件内容

• DS33Z44DK 主板

• 具有 DS21458 T1/E1 SCT 的 4 端口串口卡

• 具有 DS3174 T3/E3 SCT 的 4 端口串口卡

• CD_ROM

o ChipView 软件和手册
o DS33Z44DK 数据资料
o 配置文件

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DS33Z44DK

目录表

概述..............................................................................................................................................1

定购信息.......................................................................................................................................1

开发套件内容 ...............................................................................................................................1

元件清单.......................................................................................................................................3

PCB勘误表.................................................................................................................................10

文件位置.....................................................................................................................................10

基本操作.....................................................................................................................................11

开发板供电 ............................................................................................................................................ 11

概要

..................................................................................................................................................................... 11

基本的DS33Z44 初始化(用于所有的快速设置)...................................................................................... 11

快速配置
快速配置
快速配置

#1 (Device Driver + CPLD

#2 (DS3174 T3E3)...............................................................................................................................12

#3 (DS21458 T1E1)............................................................................................................................. 12

环回

)........................................................................................................... 11

配置开关和跳线..........................................................................................................................13

地址映射(所有板卡)....................................................................................................................15

DS33Z44 信息............................................................................................................................15

DS33Z44DK信息 .......................................................................................................................15

技术支持.....................................................................................................................................15

文档版本历史 .............................................................................................................................15

原理图 ........................................................................................................................................16

图片列表

图 1. 系统平面图 .......................................................................................................................................................... 8

图 2. DS3174 子卡平面图............................................................................................................................................. 8

图 3. DS21458 子卡平面图........................................................................................................................................... 9

表格清单

表 1. 元件清单(未显示去耦电容) .................................................................................................................................. 3

表 2. 主板PCB配置..................................................................................................................................................... 13

表 3. DS3174 串行子卡跳线设置................................................................................................................................14

表 4. 卡地址映射概述 ................................................................................................................................................. 15

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DS33Z44DK

元件清单

表 1给出了DS33Z44 和DS33Z11/DS33Z41 开发板及其子卡的元件清单。其BOM给出了 5 块电路板的元件清单，这

些电路板是DS33Z11DK、DS33Z44DK、DS21458RC、DS3174RC和DS2155-DS21348-DS3170RC。各器件标号
仅使用一次。例如，U18 仅出现在DS33Z11DK上，而不再用于其他电路板。请参考

表 2。

表1. 元件清单(未显示去耦电容)

DESIGNATION QTY DESCRIPTION SUPPLIER PART

U18 1

U20 1

U22 1

U23 1 DS3/E3 SCT, 11X11 CSBGA, 100 PIN Dallas Semiconductor DS3170

U24 1 T1/E1/J1 XCVR 100P QFP 0-70C Dallas Semiconductor DS2156L

U25 1 3.3V LIU Dallas Semiconductor DS21348

UB08 1

U01, U09 2

U07, U11 2

U13, UB01 2

U21, UB07 2

U31, UB06, UB11 3

C11, C13, C16, C25, C27, C31–
C35, C37, C41, C47, CB10,
CB63, CB114, CB128, CB164,
CB496

CB390, CB391, CB395, CB396 4 1206 CERAM 0.1uF 25V 10% Panasonic ECJ-3VB1E104K

D01–D03, D05, DB03–DB05 7 SCHOTTKY DIODE, 1 AMP 40 VOLT International Rectifier 10BQ040
DS01, DS07, DS10–DS12,

DS17, DS20
DS02, DS03, DS09, DS14,
DS15

DS04–DS06, DS08, DS13,
DS16, DS18, DS27, DS28,
DS35, DS37, DS38, DS40

DS19, DS43 2 LED, GREEN, SMD Panasonic LN1351C
DS21–DS26, DS30, DS32–

DS34, DS36, DS39, DS41,
DS42, DS44–DS48

GND_TP01–GND_TP07,
GND_TP09-–GND_TP44,
GND_TP46–GND_TP68,
GND_TPB01–GND_TPB10

H1–H8, H17–H19 8

19 1206 CERAM 10uF 10V 20% Panasonic ECJ-3YB1A106M

7 LED, AMBER, SMD Panasonic LN1451C

5 L_LED, GREEN, SMD Panasonic LN1351C

13 LED, RED, SMD Panasonic LN1251C

19 L_LED, RED, SMD Panasonic LN1251C

76 STANDARD GROUND CLIP KEYSTONE 4954

ELITE 10/100 ETHERNET TRANSPORT OVER
SERIAL LINK 14X14 CSBGA 169 PIN

3.3V T1.E1.J1 QUAD TRANSCEIVER 0-70C 256P
BGA

QUAD 10/100 ETHERNET EXTENSION TO WAN
17X17 PBGA 256 PIN

QUAD TRIPLE DUAL SINGLE ATM PACKET PHYS
FOR DS3 E3 STS1 0-70C 400P BGA

SOIC 8PIN STEP-UP DC-DC CONVERTER 0.5A
LIMIT

8-Pin μMAX/SOIC 1.8V or Adj

MICROPROCESSOR VOLTAGE MONITOR, 2.93V
RESET, 4PIN SOT143

Dual RS-232 transceivers with 3.3V/5V internal
capacitors

8-Pin μMAX/SOIC 2.5V or Adj

KIT, 4-40 HARDWARE, .50 NYLON STANDOFF AND
NYLON HEX-NUT

Dallas Semiconductor DS33Z11

Dallas Semiconductor DS21458

Dallas Semiconductor DS33Z44

Dallas Semiconductor DS3184

Maxim MAX1675EUA

Maxim MAX1792EUA18

Maxim MAX811SEUS-T

MAXIM NA

Maxim MAX1792EUA25

NA Lab Stock

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DS33Z44DK

DESIGNATION QTY DESCRIPTION SUPPLIER PART

KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF

H9–H16 16

J01–J05 5 CONNECTOR, FASTJACK SINGLE, 8 PIN Halo Electronics HFJ11-2450E

J06, J41 2 100 MIL 2*7 POS JUMPER NA Lab Stock

J07–J12 6

J13–J22 10

J23, J29, J32, J38, J39, J43,
J44, J47, JB07

J24, J30, J31, J33 4 100 MIL 2 POS JUMPER NA Lab Stock

J25, J26, J45, J46 4 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT NA Lab Stock

9

AND NYLON HEX-NUT (1.12 STANDOFF PN =
4807K-ND)

RECEPTACLE, SMD, 140 PIN, .8MM, 2 ROW
VERTICAL

L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO
NOT POPLUATE

L_TERMINAL STRIP, SHROUDED, 10 PIN, DUAL
ROW, VERT

NA Lab Stock

AMP 5-179010-6

NA Lab Stock

3M Electronics 2510-6002UB

J27, J42 2

J28, J36 2 L_CONN, DB9 RA, LONG CASE AMP 747459-1

J48, J54, JB01 3 SOCKET, BANANA PLUG, HORIZONTAL, BLACK Mouser Electronics 164-6218

J49–J52 4 CONNECTOR BNC 75 OHM VERTICAL 5PIN Cambridge CP-BNCPC-004

J53, JB02, JB08 3 SOCKET, BANANA PLUG, HORIZONTAL, RED Mouser Electronics 164-6219

J55, JB11 2 L_RJ48 8 PIN SINGLE PORT CONNECTOR MOLEX 15-43-8588

J56–J59, J61, J63 6 CONNECTOR BNC 75 OHM RA 5PIN Trompetor UCBJR220

J60, J62, J64, J65 4 CONNECTOR BNC RA 5PIN Trompetor UCBJR220

JB05, JB06, JB09, JB10, JB13,
JB14

JB12 1 RA RJ45 8PIN 4PORT JACK MOL 43223-8140

JP01–JP19 19 100 MIL 3 POS JUMPER NA NA

L01, L03–L08, LB01, LB02 9 FERRITE 3A 100 OHM AT 100 MHZ 1206 SMD Steward HI1206N101R-00

L02, L09 2 INDUCTOR 22.0uH 2PIN SMT 20% Coiltronics UP1B-220

L10 1 XFMR 1-2CT XMIT, 1-1CT RCV, 40P WIDE SOIC Pulse T1068

R01, R02, RB10, RB11, RB18,
RB19, RB22, RB23, RB26,
RB27
R03, R04, RB12, RB13, RB20,
RB21, RB24, RB25, RB28,
RB29

R05, R06, R08, R09, R11 5

R07, R12, R16, R79, R160,
R244, R248, R250, R251,
R254, R255, RB126, RB143,
RB147, RB150, RB157

R10, R107 2 RES 1206 5.6 Ohm 1/8W 5% Panasonic

R132, R137, R142, R144,
R156, RB194, RB208, RB227

6 PLUG, SMD, 140 PIN, .8MM, 2 ROW VERTICAL AMP 179031-6

10 RES 0603 54.9 Ohm 1/16W 1% Panasonic ERJ-3EKF54R9V

10 RES 0603 49.9 Ohm 1/16W 1% Panasonic ERJ-3EKF49R9V

16 RES 0603 1.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ102V

8 L_RES 0603 0 Ohm 1/16W 1% AVX CJ10-000F

CONN 50 PIN, 2 ROW, POSTS VERT,
MOTHERBOARD FOOTPRINT

RES 0603 10.0K Ohm 1/16W 1% - Must be 1%
tolerance

SAMTEC TSW-125-07-T-D

Panasonic ERJ-3EKF1002V

ERJ­8GEYJ5R6V

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DS33Z44DK

DESIGNATION QTY DESCRIPTION SUPPLIER PART

R13–R15, R18–R20, R22, R23,
R29, R30, RB01, RB03, RB07,
RB09, RB15–RB17, RB30–
RB32, RB34–RB38, RB41,
RB44, RB47, RB48, RB50–
RB52, B55, RB60, RB62, RB72,
RB73, RB75, RB80, RB82

R17, R21, R25–R28, R31, R55,
R57–R59, R71, R74–R76, R83,
R96–R102, R105, R106, R109,
R111, R112, R115–R117,
R120, R122–R126, R128,
R133, R134, R140, R141,
RB61, RB96, RB97, RB99,
RB100, RB102–RB110, RB112,
RB114–RB119, RB121,
RB123–RB125, RB127, RB128,
RB130, RB131, RB133,
RB135–RB138, RB145, RB148,
RB149, RB160, RB161, RB164,
RB165, RB167–RB171,
RB173–RB181, RB184, RB187,
RB311, RB320, RB335, RB339,
RB359
R171, R172, R174, R175,
R190, R191, R240, R241
R198–R200, R210–R213,
RB306, RB325, RB326
R201–R208, RB321–RB324,
RB327–RB330

R239, RB349 2 RES 0805 51.1 Ohm 1/10W 1% Panasonic ERJ-6ENF51R1V

R24, R114, R197, RB14, RB33,
RB40, RB42, RB43, RB49,
RB53, RB54, RB57–RB59,
RB71, RB77, RB78, RB152–
RB156, RB221, RB234, RB251,
RB284, RB304, RB331, RB332,
RB342, RB344, RB350, RB354,
RB360

R242, R243, RB144, RB166,
RB355–RB358, RB368–RB371

R32, R70, R78, R161, R176,
R194, R195, R237, R238,
RB129, RB134, RB146, RB193
R33–R54, R60–R69, R72, R73,
R131, R136, R143, R147,
R150, R154, R158, R163,
R166, R169, R173, R178–
R189, R215–R228, RB89–
RB95, RB101, RB188–RB191,
RB196–RB199, RB202–RB205,
RB210–RB213, RB216–RB219,
RB223–RB226, RB230–RB233,
RB239–RB242, RB244–RB249,
RB252–RB260, RB265–RB268,
RB270-RB282, RB289–RB297

R56, R90 2 RES 0603 1.0M Ohm 1/16W 5% Panasonic ERJ-3GEYJ105V

R77, RB159 2 L_RES 1206 0 Ohm 1/8W 5% Panasonic

R80, R81, R84, R87, R89, R91–
R93, R95, R108, R110, R118,
R127, R152, R153, R196,
R209, R214, R229–R236,
RB200, RB237, RB238, RB263,
RB264, RB286, RB287, RB300,
RB301, RB333, RB364

40 RES 0603 5.1K Ohm 1/16W 5% Panasonic ERJ-3GEYJ512V

104 RES 0603 30 Ohm 1/16W Panasonic ERJ-3GEYJ300V

8 L_RES 0805 0.0 Ohm 1/10W 5% Panasonic

10 RES 0603 332 Ohm 1/16W 1% Panasonic ERJ-3EKF3320V

16 RES 1206 0 Ohm 1/8W 5% Panasonic

34 L_RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V

12 RES 0603 51 Ohm 1/16W 5% Panasonic ERJ-3GEYJ510V

13 RES 0603 330 Ohm 1/16W 5% Panasonic ERJ-3GEYJ331V

152 RES 0402 30 Ohm 1/16W 5% Panasonic ERJ-2GEJ300X

37 RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V

ERJ­6GEY0R00V

ERJ­8GEYJ0R00V

ERJ­8GEYJ0R00V

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DS33Z44DK

DESIGNATION QTY DESCRIPTION SUPPLIER PART

R85, R88, R94, R104, R113,
RB02, RB04–RB06, RB08,
RB39, RB45, RB46, RB56,
RB63–RB70, RB76, RB83,
RB98, RB183, RB185, RB192,
RB209, RB228, RB302, RB303,
RB305, RB338, RB340, RB341,
RB346–RB348, RB351–RB353,
RB361–RB363, RB365–RB367

R86, R103, R119, R121, R129,
R130, R135, R138, R139,
R145, R146, R149, R151,
R157, R162, R164, R167,
R168, R170, R177, R192,
R193, R245-R247, R249, R252,
R253, R256, R257, RB74,
RB79, RB132, RB139-RB141,
RB151, RB162, RB163, RB172,
RB182, RB186, RB206, RB207,
RB214, RB215, RB220, RB222,
RB229, RB235, RB236, RB243,
RB250, RB261, RB262, RB269,
RB308–RB310, RB343, RB345

RB201, RB285 2 RES 0805 330 Ohm 1/10W 5% Panasonic ERJ-6GEYJ331V

RB283 1

RB298, RB299, RB312–RB319,
RB336, RB337

RB81, RB84–RB88, RB111,
RB113, RB120, RB122

SW01–SW05, SW08–SW21,
SW24–SW26, SW29–SW31,
SW33–SW44

48 RES 0603 2.0K Ohm 1/16W 5% Panasonic ERJ-3GEYJ202V

61 L_RES 0603 10K Ohm 1/16W 5% Panasonic ERJ-3GEYJ103V

RES 0603 10K Ohm 1/10W 5% - SEE SPECIAL
INSTRUCTIONS

12 RES 0805 61.9 Ohm 1/10W 1% Panasonic ERJ-6ENF61R9V

10 RES 0603 DO NOT POPULATE NA NA

37 L_SWITCH, SP3T SLIDE, 4PIN TH Tyco 3-1437575-3

Panasonic

603_ERJ­3GEYJ103V

SW06, SW22 2 L_SWITH 8POS 16PIN DIP LOW PROFILE AMP 435668-7

SW07, SW23 2 SWITCH MOM 4PIN SINGLE POLE Panasonic EVQPAE04M

SW27, SW28, SW32 3 L_DIPSWITCH, 10 POS AMP 435668-9

T01, T03 2 XFMR 16P SMT Pulse TX1099

T02, TB01 2 XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN Pulse T3049

TP01–TP78, TPB01, TPB02 80 TESTPOINT, 1 PLATED HOLE, DO NOT STUFF NA NA

U02–U06 5

U08, U12, U29 3 1MBit Flash based config mem Avnet XCF01SV020C

U10 1 XILINX SPARTAN xc200 2.5V FPGA,256 PIN BGA Xilinx

U14, U26, U30, UB05 4 CYPRESS SRAM, LAB STOCK NA NA

U15, U19 2 mmc2107 processor Motorola MMC2107

U16, U27 2 XILINX SPARTAN 2.5V FPGA,256 PIN BGA Xilinx

U17, U28, U32 3 10 pin res pack, 10K ohm NA NA

UB02, UB03, UB04 3 100 PIN CPLD XILINX

UB09, UB10 2

IC, DsPHYTER11-SINGLE 10/100 ETHERNET
TRANSCEIVER, 65 PIN LLP

SYNCHRONOUS DRAM, 1MEGX32X4 BANKS,
TSOP 86 PIN

National
Semiconductor

Micron

DP83847ALQA5
6A

XC2S200­5FG256C

XC2S50­5FG256C

XC95144XL­10TQ100C

MT48LC4M32B2
TG-7

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DS33Z44DK

DESIGNATION QTY DESCRIPTION SUPPLIER PART

UX01–UX12, UXB02–UXB04,
UXB06–UXB08

UXB01, UXB05 2 HIGH SPEED INVERTER Fairchild NC7SZ86

X01, X02 2 XTAL LOW PROFILE 8.0MHZ ECL EC1-8.000M

Y01, Y09 2

Y02, Y13 2

Y03 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ SaRonix

Y05, Y06 2

Y07 1 OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ SaRonix

Y08 1 OSCILLATOR, CRYSTAL CLOCK, 5.0V - 44.736 MHZ SaRonix

YB02 1

18 HIGH SPEED BUFFER Fairchild NC7SZ86

OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000
MHZ, Low Jitter required for PHY

SPI SERIAL EEPROM 16K 8 PIN DIP 2.7V NEEDS
SOCKET

OSCILLATOR, CRYSTAL CLOCK, 3.3V - 100.000
MHZ

L_OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048
MHZ

SaRonix

Atmel

SaRonix

SaRonix

NTH089AA3-

25.000

AT25160A-10PI-

2.7

NTH039A3-

2.0480

NTH089A3-

100.0000

NTH089AA3-

44.736

NTH089AA-

44.736

NTH039A3-

2.0480

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图1. 系统平面图

ETHERNET PHYs,

MAGNETIC,

LEDS, AND

JUMPERS

HARDWARE

MODE SWITCHES

FOR DS33Z44

DS33Z44 MAINBOARD

LEDS AND TESTPOINTS

SDRAM

DS33Z44

MICROPROCESSOR

AND SERIAL PORT

(57600-8-N-1)

DS33Z44DK

DS21458 RESOURCE CARD

(DETAIL PROVIDED BELOW)

DS3184 RESOURCE CARD

(DETAIL PROVIDED BELOW)

SERIAL INTERFACE

2 X 140 PIN CONNECTORS

图2. DS3174 子卡平面图

+ JUMPERS

TEST POINTS

140 PIN CONNECTORS (2 TOP, 2 BOTTOM)

JUMPERS

CPLD

(MUX)

CPLD

(MUX)

OSC

DS3174

QUAD-PORT

T3/E3

TRANSCEIVER

LOOPBACK

JUMPER

DS3174 PORT 3
LAN PORT 3

BNC Tx Rx
DS3174 PORT 1
LAN PORT 4

DS3174 PORT 2
LAN PORT 2

JTAG

DS3174 PORT 4
LAN PORT 1

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DS33Z44DK

J
G

TRANSFORMER

DS3174 四端口T3/E3 的PCB平面图在
设置为三态/使能。电路板方向如

还增加了一个 2 引脚跳线 JP24 以允许环回。安装短路器后，该电路板通过 CPLD 实现环回；DS33Z44 发送的所有
通信数据将送回 Z44，在 CPLD 环回模式，DS3174 发出的信息将被忽略。

四端口 T3/E3 板用于连接 DS33Z11 或 DS33Z44 主板。四端口 T3/E3 板可与四端口 T1/E1 板配合使用，以这种方式
使用时，四端口 T1/E1 板安装在四端口 T3/E3 板的下方。这样 T3/E3 板上的跳线可分别控制两块电路板的各端口为
三态或使能状态。

图 3给出了DS21458 四端口T1/E1 PCB的平面图。当前的配置是采用板载 2.048MHz振荡器作为MCLK1 振荡器。

WAN卡上提供port 3 和port 4 的测试点，主板上提供port 1 和 2 的测试点。

四端口 T1/E1 板可与四端口 T3/E3 板配合使用。以这种方式使用时，四端口 T1/E1 板安装在四端口 T3/E3 板的下
方。这样 T3/E3 板上的跳线可分别控制两块电路板的各端口为三态或使能状态。

图 2中给出。JP16、JP17、JP18 和JP19 为 3 引脚跳针，用于将T3/E3 端口

图 2所示时，各跳线上部的两个引脚短接可使能T3/E3 通信。

图3. DS21458 子卡平面图

TEST POINTS

140 PIN CONNECTORS

INT LED

FPGA

TA

OSC

MCLK1, 2

DS21458

QUAD-PORT

T1/E1

TRANSCEIVER

QUAD

RLOS LEDS

PORT 2

PORT 4

PORT 1

QUAD-PORT RJ45

PORT 3

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DS33Z44DK

PCB 勘误表

• 串联子卡配置开关SW27、SW28 和SW32 的VCC和地的丝印标号方向有错。需用粘性标签加以修正。

• 四端口 T1E1 卡的 JTAG 连接器的信号描述有误。需用粘性标签加以修正。

• 在 PCB 布局中变压器初级位于错误的一侧(由此产生 2:1 的绕线而非 1:2)。原理图对此进行了修正，PCB/装配图

纠正了这个错误。

文件位置

该开发板依靠几个支持文件，由CD 光盘提供并且作为一个zip 文件可从Maxim 网站获得www.maxim-

ic.com.cn/DS33Z44DK。

所有位置都相对于 CD/zip 文件的顶层目录。

• DS33Z44 的寄存器定义文件和配置文件：

o .\cfg_demo_gui\DS33Z44_cfg_demo_gui\DS33Z44.def
o .\DS33Z44_cfg_demo_gui\SU_LI_PORT4.def (def files for port 3, 2, 1 not shown)
o .\DS33Z44_cfg_demo_gui\basic_config.mfg

• DS21458 的寄存器定义文件和配置文件：

o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC.def
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\DS21458RC_FPGA.def
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\e1_gapclk_crc4_hdb3_nocas.ini
o .\DS33Z44_cfg_demo_gui\Qt1e1_DS21458\gapclk_DS21458_T1_ESF_LBO0.ini

• DS3174 的寄存器定义文件和配置文件：

o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\ds3184_evbrd_reduced.def
o ….. 14 other low level def files ….
o .\DS33Z44_cfg_demo_gui\Qt3e3_DS3184\84_t3_sct_needscoaxlb.mfg

10 of 59

DS33Z44DK

基本操作

开发板供电

• 将子卡插入主板。

• 给 PCB 上的 3.3V 和 GND 香蕉插头连接电源，启动时系统会消耗约 1A 电流。

• 将开关设置为

• 左上排：除 MODEC0 为高外，全低

• 右上排：A2、A1、A0 在中间位置，SCANTRI 为低

• 下排：全高(AFCS、FULLDS、H1OS)

概要

• 上电后，处理器 FPGA 的状态指示 LED (绿色的 DS19)被点亮，中断指示 LED (红色的 DS42)被点亮。
DS33Z44 的队列溢出指示 LED (红色的 DS45、DS46、DS47、DS48)不会点亮。如果连接有以太网则 PHY
LINK LED (绿色的 DS02、DS03、DS14)将被点亮。

接下来为几个基本的系统初始化。

基本的 DS33Z44 初始化 (用于所有的快速设置)

本章节介绍配置 Z44 的四种基本方法。这些初始化中的任意方法都可参考下面的例子快速设置：

1. 上电后，板载器件驱动为 DS33Z44 及其串行子卡提供基本的配置。这将使能以太网端口与串行端口之间的
通信。更多详细信息请参考器件驱动文档。器件驱动操作依赖于跳线设置，详细资料在表 2 中列出。

2. 基于寄存器的配置。运行ChipView.exe并选择Register View。在提示定义文件时，选择名为DS33Z44.def的

文件。加载定义文件后，转到文件菜单并选择
择名为 4Portsbasic_config.mfg的文件。

3. 硬件模式。按照开发板供电章节所述对开关进行设置，然后进行以下改动：HWMODE←3.3V，A0←3.3V，
A1←3.3V，A2←0V。这可将端口设置为 LSB 在前，加扰关闭，封装 HDLC。此后数据将从以太网端口传送
至串口。在这种模式下，不传送广播帧(例如 ping)。

4. DK 提供 EEPROM 模式，但是超出了本手册的范围。

快速配置

• 在串行子卡上安装跳线 24。跳线JP16–JP19 必须为高。这将使卡进入CPLD回环并按照表 3所述使能所有四个端

• 按照前面章节所述完成硬件配置和 DS33Z44 的一个基本配置。

• 使用附带的电缆，将以太网连接器连接至通用 PC 或网络测试设备。这将使链接 LED 点亮。

• 此后，发送给 DS33Z44 的任何数据包都将被重复发回。输入包(例如：ping)将使 RX LED 闪烁。之后 TX LED

• 要配合使用器件驱动，请从下拉菜单中选择：

#1 (Device Driver + CPLD

口。

会闪烁。

• Tools→Plugins→Load Plugins。在询问 DLL 是否已注册时选择是

• Select Tools→Plugins→DS33Z44/11/41 Device Driver Demo

• 一个名叫‘Zchip Configuration’的程序弹出。

• 通过选择 File→Load Settings (在 ‘Zchip Configuration’ 程序中)为 GUI 预加载基本的配置。选择名为

‘basic_Config.eset’的文件

表 2 (带有简短描述)所述的软件模式。

File→Memory Config File→Load .MFG file。出现提示后，选

环回

)

11 of 59

DS33Z44DK

快速配置

• 在DS3174 串行子卡上安装跳线J24。跳线JP16–JP19 应设置为高。这将使卡进入DS3174 模式并按照表 3所述

• 按照前文所述完成硬件配置和 DS33Z44 的一个基本配置。

• 使用附带的电缆，将以太网连接器连接至通用 PC 或网络测试设备。这将使链接 LED 点亮。

• 运行ChipView.exe (如果它已被打开，则退出会话)并选择Register View。在提示定义文件时，选择名为

• 在 DS3174 的网络侧安装回环连接器。

• 此后，发送给 DS33Z44 的任何数据包将被重复发回。输入数据包(例如：ping)将使 RX LED 闪烁，之后 TX LED

快速配置

• 按照前文所述完成硬件配置和 DS33Z44 的一个基本配置。

• 使用附带的电缆，将以太网连接器连接至通用 PC 或网络测试设备。这将使链接 LED 点亮。

• 运行ChipView.exe (如果它已被打开，则退出会话)并选择Register View。在提示定义文件时，选择名为

• 在 DS21458 的网络侧安装环回连接器；RLOS LED 将熄灭。

• 此后，发送给 DS33Z44 的任何数据包将被重复发回。输入数据包(例如：ping)将使 RX LED 闪烁，之后 TX LED

#2 (DS3174 T3E3)

使能所有四个端口。

ds3184_evbrd_reduced.def 的文件。加载定义文件后，转至文件菜单选择

File→

Load .MFG file。出现提示后，选择名为 84_t3_sct_needscoaxlb.mfg的文件。

也闪烁。

#3 (DS21458 T1E1)

DS21458.def的文件。加载定义文件后，转至文件菜单选择
名为e1_gapclk_crc4_hdb3_nocas.ini的文件。

也闪烁。

File→Reg Ini File→Load Ini File。出现提示后，选择

File→Memory Config

12 of 59

DS33Z44DK

配置开关和跳线

DS33Z44DK具有数个配置开关、香蕉插头、振荡器和跳线。表 2按照在PCB上出现的顺序(从左到右，从上至下)，
提供了这些信号的描述。

表2. 主板 PCB 配置

SILKSCREEN
REFERENCE

J25.9 + J25.10 Reserved Not Installed —

J25.7 + J25.8 Enable device driver User decision —

J25.5 + J25.6 Enable callbacks User decision —

GROUND
(banana plug)
VDD 3.3V
(banana plug)
OnCe BDM — — Debug connector for processor
DCEDTES
(3pos switch)
RMIIMII
(3pos switch)
CKPHA
(3pos switch)
MODEC0
(3pos switch)
MODEC1
(3pos switch)
HWMODE
(3pos switch)
SCANMO
(3pos switch)
SCANTRI
(3pos switch)

….testpoints…. DS33Z44 testpoints — —

Z-RESET (button) DS33Z44 reset — — System reset

A2, A1, A0
(3pos switches)

SDRAM CLOCK

MII CLOCK PHY MII clock Installed Installed

spi_cs, spi_ck,
spi_miso,
spi_mosi

FUNCTION

Power supply ground — —

Power supply VDD — —

DS33Z44 mode pin;
DTE/DCE selection

DS33Z44 mode pin Low Low High for RMII, low for MII

DS33Z44 mode pin Low Low

DS33Z44 mode pin High Low Software mode selected

DS33Z44 mode pin Low Low Software mode selected

DS33Z44 mode pin Low Low

DS33Z44 mode pin Low Low Set low for normal operation

DS33Z44 mode pin Low Low Set low for normal operation

DS33Z44/SPI pins Mid position Mid position

DS33Z44 SDRAM
clock

— — — SPI signals (for EEPROM memory)

BASIC SETTING
SW MODE HW MODE

Low Low Low for DTE

Installed Installed

DESCRIPTION

This jumper is not for use with the
DS33Z44 design kit. Pin J25.10 has
been removed to prevent accidental
installation.
When installed the device driver will
con 图 the DS33Z44 and the
Transceiver during power-up.
When installed the driver will
respond to interrupts.
System Ground. Always connected
to power supply.
System VDD. Always connected to
power supply.

SPI EEPROM hardware mode
configuration switch

Hardware/software mode (software
mode selected)

Processor bus, JTAG and LAN side
testpoints for Zchip

Address pin/EEPROM config switch.
Set to mid position to allow
connection to processor.
100MHz oscillator to drive SDRAM
clock
25MHz oscillator to drive SDRAM
clock

….testpoints….. DS33Z44 testpoints — — DS33Z44 serial port testpoints

AFCS
(1 per port)

DS33Z44 mode pin HW mode only High Set high to enable auto flow control.

13 of 59

SILKSCREEN
REFERENCE

FULLDS
(1 per port)

H10S
(1 per port)

GROUND/VDD
(banana plug)

VDD 3.3V
(banana plug)

FUNCTION

DS33Z44 mode pin HW mode only High Set high to enable full duplex.

DS33Z44 mode pin HW mode only High Set high to confg for 100Mb.

Power supply
ground/3.3V

Power supply VDD — —

表3. DS3174 串行子卡跳线设置

BASIC SETTING
SW MODE HW MODE

— —

DS33Z44DK

DESCRIPTION

Redundant connection to system
power. Use plugs at either top or
bottom of board.
Redundant connection to system
power. Use plugs at either top or
bottom of board.

JUMPER
SETTINGS

JP16

JP17

JP18

JP19

J243 CPLD loopback

MODE COMMENT

Port 4 tri-state
(at CPLD)

Port 2 tri-state
(at CPLD)

Port 3 tri-state
(at CPLD)

Port 1 tri-state
(at CPLD)

When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.
When the middle pin of this 3 position jumper is set to VCC, the
CPLD passes traffic from the DS3174 to the DS33Z44. When the pin
is set low, the CPLD tri-states this port.

CPLD loopback makes the following connections:
Zrser ← Ztser, Ztden ← 3.3V, Zrden ← 3.3V,
Ztclki ← OscY03, Zrclki ← OscY03

14 of 59

DS33Z44DK

地址映射(所有板卡)

Motorola 子卡地址空间起始于 0x81000000。下面给出的所有偏移都是相对于子卡地址空间(在前文中给出)的起始
值。

表4. 子卡地址映射概述

OFFSET DEVICE DESCRIPTION

0X0000 to

0X0087

0X1000 to

0X1FFF

0X2000 to

0X2FFF

0X4000 to

0X4010

0X3000 to

0X3FFF

DS33Z44、DS21458 和 DS3174 内的寄存器可方便的使用基于主机的 ChipView 用户界面软件和之前提到的定义文
件来进行修改。

FPGA Processor board identification

DS33Z44 DS33Z44. Uses CS_X1.

DS21458 T1E1 DS21458 resource card. Uses CS_X2.

FPGA on DS21458 resource card. Used to facilitate IBO mode.

FPGA

DS3174 T3E3 resource card. Uses CS_X3.

Default configuration of FPGA is compatible with non-IBO mode
functionality. The FPGA settings do not require modification for
use with the DS33Z44.

DS33Z44 信息

关于DS33Z44 的更多信息，请参考我们网站www.maxim-ic.com.cn/DS33Z44提供的DS33Z44 数据资料。

DS33Z44DK 信息

关于DS33Z44DK的更多信息，请参考我们网站www.maxim-ic.com.cn/DS33Z44DK.提供的DS33Z44DK数据资料。

技术支持

若需进一步的技术支持，请将您的问题e-mail至[e-mail] (English only)。

文档版本历史

版本日期 说明

032305

042205

051105

110106

第一版 DS33Z44DK 数据资料发布。

基本的

更新

增加新的 PCB 勘误。
更新原理图。

DS33Z44

初始化

章节；增加

15 of 59

快速配置

#1 步骤

。

DS33Z44DK

2 X 140 PIN CONNECTORS

原理图

DS33Z44DK 的原理图在后续页中给出。由于采用了层次化原理图，以下说明也按顺序进行。主板由六个分层模块组
成：处理器模块，DS33Z44 模块，以及作为嵌套模块、包含在 DS33Z44 模块中的四个以太网模块。各串口卡
(DS21458 和 DS3174)由单层模块组成，连接至主板上的 140 引脚卡入式 AV 总线。

除V

和地之外，各层内的信号都为本地信号。输入端口和输出端口连接器可使分层模块内部的信号能作为分层模块

CC

符号的引脚来访问。这样一来，模块可以像普通元件一样用线连接在一起。下面再一次给出了带有各功能模块原理
图页码的系统框图。

这里未给出该系统中包含的其他分层模块(主要是单端口串口卡和 DS33Z11 主板)。由于这一点，页码将不连续并且
相对于总的页数将会有一些间断。但是，任何给定分层模块内部的页码是连续的。

DS33Z44 MAINBOARD TOP LEVEL

PHY SYMBOLS ON
PAGES 26-27

PORT 1 ETHERNET
PHY
SCHEMATIC
PAGES 30-31

PORT 3 ETHERNET
PHY
SCHEMATIC
PAGES 36-37

PORT 2 ETHERNET
PHY
SCHEMATIC
PAGES 32-33

DS33Z44 BLOCK
PAGE 20 SYMBOL

SCHEMATIC
PAGES 22-29

µP BLOCK
PAGE 21 SYMBOL

SCHEMATIC
PAGES 38-44

SCHEMATIC
PAGES 46-55

SERIAL INTERFACE

SCHEMATIC
PAGES 56-63

DS21458 RESOURCE CARD

DS3184 RESOURCE CARD

Maxim/Dallas Semiconductor不对Maxim/Dallas Semiconductor

没有任何通报的前提下修改产品资料和规格的权利。

Maxim Integrated Products, 120 San Gabriel D rive, Sunnyvale, CA 94086 408-737-7600

Maxim 标志是 Maxim Integrated Products, Inc.的注册商标。Dallas 标志是 Dallas Semiconductor Corp.的注册商标

16 of 59

产品以外的任何电路使用负责，也不提供其专利许可。

© 2006 Maxim Integrated Products • Printed USA

Maxim/Dallas Semiconductor

保留在任何时间、

。

D

20B 5<>

20B 8<>

20C 8<>

25B 3v

25B 7v

25D 7v

20B 3<>

20C 6<>

25B 2v

25B 5v

25C 5v

25D 2v

1

20C8<

Z44INT

Z44_RSER<4..1>

Z44_RDEN<4..1>

Z44_TSER<4..1>

25D 3v

22B 6v

22B 6v

22B 6v

21B7<

21B7<

21B7<

GND

V3_ 3

09/16/2004

1

1/2(BLOCK)

20/71(TOTAL)

BIS1_DUT

BIS0_DUT

BTS_DUT

Z44_TCLK<4..1>

Z44_TDEN<4..1>

Z44_RCLK<4..1>

V3_3

DATE:

PAGE:

INT

HWMODE

MODEC1

MODEC0

RDEN<4..1>

2

RSER<4..1>

TDEN<4..1>

TSER<4..1>

RCLKI<4..1>

TCLKI<4..1>

20C 6<>

20B3<>

2

_z44andlan_dn

HIERARCHICAL BLOCK

PAGES 22-29

25D 2v

DAT<7..0>

ADDR<9..0>

CS

WR

RD

RESET_B

3

CS_X1

WR_DUT

RD_DUT

21C4>

21B7<

21B7<

A_DUT<9..0 >

D_DUT<7..0 >

22B 6v

22B 6v

22B 6v

21B7<

21B7<

22B 5v

22A 1v22B1 v22D5v

4

21C4>

ALE

CS_ X4

GND

GND

3

1

6

5

4

2

RESET_B

20C 7<>

21C4>

22B 6v

GND

7

8

9

11

10

GND

14

13

12

159016

172219

GND

GND

18

20

23

21

PLUG

73

71

72

JB10

7478777675

79

818384

80

87

85

82

86

92

932491

89

88

94

959997

25C 2v

25D 2v

20D1>

20D1>

20D1>

Z44_TCLK<3>

Z44_TDEN<3>

Z44_TSER<3>

GND

GND

GND

35

3230333134

36

262725

29

28

101

100

102

98

96

37

104

105

106

107

103

25B 2v

20D1>

Z44_TSER<4>

GND

GND

39

38

40

42

41

43

110

109

111

108

112

113

25B 2v

20D1>

Z44_TDEN<4>

SIG_RETURN

GND

46474954525051

45

44

114

115

116

25B 2v

20C 6<>

20D1>

20A2>

20A 8<>

Z44_TCLK<4>

FPGAGC LK1 _NU

GND

GND

48

118

117

5358565557

123

120

119

122

121

125

124

0

GND

596260

129

128

127

126

XD<7..0>

3

1

5

GND

61

64

63

134

132

133

131

130

SIG_RETURN

STEVE SCULLY

DS33Z11/41/44DK01A0

GND

TITLE:

21B4>

7

ENGINEER:

3

RW_X

GND

GND

70

66

65

69

68

67

135

136

140

139

138

137

45

GND

P1 CONNECTOR (PLUG)

GND

20A1>

CS_ X5

21C4>

20A1>

GND

GND

GND

V3_ 3

GND

V3_ 3

GND

GND

GND

V3_ 3

GND

GND

GND

V3_ 3

GND

GND

V3_ 3

GND

20A1>

GND

GND

OSC 1_N U

2

V3_ 3

WR_X

CS_X3

CS_X2

6

4

21B4>

21C4>

21C4>

20A1>

56

Z44_RSER<3>

20D1>

Z44_RCLK<3>

Z44_RDEN<3>

20D1>

20D1>

20A1>

Z44_RSER<4>

20A 8<> 2 0A5<>

20D1>

20D1>

20D1>

20A1>

20A 5<>

Z44_RCLK<4>

Z44_RDEN<4>

XD<7..0>

25D 3v

25C 3v

25D 3v

20C6<>

20C 5<> 2 0B8<> 2 0B5 <> 20A8 <> 20 A5<>

25D 6v

25C 6v

20B 3<>

25C 5v

20C8<>

22B 6v

20A1

22B 7v

20D1>

20C3<21C4 >

21C7<

20D1>

20D1>

20A2>

20C 6<>20B 3<>

20C 5<> 2 0B8<> 2 0B5 <> 20A8 <> 20 A5<>

25B 6v

25B 6v

25B 5v

20D1>

20A1 20C8<>

20D1>

20A2>

20D1>

20C 5<> 2 0B8<> 2 0B5 <> 20A8 <> 20 A5<>

25B 3v

20B8<> 20B5<>

20C 8<> 2 0C5<>

20A1

20C 5<> 2 0B8<> 2 0B5 <> 20A8 <> 20 A5<>

20B5<> 20A8<>

21B4>

20A 3

6

20C 8<> 2 0C5<> 2 0B8 <>

20A1

25B 3v

25B 3v

XA<15..0>

20C 8<>

21C7<

21C7<

Z44_TCLK<1>

INT3

INT4

INT2

RESET_ B

GND

7

1

2

GND

3

7

6

5

4

Z44_TDEN<1>

Z44_TSER<1>

SIG_RETURN

GND

8

9

11

10

GND

GND

14

13

12

159016

172219

18

Z44_TSER<2>

SIG_RETURN

GND

20

24

23

21

Z44_TCLK<2>

Z44_TDEN<2>

262725

20A1 20C8<>

GND

GND

GND

35

3230333134

36

39

38

29

28

37

20A1 20C8<>

GND

GND

GND

40

41

42

44

43

46474954525051

48

45

21A5>

TDO _NU

TCK _NU

GND

5358565557

21A5>

3

1

5

GND

GND

10

8

6

GND

OSC 3_N U

21B4>

20A 8

GND

GND

MOTHERBOARD CONNECTORS FOR WAN R.C.

7

596260

61

65

64

63

70

66

69

68

67

PLUG

P2 CONNECTOR (PLUG)

DS33Z44 TOP LEVEL

JB14

73

71

72

VDD

7478777675

GND

GND

INT2

INT5

79

818384

80

82

GND

V3_ 3

87

85

86

GND

GND

92

93

91

89

88

GND

V3_ 3

20A1>

94

959997

96

GND

98

GND

104

105

101

100

103

102

GND

V3_ 3

20A1>

8

Z44_RDEN<2>

Z44INT

20D1>

21C7<

D

Z44_RSER<1>

25D 7v

20D1>

25C 7v

20D1>

25C 7v

20D1>

C C

Z44_RCLK<1>

Z44_RDEN<1>

Z44_RSER<2>

20C 8<> 2 0C5<> 2 0B8 <>

25B 7v

20D1>

20A1

20B 5<> 2 0A8<> 2 0A5 <>

Z44_RCLK<2>

20C 8<> 2 0C5<> 2 0B8 <>

20A 8<> 2 0A5<>

25B 7v

20D1>

25B 7v

20D1>

20A1

20B5<>

110

109

106

107

108

GND

114

111

115

118

117

116

112

113

GND

V3_ 3

GND

20A1>

20C 8<> 2 0C5<> 2 0B8 <>

20A 8<> 2 0A5<>

20A1

20B5<>

123

120

119

122

121

124

GND

GND

TMS _NU

TDI _NU

FPGAGC LK1 _NU

21A6>

21A6>

20A 3<>

129

128

127

126

125

GND

V3_ 3

20B 8<>

20A1>

402

20A 5<>

20A1

20C8<> 20C5<>

20B5<> 20A8<>

B B

134

132

135

133

136

140

139

138

131

130

GND

7

XA<15..0>

137

GND

OSC 4_N U

OSC 2_N U

V3_ 3

11

9

20A1

20C8<> 20C5<>

20B8<> 20B5<>

20A8<> 20A5<> 20A1>

8

A A

D

1

09/16/2004

1

2/2(BLOCK)

21/71(TOTAL)

DATE:

2

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

3

TITLE:

ENGINEER:

3

20A 6 20 A8 4 2C7v

20A 3 20 A5 4 2B3v

4

42B 3v

42B 3v

20C 3<> 42A 4v

20A 5<>

20D3<

20A 5<> 42A 4v

CS_X1

CS_X2

20C 5<> 42A 4v

CS_X3

CS_X4

CS_X5

20C3< 38A5v

20C 7<>

20A 5<> 42B 3v

20A 3<> 42B 3v

20A 7<> 44A 7v20A 7<> 44A 7v20A 8<>20A 8<> 44A 7v

XD<7..0>

XA<15..0>

WR_X

RW_X

45

RESET_B

56

I1

CS_X1

CS_X2

CS_X3

CS_X5

CS_X4

RESET_B

WR

RW_X

XD<7..0>

XA<15..0>

TDO_NU
TCK_NU

TDI_NU

TMS_NU

44A 7v

TDO_NU

TCK_NU

TDI_NU

TMS_NU

6

HIERARCHICAL BLOCK

INT2

INT3

INT4

INT5

INT4

INT5

INT3

7

INT2

20C 7<>

20C 7<>20C8<>

38B7v

20C 8<>

20C 7<>

38B7v

39D4v

38B7v

8

PAGES 38-44

_motprocrescard_dn

RD_DUT

RD_DUT

A_DUT<11..0>

WR_DUT

D_DUT<7..0>

BIS0_DUT

BIS1_DUT

BTS_DUT

BTS_DUT

BIS1_DUT

WR_DUT

BIS0_DUT

7

20C1>

20C1>

20D3<

20D3<

42C 3v

42C 3v

20C1>

42C 3v

42C 3v

42C 3v

D_DUT<7..0>

A_DUT<11..0>

20D3<

20D3<

42D 5v

42A 5v42 A6v

8

D

C C

B B

A A

D

10K

V3_3

RB74

10K

1

RB79

3

7

8

4

22C4<

20D3^

0

IN

V3_3

4

GND

WP*

VCC

HOLD*

SW04

2.7V

2

Y02

SI

SO

SCK

CS*

1

6

2

5

ZMISO

ZSPISCK

ZMOSI

22C 4<>

ZSPICS

22A6>

22C 4<>

22B 4<>

AT25160A_U

SP3T

SW08

ZADDR0

22D4<

ZADDR1

ADDR<9..0>

1

4

22C4<

2

09/16/2004

1

1/8(BLOCK)

22/71(TOTAL)

4

SP3T

SW18

SP3T

DATE:

PAGE:

ZADDR2

2

22C4<

STEVE SCULLY

DS33Z11/41/44DK01A0

3

TITLE:

V3_3

22B1<

20D 3^

IN

ADDR<9..0>

22A 2<>

22B 2<>

22B 2<>

4

ZADDR0

ZADDR1

3

ZADDR2

7

8

645

0

9

ZMOSI

3

1

2

ZMISO

ZSPISCK

6

5

4

20D 3^

DAT<7..0>

IO

7

J32

TMS _NU

TCK _NU

TDI _NU

TDO _NU

10

65

4

2

1

8

6108

412

3

7

5

9

3

7

9

ENGINEER:

3

45

CONN_10P

A7

A6

A1

A<0>

B2

B1

A<1>

C2

A2

A<2>

A<4>

A<3>

C3

A4

B3

A3

A<5>

A<6>

A<8>

A<7>

56

A5

B4

A<9>

22C2<

D<0>/MOSI

B5

D<3>

22C2<

22C2>

D<1>/MISO

D<2>/SPICK

C5

B7

B6

D<4>

C6

D<7>

D<5>

D<6>

CKPHA

F6

SCAN MODE

SCAN ENABLE

CKPHA

E8

SCANMOD

E7

28B4<

28C4<

28B4<

JTCLK

JTMS

JTDO

JTDI

JTRST

22D6<

22D6<

22D6<

22D6<

22D 6<>

SCANEN

RMIIMIIS

22A5<>

22A5<>

22A5<>

22A5<>

22A5<>

JTRST

E6

JTCLK

D4

JTDO

E5

JTDI

E4

JTMS

F7

JTRST

JTCLK

JTDO

JTDI

JTAG

U22

JTMS

DS33Z44_U1

MII/RMII

SDRAM CONTROL

MICRO PORT/SPI MASTER PORT

C4

DCEDTES

MODEC<1>

MODEC<0>

HWMODE

RST*

WR*/RW*

RD*/DS*

SPI_CS*

CS*

INT*

RMIIMIIS

A15

DCEDTES

D7

MODEC1

D6

MODEC0

D5

HWMODE

D8

RESET_B

E2

WR

E1

RD

E13

ZSPICS

D1

CS

D3

INT

OUT

OUT

OUT

OUT

28C4<

28D2<

28D4<

20C2^

28D2<

20C2^

28D4<

20C2^

IN

20D3^

IN

20D3^

22C2<

IN

20D3^

20D2^ 22A6<>

20D 2^

22A7>

6

INT

11

NC7SZ8 6_U

BUFFER

MDC

REF_CLKO

REF_CLK

MDIO

SBA<0>

SDMASK<0>

SBA<1>

SDMASK<1>

SDMASK<3>

SDMASK<2>

SYSCLKI

SDCLKO

SDCS*

SWE*

SCAS*

SRAS*

7

R8

C15

TPB02

1

RB181

8

REF_CLK

28A4<

F10

B15

F11

TPB01

TP34

11

R99

RB161

MDC

MDIO

27B6>

27B6>

R9

RB246

RB230

SD_BA1

SD_BA0

24B4<

24B4<

M7

T8

T11

R147

RB239

R166

SD_DQM1

SD_DQM0

SD_DQM2

24C4<

24C4<

24C4<

P8

N11

RB217

SD_DQM3

24C4<

T7

RB226

R158

SD_CS

SD_CLKO

24C4<

24C3<

N7

T15

RB219

SD_CLKI

28D5<

R7

P15

RB282

R163

SD_RAS

SD_CAS

SD_WE

24C4<

24C4<

24C4<

UNMARKED RESISTORS ARE 30 OHM

4

UXB07

7

22

RED

DS42

330

RB332

1

8

V3_3

REF_CLKO

27B3> 26B6> 26B3>

27B3> 26B6> 26B3>

D

C C

B B

A A

D

1

09/16/2004

1

2/8(BLOCK)

23/71(TOTAL)

DATE:

2

3

1

2

0

RB267

RB249

R173

4

RB280

RB268

RB265

7

9

8

6

5

R169

RB281

RB248

RB241

11

10

121413

RB233

RB247

RB242

RB213

RB240

16

17

19

15

RB279

RB197

18

20

R143

RB189

RB198

RB202

R136

23

22

21

R13 1

RB204

RB188

26

25

24

RB199

RB203

SD_DQ<31..0>

24D 7

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

N15

P13

P14

R14

R13

T14

T12

T13

P12

N12

R12

P4

N5

N4

M5

M3

P7

R6

T6

T5

R5

T4

P5

R4

3

M6N6P6

TITLE:

ENGINEER:

3

SDATA<0>

SDATA<1>

G12

F13

E14

K12

M14

L13

N3

4

P2

A14

V1_8ZCHIP

M4

F4

29A 4<>

E3

D2

C1

29B6< 23B4<

H10

H9

56

V3_3

H8

H7

H6

H5

H4

H3

G10

G9

G8

G7

1.8VDD13

1.8VDD12

1.8VDD11

1.8VDD10

1.8VDD9

1.8VDD8

1.8VDD7

1.8VDD6

1.8VDD5

1.8VDD4

1.8VDD3

1.8VDD2

1.8VDD1

V3_3

1.8VDD0

3.3VDD15

3.3VDD14

3.3VDD13

3.3VDD12

3.3VDD11

3.3VDD10

3.3VDD9

3.3VDD8

3.3VDD7

3.3VDD6

3.3VDD5

3.3VDD4

10UF

SDATA<2>

SDATA<3>

SDATA<4>

SDATA<5>

SDATA<6>

SDATA<7>

SDATA<9>

SDATA<8>

SDATA<10>

SDATA<11>

SDATA<12>

SDATA<13>

SDATA<14>

SDATA<15>

SDATA<16>

SDATA<17>

SDATA<18>

SDATA<19>

SDATA<20>

SDATA<21>

SDATA<22>

SDATA<23>

SDATA<24>

SDATA<25>

CB115

10UF

CB202

10UF

CB495

10UF

CB361

10UF

CB492

10UF

CB402

10UF

CB446

10UF

CB335

10UF

CB469

0.1UF

1

1

1

1

1

1

1

1

1

1

1

1

2

CB421

0.1UF

2

CB301

0.1UF

2

CB423

0.1UF

2

CB323

0.1UF

2

CB298

0.1UF

2

CB315

0.1UF

2

CB312

0.1UF

2

CB47

0.1UF

2

CB240

0.1UF

2

C184

0.1UF

2

CB289

470UF

2

CB26

I182

NA

DS33Z44

U22

PWR/GND

DS33Z44_U1

SDRAM CONTROL

V1_8ZCHIP

29A 4<>

29B6< 23D4<

470UF

1

1

1

1

1

1

1

1

1

1

1

1

1

2

CB211

0.1UF

2

CB387

0.1UF

2

CB247

0.1UF

2

CB255

0.1UF

2

CB256

0.1UF

2

CB178

0.1UF

2

CB246

0.1UF

2

CB227

0.1UF

2

CB177

0.1UF

2

CB386

0.1UF

2

C102

0.1UF

2

CB162

0.1UF

2

CB400

10UF

C90

10UF

CB408

10UF

CB417

10UF

C101

10UF

C88

10UF

C89

10UF

CB381

SDATA<26>

UNMARKED RESISTORS ARE 30 OHM

SDATA<27>

N13

SDATA<28>

M13

SDATA<29>

L12

SDATA<30>

M12

SDATA<31>

M11

VSS24

L9

VSS23

L8

VSS22

L7

VSS21

L6

VSS20

L5

VSS19

L4

VSS18

L3

VSS17

K10

VSS16

K9

VSS15

K8

VSS14

K7

VSS13

K6

VSS12

M10

VSS11

L10

VSS10

K4

VSS9

K3

VSS8

J10

VSS7

J9

VSS6

J8

VSS5

J7

VSS4

K5

RB212

RB191

RB211

RB210

RB218

27

28

29

31

45

UNMARKED RESISTORS ARE 30 OHMS

6

3.3VDD3

3.3VDD2

3.3VDD1

3.3VDD0

SDA<0>

G3

G4

G5

G6

T10

R10

R150

RB196

7

1

0

SDA<3>

SDA<4>

SDA<5>

SDA<6>

SDA<7>

SDA<8>

SDA<10>

SDA<11>

NC1

NC2

NC3

SDA<1>

SDA<2>

M8

N9

M9

R11

P11

RB190

RB223

RB216

N10

RB205

RB224

RB231

SDA<9>

P9

N8

P10

RB232

RB225

RB266

F3

T9

TP51

1111

R154

NC4

G1

F9

F8

TP52

TP50

TP49

VSS2

VSS0

J4

J3

VSS3

VSS1

J6

J5

7

3

4

2

7

6

5

10

11

9

8

J53

J48

B

A

BLACK

1

2

RED

CONN_B ANANA_ 2P

B

A

1

CONN_B ANANA_ 2P

2

V3_3

SD_A<11..0>

8

8

24A3>

D

C C

B B

A A

D

1

09/16/2004

1

3/8(BLOCK)

24/71(TOTAL)

DATE:

2

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

3

V3_3

23C 8

TITLE:

ENGINEER:

3

22B8<

22C8<

22C8<

22C8<

22C8<

22B8<

22B8<

22B8<

22C8<

22C8<

22C8<

SD_A<11..0>

SD_CLKO

FROM Z11 SYSCLKO

SD_BA0

SD_DQM3

SD_DQM2

SD_DQM1

SD_DQM0

SD_RAS

SD_CAS

SD_WE

SD_CS

18

4

682067

CLK

V3_3

3
9
35
41
49
55

56

75
81

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

17

CKE

CS*

WE*

CAS*

16

19

RAS*

71

28

59

22

BA<0>

DQM<3>

DQM<2>

DQM<1>

DQM<0>

0

SD_BA1

23

25

A<0>

BA<1>

1

266027

A<1>

3

4

2

616362

A<4>

A<2>

A<3>

7

9

8

6

5

A<7>

A<5>

A<6>

656466

A<8>

10

11

24

21

A<9>

A<11>

A<10>

VSSQ1

6

VSSQ2

12

VSSQ3

32

VSSQ4

38

VSSQ5

46

VSSQ6

52

VSSQ7

78

VSSQ8

84

45

1
15
29
43

0

1

SD_DQ<31..0>

7

23A 2

2
4

VDD1

VDD2

VDD3

VDD4

DQ<0>

DQ<1>

DQ<3>

DQ<2>

DQ<4>

DQ<5>

7

8

5

2

10

11

3

6

5

4

DQ<8>

DQ<7>

DQ<6>

13

74

7

8

DQ<11>

DQ<10>

DQ<9>

76

77

79

11

10

9

DQ<12>

808382

12

UB09

MT48LC4M32B2_TSOP_U

DQ<15>

DQ<13>

DQ<14>

85

15

14

13

SYNCHRONOUS DRAM

MT48LC4M32B2 - 1 MEG X 32 X 4 BANKS

DQ<28>

DQ<27>

DQ<26>

DQ<24>

DQ<22>

DQ<21>

DQ<19>

DQ<20>

DQ<18>

DQ<17>

DQ<16>

31

33

343736

18

17

16

39

40

19

22

21

20

DQ<25>

DQ<23>

42

474548

50

51

28

27

26

25

24

23

VSS1

44

VSS2

58

VSS3

72

VSS4

86

DQ<31>

DQ<30>

DQ<29>

31

56

30

54

6

53

29

7

8

D

C C

B B

A A

8

D

1

20D 2^

20D 2^

27D8<

27D8<

27D8<

IN

OUT

TXD0<3>

TSER<3>

30

RB311

TXD1<3>30TXD2<3>30TXD3<3>30TX_EN<3>

30

27D8<

30

TDEN<3>

R97

R123

RB187

RB169

RB170

27D5>

27D8<

27C8<26D5>

29C 8<>

29C4<

29C4<

RX_CLK<3>

TX_CLK<3>

H10S<3>

QOVF<3>

AFCS<3>

20D 2^

20D 2^

27D4<

27D4<

27D4<

IN

OUT

TXD0<4>

TSER<4>

30

RB320

TXD1<4>30TXD2<4>30TXD3<4>30TX_EN<4>

30

27D4<

30

TDEN<4>

R126

RB171

RB167

RB168

R124

27D2>

27D4<

27C4<

29C 8<>

29A4<

29A4<

RX_CLK<4>

TX_CLK<4>

H10S<4>

QOVF<4>

AFCS<4>

09/16/2004

DATE:

2

H13

M2

P3

M1

F15

TSER

TXD0

TDEN/TBSYNC

H14

G14

TXD1

TXD3

TXD2

H16

G16

E15

TX_EN

RX_CLK

TX_CLK

J11

F12

B8

H10S

QOVF

AFCS

R2R3R1

TSER

TDEN/TBSYNC

D16

B16

C16

TXD1

TXD0

TXD2

A16

A13

G13

E16

TXD3

TX_EN

RX_CLK

TX_CLK

C12

B12

A8

H10S

QOVF

AFCS

1

4/8(BLOCK)

25/71(TOTAL)

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

PORT

3

U22

DS33Z44_U1

U22

RSER

RCLKI TCLKI

RDEN/RBSYNC

RXD0

RXD1

RXDV

RX_CRS/CRS_DV

RX_ERR

COL_DET

RXD2

RXD3

FULLDS

DS33Z44_U1

PORT

TITLE:

RSER

RCLKI TCLKI

RDEN/RBSYNC

RXD0

RXD1

RXDV

RX_CRS/CRS_DV

RX_ERR

COL_DET

RXD2

RXD3

FULLDS

ENGINEER:

3

T1

T2

N1

P1

N2

RCLKI<3> TCLKI<3>

RSER<3>

4

56

REV01A0 SCHEMATIC SYMBOL (AND PCB) FOR Z44 HAD ERRORS

TXD/RXD PINS FOR PHY CONNECTION WERE INCORRECT

CORRECT PINOUT SHOWN AT BO TT OM OF PAGE

PORT3 PIN N2

IN

IN

20D 2^

20D 2^ 20D 2^

IN

30

RB335

J14

G15

RDEN<3>

RXD0<3>

RXD1<3>

IN

27D5>

27D5>

20D 2^

20D 2^

OUT

20D 2^

26D8<

IO

TXD0<1>

TSER<1>

30

R105

R122

TDEN<1>

K11

J12

J13

RXD2<3>

27D5>

26D8<

TXD1<1>

30

R96

M15

RXDV<3>

RXD3<3>

RX_CRS<3>

27C5>

27C5>

27D5>

26C8<

26D8<

26D8<

TX_EN<1>

TXD3<1>

TXD2<1>

30

30

R115

R98

H11

G11

RX_ERR<3>

H12

COL_DET<3>

FULLDS<3>

PORT4 PIN T3

27C5>

27C5>

29D4<

29D2<

29C2<

29D 8<>

26D8<

26D5>

H10S<1>

AFCS<1>

QOVF<1>

30

RX_CLK<1>

TX_CLK<1>

T3

RCLKI<4> TCLKI<4>

INIOIN

20D 2^ 20D 2^

A12

F16

D14

F14

D15

C14

B14

C13

B13

RSER<4>

RDEN<4>

RXD0<4>

RXD1<4>

RXDV<4>

RXD2<4>

RXD3<4>

RX_CRS<4>

RX_ERR<4>

COL_DET<4>

FULLDS<4>

45

IN

27D2>

27D2>

27D2>

27D2>

27C2>

27C2>

27C2>

27C2>

29B4<

20D 2^

20D 2^

26D2>

20D 2^

26D5<

26D5<

26D5<

20D 2^

20D 2^

OUT

IN

IO

TXD0<2>

TSER<2>

30

TCLKI<2>

RB339

30

RB164

TDEN<2>

RB165

TXD3<2>

TXD2<2>

TXD1<2>

30

30

RB121

RB180

26D5<

26C5<

26D5<

TX_CLK<2>

TX_EN<2>

30

30

RB179

29D 8<>

29A2<

29B2<

RX_CLK<2>

H10S<2>

QOVF<2>

AFCS<2>

TP65

TP64

TP63

C10

B10

B9

F2

F1

TSER

C9

F5

TXD1

TXD0

TDEN/TBSYNC

E10D9E9

TXD3

TXD2

TX_EN

C7A9A11

H10S

QOVF

AFCS

RX_CLK

TX_CLK

PORT

DS33Z44_U1

7

U22

RCLKI TCLKI

RDEN/RBSYNC

RXD0

RXD1

RSER

H2

H1

G2

TP57

B11

TP59

TP58

RXD2

E11

D11

C11

RX_CRS/CRS_DV

RX_ERR

COL_DET

RXD3

RXDV

E12

D12

D10

FULLDS

A10

D13

PORT1 PIN G2

RXD0<1>

RXD1<1>

8

RCLKI<1> TCLKI<1>

RDEN<1>

RSER<1>

26D5>

26D5>

INININ

RXDV<1>

RXD2<1>

26D5>

RX_ERR<1>

26C5>

26C5>

26C5>

RX_CRS<1>

RXD3<1>

FULLDS<1>

COL_DET<1>

26C5>

29D2<

U22

DS33Z44_U1

PORT2 PIN L2

TP61

TP60

TP62

L11

L16

L14

L15

R15

J2K2J1

TSER

R16

TXD1

TXD0

TXD2

TDEN/TBSYNC

M16

N14

TXD3

TX_EN

RX_CLK

TX_CLK

PORT

RCLKI TCLKI

RDEN/RBSYNC

RXD0

RXD1

RSER

L1

K1

L2

TP54

TP56

TP55

RCLKI<2>

RSER<2>

RDEN<2>

INIOIN

IN

20D 2^

20D 2^

20D 2^

RXD2

K16

H15

K14

K13

RXD0<2>

RXD1<2>

RXD2<2>

RXD3<2>

26D2>

26D2>

26D2>

RX_CRS/CRS_DV

RXD3

26D2>

RX_ERR

RXDV

K15

T16

N16

RXDV<2>

RX_CRS<2>

RX_ERR<2>

26C2>

26C2>

26C2>

J16

C8

H10S

QOVF

AFCS

PORT1 RXD0--RXD3 B11 ,C11,D11,E11

PORT4 RXD0--RXD3 B13,C13,B14,C14

PORT3 RXD0--RXD3 G15,J14,J13,J12

PORT2 RXD0--RXD3 K13,K14,H15,K16

COL_DET

FULLDS

J15

P16

6

7

FULLDS<2>

COL_DET<2>

29B2<

26C2>

8

PORT4 TXD0--TXD3 B16,C16,D16,E16

PORT3 TXD0--TXD3 F15,G14,H13,H14

PORT2 TXD0--TXD3 R15,R16,L15,N14

20D 2^

20D 2^ 20D 2^

20D 2^

D

C C

B B

A A

PORT1 TXD0--TXD3 B9, C9, D9, E9

D

1

32A7v

32A7v25A8<

32A7v25A8<

32A7v25A8<

32A7v25B8<

32A7v25A8<

25A 5<>

32A7v25A8<

32A7v25A8<

32A7v25A8<

32C7v30C7v26B7<22A6<27C7>27C3>

0.1UF

1

1

2

C04

10UF

CB02

10UF

CB01

10UF

CB03

CHASSI S

1

09/16/2004

DATE:

1

5/8(BLOCK)

26/71(TOTAL)

PAGE:

CHASSIS GND FOR PHY

2

RX_CLK<2>

RX_ERR<2>

RXD3<2>

RXD1<2>

RXD0<2>

RXD2<2>

RXD3

RXD2

RXD1

RXD0

RX_CRS<2>

RXDV<2>

COL_DET<2>

RXDV

RX_CLK

RX_ERR

RX_CRS

COL_DET

MII_CLK

32C7v

30C5v

28A4< 30C5v32C5v22C8<27B6>27B3>26B6>

32C5v22C8<27B6>

20C 3^

27B3>26B6>

L01

100O100MZH

2

LB02

100O100MZH

2

V3_3

MII_CLK<2>

2

STEVE SCULLY

DS33Z11/41/44DK01A0

MDC

MDIO

3

MDC
MDIO

TITLE:

ENGINEER:

3

RESET_B

RESET_B

V3_3

_mii_wan_dn

HIERARCHICAL BLOCKHIERARCHICAL BLOCK

RB33

R22

TX_CLK

TXD0

TXD1

TXD3

TXD2

TX_EN

LED_DPLX_ADD0

LED_COL_ADD1

LED_RX_ADD4

LED_TX_ADD3

LED_GDLINK_ADD2

R18

5.1K

RB34

5.1K

330

5.1K

2

DS02

1

4

LED_DPLX_A0<2>

TXD1<2>

TXD0<2>

32A5v 25B5<

TXD3<2>

TXD2<2>

32A5v 25A5<

32A5v 25A5<

TX_CLK<2>

TX_EN<2>

25A 5<>

32A5v 25A5<

32A5v 25A5<

32A5v

LED_GDLINK_A2< 2>

LED_DPLX_A0<2>

LED_COL_A1<2>

LED_RX_A4<2>

LED_TX_A3<2>

26A 4<>

26A 4<>

26A 4<>

32C5v 26C5<

LED_COL_A1<2>

LED_GDLINK_A2< 2>

32C5v 26C5<

32C5v 26C5<

RB14

330

RB15

5.1K

AMBER

2

DS01

1

RB42

330

R14

RED

5.1K

2

DS05

1

45

LED_TX_A3<2>

32C5v 26C5<

56

32C5v 26B4<

32C5v 26B4<

32C5v

32C5v

32C5v

30A7v

30A7v25C8<

30A7v25C8<

30A7v25C8<

30A7v25C8<

30A7v25C8<

30A7v25C8<

25C 5<>

30A7v25C8<

30A7v

25C8<

30C5v32C5v22C8<27B6>

COL_DET<1>

RXD0<1>

RXD1<1>

RXD2<1>

RXD3<1>

RX_CLK<1>

RXD3

RXD2

RXD1

RXD0

RX_CLK

7

_mii_wan_dn

RXDV<1>

RX_CRS<1>

RX_ERR<1>

27B3>26B3> 30C5v32C5v22C8<27B6>27B3>26B3>30C7v28A4<

6

RXDV

RX_ERR

RX_CRS

COL_DET

MII_CLK

MDC

MDIO

RESET_B

MII_CLK<1>

MDC
MDIO

IN

RESET_B

V3_3

7

PAGES 30-31 PAGES 32-33

RB58

RB75

RB80

5.1K

5.1K

TX_CLK

TXD0

TXD1

TXD3

TXD2

TX_EN

LED_DPLX_ADD0

LED_COL_ADD1

LED_RX_ADD4

LED_TX_ADD3

LED_GDLINK_ADD2

R19

330

5.1K

2

GREEN GREEN

DS09

1

RB49

330

R13

5.1K

AMBER

2

DS07

1

RB7 1

330

R23

5.1K

2

RED

DS13

1

LED_DPLX_A0<1>

LED_COL_A1<1>

8

TXD2<1>

TXD3<1>

TX_CLK<1>

TXD1<1>

TXD0<1>

30A5v 25C5<

30A5v 25C5<

30A5v 25C5<

30A5v 25C5<

D

TX_EN<1>

30C5v 26C8<

30C5v 26C8<

25C 5<>

LED_DPLX_A0<1>

30A5v 25C5<

30A5v

LED_TX_A3<1>

LED_COL_A1<1>

LED_GDLINK_A2< 1>

LED_RX_A4<1>

C C

B B

LED_GDLINK_A2< 1>

30C5v 26C8<

A A

LED_TX_A3<1>

LED_RX_A4<1> LED_RX_A4<2>

8

30C5v 26C8<

30C5v 26C8< 32C5v 26C5<

D

1

09/16/2004

1

6/8(BLOCK)

27/71(TOTAL)

DATE:

34A7v

34A7v25 A4<

34A7v25B4<

34A7v25B4<

34A7v25A4<

34A7v25A4<

25A 1<>

2

RXD0<4>

RXD1<4>

RXD2<4>

RXD3<4>

RX_CLK<4>

RX_CRS<4>

RXD3

RXD2

RXD1

RXD0

RX_CLK

RX_CRS

34A7v25 A4<

34A7v25 A4<

34A7v25A4<

RXDV<4>

RX_ERR<4>

COL_DET<4>

RXDV

RX_ERR

COL_DET

MII_CLK

34C7v36C7 v26B7<22A6<

34C7v28 A4< 36C5v34C5v22 C8<27B6>26B6>26B3>

36C5v34C5v22C8<27B6>

20C 3^

27C7>26B3>

26B6>26B3>

MII_CLK<4>

PAGE:

2

STEVE SCULLY

MDC

MDIO

3

RESET_B

RESET_B

MDC
MDIO

DS33Z11/41/44DK01A0

TITLE:

ENGINEER:

3

V3_3

_mii_wan_dn

HIERARCHICAL BLOCK

TXD0

TXD1

TXD2

PAGES 34-35

R24

330

R30

R29

5.1K

5.1K

TX_CLK

TXD3

TX_EN

LED_DPLX_ADD0

LED_COL_ADD1

LED_RX_ADD4

LED_TX_ADD3

LED_GDLINK_ADD2

1

RB73

5.1K

2

DS14

GREEN

RB59

330

R20

5.1K

AMBER

2

DS10

1

RB53

330

R15

5.1K

RED

2

DS08

1

4

LED_DPLX_A0<4>

LED_COL_A1<4>

TXD2<4>

TXD3<4>

TX_CLK<4>

TXD1<4>

TXD0<4>

34A5v 25A1<

34A5v 25A1<

34A5v 25B1<

34A5v 25B1<

56

36A7v25C4<

36A7v25C4<

36A7v25C4<

36A7v25C4<

RXD0<3>

RXD1<3>

RXD3<3>

RXD2<3>

TX_EN<4>

25A 1<>

LED_DPLX_A0<4>

34A5v 25A1<

34A5v

34C5v 27B4<

36A7v

36A7v25C4<

25C 1<>

RX_CRS<3>

RX_CLK<3>

36A7v25 C4<

36A7v25 C4<

36A7v25C4<

RX_ERR<3>

COL_DET<3>

RXDV<3>

LED_TX_A3<4>

LED_COL_A1<4>

LED_GDLINK_A2< 4>

LED_RX_A4<4>

27A 4<>

27A 4<>

27A 4<>

34C5v 27B4<

34C5v

34C5v

34C5v

36C7v28A4<

36C5v34C5v22C8<27B3>

34C5v 27C5<

34C5v 27C5<

LED_GDLINK_A2< 4>

34C5v 27C5<

LED_TX_A3<4>

34C5v 27C5<

34C5v 27C5<

45

26B6>26B3> 36C5v34C5v22C8<27B3>26B6>26B3>

RXD3

RXD2

RXD1

RXD0

RX_CLK

RX_CRS

7

HIERARCHICAL BLOCK

TXD0

TXD1

_mii_wan_dn

PAGES 36-37

TXD3

TXD2

TX_CLK

8

TXD2<3>

TXD3<3>

TXD1<3>

TXD0<3>

36A5v 25C1<

36A5v 25C1<

36A5v 25C1<

36A5v 25C1<

TX_EN<3>

TX_CLK<3>

25C 1<>

36A5v 25C1<

36A5v

D

RXDV

RX_ERR

TX_EN

COL_DET

MII_CLK

MDC

MDIO

RESET_B

LED_RX_ADD4

LED_DPLX_ADD0

LED_COL_ADD1

LED_TX_ADD3

LED_GDLINK_ADD2

RESET_B

MII_CLK<3>

MDC
MDIO

V3_3

V3_3

RB40

RB82

RB5 1

5.1K

5.1K

LED_DPLX_A0<3>

LED_COL_A1<3>

RB32

330

5.1K

2

GREEN

DS03

1

RB77

330

RB62

5.1K

2

AMBER

DS12

1

LED_TX_A3<3>

RB43

330

RB36

5.1K

RED

2

DS04

1

LED_RX_A4<3> LED_RX_A4<4>

LED_GDLINK_A2< 3>

36C5v 27C8<

36C5v 27C8<

36C5v 27C8<

LED_TX_A3<3>

LED_COL_A1<3>

LED_DPLX_A0<3>

36C5v

36C5v

27B8<

27B8<

LED_RX_A4<3>

LED_GDLINK_A2< 3>

C C

B B

36C5v 27C8<

A A

36C5v 27C8<

6

7

8

D

V3_3

1

MODEC0TRI

3

1

4

DCEDTESTRI

3

1

4

09/16/2004

1

7/8(BLOCK)

28/71(TOTAL)

DATE:

SW02

2
2

RB06

2.0K

1

2

MODEC0

22A6>

20C 2^

SW09

SP3T

SP3T

2
2

RB56

2.0K

1

(HELPS PCB NETLIST)

SIGNAME_TRI DOES NOT

DCEDTES

22A6<

CONNECT ANYWHERE

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

V3_3

3

HWMODETRI

3

1

4

MODEC1TRI

3

1

4

RMIIMIISTRI

3

1

4

SCANMODTRI

3

1

4

SCANENTRI

3

1

4

CKPHATRI

3

1

4

TITLE:

ENGINEER:

3

SW21

2
2

RB98

2.0K

1

4

HWMODE

22A6>

20C 2^

56

SW01

SP3T

2
2

RB02

2.0K

1

MODEC1

22A6>

20C 2^

22B8<

SW05

SP3T

2
2

RB39

2.0K

1

RMIIMIIS

22A6<

SW19

SP3T

SP3T

2
2

RB76

2.0K

1

SW20

2
2

RB83

2.0K

1

SCANEN

SCANMOD

22A5<

22A5<

SW03

SP3T

RB08

CKPHA

SP3T

2
2

26B6>

27B6>

26B2>

27B2>

2.0K

22D 8<>

1

MII_CLK<3>

MII_CLK<1>

MII_CLK<2>

MII_CLK<4>

REF_CLK

45

30

30

30

30

30

22A5<

R25

R17

R100

RB6 1

R116

V3_3

8

VCC

OSC

Y01

1

GND OUT

25.000MHZ_3.3V

1

4 5

SD_CLKI

3030

R11 1

4

UXB03

BUFFER

NC7SZ8 6_U

1

OSC100MHZ

V3_3

R112

6

8

7

VCC

100.000MHZ_3.3V

OSC

Y05

1

GND OUT

7

1

4 5

GND

V3_ 3

8

V3_3

D

C C

B B

A A

8

D

V3_3

1

2

FULLDSTRI<1>

3

1

4

SW30

SP3T

2
2

2.0K

RB341

1

AFCSTRI<1>

3

1

4

SW31

SP3T

2
2

2.0K

RB338

1

AFCS<1>

H10STRI<1>

V3_3

3

1

4

FULLDSTRI<2>

3

1

4

SW29

2
2

SP3T

SW35

SP3T

2

2.0K

RB340

2

AFCSTRI<2>

3

1

4

SW34

SP3T

2
2

H10STRI<2>

3

1

4

SW33

SP3T

2
2

09/16/2004

DATE:

1

8/8(BLOCK)

29/71(TOTAL)

PAGE:

1

2.0K

RB348

1

2.0K

RB347

1

2.0K

RB346

1

2

H10S<1>

FULLDS<1>

25B5<

25C8<

25C5<

FULLDS<2>

25A8<

AFCS<2>

25A5<

H10S<2>

25A5<

STEVE SCULLY

DS33Z11/41/44DK01A0

3

4

V3_3

FULLDSTRI<3>

3

1

4

SW38

SP3T

2

2.0K

RB353

FULLDS<3>

25C4<

AFCSTRI<3>

3

1

4

SW37

SP3T

2

2.0K

RB351

AFCS<3>

25C1<

H10STRI<3>

V3_3

3

1

4

FULLDSTRI<4>

3

1

4

SW36

2

SP3T

SW40

SP3T

2

2.0K

RB352

2

2.0K

RB363

1

AFCSTRI<4>

3

1

4

SW41

SP3T

2
2

2.0K

RB362

1

H10STRI<4>

3

1

4

SW39

SP3T

2
2

2.0K

RB361

1

29B6<23D4<23B4<

TITLE:

ENGINEER:

3

45

H10S<3>

AFCS<4>

25C1<

FULLDS<4>

25A1<

25A4<

H10S<4>

25A1<

56

V1_8ZCHIP

1UF

2

0.1UF

V3_3

MAX1792

2

2

2

8

OUT

IN

1

1

V1_8ZCHIP

1

29A 4<>

1

1

1

23D4< 23B4<

1

1

1

RED

2

1

DS45

7

RB344

330

RED

2

1

DS46

RB350

330

RED

2

1

DS47

RB354

330

RED

2

1

DS48

RB360

330

1

1

1

TP67

TP68

TP73

TP76

V3_3

1

1

1

1

1

QOVF<1>

8

25C5>

QOVF<2>

25A5>

QOVF<3>

25C1>

QOVF<4>

1

25A1>

1

2

CB368

0.1UF

2

CB380

0.1UF

2

CB261

0.1UF

2

CB366

0.1UF

2

CB231

0.1UF

2

CB367

0.1UF

2

CB248

0.1UF

2

CB228

0.1UF

2

CB254

0.1UF

2

CB15

0.1UF

2

CB279

0.1UF

2

CB411

0.1UF

2

CB439

0.1UF

2

CB241

0.1UF

2

CB358

0.1UF

2

CB185

0.1UF

2

C213

0.1UF

2

C214

U11

1

CB176

1UF

1

C80

1UF

1

C51

10UF

6

1

CB133

7

5

6

OUT

SET

GND

7

IN

SHDN

RST

3

4

2

1UF

1

1

1

2

2

CB184

1UF

2

CB13

1UF

2

8

C64

1UF

1

CB468

D

C C

B B

A A

D

1

1

1

AN_V3_3

1

1

L08

100O100MZH

2

1

2

1

1

1

1

V3_3

1

1

0.1UF

2

CB73

0.1UF

2

CB81

10UF

2

C25

10UF

2

CB10

10UF

CB87

10UF

CB292

0.1UF

2

CB40

0.1UF

2

CB72

0.1UF

2

C18

0.1UF

2

CB291

0.1UF

2

CB284

0.1UF

2

CB221

3

09/16/2004

DATE:

DS33Z11/41/44DK01A0

TITLE:

1

1/2(BLOCK)

30/71(TOTAL)

PAGE:

2

STEVE SCULLY

ENGINEER:

3

V3_3

4

LEDS NEED TO BE ATTACHED

OUTSIDE OF MODUL E DUE TO

STRAP ADAPTING OPTION OF DP83847

AN_EN

IO

IO

IO

IO

IO

26C 6^

IN

IO

AN1

JP12

3

3

3

1

2

JP07

1

2

JP01

1

2

31C8<

26D 8^

31C8<

31C8<

31C8<

V3_3

26D 8^

IN

26D 8^

26D 8^

IN

IN

IN

45

AN0

MDC

RB09

RB30

RB37

5.1K

5.1K

LED_TX_ADD3

MDIO

56

30

R10 1

24

25

LED_COL_ADD1

LED_DPLX_ADD0

22

23

LED_RX_ADD4

TP02

1

LED_GDLINK_ADD2

18

19

21

20

5.1K

15

16

17

J15

MDC

MDIO

V3_3

63

59

57

AN_V3_3

14

56

28

34

13

12

9

8

5

4

VDD3

VDD2

VDD1

LED_COL/PHYAD1

LED_DPLX/PHYAD0

LED_GDLNK/PHYAD2

LED_SPEED

LED_RX/PHYAD4

LED_TX/PHYAD3

VDD/ANA_VDD

VDD/IO_VDD2

VDD/IO_VDD1

RESERVED9

RESERVED8

U02

CONTROL

RESERVED7

RESERVED6

DP83847_U1

RESERVED5

RESERVED4

RESERVED3

7

AN_1

AN_0

AN_EN

GND5

65

GND4

64

GND3

62

GND2

60

GND1

58

RESERVED18

61

RESERVED17

55

RESERVED16

54

RESERVED15

53

RESERVED14

52

RESERVED13

51

RESERVED12

50

TXD2

TXD3

4

2

412

3

3

1

TX_CLK

OUT

31C5<

31C4<

26D 8^

26C 6^

OUT

OUT

RXDV

RX_CRS

4

2

412

65

6108

5

31B5<

26C 6^

OUT

COL_DET

65

6108

TXD0

TXD1

10

8

7

9

7

9

CONN_10P

TX_EN

IN

26C 6^

31C8<

26C 8^

31C6<>

OUT

OUT

RX_CLK

RX_ERR

10

8

6

7

3

7

5

X1

464248

X2C1RESET*

RESERVED11

RESERVED10

44

47

RESERVED1

RESERVED2

1

2

RBIAS

3

49

J16

3

1

9

7

9

CONN_10P

RBIAS

RXD0

RXD1

RXD2

MII_CLK

C1PIN

0.1UF

1

8

COMPONETS FOR

C1 AND RBIAS M UST

BE PLACED CLO SE TO PI N

10UF

1

R06

2

CB104

2

C41

D

RESET_B

10.0K

IN

IN

26C 6^

26C 7^

OUT

OUT

26D 6^

V3_3

31B8<

26D 6^

31B8<

C C

B B

RXD3

0.2 BETWEEN CONNECTO RS.

ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW

ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE

TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO

PLACEMENT NOTE:

OUT

OUT

26D 6^

26D 6^

31B8<

31B8<

A A

8

D

9

CHASSI S

1

J1

J2

J3

SH1

SYM_1

J01

2

P1

P4

P3

P2

J6

J4,5

P5

P6

10

CHASSI S

09/16/2004

SH2

J7,8

P8

DATE:

1

2/2(BLOCK)

31/71(TOTAL)

PAGE:

2

CONN_HFJ11_2450_U

1

4

.1U F

CB32

RD_P

RB22

RB23

54.9

3

2

RD_N

6

5

TD_P

TD_N

8

.1UF

CB299

CHASSI S

STEVE SCULLY

DS33Z11/41/44DK01A0

54.9

RB24

RB25

49.9

49.9

CAPS FOR XFRM CENTER TAP

SHOULD BE PLACED CLO SE TO PH Y

RESISTORS FOR TD+ -/ RD+-

SHOULD BE PLACED CLOSE TO XFRM

3

.1U F

CB60

V3_3

TITLE:

4

RX_CLK

TX_CLK

30

RB105

4

RB84

UX05

BUFFER

NC7SZ8 6_U

1

DNP

RB113

DNP

30

RB119

4

UX10

BUFFER

NC7SZ8 6_U

1

ENGINEER:

3

45

56

2

RB139

10K

RX_CRS

COL_DET

30

30

TD_P

RB127

RX_ERR

RXDV

32

31

33

RX_DV

RX_ER/PAUSE_EN*

36

TX_CLK

RX_CLK

RB135

43

45

COL

CRS/LED_CFG*

TD_N

6

11

10

TD+

TD-

PORT

7

U02

DP83847_U1

RXD<2>

RXD<0>

TX_ER

35

37

38

39

TXD<3>

TXD<2>

41

40

TXD<1>

TXD<0>

TX_EN

RXD<1>

293027

RXD<3>

26

RD-

RD+

7

6

7

303030

30

RB125

RB112

RB100

TX_EN

TXD0

TXD3

TXD1

TXD2

8

RXD0

D

C C

R106

8

RD_N

RXD1

RXD2

RD_P

RXD3

B B

A A

D

1

1

1

AN_V3_3

1

1

L06

100O100MZH

2

1

2

1

1

1

1

V3_3

1

1

0.1UF

2

CB57

0.1UF

2

CB46

10UF

2

C13

10UF

2

CB496

10UF

CB125

10UF

CB174

0.1UF

2

CB476

0.1UF

2

CB473

0.1UF

2

C209

0.1UF

2

CB88

0.1UF

2

CB91

0.1UF

2

CB209

3

09/16/2004

DATE:

DS33Z11/41/44DK01A0

TITLE:

1

1/2(BLOCK)

32/71(TOTAL)

PAGE:

2

STEVE SCULLY

ENGINEER:

3

V3_3

4

LEDS NEED TO BE ATTACHED

OUTSIDE OF MODUL E DUE TO

STRAP ADAPTING OPTION OF DP83847

AN_EN

IO

IO

IO

IO

IO

26C 3^

IN

IO

AN1

JP11

3

3

3

1

2

JP06

1

2

JP03

1

2

33C8<

26D 4^

33C8<

33C8<

33C8<

V3_3

26D 4^

IN

26D 4^

26D 4^

IN

IN

IN

45

AN0

MDC

RB16

RB3 1

RB38

5.1K

5.1K

LED_TX_ADD3

MDIO

56

30

R117

24

25

LED_COL_ADD1

LED_DPLX_ADD0

22

23

LED_RX_ADD4

TP04

1

LED_GDLINK_ADD2

18

19

21

20

5.1K

15

16

17

J19

MDC

MDIO

V3_3

63

59

57

AN_V3_3

14

56

28

34

13

12

9

8

5

4

VDD3

VDD2

VDD1

LED_COL/PHYAD1

LED_DPLX/PHYAD0

LED_GDLNK/PHYAD2

LED_SPEED

LED_RX/PHYAD4

LED_TX/PHYAD3

VDD/ANA_VDD

VDD/IO_VDD2

VDD/IO_VDD1

RESERVED9

RESERVED8

U05

CONTROL

RESERVED7

RESERVED6

DP83847_U1

RESERVED5

RESERVED4

RESERVED3

7

AN_1

AN_0

AN_EN

GND5

65

GND4

64

GND3

62

GND2

60

GND1

58

RESERVED18

61

RESERVED17

55

RESERVED16

54

RESERVED15

53

RESERVED14

52

RESERVED13

51

RESERVED12

50

TXD2

TXD3

4

2

412

3

3

1

TX_CLK

OUT

33C5<

33C4<

26D 4^

26C 2^

OUT

OUT

RXDV

RX_CRS

4

2

412

65

6108

5

33B5<

26C 2^

OUT

COL_DET

65

6108

TXD0

TXD1

10

8

7

9

7

9

CONN_10P

TX_EN

IN

26C 2^

33C8<

26C 4^

33C6<>

OUT

OUT

RX_CLK

RX_ERR

10

8

6

7

3

7

5

X1

464248

X2C1RESET*

RESERVED11

RESERVED10

44

47

RESERVED1

RESERVED2

1

2

RBIAS

3

49

J20

3

1

9

7

9

CONN_10P

RBIAS

RXD0

RXD1

RXD2

MII_CLK

C1PIN

0.1UF

1

8

COMPONETS FOR

C1 AND RBIAS M UST

BE PLACED CLO SE TO PI N

10UF

1

R05

2

CB103

2

C37

D

RESET_B

10.0K

IN

IN

26C 3^

26C 3^

OUT

OUT

26D 2^

V3_3

33B8<

26D 2^

33B8<

C C

B B

RXD3

0.2 BETWEEN CONNECTO RS.

ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW

ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE

TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO

PLACEMENT NOTE:

OUT

OUT

26D 2^

26D 2^

33B8<

33B8<

A A

8

D

9

CHASSI S

1

J1

J2

J3

SH1

SYM_1

J05

2

P1

P4

P3

P2

J6

J4,5

P5

P6

10

CHASSI S

09/16/2004

SH2

J7,8

P8

DATE:

1

2/2(BLOCK)

33/71(TOTAL)

PAGE:

2

CONN_HFJ11_2450_U

1

4

.1U F

CB25

RD_P

RB26

RB27

54.9

3

2

RD_N

6

5

TD_P

TD_N

8

.1UF

CB282

CHASSI S

STEVE SCULLY

DS33Z11/41/44DK01A0

54.9

RB28

RB29

49.9

49.9

CAPS FOR XFRM CENTER TAP

SHOULD BE PLACED CLO SE TO PH Y

RESISTORS FOR TD+ -/ RD+-

SHOULD BE PLACED CLOSE TO XFRM

3

.1U F

C05

V3_3

TITLE:

4

RX_CLK

TX_CLK

30

RB103

4

RB85

UX07

BUFFER

NC7SZ8 6_U

1

DNP

RB122

DNP

30

R28

4

UX02

BUFFER

NC7SZ8 6_U

1

ENGINEER:

3

45

56

2

RB132

10K

RX_CRS

COL_DET

30

30

TD_P

R21

RX_ERR

RXDV

32

31

33

RX_DV

RX_CLK

RX_ER/PAUSE_EN*

RB131

36

TX_CLK

43

45

COL

CRS/LED_CFG*

TD_N

6

11

10

TD+

TD-

PORT

7

U05

DP83847_U1

RXD<2>

RXD<0>

TX_ER

35

37

38

39

TXD<3>

TXD<2>

41

40

TXD<1>

TXD<0>

TX_EN

RXD<1>

293027

RXD<3>

26

RD-

RD+

7

6

7

303030

30

RB116

RB108

RB97

TX_EN

TXD0

TXD3

TXD1

TXD2

8

RXD0

D

C C

R27

8

RD_N

RXD1

RXD2

RD_P

RXD3

B B

A A

D

1

1

1

AN_V3_3

1

1

L05

100O100MZH

2

1

2

1

1

1

1

V3_3

1

1

0.1UF

2

CB51

0.1UF

2

CB38

10UF

2

C11

10UF

2

CB128

10UF

CB64

10UF

CB357

0.1UF

2

CB283

0.1UF

2

CB196

0.1UF

2

CB474

0.1UF

2

CB74

0.1UF

2

CB71

0.1UF

2

CB167

3

09/16/2004

DATE:

DS33Z11/41/44DK01A0

TITLE:

1

1/2(BLOCK)

34/71(TOTAL)

PAGE:

2

STEVE SCULLY

ENGINEER:

3

V3_3

4

LEDS NEED TO BE ATTACHED

OUTSIDE OF MODUL E DUE TO

STRAP ADAPTING OPTION OF DP83847

AN_EN

IO

IO

IO

IO

IO

27C 3^

IN

IO

AN1

JP13

3

3

3

1

2

JP08

1

2

JP04

1

2

35C8<

27D 4^

35C8<

35C8<

35C8<

V3_3

27D 4^

IN

27D 4^

27D 4^

IN

IN

IN

45

AN0

MDC

RB17

RB35

RB4 1

5.1K

5.1K

LED_TX_ADD3

MDIO

56

30

R102

24

25

LED_COL_ADD1

LED_DPLX_ADD0

22

23

LED_RX_ADD4

TP01

1

LED_GDLINK_ADD2

18

19

21

20

5.1K

15

16

17

J21

MDC

MDIO

V3_3

63

59

57

AN_V3_3

14

56

28

34

13

12

9

8

5

4

VDD3

VDD2

VDD1

LED_COL/PHYAD1

LED_DPLX/PHYAD0

LED_GDLNK/PHYAD2

LED_SPEED

LED_RX/PHYAD4

LED_TX/PHYAD3

VDD/ANA_VDD

VDD/IO_VDD2

VDD/IO_VDD1

RESERVED9

RESERVED8

U06

CONTROL

RESERVED7

RESERVED6

DP83847_U1

RESERVED5

RESERVED4

RESERVED3

7

AN_1

AN_0

AN_EN

GND5

65

GND4

64

GND3

62

GND2

60

GND1

58

RESERVED18

61

RESERVED17

55

RESERVED16

54

RESERVED15

53

RESERVED14

52

RESERVED13

51

RESERVED12

50

TXD2

TXD3

4

2

412

3

3

1

TX_CLK

OUT

35C5<

35C4<

27D 4^

27C 2^

OUT

OUT

RXDV

RX_CRS

4

2

412

65

6108

5

35B5<

27C 2^

OUT

COL_DET

65

6108

TXD0

TXD1

10

8

7

9

7

9

CONN_10P

TX_EN

IN

27C 2^

35C8<

27C 4^

35C6<>

OUT

OUT

RX_CLK

RX_ERR

10

8

6

7

3

7

5

X1

464248

X2C1RESET*

RESERVED11

RESERVED10

44

47

RESERVED1

RESERVED2

1

2

RBIAS

3

49

J22

3

1

9

7

9

CONN_10P

RBIAS

RXD0

RXD1

RXD2

MII_CLK

C1PIN

0.1UF

1

8

COMPONETS FOR

C1 AND RBIAS M UST

BE PLACED CLO SE TO PI N

10UF

1

R09

2

CB101

2

C35

D

RESET_B

10.0K

IN

IN

27C 3^

27C 3^

OUT

OUT

27D 2^

V3_3

35B8<

27D 2^

35B8<

C C

B B

RXD3

0.2 BETWEEN CONNECTO RS.

ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW

ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE

TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO

PLACEMENT NOTE:

OUT

OUT

27D 2^

27D 2^

35B8<

35B8<

A A

8

D

9

CHASSI S

1

J1

J2

J3

SH1

SYM_1

J03

2

P1

P4

P3

P2

J6

J4,5

P5

P6

10

CHASSI S

09/16/2004

SH2

J7,8

P8

DATE:

1

2/2(BLOCK)

35/71(TOTAL)

PAGE:

2

CONN_HFJ11_2450_U

1

4

.1U F

CB29

RD_P

RB19

RB18

54.9

3

2

RD_N

6

5

TD_P

TD_N

8

.1UF

C106

CHASSI S

STEVE SCULLY

DS33Z11/41/44DK01A0

54.9

RB20

RB2 1

49.9

49.9

CAPS FOR XFRM CENTER TAP

SHOULD BE PLACED CLO SE TO PH Y

RESISTORS FOR TD+ -/ RD+-

SHOULD BE PLACED CLOSE TO XFRM

3

.1U F

CB34

V3_3

TITLE:

4

RX_CLK

TX_CLK

30

RB104

4

RB86

UX08

BUFFER

NC7SZ8 6_U

1

DNP

RB120

DNP

30

RB115

4

UX09

BUFFER

NC7SZ8 6_U

1

ENGINEER:

3

45

56

2

RB140

10K

RX_CRS

COL_DET

30

30

TD_P

RB123

RX_ERR

RXDV

32

31

33

RX_DV

RX_ER/PAUSE_EN*

36

TX_CLK

RX_CLK

RB133

43

45

COL

CRS/LED_CFG*

TD_N

6

11

10

TD+

TD-

PORT

7

U06

DP83847_U1

RXD<2>

RXD<0>

TX_ER

35

37

38

39

TXD<3>

TXD<2>

41

40

TXD<1>

TXD<0>

TX_EN

RXD<1>

293027

RXD<3>

26

RD-

RD+

7

6

7

303030

30

RB137

R125

RB128

TX_EN

TXD0

TXD3

TXD1

TXD2

8

RXD0

D

C C

RB138

8

RD_N

RXD1

RXD2

RD_P

RXD3

B B

A A

D

1

1

1

AN_V3_3

1

1

L07

100O100MZH

2

1

2

1

1

1

1

V3_3

1

1

0.1UF

2

CB77

0.1UF

2

CB83

10UF

2

C31

10UF

2

CB164

10UF

CB470

10UF

CB20

0.1UF

2

CB76

0.1UF

2

C29

0.1UF

2

C24

0.1UF

2

C17

0.1UF

2

CB326

0.1UF

2

CB325

3

09/16/2004

DATE:

DS33Z11/41/44DK01A0

TITLE:

1

1/2(BLOCK)

36/71(TOTAL)

PAGE:

2

STEVE SCULLY

ENGINEER:

3

V3_3

4

LEDS NEED TO BE ATTACHED

OUTSIDE OF MODUL E DUE TO

STRAP ADAPTING OPTION OF DP83847

AN_EN

IO

IO

IO

IO

IO

27C 6^

IN

IO

AN1

JP10

3

3

3

1

2

JP05

1

2

JP02

1

2

37C8<

27D 8^

37C8<

37C8<

37C8<

V3_3

27D 8^

IN

27D 8^

27D 8^

IN

IN

IN

45

AN0

MDC

RB50

RB03

RB0 1

5.1K

5.1K

LED_TX_ADD3

MDIO

56

30

R26

24

25

LED_COL_ADD1

LED_DPLX_ADD0

22

23

LED_RX_ADD4

TP05

1

LED_GDLINK_ADD2

18

19

21

20

5.1K

15

16

17

J17

MDC

MDIO

V3_3

63

59

57

AN_V3_3

14

56

28

34

13

12

9

8

5

4

VDD3

VDD2

VDD1

LED_COL/PHYAD1

LED_DPLX/PHYAD0

LED_GDLNK/PHYAD2

LED_SPEED

LED_RX/PHYAD4

LED_TX/PHYAD3

VDD/ANA_VDD

VDD/IO_VDD2

VDD/IO_VDD1

RESERVED9

RESERVED8

U03

CONTROL

RESERVED7

RESERVED6

DP83847_U1

RESERVED5

RESERVED4

RESERVED3

7

AN_1

AN_0

AN_EN

GND5

65

GND4

64

GND3

62

GND2

60

GND1

58

RESERVED18

61

RESERVED17

55

RESERVED16

54

RESERVED15

53

RESERVED14

52

RESERVED13

51

RESERVED12

50

TXD2

TXD3

4

2

412

3

3

1

TX_CLK

OUT

37C5<

37C4<

27D 8^

27C 6^

OUT

OUT

RXDV

RX_CRS

4

2

412

65

6108

5

37B5<

27C 6^

OUT

COL_DET

65

6108

TXD0

TXD1

10

8

7

9

7

9

CONN_10P

TX_EN

IN

27C 6^

37C8<

27C 8^

37C6<>

OUT

OUT

RX_CLK

RX_ERR

10

8

6

7

3

7

5

X1

464248

X2C1RESET*

RESERVED11

RESERVED10

44

47

RESERVED1

RESERVED2

1

2

RBIAS

3

49

J18

3

1

9

7

9

CONN_10P

RBIAS

RXD0

RXD1

RXD2

MII_CLK

C1PIN

0.1UF

1

8

COMPONETS FOR

C1 AND RBIAS M UST

BE PLACED CLO SE TO PI N

10UF

1

R11

2

C28

2

C34

D

RESET_B

10.0K

IN

IN

27C 6^

27C 7^

OUT

OUT

27D 6^

V3_3

37B8<

27D 6^

37B8<

C C

B B

RXD3

0.2 BETWEEN CONNECTO RS.

ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW

ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE

TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO

PLACEMENT NOTE:

OUT

OUT

27D 6^

27D 6^

37B8<

37B8<

A A

8

D

9

CHASSI S

1

J1

J2

J3

SH1

SYM_1

J02

2

P1

P4

P3

P2

J6

J4,5

P5

P6

10

CHASSI S

09/16/2004

SH2

J7,8

P8

DATE:

1

2/2(BLOCK)

37/71(TOTAL)

PAGE:

2

CONN_HFJ11_2450_U

1

4

.1U F

C09

RD_P

RB10

RB1 1

54.9

3

2

RD_N

6

5

TD_P

TD_N

8

.1UF

C112

CHASSI S

STEVE SCULLY

DS33Z11/41/44DK01A0

54.9

RB12

RB13

49.9

49.9

CAPS FOR XFRM CENTER TAP

SHOULD BE PLACED CLO SE TO PH Y

RESISTORS FOR TD+ -/ RD+-

SHOULD BE PLACED CLOSE TO XFRM

3

.1U F

CB33

V3_3

TITLE:

4

RX_CLK

TX_CLK

30

RB99

4

RB8 1

UX06

BUFFER

NC7SZ8 6_U

1

DNP

RB111

DNP

30

RB117

4

UX01

BUFFER

NC7SZ8 6_U

1

ENGINEER:

3

45

56

2

RB141

10K

RX_CRS

COL_DET

30

30

TD_P

RB124

RX_ERR

RXDV

32

31

33

RX_DV

RX_ER/PAUSE_EN*

36

TX_CLK

RX_CLK

RB136

43

45

COL

CRS/LED_CFG*

TD_N

6

11

10

TD+

TD-

PORT

7

U03

DP83847_U1

RXD<2>

RXD<0>

TX_ER

35

37

38

39

TXD<3>

TXD<2>

41

40

TXD<1>

TXD<0>

TX_EN

RXD<1>

293027

RXD<3>

26

RD-

RD+

7

6

7

303030

30

RB114

RB107

RB96

TX_EN

TXD0

TXD3

TXD1

TXD2

8

RXD0

D

C C

RB130

8

RD_N

RXD1

RXD2

RD_P

RXD3

B B

A A

D

PA<22..0>

1

V3_3

.1UF

2

1

C87

0.0

2

1

2

RB159

VDDSYN

FLASH_VPP

VRH

3

TEA

TA

RCON

OE

RW

VDD1

9

VDD2

19

VDD3

33

VDD4

45

VDD5

65

VDD6

77

VDD7

129

VDD8

141

123

VDDH

103

VDDF

74

VDDA

115

VPP

87

VRL

112

VRH

113

92

102

99

97

95

59

VSTBY

TEA*

TA*

SHS*

OE*

RW

20

21

22

119

117

116

A22

A21

A20

VDDSYN

17

131

122

121

A19

A18

A17

PORT

MMC2107

14

15

16

132

A16

13

137

136

134

A15

A14

A13

10

11

12

11

139

6

A12

A11

A10

7

9

13

A9

6

8

14

24

23

A8

A7

A6

3

1

2

4

5

29

28

26

A5

A4

A3

0

50

49

47

A2

A1

A0

VSS1

8

VSS2

18

VSS3

32

VSS4

44

VSS5

64

VSS6

76

VSS7

127

VSS8

140

VSSSYN

126

VSSF

73

VSSA

D0

51

D1

48

D2

46

D3

43

D4

42

D5

41

D6

40

D7

39

D8

38

D9

37

D10

36

PD<31..0>

114

0

1

2

3

4

5

MMC2107

PROCESSOR RESOURCE CARD

6

7

8

9

10

09/16/2004

DATE:

DS33Z11/41/44DK01A0

TITLE:

1

1/7(BLOCK)

38/71(TOTAL)

PAGE:

2

STEVE SCULLY

ENGINEER:

3

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D19

I51

MMC2107

NA

TQFP

4

U19

D31

3

1

2

144

30

31

281927

29

7

5

4

25

26

15

12

10

22

23

24

D20

17

16

20

20

21

D17

D18

21

22

25

1618171918

D14

D15

D16

30

31

27

14

15

13

D11

D12

D13

34

35

45

11

12

RESET_B

V3_3

4

2

MAX811_U

VCC

RESET*

MR*

GND

3

1

56

TC1

TC2

CSE0

CSE1

CS1

CS3

CS0

CS2

RESET_B

SCK

CPUCLK_OUT

PROC_RESET_OUT

SS

I70

SOT143

2.93V

MAX811SEUS-T

UB01

ONCE_DE_B

118

128

120

60

CSE1

2107_TDO
ONCE_TDI

PQA0
PQA1
PQA3

PQA4
PQB0

PQB1
PQB2

7

PQB3

EB0
EB1

EB2
EB3

TIM_16H_8L

TDO

135

TDI

133

111

110

109

108

107

106

105

104

101

100

98

96

88

U19

CSE0

PQA0

PQA1

PQA3

PQA4

PQB0

PQB1

PQB2

PQB3

EB0*

EB1*

EB2*

EB3*

INT6*

ICOC23

ICOC22

53

52

81

TC1

TC2

CS3*

MMC2107

CONTROL

ICOC13

ICOC21

ICOC20

55

54

56

78

62

67

86

83

85

CS0*

CS1*

CS2*

ICOC12

ICOC11

58

57

ICOC10

RESET*

636166

CLKOUT

TXD2

TEST

143

93

94

3

SS*

DE*

SCK

RSTOUT*

RXD1

RXD2

TXD1

70

69

68

TMS

138

TRST*

142

TCLK

130

EXTAL

125

XTAL

124

MISO

91

MOSI

90

YC0

80

INT0*

71

INT1*

72

INT2*

75

INT3*

79

INT4

82

INT5*

84

INT7*

89

ONCE_TMS
ONCE_TRST_B
ONCE_TCLK
OSC_MCU
XTAL

MISO
MOSI

YCO

INT2

TIM_STATUS

RUN_KIT_USR
INT4
INT3

USER_LED2

USER_LED1

4

I64

SW07

1

2

6

7

8

TQFP

TEST

8

I69

MMC2107

NA

I68

ICOC10

ICOC11

ICOC12

ICOC13

ICOC20

ICOC21

ICOC22

ICOC23

D

C C

GND

SCI2_OUT

SCI1_IN

SCI1_OUT

SCI2_IN

B B

A A

D

V3_3

2

I65

DS17

1

1

AMBER

30

RB118

.1UF

2

1

09/16/2004

DATE:

1

2/7(BLOCK)

39/71(TOTAL)

PAGE:

CB149

1.0K

V3_3

2

FLASH_VPP

1

RB126

16

15

2

SWITCH

8 POS

I69

SW22

1

2

12

11

14

13

ECJ-2VB1C104K

0L_SMT0805_10PCT

3

4

10

9

2

7

6

5

8

RESET AND CHIP CONFIGURATION

STEVE SCULLY

DS33Z11/41/44DK01A0

PD<23..16>

BIS0OBSXI

BIS1OBSXI

BTS_OBSXI

V5_0

3

INT3

INT5

USERFPGA2

INT4

1.0K

1

V3_3

1

4

2

2

RB143

1.0K

R251

1.0K

R250

1.0K

1

2

2

2

1

2

RB147

1.0K

1

RB157

2

RB150

1.0K

1

R244

1.0K

V3_3

1

CY62128V

16

CS0

22

30

OE

24

EB1

29

1

32

I18

NA

CY62128V

U14

22

23

19

18

IO6

IO7

GND

CE1*

CE2

OE*

WE*

N_C

CY62128V

VCC

A16

A15

A14

9

12

25

16

17

15

19

20

14

15

21

IO3

IO4

IO5

A13

A12

A11

10

11

26

12

13

14

16

17

18

17

13

20

IO1

IO2

IO0

A0

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A10

A9

A8

31

27

28

10

11

9

1

23

2

3

4

5

6

7

8

PA<17..1>PA<17..1>

TITLE:

ENGINEER:

3

45

56

1

10K

R153

2

RCON

V3_3

D18 HAS A 10.5K LOAD TO V3V

D18 HAS A 10K LOAD TO GND

BOOT EXT

BOOT INTERNAL

WHEN SET FOR

6

PD<31..24>

1

2

2

2

2

RESET CONFIGURATION

10K

10K

10K

10K

10K

R93

RB300

RB238

RB301

RB263

R92

1

1

2

7

PD<17>

PD<26>

1

1

PD<23>

PD<21>

PD<16>

2

2

2

1

RB264

10K

10K

R127

1

1

PD<28>

PD<22>

PD<19>

2

10K

RB237

10K

1

16

CS0

22

PD<18>

30

OE

24

EB0

29

1

V3_3

32

30

31

19

21

IO6

IO7

GND

CE1*

CE2

OE*

WE*

N_C

CY62128V

VCC

27

28

29

18

15

17

IO3

IO4

IO5

242125

26

14

13

20

IO1

IO2

IO0

A0

A1

A2

A3

A4

9

A5

8

A6

7

A7

6

1

23

2

12

3

11

4

10

7

5

6

7

8

A16

A15

A14

A13

A12

A11

A10

A9

I54

NA

CY62128V

CY62128V

INTERNAL

MASTER MODE

8

D

FULL DRIVE

XTAL W/ PLL

FLASH ENABLE

C C

INTERN/EXTERN

BOOT

B B

UB05

3

2

5

25

16

15

17

4

28

26

13

14

11

12

A8

31

27

10

9

A A

8

D

1

10K

1

2

10K

2

R118

1

R108

09/16/2004

1

3/7(BLOCK)

40/71(TOTAL)

DATE:

VDDSYN

ONCE_TMS

ALIGN KEY

ONCE_DE_B

ONCE_TRST_B

10

12

8

6

4142

I1

NA

CON14P

CON14P

J41

2

V3_3

3

CON14P

3

1

7

9

5

13

11

V3_3

10K

1

R91

2

2107_TDO

ONCE_TCLK

ONCE_TDI

RESET_B

V3_3

I11

U09

MAX1675

1

3

1

OUT FB

8

68UF

4

2

LBI

REF

LBO*

LX

GND

SHDN

7

5

6

2

C36

.1UF

1

2

CB148

C104

2

68UF

1

SMT1206_5PCT

ERJ-8GEYJ5R6V

R107

22.0UH

2

1

L09

I13

1UF

1

2

CB199

1UF

2

1

CB484

1UF

2

1

CB466

1UF

2

1

CB262

1UF

1

2

TITLE:

CB35

1UF

5.6

2

1

C84

1UF

1

2

C83

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

1UF

2

4

330

2

1

2

R78

1

C91

45

1UF

1

C118

1UF

2

1

C39

10UF

2

1

CB114

56

1

2

10UF

JTAG CONFIGURATION

...FPGA+FLASH...

TDI

PIN

ONCETDO

C47

MMC2107

XTAL

OSC_MCU

V5_0

1UF

2

1

PIN

ONCETDI

C43

6

BUT DO NOT POPULATE

PLACE PADS FOR CAP

1.0M

1

7

I47

8.0MHZ

X02

8

2

R90

11

12

13

14

15

16

17

18

19

20

V-

C2-

C2+

C1-

C1+

V+2

GND

R2IN

T2OUT

1

2

MAX3233E

I31

NA

MAX3233E

MAX3233E

UB07

V3_3

INVALID*

T2IN

R2OUT

1

2

T1IN

3

4

5

T1OUT

R1OUT

FORCEON

6

R1IN

7

8

V+1

VCC

FORCEOFF*

9

10

V3_3

10K

2

1

RB200

10K

1

1

2

RB286

7

6

F

B

J36

A

1

2

I35

10K

9

8

H

J

G

D

E

C

3

5

4

2

7

CONN_DB9P

RB287

PRT1_IN

PRT1_OUT

8

SCI1_OUT

D

C C

B B

PRT1_IN

SCI1_IN

PRT1_OUT

A A

D

RED

1

RED

RED

09/16/2004

1

4/7(BLOCK)

41/71(TOTAL)

DATE:

2

RED

DS27

1

1

330

2

RB193

2

2

1

RED

DS37

2

330

R194

1

2

DS40

1

RED

1

330

R195

2

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

V3_3

3

1

TITLE:

ENGINEER:

3

330

TIM_INTERUPT_IND

USER_LED1

USER_LED2

1

2

2

RB146

DS19

GREEN

CFG_DIN

PA<16..0>

7

8

4

L15

K13

C5

56

L16

D5

E10

SCI2_OUT

F12

SCI2_IN

E6

J13

H14

E7

A8

D8

IO22_1

IO21_1

IO20_1

IO19_1

IO18_1

IO17_1

IO16_1

IO15_1

IO14_1

IO13_1

IO12_1

IO11_1

IO10_1

B9

B5

TEA

A7

TA

F14

EB1

A14

EB0

C11

CS2

D6

CS1

C13

CS0

B13

RW

C9

OE

7

IO8_1

IO7_1

IO6_1

IO5_1

IO3_1

GCK2

TIM_INTERUPT

H16

H15

IO2_2\VREF

IO2_1\IRDY

BANK 1

IO9_1\VREF

IO4_1\VREF

IO2_1\WRITE*

IO1_1\CS*

PROC_RESET_OUT

H13

G16

R16

F15

IO5_2

IO4_2

IO3_2\D3

IO6_2\D2

L13

E16

P16

F13

D7

D14

IO9_2

IO8_2

IO7_2\D1

IO11_2

IO10_2\VREF

IO12_2\(DIN,D0)

BANK 2

U16

XC2S50_BGA

BANK 0

15

14

12

C15

A10

A11

C12

F16

E15

IO18_2

IO17_2

IO16_2

IO15_2

IO14_2

IO13_2\(DOUT,BUSY)

9

11

10

A13

C16

D16

IO21_2

IO20_2

IO19_2

BANK 3

6

B12

C8

D9

IO24_2

IO23_2

IO22_2

IO23_3

IO22_3

IO21_3

IO20_3

IO19_3

IO18_3

IO17_3

IO16_3

IO15_3

IO14_3

IO13_3\TRDY

IO12_3

IO11_3\D4

IO10_3\VREF

IO9_3

IO8_3\D5

IO7_3\D6

IO6_3

IO5_3

C7

IO4_3\VREF

IO3_3

C6

IO2_3\D7

IO1_3\INIT*

5

D10

4

G14

3

D11

2

B16

1

A12

0

E11

M15

M14

G12

T15

J15

K15

J16

K16

K14

M16

N16

16

C10

17

L14

18

19

N14

N15

45

6

7

IO4_0

IO3_0

IO2_0\VREF

IO1_0

GCK3

B8

B7

L12

K12

3

5

4

SPARE_B<5..0>

3

65

6108

5

1

2

10

8

7

9

7

9

CONN_10P

C C

5134

4

2

4

2

8

J25

D

3

1

3

1

2

IO5_0

B6

M13

J14

1

IO8_0

IO7_0\VREF

IO6_0

B4

G13

IO11_0

IO10_0

IO9_0

A9

E14

D12

30

31

29

B B

IO14_0

IO13_0

IO12_0

A3

B10

E13

28

27

26

IO15_0

G15

251624

IO17_0

IO16_0

A5

B11

23

IO20_0

IO19_0

IO18_0

A4

A6

B3

22

21

20

A A

X_INIT

PD<31..16>

8

D

1

09/16/2004

1

5/7(BLOCK)

42/71(TOTAL)

DATE:

2

PAGE:

2

BUS MODE

DETECTION (DUT AT CS_X2)

XD<7..0>XD<7..0>

3

7

6

5

4

3

CS_X2

CS_X1

WR

BIS1_DUT

BTS_DUT

WR_DUT

ALE_DUT

RD_DUT

BIS0_DUT

RW_X

1

2

0

RW ALSO FUNCTIONS AS ALT_RD_DS

WE ALSO FUNCTIONS AS ALT_WR_RW

DS33Z11/41/44DK01A0

TITLE:

STEVE SCULLY

ENGINEER:

3

L4

H1

J3

J1

J2

IO2_6

IO3_6

IO1_6\TRDY

4

0

1

2

3

4

5

D_DUT<7..0>

6

7

M4

R7

L3

C2

N9

F1

P11

M6

N5

R13

CPUCLK_OUT

56

1

2

3

4

5

6

7

8

9

N11

P8

P13

F2

T14

P12

T11

T4

E4

R8

IO19_5

IO18_5

IO17_5

IO16_5

IO15_5

IO14_5

IO13_5

IO12_5

IO11_5

IO10_5

IO9_5

IO8_5\VREF

IO7_5

IO6_5

IO5_5

IO4_5

IO3_5

IO2_5\VREF

IO1_5

GCK1

IO4_6\VREF

BANK 5

K1

P5

M3

M11

P6

IO5_6

IO6_6

IO7_6

IO8_6

IO9_6

I46

U16

L1

N6

R1

N1

IO11_6

IO12_6

IO13_6

IO14_6

IO10_6\VREF

F5

F4

G2

IO15_6

IO16_6

IO17_6

BANK 6

XC2S50_BGA

BANK 4

H2

G5

IO18_6

K3

G4

IO19_6

P7

T8

IO23_6

IO22_6

IO21_6

IO20_6

IO23_7

IO22_7

IO21_7

IO20_7

IO19_7

IO18_7

IO17_7

IO16_7

IO15_7

IO14_7

IO13_7

IO12_7\IRDY

BANK 7

IO11_7

IO10_7

IO9_7\VREF

IO8_7

IO7_7

IO6_7

IO5_7

IO4_7

IO3_7\VREF

IO2_7

IO1_7

CS_X3

N7

CS_X4

M7

CS_X5

L5

CS_X6

K5

R12

ALE

J4

E2

F3

D2

E3

A2

G1

K2

H3

G3

K4

E1

D1

C1

T9

0

1

2

3

4

M10

5

6

7

8

9

10

R11

11

USERFPGA2

P10

INT5

45

A_DUT<11..0>

6

SPARE_A<10..1>

IO2_4

IO3_4\VREF

IO1_4

GCK0

H4

N8

10

3

65

6108

5

8

1

2

10

8

7

9

7

9

7

6

CONN_10P

5

7

I34

CONN_THRU-HOLENANA

J26

8

4

4

2

412

3

3

1

10

9

P9

R9

IO5_4

IO4_4

R6

T7

T10

10

11

IO8_4

IO7_4

IO6_4

R5

M2

8

9

IO10_4

IO9_4\VREF

T6

T12

7

6

XA<11..0>

IO13_4

IO12_4

IO11_4

M1

T5

N2

3

4

5

IO16_4

IO15_4

IO14_4

P1

T3

T2

R10

1

0

2

IO19_4

IO18_4

IO17_4

T13

N12

IO22_4

IO21_4

IO20_4

L2

B1

N10

7

8

D

C C

B B

A A

D

44B1<43A7<

1

21C 5^

09/16/2004

1

6/7(BLOCK)

43/71(TOTAL)

21C 7^

21C 7^

21C 7^

43C 6<>

43C 6<>42A6<>

43C 6<>

39C3<>38A7<>

39D3<>38A7<>

39C3<>

INT4

INT5

INT3

2

INT2

INININ

40C 3<>

21C 7^

38B5<>

43C 6<>

38A4>

38A7<>

OUT

RESET_ B

IN

21B 6^

21B 7^

21B 7^

21B 7^

44A 6<>

OUT

42C 3<>

42C 3<>

42C 3<>

TDO _NU

TCK _NU

BTS _DU T

BIS1_D UT

BIS0_D UT

IN

IN

IN

21C 5^

21C 5^

21C 5^

21C 5^

21C 5^

21B 6^

43B 6<>42A4<>

43B 6<>42B3<>

43B 6<>42B3<>

43B 6<>42A4<>

43B 6<>42A4<>

21B 6^

21B 6^

44A 6<>

44A 6<>

44A 6<>

TMS _NU

TDI _NU

CS_X4

INININ

OUT

OUT

OUT

OUT

OUT

CS_X3

CS_X2

CS_X1

CS_X5

WR

43C 643B 742A6

21B 5^

21B 7^

21B 5^

43A 6<>42C3<>

43A 6<>42C3<>

21B 5^

42B 3<>

21B 7^

42B 3<>

IO

OUT

OUT

RW_X

WR_ DUT

IO

OUT

OUT

OUT

OUT

RD_ DUT

DATE:

PAGE:

2

STEVE SCULLY

XD<7..0>

XA<15..0>

D_DUT<7..0>

A_DUT<11..0>

21B 5^

3

42B 7

DS33Z11/41/44DK01A0

TITLE:

ENGINEER:

3

10K

2

1

R247

10K

4

2

V3_3

2

1

45

R245

10K

1

R246

10K

2

1

R249

56

INT4

INT2

INT5

INT3

A_DUT<11..0>

D_DUT< 7.. 0>

CS_X1

CS_X6

9

11

2

A11

MBVER

J27

CONN_50P_T1E1

GND1

1

8

10

12

14

10

6

4

8

A9

A8

A10

GND3

GND2

3

5

INT5

GND4

USER1

7

9

16

INT2

INT3

INT4

USER3

USER4

USER2

11

15

13

CS_X5

18

22

20

CS1

CS6

CS5

USER6

USER5

USER7

17

19

21

CS_X2

CS_X3

CS_X4

24

CS4

USER8

23

7

6

30

28

CS2

USER10

272529

32

AD6

AD7

USER12

USER11

31

26

CS3

USER9

3

5

34

AD5

USER13

33

2

4

36

38

40

AD3

AD4

AD2

USER14

USER15

USER16

39

37

35

7

3

1

0

4

2

7

6

5

WR_ DUT

1

42

AD1

3.3V1

41

RD_ DUT

0

44

AD0

3.3V2

43

ALE _DU T

50

46

48

RD

WR

ALE

5V2

5V1

USER17

45

47

49

6

7

A_DUT<11..0>

SCK

SS

MISO

MOSI

RESET_B

V3_3

8

D

C C

B B

A A

8

D

V3_3

DONE

1

XI_TMS

ONCE_TCLK

R238

JTD_SPART2FLASH

JTD_SPART_TDI

CCLK

2

RESET_B

330

1

09/16/2004

DATE:

1

7/7(BLOCK)

44/71(TOTAL)

PAGE:

U16

XRST

D15

R14

N3

P2

R3

R4

P15

M2

M1

M0

DONE

CCLK

PROGRAM*

CONTROL

XC2S50_BGA

P4

NC1

NC2

GND36

T16

GND35

T1

GND34

R15

GND33

R2

GND32

L11

GND31

L10

GND30

L7

GND29

L6

GND28

K11

GND27

K10

GND26

K9

GND25

K8

GND24

K7

GND23

K6

GND22

V3_3

.1UF

2

1

CB78

.1UF

1

2

CB373

.1UF

2

1

CB409

.1UF

2

1

CB378

.1UF

1

2

CB353

.1UF

2

1

CB375

.1UF

2

1

CB352

.1UF

1

2

CB372

1UF

2

2

1

CB195

1UF

1

CB270

J10

GND21

J9

GND20

J8

GND19

J7

GND18

H10

GND17

H9

GND16

H8

GND15

H7

GND14

G11

GND13

G10

GND12

G9

GND11

G8

GND10

G7

GND9

G6

GND8

F11

GND7

F10

GND6

F7

GND5

F6

GND4

B15

GND3

B2

GND2

A16

GND1

A1

DS33Z11/41/44DK01A0

TITLE:

2

STEVE SCULLY

ENGINEER:

3

45

D3

A15

C4

B14

TDO

TCK

TDI

TMS

2

1UF

1

2

CB489

1UF

V2_5XI

1

2

CB187

1UF

1

2

CB171

3

P14

P3

N13

N4

M12

M5

E12

E5

D13

D4

4

C14

C3

VCCINT12

VCCINT11

VCCINT10

VCCINT9

VCCINT8

VCCINT7

VCCINT6

VCCINT5

VCCINT4

VCCINT3

VCCINT2

VCCINT1

UB11

MAX1792

V3_3

8

OUT

IN

1

10UF

1

2

CB157

7

5

6

OUT

SET

GND

IN

SHDN

RST

3

2

1UF

4

1

1

2

2

2

CB316

1UF

2

CB457

1UF

1

CB295

1UF

1

CB100

56

VCCO3

VCCO2

VCCO1

E8

F8

V3_3 V3_3

VCCO5

VCCO4

F9

E9

H12

H11

JTD_FLASH_TDO

18

19

20

7

VCCJ

VCCO

16

17

DNC3

VCCINT

TDO

VCCO8

VCCO10

VCCO9

VCCO7

VCCO6

L9

L8

J11

15

14

DNC5

DNC4

M9

J12

13

12

11

GND

DNC6

CEO*

VCCO13

VCCO12

VCCO11

M8

J5

VCCO16

VCCO15

VCCO14

H5

H6

J6

6

V3_3

TMS _NU

TDO _NU

TDI _NU

TCK _NU

10

65

4

2

J43

10K

V3_3

1

2

1

8

6108

412

3

7

5

9

3

7

9

7

CONN_10P

R89

U12

1

CLKD0DNC1

3

2

4

TCK

TMS

TDI

5

CF*

7

6

8

CE*

OE/RST*

DNC2

9

XILINX_XCF01S

10

XI_TMS

ONCE_TCLK

JTD_SPART_TDI

JTD_FLASH_TDO

X_INIT

2

8

CFG_DIN

CCLK

XI_TMS

ONCE_TCLK

10K

XRST

RB364

DONE

1

8

JTD_SPART2FLASH

V2_5XI

D

C C

B B

A A

D

1

46B7<

55A455A254C3

55A755A554C7

I41

IO

IN

2

ADDR<9..0>

3

1

2

0

H3

H2

E10

G4

6

5

4

N7

B9

879

H6

T7

G2

DAT<7..0>

3

1

0

J11

P8

D10

4

2

N8

P7

M7

7

6

5

R7

G1

G3

51C7<

MUX

BTS

B10

R8

51C7<

51C7<

51B7<

51C7<

ESIBR0

ESIBRD

ESIBR1

H8

J8

J9

RESET_AH

4

NC7SZ86

NA

INVERT ER

NC7SZ8 6_U

UXB05

1

RESET_B

52B1< 5 5D6<>

09/16/2004

DATE:

1

46/71(TOTAL)

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

MUX

A<0>

3

A<3>

A<2>

A<1>

A<7>/ALE_AS

AD<0>

AD<3>

AD<2>

AD<1>

AD<6>

AD<5>

AD<4>

A<9>

A<8>

A<6>

A<5>

A<4>

BTS

AD<7>

ESIBRD

ESIBS<1>

ESIBS<0>

NC3

E9

NC2

P3

NC1

K9

TITLE:

ENGINEER:

3

L16
L15
F2
F1
B11
A11
T6

4

R6

T8
A9
J16
H1

N14
M14
L14
F3

56

E3
D3
C13

V3_3

C12
C11
P6
P5
P4

TVDD42

TVDD41

TVDD32

TVDD31

TVDD22

TVDD21

TVDD12

TVDD11

RVDD4

RVDD3

RVDD2

RVDD1

DVDD43

DVDD42

DVDD41

DVDD33

DVDD32

DVDD31

DVDD23

DVDD22

DVDD21

V3_3

DVDD13

DVDD12

DVDD11

10UF

CB112

10UF

CB340

10UF

CB151

10UF

C103

10UF

CB154

10UF

CB126

10UF

CB236

10UF

C48

10UF

C42

V3_3

V3_3

0.1UF

1

1

2

2

2

CB220

0.1UF

2

CB200

0.1UF

1

CB127

0.1UF

1

CB155

U20

CONTROL

DS21458_U

0.1UF

2

1

1

2

1

1

1

1

1

1

CB205

0.1UF

2

CB138

0.1UF

2

CB204

0.1UF

1

CB120

0.1UF

2

CB156

0.1UF

2

CB160

0.1UF

2

CB161

0.1UF

2

CB144

0.1UF

2

CB179

DS21458 WAN INTERFACE BLOCK

TVSS42

TVSS41

TVSS32

TVSS31

TVSS22

TVSS21

TVSS12

TVSS11

RVSS43

RVSS42

RVSS41

RVSS33

RVSS32

RVSS31

RVSS23

RVSS22

RVSS21

RVSS13

RVSS12

RVSS11

DVSS43

DVSS42

DVSS41

DVSS33

DVSS32

DVSS31

M16

M15
E2
E1

B12

A12
T5
R5

45

55D5>46C7>

T9

T13

T12
A4
A8

WAN_INT

A5

D16

H16

E16

I37

NA

M1
J1

NC7SZ86

11

NC7SZ8 6_U

BUFFER

UX11

4

N1

N13

M13

I38

L13
F4
E4
D4

2

DS25

RED

2

R114

330

6

1

INT*

JTCLK

JTDI

JTMS

JTRST

K14

J15

53B6<>

46C7<

7

MCLK

MCLK2FPGA

30

30

RB184

V3_3

RB160

XI_TMS

52C1< 52 C8<> 52A 7<>

JTDO

K13

K16

C10

ONCE_TCLK

JTDO458

JTD_FLASH_TDO

52A7<>

52C6<>

52C1< 52 C8<> 52A 7<>

LIUC

MCLK1

MCLK2

H9

H4

H5

D9

J12

WAN_INT

LIUC

MCLK

OUT

51D7<

46D7<

55D5> 4 6A4<>

RPOSI

TEST1

TEST2

TSTRST

CS*

RD*

WR*

DVSS11

DVSS12

DVSS13

DVSS21

DVSS22

RCLKI

RNEGI

G8

H10

J13

J14

M8

K15

C9

A10

WR

CS

RD

IN

IN

IN

N6

N5

N4

RESET_AH

55A4<

IN

55A3<> 54C7<>

55A2<> 54C7<>

46A1<>

DVSS23

D13

D12

D11

V3_3

BLOCK NAME: _quadte1wan_dn. PARENT BLOCK: \_wan4z44_dn\

7

8

VCC

I73

2.048MHZ_3.3V

8

OSC

YB02

1

GND OUT

8

1/10(BLOCK)

1

4 5

D

C C

B B

A A

D

1

09/16/2004

1

2/10(BLOCK)

47/71(TOTAL)

DATE:

53A 2<>

49B5<

49C5<

TRING2

TTIP2

IN

TCLK2

53B 2<>

IN

TSER2

TSYNC2

53D7<

53D 4<>

53D 4<>

TSYSCLK2

TSSYNC2

2

A13

B13

TTIPA

TRINGA

TRINGB

A15

G12

TCLK

TTIPB

TCLKO

B15

F11

F12

TCLKI

TLINK

TNEGO

F13

A16

E12

TNEGI

TPOSO

TPOSI

E13

C16

E11

G9

TSER

TSIG

TCHBLK

B16

D15

TSYNC

TLCLK

TCHCLK

B14

A14

H13

D14

J10

BPCLK

TSSYNC

TSYSCLK

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

PORT

U20

3

DS21458_U

RLCLK

RCHCLK

RCLKO

RTIP

RRING

RCLK

RLINK

RPOSO

RNEGO

RCHBLK

RSIG

RSER

RSYNC

RSYSCLK

RSIGF

RMSYNC

RLOS/LOTC

RFSYNC

TITLE:

ENGINEER:

3

H12

H11

C15

PORT2_RRING = PIN F16

F16

RRING2

49A5<

F10

G16

RTIP2

49A5<

C14

RCLK2

OUT

4

53B 7<>

H14

G15

G10

G11

F15

RSER2

OUT

53A 7<>

53C2<

RGAPCLK2 TGAPCLK2

IN IO

53B 7<> 53A 2<>

H15

E14

G13

RSYNC2

RSYSCLK2

53D7<

53D 5<>

E15

F14

G14

RLOS2

51A 6<>

45

56

53B 2<>

49D8<

49D8<

TRING1

TTIP1

IN

TCLK1

53B 2<>

IN

TSER1

53D7<

53D 5<>

53D 4<>

TSYNC1

53C 6<>

BPCLK1

TSYSCLK1

TSSYNC1

6

L7

T4

T3

T2

TCLK

TTIPB

TTIPA

TRINGA

TRINGB

TCLKO

T1

TCLKI

TLINK

TNEGO

K7

L6

L5

R3

R4

L4

R2

M5

TNEGI

TPOSO

TPOSI

N2

P1

M6

TSER

J7

TSIG

TLCLK

TCHCLK

TCHBLK

H7

N3

TSYNC

J5

M4

BPCLK

TSSYNC

TSYSCLK

PORT

U20

7

DS21458_U

7

RLCLK

RCHCLK

RCLKO

RTIP

RRING

L1

K1

RCLK

K8

R1

RLINK

J2

P2

RPOSO

RNEGO

J6

RCHBLK

RSIG

RSER

K2

K3

J4

L2

RSYNC

RSYSCLK

RSIGF

RMSYNC

K6

M2

J3

M3

RLOS/LOTC

RFSYNC

K5

L3

K4

RCLK1

RTIP1

RRING1

PORT1_RRING = PIN L1

49C8<

49C8<

OUT

8

53B 7<>

D

C C

RSER1

OUT

53A 7<>

53C2<

RGAPCLK1 TGAPCLK1

RSYNC1

RSYSCLK1

IN IO

53D7<

53D 5<>

53B 7<> 53A 2<>

B B

RLOS1

51A 6<>

8

A A

D

1

53A 2<>

50B5<

50C5<

TRING4

TTIP4

P15

N15

N16

IN

TCLK4

L9

P16

L12

L11

R16

R15

M12

T16

53B 2<>

IN

IO

53C7<

53D 4<>

53D 4<>

TSER4

TSYSCLK4

TSSYNC4

TSYNC4TSYNC3

K10

L10

K11

R13

T14

P13

L8

R14

M11

N9

09/16/2004

DATE:

2

TCLK

TCLKI

TLINK

TNEGO

TTIPA

TRINGB

TRINGA

TCLKO

TTIPB

TNEGI

TSER

TPOSO

TSIG

TPOSI

TCHBLK

TSYNC

TLCLK

TCHCLK

BPCLK

TSSYNC

TSYSCLK

PORT

1

3/10(BLOCK)

48/71(TOTAL)

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

U20

DS21458_U

RPOSO

RRING

RTIP

RCLKO

RCLK

RLINK

RNEGO

RSER

RCHCLK

RCHBLK

RSIG

RMSYNC

RSYNC

RLCLK

3

T11

K12

T10

P14

P10

T15

P9

N10

M9

R10

R11

R12

N12

M10

RFSYNC

RSYSCLK

RSIGF

RLOS/LOTC

R9

P12

N11

P11

TITLE:

ENGINEER:

3

RTIP4

PORT4_RRING = PIN T11

RRING4

50A5<

RCLK4

50A5<

OUT

53B 7<>

RSER4

OUT

53A 7<>

RGAPCLK4 TGAPCLK4

IN

53B 7<> 53A 2<>

4

53C2<

RSYSCLK4

RSYNC4

53D7<

53D 4<>

RLOS4

51A 6<>

45

56

53A 2<>

50D8<

50D8<

IN

53B 2<>

53C7<

IN

IO

53D 4<>

53D 4<>

TCLK3

TTIP3

TRING3

C2

C1

D1

D2

B2

F6

F7

E5

A1

G7

TSER3RSER3

C5

F5

G6

D5

B1

C4

B4

TSYSCLK3

TSSYNC3

A3

D8

B3

E8

6

TCLK

TTIPB

TTIPA

TRINGA

TRINGB

TCLKI

TLINK

TNEGO

TCLKO

TNEGI

TSER

TPOSO

TSIG

TPOSI

TCHBLK

TSYNC

TLCLK

TCHCLK

BPCLK

TSSYNC

TSYSCLK

PORT

U20

DS21458_U

RLCLK

RCHCLK

RCLKO

RTIP

7

RRING

A6

A7

RTIP3

RRING3

PORT3_RRING = PIN A6

50C8<

RCLK

G5

RCLK3

50C8<

OUT

RLINK

F8

C3

A2

RPOSO

RNEGO

C8

F9

RCHBLK

RSIG

RSER

B7

C7

D7

RGAPCLK3 TGAPCLK3

OUT

RSYNC

RSYSCLK

RSIGF

RMSYNC

RLOS/LOTC

RFSYNC

7

B6

IN

B8

B5

E6

RSYSCLK3

RSYNC3

53D7<

53D 4<>

D6

E7

C6

RLOS3

51A 6<>

53B 7<>

8

D

C C

53A 7<>

53C2<

53B 7<> 53A 2<>

8

B B

A A

D

1

09/16/2004

1

4/10(BLOCK)

49/71(TOTAL)

DATE:

2

A3

A5

A7

7

5

JB12

I25

RJ45_4PORT

A8

3

6

8

A6

4

A4

A1

3

1

2

RJ45

A2

TITLE:

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

18

23

24

25

XMIT

16

L10

I2

17

1

1UF

C173

2

4

56

2

2

R204

0

R203

1

TTIP2

47C2>

0

1

TRING2

47C2>

19

20

I26

RCV

22
2

RB322

0

1

L10

21
2

RB321

0

1

RB312

1

61.9

2

0.1UF

45

2

RB313

1

61.9

RRING2

RTIP2

47C4<

47C4<

1

2

CB390

6

C7

C5

7

5

JB12

I13

RJ45_4PORT

C8

33

34

7

35

XMIT

6

L10

7

I11

6

8

C6

4

C4

C1

C3

3

1

2

RJ45

C2

10

8

9

I14

RCV

32
2

L10

31
2

7

1

RB327

RB328

0

0

1

1UF

C176

2

2

2

8

R208

0

R207

1

0

1

1

RB316

1

61.9

2

0.1UF

2

CB395

1

RB317

61.9

1

2

8

THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28- 30 AND 23-25

AS THE TX PRI MARY. THIS HAS BEEN CORR ECTED IN THE SCHEMATIC,

RRING1

TTIP1

TRING1

D

RTIP1

C C

B B

A A

THE PC B / ASS EMBLY HAS BE EN MODIFIED TO ACCOMMODATE THIS.

D

1

09/16/2004

1

5/10(BLOCK)

50/71(TOTAL)

DATE:

2

B7

B5

7

5

JB12

I8

RJ45_4PORT

B8

3

30

28

29

XMIT

11

L10

I7

12

6

8

B6

4

B4

1

1UF

C174

2

2

4

R206

2

0

R205

1

0

1

B1

B3

3

1

2

RJ45

B2

TITLE:

13

15

14

I9

RCV

27
2

RB324

0

1

L10

26
2

RB323

0

1

RB314

RB315

2

2

0.1UF

CB391

1

1

61.9

1

61.9

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

2

45

TRING4

TTIP4

48C1>

48C1>

56

D7

D5

7

5

JB12

I19

RJ45_4PORT

D8

6

8

D6

4

D4

D1

D3

3

1

2

RJ45

D2

RTIP4

RRING4

48C4<

48C4<

6

38

39

40

7

XMIT

1

L10

2

I24

3

5

4

I25

RCV

37
2

L10

36
2

7

1

RB329

RB330

1UF

C175

1

2

2

2

R202

0

R201

8

1

TTIP3

0

1

TRING3

D

RTIP3

C C

0

0

1

RB318

1

61.9

2

0.1UF

2

CB396

RB319

1

61.9

RRING3

1

2

8

THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28- 30 AND 23-25

THE PC B / ASS EMBLY HAS BE EN MODIFIED TO ACCOMMODATE THIS.

AS THE TX PRI MARY. THIS HAS BEEN CORR ECTED IN THE SCHEMATIC,

B B

A A

D

1

09/16/2004

1

6/10(BLOCK)

51/71(TOTAL)

DATE:

2

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

3

TITLE:

ENGINEER:

3

4

45

56

47A8>

V3_3

2

RB185

2.0K

1

2

RB209

1

2

RB192

2.0K

2.0K

1

MOT

2

2

RB228

RB183

2.0K

2.0K

1

1

NOTMUX

2

RB303

2.0K

1

RLOS1

1

DS30

2

2

47A4>

RLOS2

1

2

DS32

2

48A8>

RLOS3

1

2

DS33

2

48A4>

RLOS4

1

2

DS34

2

6

RB221

330

LIUC

46C7<

ESIBRD

46A 2<>

ESIBR0

46A 2<>

ESIBR1

BTS

46A2<

46A 2<>

MUX

46A2<

1

7

RB234

330

1

RB251

330

1

RB284

330

1

7

ALL UNMARKED BIAS RESISTORS ARE 10K

8

8

D

C C

B B

A A

D

52B 8<>

52C 8<>

V3_3

DONE

1

XI_TMS

ONCE_TCLK

RB129

JTD_SPART2FLASH

JTD_SPART_TDI

CCLK

2

RESET_B

330

1

09/16/2004

DATE:

1

7/10(BLOCK)

52/71(TOTAL)

PAGE:

U10

XRST

D15

R14

N3

P2

R3

R4

P15

M2

M1

M0

DONE

CCLK

52B 8<>

PROGRAM*

CONTROL

XC2S50_BGA

P4

NC1

NC2

GND36

T16

GND35

T1

GND34

R15

GND33

R2

GND32

L11

GND31

L10

GND30

L7

GND29

L6

GND28

K11

GND27

0.1UF

1

1

1

1

V3_3

2

C125

0.1UF

2

C142

0.1UF

2

C123

0.1UF

2

CB62

.1UF

2

1

C192

.1UF

1

2

CB269

.1UF

2

1

CB338

.1UF

2

1

CB278

.1UF

1

2

CB337

.1UF

2

1

CB216

.1UF

2

1

CB135

.1UF

1

2

CB275

1UF

2

2

1

C188

1UF

1

C77

K10

GND26

K9

GND25

K8

GND24

K7

GND23

K6

GND22

J10

GND21

J9

GND20

J8

GND19

J7

GND18

H10

GND17

H9

GND16

H8

GND15

H7

GND14

G11

GND13

G10

GND12

G9

GND11

G8

GND10

G7

GND9

G6

GND8

F11

GND7

F10

GND6

F7

GND5

F6

GND4

B15

GND3

B2

GND2

A16

GND1

A1

DS33Z11/41/44DK01A0

TITLE:

2

STEVE SCULLY

ENGINEER:

3

45

D3

A15

C4

B14

TDO

TCK

TDI

TMS

2

1UF

52B8<

1

2

CB274

1UF

V2_5XI

1

2

CB230

1UF

1

2

C86

3

P14

P3

N13

N4

M12

M5

E12

E5

D13

D4

4

C14

C3

56

VCCINT12

VCCINT11

VCCINT10

VCCINT9

VCCINT8

VCCINT7

VCCINT6

VCCINT5

VCCINT4

VCCINT3

VCCINT2

VCCINT1

0.1UF

1

1

1

1

1

1

2

C108

0.1UF

2

CB134

0.1UF

2

CB168

0.1UF

2

CB150

0.1UF

2

CB190

0.1UF

2

CB257

UB06

MAX1792

V3_3

8

OUT

IN

1

10UF

1

2

C114

7

5

6

OUT

SET

GND

IN

SHDN

RST

3

2

1UF

4

2

2

2

2

1

CB66

1UF

1

CB65

1UF

1

C23

1UF

1

C22

VCCO3

VCCO2

VCCO1

E8

F8

V3_3 V3_3

VCCO5

VCCO4

F9

E9

H12

H11

46C7<

JTD_FLASH_TDO

18

19

20

7

VCCJ

VCCO

U08

1

2

0.1UF

1

1

8

V3_3

1

2

C135

0.1UF

2

C85

0.1UF

2

CB245

CFG_DIN

53B 2<>

16

17

DNC3

VCCINT

TDO

TMS

CLKD0DNC1

TDI

3

5

4

CCLK

XI_TMS

52B 1<>

52C1<

52A 7<>

JTD_SPART2FLASH

46C7<

D

C C

VCCO8

VCCO10

VCCO9

VCCO7

VCCO6

L9

L8

J11

15

14

DNC5

DNC4

TCK

CF*

7

6

XRST

ONCE_TCLK

52B1<

52C1<

52A 7<>

46C7<

M9

J12

13

12

11

GND

DNC6

CEO*

CE*

OE/RST*

DNC2

9

8

10

X_INIT

1

10K

R84

DONE

2

52B 1<>

V2_5XI

VCCO13

VCCO12

VCCO11

M8

J5

XILINX_XCF01S

B B

VCCO16

VCCO15

VCCO14

H5

H6

J6

6

52C1<46C7<

52C1<46C7<

46C7>

52C1<

52C 8<>

52C 8<>

JTDO458

XI_TMS

ONCE_TCLK

V3_3

JB07

JTD_SPART_TDI

10

65

4

2

2

1

1

8

6108

4

3

7

5

9

3

7

9

TDI _NU

TMS _NU

TCK _NU

TDO _NU

A A

CONN_10P

7

8

D

2.0K

1

(IMPLEMENTS IMUX)

RSER1

RSER2

TSER PULLDNS USED IN IBO MODE

RSER3

R94

2.0K
R104

2.0K
R113

2.0K
R88

RSER4

09/16/2004

DATE:

2

47B8>

47B4>

48B8>

48B4>

TP30

TP32

53A 7<>

53A 7<>

53A 7<>

53A 7<>

1 1

52C 8<>

48B 1<>

48B 5<>

47B 1<>

47C5<

47B5<

47B1<

48B5<

47C1<

48B1<

47B 5<>

48C5<

48C1<

1

8/10(BLOCK)

53/71(TOTAL)

PAGE:

2

SPARE_TP2

SPARE_TP1

H16

H15

H13

G16

G13

F15

E16

F14

D16

3

IO2_2\VREF

IO2_1\IRDY

A9

E10

48B1<>

48B5<>

47B2<>

47B6<>

TSYNC4

A10

TSYNC3

D10

TSYNC2

B10

TSYNC1

A12

D11

4

48B1<

48B4<>

48B5<

48B8<>

47B2<

47B4<>

TSSYNC4

A13

RSYNC4

B12

TSSYNC3

D12

RSYNC3

C12

TSSYNC2

A8

RSYNC2

D9

B9

C10

47B6<

47B8<>

56

TSSYNC1

A11

RSYNC1

B11

E11

C11

A14

C13

B13

C9

IO22_1

IO21_1

IO20_1

IO19_1

IO18_1

IO17_1

IO16_1

IO15_1

IO14_1

IO13_1

IO12_1

IO11_1

IO10_1

BANK 1

IO9_1\VREF

IO8_1

IO7_1

IO6_1

IO5_1

IO4_1\VREF

IO3_1

IO2_1\WRITE*

IO1_1\CS*

GCK2

IO5_2

IO4_2

IO3_2\D3

IO6_2\D2

IO9_2

IO8_2

IO7_2\D1

U10

BANK 0

CFG_DIN

TCLK1

TCLK2

TCLK3

TCLK4

TSER1

F13

E13

IO11_2

IO10_2\VREF

BANK 2

TSER2

TSER3

TSER4

H14

D14

C15

J13

G14

G15

G12

IO18_2

IO17_2

IO16_2

IO15_2

IO14_2

IO12_2\(DIN,D0)

IO13_2\(DOUT,BUSY)

TGAPCLK1

F16

F12

E15

IO21_2

IO20_2

IO19_2

BANK 3

XC2S50_BGA

TGAPCLK4

TGAPCLK3

TGAPCLK2

E14

C16

B16

DS33Z11/41/44DK01A0

TITLE:

IO24_2

IO23_2

IO22_2

IO23_3

J14

IO22_3

K12

IO21_3

L15

IO20_3

K13

IO19_3

L16

IO18_3

L12

IO17_3

M15

IO16_3

M14

IO15_3

R16

IO14_3

T15

IO13_3\TRDY

J15

IO12_3

K15

IO11_3\D4

J16

IO10_3\VREF

K16

IO9_3

K14

IO8_3\D5

M16

IO7_3\D6

N16

IO6_3

L13

IO5_3

P16

IO4_3\VREF

L14

IO3_3

M13

IO2_3\D7

N14

IO1_3\INIT*

N15

X_INIT

STEVE SCULLY

ENGINEER:

3

45

52B8<>

IO4_0

IO3_0

IO2_0\VREF

IO1_0

GCK3

A7

B8

B7

C7

RSYSCLK

TSYSCLK

BPCLK1

47B6>

IO5_0

A5

B6

MCLK2FPGA

46D7<

7

RSYSCLK1

RSYSCLK2

RSYSCLK3

RSYSCLK4

TSYSCLK1

47B8<

47B4<

48B4<

48B8<

47B6<

TSYSCLK3

TSYSCLK2

47B2<

TSYSCLK4

48B1<

48B5<

IO8_0

IO7_0\VREF

IO6_0

C6

B4

A3

B3

RGAPCLK2

RGAPCLK1

47B8<

IO11_0

IO10_0

IO9_0

D8

A6

RGAPCLK4

RGAPCLK3

48B4<

48B8<

47B4<

IO14_0

IO13_0

IO12_0

C8

D7

E7

RCLK3

RCLK2

RCLK1

48C8>

47C4>

47C8>

IO17_0

IO16_0

IO15_0

B5

D6

A4

E6

RSER3

RSER2

RSER1

RCLK4

48C4>

53C2< 47B4>

53C2< 47B8>

IO20_0

IO19_0

IO18_0

D5

C5

6

RSER4

7

53C2< 48B8>

53C2< 48B4>

8

D

C C

B B

A A

8

D

1

09/16/2004

1

9/10(BLOCK)

54/71(TOTAL)

DATE:

55C 1<>

55C 1<>

55C 4<>

55B 1<>

55B 4<>

55C 4<>

2

R43

Z44_RCLK<3>

Z44_RSER<3>

30

30

R42

RB94

Z44_TDEN<3>

Z44_RDEN<3>

Z44_TCLK<3>

30

30

30

RB101

R44

55B 1<>

55B 1<>

55B 1<>

55B 4<>

55B 4<>

55B 4<>

Z44_TCLK<4>

Z44_RCLK<4>

Z44_RSER<4>

30

30

R41

R39

RB93

Z44_TDEN<4>

Z44_RDEN<4>

30

30

30

RB92

R40

DAT<7..0>

Z44_TSER<3>

3

7

5

4

6

55A 4 55 A2

3

46B 1<>

1

2

OBS_RSER<3>

0

TP29

1111

OBS_TCLK<3>

OBS_RDEN<3>

OBS_RCLK<3>

TP27

TP17

1

OBS_TDEN<3>

TP28

TP15

TP16

111

Z44_TSER<4>

OBS_RDEN<4>

OBS_TCLK<4>

OBS_RSER<4>

OBS_RCLK<4>

TP26

TP24

TP14

OBS_TDEN<4>

TP12

TP25

TP13

1

11 1

TITLE:

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

H1

J2

IO2_6

IO1_6\TRDY

K3

R7

P7

4

T6

N7

IO19_5

IO18_5

IO17_5

IO16_5

IO15_5

L1

J3

J1

IO3_6

IO5_6

IO6_6

IO7_6

IO8_6

IO4_6\VREF

T11

T7K2T5

R1

N1

IO9_6

IO11_6

IO12_6

IO13_6

IO14_6

IO10_6\VREF

BANK 6

L3

L4

K4

L2

IO14_5

M6

J4

M3

N5

M4

P8

M7

56

R6

P6

R5

N6

T4

L5

R8

IO13_5

IO12_5

IO11_5

IO10_5

IO9_5

IO8_5\VREF

IO7_5

BANK 5

IO6_5

U10

XC2S50_BGA

IO5_5

IO4_5

IO3_5

IO2_5\VREF

IO1_5

GCK1

BANK 4

K1

T10

T8

P5

P1

M1

T3

M2

IO15_6

IO16_6

IO17_6

IO20_6

IO19_6

IO18_6

T2

IO23_6

IO22_6

IO21_6

IO23_7

H4

IO22_7

H2

IO21_7

G2

IO20_7

F5

IO19_7

F4

IO18_7

F1

IO17_7

E2

IO16_7

F3

IO15_7

D2

IO14_7

E3

IO13_7

A2

IO12_7\IRDY

G1

IO11_7

BANK 7

G5

IO10_7

G4

IO9_7\VREF

H3

IO8_7

G3

IO7_7

F2

IO6_7

E1

IO5_7

D1

IO4_7

E4

IO3_7\VREF

C1

IO2_7

B1

IO1_7

C2

55B2<>

T3ENH_T1ENLPRT4

55C2<>

T3ENH_T1ENLPRT3

55C6<>

T3ENH_T1ENLPRT2

55D6<>

T3ENH_T1ENLPRT1

54A8<

54A8<

54A8<

54A8<

45

6

IO2_4

IO3_4\VREF

IO1_4

GCK0

N8

N9

R9

IO4_4

K5

P9

CS_X4

1

2

30

0

55D 2<>

IO7_4

IO6_4

IO5_4

N2

R11

M11

R48

R47

WR

30

55A 3<>

7

46B7<

Z41TSYNC

Z41RSYNC

ADDR<9..0>

55C 6<>

55C 6<>

46C2<

IO10_4

IO9_4\VREF

IO8_4

T12

R13

N11

P13

RD

55A 2<>

46B7<

R50

30

30

Z44_TDEN<1>

IO13_4

IO12_4

IO11_4

T9

M10

R10

R51

R49

R53

30

30

Z44_RCLK<1>

Z44_RDEN<1>

Z44_TCLK<1>

IO16_4

IO15_4

IO14_4

P10

R12

P11

R54

30

30

Z44_RSER<1>

Z44_TSER<1>

IO19_4

IO18_4

IO17_4

T13

N12

R45

R72

R52

303030

Z44_TCLK<2>

Z44_RDEN<2>

Z44_TDEN<2>

8

55A 7 55 A5

55C 8<>

55C 6<>

55D 6<>

55D 8<>

55C 8<>

55C 6<>

55C 6<>

55C 8<>

55C 6<>

IO22_4

IO21_4

IO20_4

T14

P12

N10

2.0K

R46

R73

30

Z44_RSER<2>

Z44_RCLK<2>

Z44_TSER<2>

RB46

2.0K
RB45

2.0K
RB05

2.0K
RB04

7

8

T3ENH_T1ENLPRT1

T3ENH_T1ENLPRT2

T3ENH_T1ENLPRT3

T3ENH_T1ENLPRT4

55C 6<>

55C 8<>

55C 8<>

PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING J UM PERS ON T3 BRD

55D 6<> 54A6< >

55C 6<> 54A5< >

55C 2<> 54A5< >

55B 2<> 54A5< >

D

C C

B B

A A

D

1

SIG_RETURN

09/16/2004

I27

DATE:

GND

DS33Z11/41/44DK01A0

Z44_TDEN<4>

44

43

114

113

55C 6<>

54B1<

55A1>

54A1<

Z44_TCLK<4>

SIG_RETURN

GND

46474954525051

45

115

117

116

46B7<

54C 7<>

DAT<7..0>

3

1

0

55A 4

7

5

RD

GND

48

118

5358565557

123

120

119

122

121

GND

GND

54C 3 46 B1< >

596260

61

132

131

130

129

128

127

126

125

124

GND

GND

63

65

64

135

133

134

GND

70

69

66

68

67

136

140

139

138

137

54A8<

54B1<

54B1<

54A 5<>

54B 1<>

54C 7<>

Z44_TCLK<3>

ALE

2

CS_ X4

T3ENH_T1ENLPRT3

Z44_TDEN<3>

Z44_TSER<3>

54A8<

54A 5<>

54B 1<>

Z44_TSER<4>

T3ENH_T1ENLPRT4

J09

GND

GND

GND

7

8

6

767579

9

GND

10

80

13

11

12

818384

82

14

172219

159016

85

87

86

GND

3

1

5

4

2

73

71

72

747877

GND

18

20

21

23

92

932491

89

88

94

262725

959997

96

GND

GND

GND

35

3230333134

36

38

29

28

100

102

101

98

37

105

103

106

104

107

108

GND

GND

39

40

42

41

109

111

110

112

1

10/10(BLOCK)

55/71(TOTAL)

PAGE:

2

STEVE SCULLY

3

RECEPTACLE

P1 CONNECTOR (RECEPTICAL)

GND

GND

CS_ X5

GND

V3_ 3

GND

GND

GND

V3_ 3

GND

GND

Z44_RDEN<3>

Z44_RSER<3>

54B1<

54B1<

GND

V3_ 3

Z44_RCLK<3>

54B1<

GND

GND

V3_ 3

GND

GND

Z44_RSER<4>

54B1<

Z44_RCLK<4>

Z44_RDEN<4>

54B1<

54B1<

V3_ 3

GND

GND

GND

OSC 1_N U

GND

V3_ 3

CS_X2

WR

CS_X3

I29

2

4

6

54C 7<>

CS

46B7<

46B7<

NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4

TITLE:

DAT<7..0>

4

55A 2 54 C3 4 6B1<>

55A 754C7

ENGINEER:

3

45

56

46C2<

ADDR<9..0>

3

1

GND

128

127

5

596260

129

8

6

OSC 3_N U

GND

GND

GND

70

63

61

64

133

134

132

131

130

69

66

65

68

67

135

136

140

139

138

137

WAN R.C. CONNECTOR TO MOTHERBOARD

6

J12

55C 6<>55B2<>

46C7>

46A 4<>

WAN_INT

I28

INT3

GND

3

1

2

73

71

72

VDD

52B1<

46A 2<>

55D 7<>

INT2

RESET_ B

GND

6

5

4

747877

767579

54A8<

54B8<

54B8<

55A1>

54A 6<>

54B 8<>

Z44_TDEN<1>

Z44_TSER<1>

T3ENH_T1ENLPRT1

SIG_RETURN

GND

7

8

9

11

10

12

818384

80

82

54C7<

54C7<

Z44_TCLK<1>

Z41RSYNC

Z41TSYNC

GND

14

13

172219

159016

18

87

85

88

86

55C 6<>5 5B2 <>

54A8<

54B8<

55A1>

54B 8<>

54A 5<>

52A 8<>

Z44_TCLK<2>

Z44_TDEN<2>

Z44_TSER<2>

SIG_RETURN

T3ENH_T1ENLPRT2

GND

GND

20

23

21

92

932491

89

94

262725

959997

96

GND

GND

GND

35

3230333134

36

38

29

28

101

100

102

98

37

105

106

104

107

103

108

GND

42

112

44

43

114

113

GND

48

46474954525051

45

115

118

117

116

GND

39

40

41

109

111

110

52A 8<>

TCK _NU

TDO _NU

GND

GND

5358565557

123

120

119

122

121

126

125

124

7

8

RECEPTACLE

P2 CONNECTOR (RECEPTICAL)

GND

V3_ 3

GND

GND

INT5

INT2

55D 6<>

GND

V3_ 3

Z44_RSER<1>

Z44_RDEN<1>

54B8<

54B8<

GND

GND

Z44_RCLK<1>

54B8<

GND

V3_ 3

Z44_RSER<2>

54A8<

GND

GND

Z44_RCLK<2>

Z44_RDEN<2>

54B8<

54B8< 54B8<

GND

V3_ 3

GND

GND

GND

V3_ 3

GND

GND

TDI _NU

52A 8<>

GND

V3_ 3

TMS _NU

4

2

0

52A 8<>

54C 7

GND

GND

46C2<

OSC 4_N U

OSC 2_N U

V3_ 3

7

9

55A 5

ADDR<9..0>

7

8

V3_3

D

C C

B B

A A

D

1

09/16/2004

1

1/8(BLOCK)

56/71(TOTAL)

DATE:

2

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

63A 763A 662A 762A6

3

63A 563A362A562A3

TITLE:

ENGINEER:

3

60B1<56C 7<

V3_3

0.0

IN

IO

V3_3

R142

ADDR<10..0>

4

N15

56

V3_3

DS3184 WAN INTERFACE BLOCK

63B 7<>62B 7<>

63B 7<>62B 7<>

63B 6<>62B 6<>

63B 6<>62B 6<>

P13
P14
P15
R13
R14
R15
W1
N6
N7
N8
P6
P7
P8
R6
R7
R8
A2

VDD9

F6

VDD8

F7

VDD7

F8

VDD6

G6

VDD5

G7

VDD4

G8

VDD3

H6

VDD2

H7

VDD1

H8

3

1

2

H2E1H1

A<1>

A<2>

A<0>/BSWAP

VDD27
VDD26
VDD25
VDD24
VDD23
VDD22
VDD21
VDD20
VDD19
VDD18
VDD17
VDD16
VDD15
VDD14
VDD13
VDD12
VDD11
VDD10

7

4

5

8

6

E3

G3

D2H3E2

G2

A<3>

A<4>

A<6>

A<5>

A<7>

A<8>

DAT<7..0>

1

0

9

10

P1U1N2C3D3

ALE

A<9>

D<1>

D<0>

A<10>

D<2>

7

6

50432

P3W2N3P2U2

T2

D<3>

D<4>

D<6>

D<5>

D<7>

UB08

DS3184

VALUE NOT SHOWN FOR 10K RES

56B 8<>

R151

RB186

RB206

R135

RB222

R121

RB229

R146

P4V3N4T3U3

D<9>

D<8>

D<11>

D<10>

D<12>

D<13>

D20

E19

J5

T4

D<14>

D<15>

D19

TSPA

TDXA<4>

TDXA<3>

TDXA<2>

TDXA<1>/TPXA

K20

K16

K17

R4

CONTROL

V3_3

CLKB

K19

RPRTY*

RDXA1/RPXA

G18

M20

E20

F18

F19

REN*

RSCLK

RDXA<2>

RDXA<3>

RDXA<4>

VSS35

M13

VSS34

N11

VSS33

N12

VSS32

Y1

VSS31

P9

VSS30

P10

VSS29

P11

VSS28

P12

VSS27

R9

VSS26

R10

VSS25

R11

VSS24

R12

VSS23

L8

VSS22

L9

VSS21

L10

VSS20

M8

VSS19

M9

VSS18

M10

VSS17

N9

VSS16

N10

VSS15

A1

VSS14

J6

VSS13

J7

VSS12

K6

VSS11

K7

VSS10

L6

VSS9

L7

VSS8

M6

VSS7

M7

VSS6

J8

VSS5

J9

VSS4

J10

VSS3

K8

VSS2

K9

VSS1

K10

63D5>62D5 >56B8>

T3_INT

TP66

1

NC7SZ8 6_U

45

6

UX12

4

TDI _NU

TMS _NU

TCK _NU

7

J39

JTCLK

10K

RB250

RB309

V3_3

8

61D2<

60D2< 56C7<

TDO _NU

HIZ*

CLKB

CLKA

RST*

TEST*

WIDTH

MODE

WR*

RD*

CS*

RADR<4>

RADR<3>

RADR<2>

RADR<1>

RADR<0>

TMOD<1>

TMOD<0>

TERR

TSX

TEOP

TSOX

TEN

TPRTY

TSCLK

JTDI

JTDO

JTRST*

JTCLK

JTMS

10

65

4

8

F3E4G4

J3

6108

412

3

7

5

9

3

7

9

JTDI

JTDOCPLD

JTMS

10K

61C2<

60C2< 56C7<

JTRST

56C7<

61C2<

RB308

56C7<

CONN_10P

10K

F4

JTCLK

JTMS

56D 8<>

56D 8<>

J20

A17

A19

W16

V15

Y16

Y17

B17

B18

R20

R19

JTDI

CLKB

JTRST

JTDO84

60C2<

56D 8<>

56D 8<>

V3_3

61C2< 60C2<

61D2< 60D2<

56B 8<>

60B1< 56B4<

L3K3K4B1L5

R18

T20

T19

RD

WR

CS

0.0

0.0

IN

R144

RB227

IN

63A5< 62A5<

IN

63A3> 62A3>

63A 4<>

62A 4<>

K1L1L2

M3

R3
2

B16

10K

RB283

CLKA

0.0

CLKB

GND

V3_ 3

R156

60B1<

RESET_B

IN

60B1< 56C7< 56B4<

63D 6<>

62D 6<>

RVAL

REOP

RSOX

CLKC

L17

L16

K18

INT*

RDY*

RMOD<1>

RMOD<0>

RERR

K2

L4

L18

L19

J19

DS41

7

RED

T3_INT

RB331

OUT

56A 6<>

63D5> 62D5>

330

8

V3_3

V3_3

D

C C

B B

A A

D

61B3>61A3>60B3>60A3>57C5>57A5>57A1>

59C4<59A8<59A4<5 7C5>57C2>57A5>

59C8<59C4<59A8<5 9A4<57C5>57A5>57A2>

59C8<59C4<59A8<5 9A4<57C5>57A5>57A2>

61C4>61B4 >60B4>57C5>57A5>57A1>

59A8<59A4<57C5>5 7C2>57A5>

61B4>60B4>57C5>5 7C2>57A5>61B4>60B4>57C5>57C2>57A1>

61B4>60B4>57C5>5 7C2>57A5>

60B3>60A3>57C5>5 7C2>57A5>61B3>61A3>60B3>6 0A3>57C5>57C2>57A1>

61B3>60B3>57C5>5 7C2>57A5>61B3>60B3>57C5>57C2>57A1>

60B4>57C5>57C2>5 7A5>

1

61B4>60B4>57C5>5 7A5>57A1>61B4>60B4>57C2>5 7A5>57A1>

61B4>60B4>57C5>5 7A5>57A1>

61B3>60B3>57C5>5 7A5>57A1>61B3>60B3>57C2>5 7A5>57A1>

09/16/2004

1

2/8(BLOCK)

57/71(TOTAL)

DATE:

59C8<59C4 <

59C8<

OUT

OUT

OUT

OUT

OUT

61B3>61A3>

61B4>

61C4>

OUT

OUT

OUT

OUT

OUT

2

TE3_RSER<4..1>

TE3_RCLK<4..1>TE3_RCLK<4..1>

TE3_TXP<4..1>

TE3_TXN<4..1>

2

2

TE3_TGAPCLK<4..1>TE3_TGAPCLK<4..1>

TE3_TCLK<4..1>TE3_TCLK<4..1>

2

2

TE3_RGAPCLK<4..1>TE3_RGAPCLK<4..1>

222

PAGE:

2

STEVE SCULLY

U10

V4

TE3_RCLK<4..1>TE3_RCLK<4..1>

TE3_RSER<4..1>

C10

333

A11

B11

TE3_RGAPCLK<4..1>TE3_RGAPCLK<4..1>

B12

TE3_TGAPCLK<4..1>TE3_TGAPCLK<4..1>

TE3_TXN<4..1>

TE3_TXP<4..1>

3

3

C11

C14

E12

E11

A6

B6

B14

TE3_TCLK<4..1>TE3_TCLK<4..1>

3

3

B10

C12

A13

D14

E13

E10

Y8

TPOS

TLCLK

3

TXP

TXN

TPOS

TNEG

TLCLK

ROH

TOHCLK

TOHSOF

ROHCLK

ROHSOF

RSER

TCLKO

TSOFO

TPDAT

RCLKO

RSOFO

TPDENO

UB08UB08

PORT

DS3184

V7V8M1M2U4

Y7U7Y2

U5

T8

U9T9W9

Y9

DS33Z11/41/44DK01A0

TXP

TXN

TNEG

ROH

TOHCLK

TOHSOF

ROHCLK

ROHSOF

RSER

TCLKO

TSOFO

TPDAT

RCLKO

RSOFO

TPDENO

TITLE:

ENGINEER:

3

RXP

RXN

RLCLK

RPOS

RNEG

TSOFI

TOH

TOHEN

TCLKI

TPDENI

RPDAT

TSER

RPDENI

PORT

UB08

DS3184

RXP

RXN

RLCLK

RPOS

RNEG

A5

B5

A15

B15

A12

D11

3

3

4

PORT3=PINA12

TE3_RXN<4..1>

TE3_RXP<4..1>

59D8<

59D4< 59B8<

59B4< 57C8<

56

57A8< 57A4<

TSOFI

TOH

TOHEN

TCLKI

TPDENI

RPDAT

TSER

RPDENI

B13

C13

A10

D13

A14

E14

D12

3

60B3>60A3>57C2>5 7A5>57A1>

TE3_TSER<4..1>

61B3>61A3>

IN

OUT

OUT

OUT

OUT

OUT

PORT2=PINW8PORT4=PINY12

W3

Y3

W8

R1

R2

2

2

W4

T5U8W7

U6T6V9

V5

2

45

TE3_RXN<4..1>

TE3_RXP<4..1>

59A4<57C5>57C2>5 7A2>

59A4<57C5>57C2>5 7A2>

59C8<59C4<59A8<

59C8<59C4<59A8<

TE3_TSER<4..1>

IN

61C4>61B4>

60B4>57C5>

57C2>57A1>

OUT

OUT

OUT

OUT

OUT

111

D7B2D5

TCLKO

TCLKI

B4

TE3_RSER<4..1>

TE3_TXN<4..1>

1

1

1

A7

TSOFO

E8D9E9B9A9

RSER

TPDAT

RCLKO

RSOFO

TPDENO

TE3_TXP<4..1>

4

4

V11

W14

V14

TXP

TXN

TPOS

TNEG

TLCLK

U14

T13

T10

T12

T11Y6W6

ROH

TOHCLK

TOHSOF

ROHCLK

ROHSOF

TE3_RSER<4..1>

444

4

4

W12

Y11

W11

V10

W10

V12

Y13

RSER

RCLKO

TCLKO

TSOFO

RSOFO

TPDAT

TPDENO

6

PORT

DS3184

TSOFI

TPDENI

RPDAT

TSER

RPDENI

D6

E6C9C5

1

RXP

RXN

RLCLK

RPOS

RNEG

Y5

W5

Y15

W15

Y12

U11

4

4

TSOFI

TOH

TOHEN

TCLKI

TPDENI

RPDAT

TSER

RPDENI

W13

V13

Y10

U13

Y14

T14

U12

4

7

TE3_TXN<4..1>

TE3_TXP<4..1>

1

1

D10C7C8

J1

J2D4C4

A8

TXP

TXN

TPOS

TNEG

TLCLK

ROH

TOHCLK

TOHSOF

ROHCLK

ROHSOF

PORT

UB08

DS3184

RXP

RXN

RLCLK

RPOS

RNEG

B3

A3

B8

F2

7

TOH

TOHEN

E5D8B7

F1

1

PORT1=PINB8

TE3_RXP<4..1>

TE3_RXN<4..1>

TE3_TSER<4..1>

IN

TE3_RXN<4..1>

TE3_RXP<4..1>

TE3_TSER<4..1>

IN

57C5<

8

59D8< 59D4< 59B8<

59D8<

59D4<

59B8<

59B4<

57C5<

57A8<

57A4<

59B4< 57C5< 57A8< 57A4<

57A8< 57A4< 61B4> 60B4>

D

C C

B B

59D8< 59D4< 59B8<

59D8< 59D4< 59B8<

59B4< 57C8< 57C5< 57A4<

59B4< 57C8< 57C5< 57A4<

57C8< 57C5<

57A4< 61B4> 60B4>

A A

8

D

1

RED

RED

2

1

DS21

RB153

330

1

TP37

RED

2

1

DS22

RB155

330

1

TP38

2

GPIO1

58B 3<>

GPIO2

58B 3<>

RED

2

2

09/16/2004

1

3/8(BLOCK)

58/71(TOTAL)

1

DS23

RB154

1

TP39

GPIO3

58B 3<>

1

DS24

RB152

330

330

1

TP40

GPIO4

58B 3<>

DATE:

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

58B 2<>

58A 2<>

58B 2<>

58A 2<>

3

GPIO3

GPIO2

GPIO1

GPIO4

TITLE:

ENGINEER:

3

L20

M19

RDATA<1>

RDATA<0>

AVDDC

K5

4

V3_3

56

V6
C6
N5
G1

T7
E7
N1
J4

Y4
A4
T1
D1

B20
F13
F14
F15
G13
G14
G15
H13
H14
H15
Y19
N13
N14

AVDDJ4
AVDDJ3
AVDDJ2
AVDDJ1

AVDDT4
AVDDT3
AVDDT2
AVDDT1

AVDDR4
AVDDR3
AVDDR2
AVDDR1

VDD40
VDD39
VDD38
VDD37
VDD36
VDD35
VDD34
VDD33
VDD32
VDD31
VDD30
VDD29
VDD28

P20

N18

N19

M18

N20

RDATA<3>

RDATA<2>

RDATA<4>

RDATA<5>

RDATA<6>

M17

N17

P17

P18

P19

RDATA<7>

RDATA<8>

RDATA<9>

RDATA<10>

RDATA<11>

H20

G20

M16

N16

P16

R16

RDATA<12>

RDATA<13>

RDATA<14>

RDATA<15>

RDATA<16>

RDATA<17>

RDATA<18>

J17

E18

J18

G19

RDATA<19>

RDATA<21>

RDATA<20>

RDATA<22>

RDATA<23>

RDATA<24>

UB08

DS3184

DATA & I/O PORT

H17

H18

H19

H16

J16

E17

F17

G17

RDATA<25>

RDATA<26>

RDATA<27>

RDATA<28>

RDATA<29>

G5

F5

G16

F16

GPIO<1>

GPIO<2>

GPIO<3>

RDATA<31>

RDATA<30>

V2C2V1

C1P5R5

GPIO<4>

GPIO<5>

GPIO<7>

GPIO<6>

GPIO<8>

H5

NC<3>

H4

NC<2>
NC<1>
NC<0>

M4

VSS68
VSS67
VSS66
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36

NC PINS UNUSED????

0.0

2

0.0

2

0.0

2

M5

0.0

2

H9

H10
A20

F9

F10
F11
F12

G9

G10
G11
G12
H11
H12
J11
J12
J13
K11
K12
K13
Y20
J14
J15
K14
K15
L14
L15
M14
M15
L11
L12
L13
M11
M12

R132

1

RB194

1

R137

1

RB208

1

45

TADR<0>

TADR<4>

TDATA<0>

TDATA<1>

TDATA<2>

TDATA<3>

TDATA<5>

TDATA<4>

TADR<1>

TADR<3>

TADR<2>

TDATA<6>

TDATA<10>

TDATA<7>

TDATA<8>

TDATA<9>

TDATA<15>

TDATA<13>

TDATA<11>

TDATA<16>

TDATA<12>

TDATA<14>

TDATA<17>

TDATA<22>

TDATA<23>

TDATA<24>

TDATA<25>

TDATA<26>

TDATA<27>

TDATA<28>

TDATA<29>

TDATA<30>

TDATA<18>

TDATA<19>

TDATA<21>

TDATA<20>

TDATA<31>

6

C18

C16

C17

T17

T16

W17

V17

W18

B19

C20

E15

D15

A16

A18

V20

T18

U20

C15

7

W20

W19

U18

V19

V18

U19

R17

Y18

V16

D17

C19

F20

E16

D16

U15

T15

U16

U17

D18

7

8

D

C C

B B

A A

8

D

1

09/16/2004

1

4/8(BLOCK)

59/71(TOTAL)

DATE:

51

2

2

TB01

5
4

3

2

1

51

2

1

RB357

75 OHM RA

J59

CONN_BNC_5P

RREF4

13

14

2:1

332

20

2

4

19

1

R213

4

TB01

5
4

3

2

1

TREF4

15

18

2

4

5
4

75 OHM VERT

J49

CONN_BNC_5P

3

2

1

51

2

1

RB355

75 OHM RA

J56

CONN_BNC_5P

RREF3

3

3

TB01

30

2

3

4

2:1

332

29

1

R210

3

TB01

5
4

3

2

1

51

2

1

RB370

75 OHM VERT

J52

CONN_BNC_5P

TREF3

1

2

2:1

32

3

332

2

31

1

RB306

3

1

RB369

16

2:1

TITLE:

332

17

1

R200

4

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

4

56

TE3_RXP<4..1>

59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57 A4<

TE3_RXN<4..1>

59D8< 59B8< 59B4< 57C8< 57C5< 57A8< 57 A4<

TE3_TXP<4..1>

59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57 A2>

TE3_TXN<4..1>

59C8< 59A8< 59A4< 57C5> 57C2> 57A5> 57 A2>

TE3_RXP<4..1>

59D8< 59D4< 59B8< 57C8< 57C5< 5 7A8< 57A 4<

TE3_RXN<4..1>

59D8< 59D4< 59B8< 57C8< 57C5< 5 7A8< 57A 4<

TE3_TXP<4..1>

59C8< 59C4< 59A8< 57C5> 57C2> 5 7A5> 57A 2>

TE3_TXN<4..1>

59C8< 59C4< 59A8< 57C5> 57C2> 5 7A5> 57A 2>

45

6

5
4

75 OHM VERT

J50

CONN_BNC_5P

3

2

1

51

2

1

RB356

75 OHM RA

J57

CONN_BNC_5P

RREF1

5

7

TB01

28

2

1

8

6

2:1

332

27

1

R211

1

TB01

5
4

3

2

1

51

2

1

RB371

75 OHM VERT

J51

CONN_BNC_5P

TREF1

7

8

2:1

332

26

2

1

25

1

R198

1

TB01

5
4

3

2

1

51

2

1

RB358

75 OHM RA

J58

CONN_BNC_5P

RREF2

11

2:1

22

2

332

2

21 12

1

R212

2

TB01

5
4

3

2

1

TREF2

9

10

51

2

1

RB368

7

2:1

24

2

332

2

23

1

R199

2

8

TE3_TXP<4..1>

TE3_RXP<4..1>

TE3_RXN<4..1>

59C4<

59A4<

57C5>

57C2>

57A5>

57A2>

D

TE3_TXN<4..1>

59C4<

59A8<

C C

59A8<

59A4<

57C5>

57C2>

57A5>

57A2>

TE3_RXP<4..1>

59D8<

59B4<

57C8<

57C5<

57A8<

57A4<

B B

TE3_RXN<4..1>

59D4<

59D8<

59D4<

59B4<

57C8<

57C5<

57A8<

57A4<

TE3_TXP<4..1>

59C8<

59A4<

57C5>

57C2>

57A5>

57A2>

A A

TE3_TXN<4..1>

59C4<

59C8<

59C4<

59A4<

57C5>

57C2>

57A5>

57A2>

D

61B 7<>60B7<>

56B4<

56B8<

56C7<

56B 8<>

1

CLKB

OSC_A

61D2<56C7<

56D 8<>

61C2<56C7<

61C2<

56C 7<>

56D 8<>

V3_3

8

30

RB145

CLKA

30

30

RB148

RB149

09/16/2004

DATE:

1

5/8(BLOCK)

60/71(TOTAL)

PAGE:

JTCLK

2

48

TCK

UB03

XILINX_CPLD

3

XILINX_XC9572XL

2.5V_3.3V 1

38

V3_3

26

JTMS

JTDT_NEXTCPLD

JTDO84

83

45

47

TMS

TDI

TDO

21

NC<8-0 >

3.3V2

2.5V_3.3V2

51

3.3V1

2.5V_3.3V3

2.5V_3.3V4

5

88

57

GND1

31

GND2

44

GND3

62

GND4

69

GND5

75

GND6

84

GND7

100

GND8

2.0K

3.3V3

98

V3_3

44.736MHZ_5.0V

Y08

61B4>60B4>57C5>5 7C2>57A5>57A1>

61B4>60B4>57C5>5 7C2>57A5>57A1>

2

J24

1

JMP_2

R85

61C4>

VCC

OSC

1

GND OUT

4 5

61B3>60B3>57C5>57C2>57A5>57A1>

57C8<57C5<57A8<5 7A4<61B4>60B4>

61B4>60B4>57C5>5 7C2>57A5>57A1>

60B3>57C5 >57C2>57A5>57A1>

61B3>

61B4>60B4>57C5>5 7C2>57A5>57A1>

60A3>57C5 >57C2>57A5>57A1>

61B3>61A3>

61B4>60B4>57C5>5 7C2>57A5>57A1>

61C4>

61B3>61A3>60B3>57C5>57C2>57A5>57A1>

57C8<57C5<57A8<5 7A4<61B4>60B4>

61B4>60B4>57C5>5 7C2>57A5>57A1>

DS33Z11/41/44DK01A0

TITLE:

2

STEVE SCULLY

ENGINEER:

3

4

14

IO19

IO18

23

56

30

63C6<>62C6<>

63C8<>62C8<>

63C6<>62C6<>

63C8<>62C8<>

63D6<>62D6<>

63D8<>62D8<>

Z44_TDEN<1>

30

Z44_RDEN<1>

30

Z44_TCLK<1>

30

Z44_RCLK<1>
Z44_TSER<1>

30

Z44_RSER<1>

22
6

R67

4

R68

12

R65

9

R66

8

3

R69

13
97
11
10
20

R62

18

R63

28

R60

25

R61

29

R64

63C6<>62C6<>

63C8<>62C8<>

63C6<>62C6<>

63C8<>62C8<>

63C6<>62C6<>

63C8<>62C8<>

30

Z44_TDEN<2>

30

Z44_RDEN<2>

30

Z44_TCLK<2>

30

Z44_RCLK<2>
Z44_TSER<2>

30

Z44_RSER<2>

GCK2

IO17

GCK1

IO16

IO15

IO14

IO13

IO12

IO11

IO10

IO9

IO8

IO7

Z44 CONNECTIONS

IO6

IO5

IO4

IO3

IO2

IO1

LOOPBACK_CTRL

TP31

1

61C 3<>

TE3_TGAPCLK<4..1>

TE3_TSER<4..1>

TE3_TCLK<4..1>

TE3_RGAPCLK<4..1>

TE3_RSER<4..1>

TE3_RCLK<4..1>

SPARE_TP1

15

27

IO20

IO2 1

GCK 3

2

2

2

2

2

30

17

IO22

72

70

60

IO24

IO23

64

68

IO25

IO26

IO27

IO28

UB04

XILINX_CPLD

XILINX_XC9572XL

TE3_RCLK<4..1>

TE3_RSER<4..1>

4

2

74

IO29

4

65

54

40

IO30

IO3 1

IO32

TE3_TSER<4..1>

TE3_TGAPCLK<4..1>

TE3_TCLK<4..1>

TE3_RGAPCLK<4..1>

4

4

4

4

55

63

58

56

IO34

IO33

IO35

IO36

IO37

32

IO38

33

IO39

35

IO40

36

IO41

59

IO42

37

IO43

61

IO44

39

IO45

41

IO46

42

IO47

66

IO48

67

IO49

49

IO50

50

IO51

71

IO52

52

IO53

53

IO54

76

45

6

IO72

IO7 1

IO70

IO69

IO68

IO67

IO66

IO65

IO64

1

99

95

7

96

92

93

94

89

90

91

IO6 1

IO63

IO62

IO60

IO59

IO58

87

85

86

81

82

IO57

IO56

787977

IO55

AND ARE DISABLED USING JUMPERS ON T3 BRD

PORTS ARE ENABLED BY DEFAULT ON T1 BRD

63C 6<>62C6<>6 0C8 <>

63D 6<>62D6<>6 0C8 <>

7

OSC_A

61B 7<>

60B1<

T3ENH_T1ENLPRT1

T3ENH_T1ENLPRT2

T3ENH_T1ENLPRT2

8

V3_3

63D 6<> 62D 6<> 60A8< >

63C 6<> 62C 6<> 60A8< >

D

C C

B B

A A

T3ENH_T1ENLPRT1

3

JP17

JMP_3

3

JP19

JMP_3

8

D

1

09/16/2004

1

6/8(BLOCK)

61/71(TOTAL)

DATE:

60D2<56C7<

56D 8<>

JTCLK

2

48

TCK

UB04

XILINX_CPLD

3

60C2<56C7<

60C2<

56D 8<>

56D 8<>

JTMS

JTDT_NEXTCPLD

JTDOCPLD

83

45

47

TMS

TDI

TDO

21

NC<8-0 >

GND1

31

GND2

44

GND3

62

GND4

69

GND5

75

GND6

84

GND7

100

GND8

61B3>60B3>57C5>5 7C2>57A5>57A1>

61B4>60B4>57C5>57C2>57A5>57A1>

61B4>60B4>57C5>57C2>57A5>57A1>

61A3>60B3>60A3>5 7C5>57C2>57A5>57A1>

61B3>60B3>57C5>5 7C2>57A5>57A1>

57C8<57C5<57A8<57A4<61B4>60B4>

61B4>60B4>57C5>57C2>57A5>57A1>

61C4>60B4>57C5>57C2>57A5>57A1>

61B4>60B4>57C5>57C2>57A5>57A1>

61B3>60B3>60A3>5 7C5>57C2>57A5>57A1>

61B4>60B4>57C5>57C2>57A5>57A1>

57C8<57C5<57A8<57A4<61B4>60B4>

TITLE:

PAGE:

2

STEVE SCULLY

DS33Z11/41/44DK01A0

ENGINEER:

3

XILINX_XC9572XL

2.5V_3.3V 1

2.5V_3.3V 2

2.5V_3.3V 3

V3_3

4

56

Z44_TDEN<3>
Z44_RDEN<3>
Z44_TCLK<3>
Z44_RCLK<3>

63C2<>62C2<>

Z44_RSER<3>

Z44_TDEN<4>
Z44_RDEN<4>
Z44_TCLK<4>
Z44_RCLK<4>

63B2<>62B2<>

Z44_RSER<4>

38

88

51

26

30

R37

30

RB89

30

R38

30

RB90

Z44_TSER<3>

30

R36

30

R34

30

RB95

30

R33

30

RB91

Z44_TSER<4>

30

R35

3.3V2

3.3V1

2.5V_3.3V 4

5

TP10

TP22

TP11

TP23

TP09

TP21

11111 11

TP07

TP19

TP06

TP18

TP08

TP20

3.3V3

98

57

I79

NA

TINYTESTPOINT

20

27

IO19

IO18

23
22

11111

3

1
97
95
6
4
15
12
99
10
14
13
17
18
8

GCK2

IO17

GCK1

IO16

IO15

IO14

IO13

IO12

IO11

IO10

IO9

IO8

IO7

IO6

Z44 CONNECTIONS

IO5

IO4

IO3

IO2

IO1

60C 4<>

LOOPBACK_CTRL

NA

TP33

1

TE3_RCLK<4..1>39TE3_RSER<4..1>

TE3_RGAPCLK<4..1>

TE3_TCLK<4..1>

TE3_TGAPCLK<4..1>

TE3_TSER<4..1>

SPARE_TP3

16

IO20

IO2 1

GCK 3

1

1

1

1

1

1

33

30

61

29

IO24

IO23

IO22

IO25

IO26

74

42

60

IO27

IO28

IO29

TE3_RSER<4..1>

TE3_RGAPCLK<4..1>

TE3_RCLK<4..1>

3

3

3

71

72

54

40

IO30

IO3 1

IO32

IO33

UB03

XILINX_CPLD

XILINX_XC9572XL

TE3_TGAPCLK<4..1>

TE3_TSER<4..1>

TE3_TCLK<4..1>

3

3

3

36

70

50

IO34

IO35

IO36

IO37

32

IO38

55

IO39

56

IO40

58

IO41

59

IO42

35

IO43

37

IO44

63

IO45

64

IO46

65

IO47

66

IO48

67

IO49

68

IO50

41

IO51

49

IO52

52

IO53

53

IO54

76

45

6

IO72

IO7 1

IO70

IO69

IO68

IO67

IO66

IO65

IO64

25

28

87

7

96

92

93

94

89

90

91

IO6 1

IO63

IO62

IO60

9

85

82

86

IO57

IO59

81

IO56

IO58

79

IO55

78

77

63B 2<>6 2B2 <>6 1C8 <>

63C 2<>6 2C2 <>6 1C8 <>

7

OSC_A

60B 7<>

60B1<

T3ENH_T1ENLPRT4

T3ENH_T1ENLPRT3

T3ENH_T1ENLPRT4

8

V3_3

63B 2<> 62B 2<> 61A 8<>

63C 2<> 62C 2<> 61A 8<>

D

C C

B B

A A

T3ENH_T1ENLPRT3

3

JP16

JMP_3

3

JP18

JMP_3

8

D

63A1>

1

63C 8<>63C6<>6 3B3 <>

62C 8<>62C6<>6 2B3 <>

63C 8<>63C6<>6 3B3 <>

63A1>

09/16/2004

DATE:

1

7/8(BLOCK)

62/71(TOTAL)

PAGE:

SIG_RETURN

2

63C 2<>61C8<>6 1A8 <>

61D5<

61D5<

63C 2<>6 1D6 <>

63C 2<>

63C 2<>

63B 2<>61C8<>61A8 <>

63B 2<>6 1D7 <>

62C 8<>62C6<>

I35

61D6<

61D6<

63B 2<>

62A1>

63B 2<>

56B8<63A3>

GND

2

STEVE SCULLY

RD

63D 3<>

63D 3<>

ALE

CS_ X4

3

Z44_TSER<3>

T3ENH_T1ENLPRT3

Z44_TCLK<3>

Z44_TDEN<3>

Z44_TDEN<4>

Z44_TSER<4>

T3ENH_T1ENLPRT4

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

62B 7<>

Z44_TCLK<4>

SIG_RETURN

FPGAGC LK1 _NU

GND

GND

0

GND

DAT<7..0>

3

1

7

5

RW

63A 3<>

GND

GND

GND

DS33Z11/41/44DK01A0

TITLE:

ENGINEER:

3

3

1

2

J07

71

72

RECEPTACLE

4

56

P1 CONNECTOR (RECEPTICAL)

GND

CS_ X5

63D 4<>

63D5>56B8>

56A 6<>

T3_INT

I36

INT3

63D 6<>

4

73

747877

GND

63D 6<>

INT4

GND

6

5

767579

63D 7<>63D6<>62D7 <>

56B8<

63D 6<>

INT2

RESET_ B

7

8

9

V3_ 3

63D 6<>60C8<>60A8 <>

63D 6<>60D6<>

Z44_TSER<1>

T3ENH_T1ENLPRT1

GND

11

10

818384

80

GND

GND

14

13

12

159016

18

17

20

23

221921

262725

29

28

100

87

85

82

86

GND

GND

60D5<

60D5<

63C 6<>

63C 6<>

Z44_TCLK<1>

Z44_TDEN<1>

GND

92

932491

89

88

GND

V3_ 3

63C 8<>63C6<>6 3B3 <>

63A1>

62C 8<>6 2B3 <>

63C 6<>60C8<>6 0A8 <>

62A1>

T3ENH_T1ENLPRT2

SIG_RETURN

GND

GND

94

63C 6<>60D7<>

Z44_TSER<2>

959997

96

GND

Z44_RSER<3>

63C 5<>

61D6<

98

GND

Z44_RDEN<3>

63C 5<>

61D5<

60D6<

60D6<

63C 6<>

63C 6<>

Z44_TCLK<2>

Z44_TDEN<2>

GND

101

V3_ 3

GND

3230333134

103

102

Z44_RCLK<3>

63C 5<>

61D5<

35

36

39

38

37

40

42

41

43

105

109

106

104

GND

111

110

107

108

112

113

GND

GND

V3_ 3

Z44_RSER<4>

63B 5<>

46474954525051

45

44

114

115

116

GND

Z44_RDEN<4>

63B 5<>

48

118

117

5358565557

123

120

119

122

121

GND

GND

128

127

126

125

124

GND

V3_ 3

596260

129

OSC 1_N U

63A 4<>

130

61

131

GND

63

64

133

134

132

246

65

135

GND

Z44_RCLK<4>

63B 5<>

DAT<7..0>

61D6<

61D6<

61D7<

63A 5 63 A3 6 2A3 56 C3<>

63B 6<>56D6<>

63B 6<>56D7<>

ADDR<10..0>

3

1

586

TDO _NU

TCK _NU

GND

GND

GND

GND

GND

GND

GND

10

GND

70

69

66

68

67

136

140

139

138

137

V3_ 3

45

CS_X2

WR

CS_X3

63A 4<>

NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4

63A 4<>

CS

56B8<

63A 4<>

63A5< 56B7<

63A 6<>

GND

OSC 3_N U

GND

6

WAN R.C. CONNECTOR TO MOTHERBOARD

3

1

2

J10

71

72

VDD

7

8

P2 CONNECTOR (RECEPTICAL)

RECEPTACLE

GND

V3_ 3

GND

INT5

63D 7<>

4

73

747877

GND

INT2

63D 7<> 63D 6<> 62D6< >

6

5

767579

7

8

9

V3_ 3

SIG_RETURN

Z44_RSER<1>

62A1>

63D 8<>

60D6<

62C 6<> 62B 3<>

63A1>

11

10

818384

80

GND

Z44_RDEN<1>

63C 8<> 63C 6<>

14

13

12

82

63C 8<>

172219

159016

18

20

23

21

87

85

89

88

86

GND

GND

V3_ 3

Z44_RCLK<1>

63C 8<>

262725

29

28

100

94

959997

96

GND

Z44_RDEN<2>

98

GND

Z44_RCLK<2>

63C 8<>

63C 8<>

92

932491

GND

Z44_RSER<2>

63C 8<>

101

V3_ 3

3230333134

103

102

35

36

39

38

37

40

42

41

43

105

109

106

104

GND

111

110

107

108

112

113

GND

V3_ 3

GND

46474954525051

45

44

114

115

116

GND

48

118

117

5358565557

123

120

119

122

121

GND

GND

TDI _NU

FPGAGC LK1 _NU

62B 3<>

63B 7<> 56D6< >

124

TMS _NU

63B 7<> 56D6< >

126

125

V3_ 3

128

127

GND

024

596260

129

63

61

65

64

135

133

134

132

131

130

63A 763A662A6

GND

GND

56D4<

7

9

70

69

66

68

67

136

140

139

138

137

7

OSC 4_N U

OSC 2_N U

V3_ 3

63A 7<>

63A 7<>

ADDR<10..0>

60D6<

60D6<

60D5<

60D5<

60D7<

8

V3_3

63B 3<>

D

C C

B B

A A

D

62C 8<>62C6<>6 2B3 <>

1

63C 8<>63C6<>6 3B3 <>

63C 8<>63C6<>

62A1>

63A1>

62C 8<>6 2C6 <>6 2B3 <>

09/16/2004

DATE:

1

8/8(BLOCK)

63/71(TOTAL)

PAGE:

SIG_RETURN

2

62C 2<>61C8<>6 1A8 <>

62B 2<>61C8<>61A8 <>

I7

2

61D5<

61D5<

62C 2<>6 1D6 <>

62C 2<>

62C 2<>

62B 2<>6 1D7 <>

61D6<

61D6<

62B 2<>

62A1>

62B 2<>

56B8<62A3>

GND

STEVE SCULLY

RD

62D 3<>

62D 3<>

ALE

CS_ X4

3

GND

GND

GND

1

2345678

I8

3

1

5

4

2

GND

GND

101112131415161718

9

7

8

6

9

10

14

13

11

12

159016

17

GND

19

20212223242527

18

20

221921

Z44_TSER<3>

T3ENH_T1ENLPRT3

GND

268828

23

262725

28

PLUG

73

71

72

747877

JB05

72

71

4

P1 CONNECTOR (PLUG)

GND

767579

75

74

73

GND

818384

80

82

79

787776

82

81

80

GND

V3_ 3

87

85

86

8786858483

GND

GND

92

932491

89

88

929190

89

GND

V3_ 3

94

959493

959997

96

96

GND

98

Z44_TCLK<3>

Z44_TDEN<3>

GND

GND

101

101

102

V3_ 3

3230333134

103

102

104

103

35

35

36

105

106

104

106

105

GND

303132333436373839

29

29

100

999897

100

GND

Z44_TCLK<4>

Z44_TDEN<4>

Z44_TSER<4>

T3ENH_T1ENLPRT4

GND

4142434445464748495051525354555657585960616263646566676869

40

39

38

37

40

42

41

109

111

110

107

108

112

108

110

109

111

107

112

GND

GND

GND

43

113

114

113

V3_ 3

SIG_RETURN

GND

46474954525051

45

44

114

115

116

117

116

115

GND

GND

GND

48

118

117

119

118

5358565557

123

120

119

122

121

125

124

125

124

123

122

121

120

GND

GND

0

GND

596260

129

128

127

126

130

129

128

127

126

GND

V3_ 3

DAT<7..0>

3

1

GND

63

61

133

132

131

130

133

132

131

GND

I6

7

5

RW

62A 3<>

GND

GND

70

70

69

66

65

64

68

67

135

136

140

139

138

137

134

140

139

138

137

136

135

134

GND

V3_ 3

DS33Z11/41/44DK01A0

TITLE:

ENGINEER:

3

45

CS_ X5

62D 4<>

62D5>56B8>

63C 8<>63B3<>

Z44_RDEN<3>

Z44_RSER<3>

62C 5<>

63A1>

61D6<

62C 8<>62C6<>62B3 <>

Z44_RCLK<3>

62C 5<>

62C 5<>

61D5<

61D5<

Z44_RSER<4>

62B 5<>

61D7<

Z44_RCLK<4>

Z44_RDEN<4>

62B 5<>

62B 5<>

61D6<

61D6<

OSC 1_N U

62A 4<>

56

56A 6<>

T3_INT

62D 6<>

I14

PLUG STYLE CONNECTORS GO ON BOTTOM OF T3E3 WAN CARD

INT4

DS21458 CONNECTS TO MOTHERBOARD BY STACKING ONTO T3E3 BRD

I25

INT3

62D 6<>

GND

1

2345678

3

1

2

62D 6<>60C8<>60A8 <>

60D5<

60D5<

62C 6<>

63D 7<>62D7<>62D6 <>

56B8<

62D 6<>

INT2

RESET_ B

62C 6<>

Z44_TCLK<1>

Z44_TDEN<1>

T3ENH_T1ENLPRT1

GND

GND

101112131415161718

9

7

8

6

9

5

4

11

10

GND

14

13

12

159016

62C 6<>60C8<>6 0A8 <>

T3ENH_T1ENLPRT2

GND

19

20212223242527

172219

18

20

21

60D6<

60D6<

62C 6<>60D7<>

62C 6<>

62C 6<>

62A1>

62B 6<>56D6<>

62B 6<>56D7<>

3

TDO _NU

TCK _NU

GND

5358565557

1

Z44_TCLK<2>

Z44_TDEN<2>

Z44_TSER<2>

SIG_RETURN

GND

23

GND

303132333436373839

268828

29

262725

29

28

GND

GND

3230333134

35

35

GND

4142434445464748495051525354555657585960616263646566676869

40

36

39

38

37

40

41

42

44

43

46474954525051

45

GND

GND

GND

48

685

GND

596260

61

CS_X2

4

6

2

DAT<7..0>

WR

CS_X3

62A 4<>

I13

62A 4<>

NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4

CS

56B8<

62A 4<>

62A5< 56B7<

63A 3 62 A5 6 2A3 56 C3<>

ADDR<10..0>

GND

63

64

62A 6<>

10

GND

OSC 3_N U

GND

6

WAN R.C. CONNECTOR TO MOTHERBOARD

70

70

69

66

65

68

67

PLUG

73

71

72

747877

JB06

VDD

72

7

8

P2 CONNECTOR (PLUG)

GND

V3_ 3

I17

I15

71

GND

767579

76

75

74

73

GND

INT2

INT5

62D 7<>

63D 6<> 62D 7<> 62D6< >

818384

80

82

797877

81

80

GND

V3_ 3

SIG_RETURN

Z44_RSER<1> Z44_TSER<1>

Z44_RDEN<1>

62A1>

62D 8<> 62D 6<>60D6<>

62C 8<>

63C 6<> 63B 3<>

60D6<

60D5<

62C 8<> 62C6< > 62B3< >

87

85

86

87

8685848382

GND

GND

Z44_RCLK<1>

62C 8<>

60D5<

92

932491

89

88

V3_ 3

94

959997

GND

GND

Z44_RSER<2>

62C 8<>

60D7<

100

98

96

9998979695949392919089

101

100

GND

Z44_RCLK<2>

Z44_RDEN<2>

62C 8<>

62C 8<>

60D6<

60D6<

105

101

104

103

102

105

104

103

102

GND

V3_ 3

109

106

107

108

108

110

109

107

106

GND

114

111

115

118

117

110

111

112

GND

116

112

113

114

113

V3_ 3

119

118

117

116

115

GND

123

120

119

122

121

125

124

126

125

124

123

122

121

120

GND

GND

V3_ 3

TMS _NU

TDI _NU

62B 7<> 56D6< >

62B 7<> 56D6< >

130

129

128

127

126

131

130

129

128

127

GND

62A 762A 6

4

2

0

135

133

136

140

139

138

137

134

132

131

140

139

138

137

136

135

134

133

132

GND

GND

OSC 4_N U

OSC 2_N U

63A 6

56D4<

7

V3_ 3

9

62A 7<>

62A 7<>

7

ADDR<10..0>

8

V3_3

63A1>

D

C C

B B

A A