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Ethernet Mapper with Integrated
GENERAL DESCRIPTION
The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
FUNCTIONAL DIAGRAM
SERIAL STREAM
T1/E1/J1
TRANSCEIVER
T1/E1
LINE
DS33R11
T1/E1/J1 Transceive
FEATURES
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control
Integrated T1/E1/J1 Framer and LIU
HDLC/LAPS Encapsulation with
Programmable FCS and Interframe Fill
Committed Information Rate Controller
Provides Fractional Allocations in 512kbps
Increments
Programmable BERT for Serial (TDM)
Interface
External 16MB, 100MHz SDRAM Buffering
Parallel Microprocessor Interface
1.8V, 3.3V Supplies
Reference Design Routes on Two Signal
Layers
IEEE 1149.1 JTAG Support
Features continued on page 11.
BERT
HDLC/X.86
MAPPER
10/100
MAC
MII/RMII
μC
SDRAM
10/100
ETHERNET
PHY
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS33R11 -40°C to +85°C 256 BGA
DS33R11
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 030807
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TABLE OF CONTENTS
1 DESCRIPTION ................................................................................................................................... 9
2 FEATURE HIGHLIGHTS.................................................................................................................. 11
2.1 GENERAL...................................................................................................................................... 11
2.2 MICROPROCESSOR INTERFACE...................................................................................................... 11
2.3 HDLC ETHERNET MAPPING .......................................................................................................... 11
2.4 X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING....................................... 11
2.5 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER ............................ 12
2.6 COMMITTED INFORMATION RATE (CIR) CONTROLLER .................................................................... 12
2.7 SDRAM INTERFACE...................................................................................................................... 12
2.8 MAC INTERFACE........................................................................................................................... 12
2.9 T1/E1/J1 LINE INTERFACE ............................................................................................................ 13
2.10 CLOCK SYNTHESIZER .................................................................................................................... 13
2.11 JITTER ATTENUATOR..................................................................................................................... 13
2.12 T1/E1/J1 FRAMER ........................................................................................................................14
2.13 TDM BUS ..................................................................................................................................... 14
2.14 TEST AND DIAGNOSTICS ................................................................................................................ 15
2.15 SPECIFICATIONS COMPLIANCE....................................................................................................... 16
3 APPLICATIONS ............................................................................................................................... 17
4 ACRONYMS AND GLOSSARY ....................................................................................................... 18
5 MAJOR OPERATING MODES ........................................................................................................ 19
6 BLOCK DIAGRAMS......................................................................................................................... 20
7 PIN DESCRIPTIONS........................................................................................................................ 25
7.1 PIN FUNCTIONAL DESCRIPTION...................................................................................................... 25
8 FUNCTIONAL DESCRIPTION ......................................................................................................... 41
8.1 PROCESSOR INTERFACE ............................................................................................................... 42
8.1.1 Read-Write/Data Strobe Modes............................................................................................................42
8.1.2 Clear on Read.......................................................................................................................................42
8.1.3 Interrupt and Pin Modes........................................................................................................................42
9 ETHERNET MAPPER ...................................................................................................................... 43
9.1 ETHERNET MAPPER CLOCKS......................................................................................................... 43
9.1.1 Ethernet Interface Clock Modes............................................................................................................45
9.1.2 Serial Interface Clock Modes................................................................................................................45
9.2 RESETS AND LOW POWER MODES................................................................................................. 46
9.3 INITIALIZATION AND CONFIGURATION.............................................................................................. 47
9.4 GLOBAL RESOURCES .................................................................................................................... 47
9.5 PER-PORT RESOURCES ................................................................................................................ 47
9.6 DEVICE INTERRUPTS ..................................................................................................................... 48
9.7 INTERRUPT INFORMATION REGISTERS ........................................................................................... 50
9.8 STATUS REGISTERS ...................................................................................................................... 50
9.9 INFORMATION REGISTERS ............................................................................................................. 50
9.10 SERIAL INTERFACE ........................................................................................................................ 50
9.11 CONNECTIONS AND QUEUES ......................................................................................................... 51
9.12 ARBITER .......................................................................................................................................52
9.13 FLOW CONTROL............................................................................................................................ 53
9.13.1 Full Duplex Flow Control.......................................................................................................................54
9.13.2 Half Duplex Flow Control......................................................................................................................55
9.13.3 Host-Managed Flow Control.................................................................................................................55
9.14 ETHERNET INTERFACE PORT......................................................................................................... 56
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.14.1 DTE and DCE Mode .............................................................................................................................58
9.15 ETHERNET MAC ........................................................................................................................... 59
9.15.1 MII Mode Options..................................................................................................................................61
9.15.2 RMII Mode.............................................................................................................................................61
9.15.3 PHY MII Management Block and MDIO Interface................................................................................62
9.16 BERT IN THE ETHERNET MAPPER ................................................................................................. 62
9.16.1 Receive Data Interface .........................................................................................................................63
9.16.2 Repetitive Pattern Synchronization.......................................................................................................64
9.16.3 Pattern Monitoring.................................................................................................................................64
9.16.4 Pattern Generation................................................................................................................................64
9.17 TRANSMIT PACKET PROCESSOR .................................................................................................... 65
9.18 RECEIVE PACKET PROCESSOR ...................................................................................................... 66
9.19 X.86 ENCODING AND DECODING.................................................................................................... 68
9.20 COMMITTED INFORMATION RATE CONTROLLER .............................................................................. 71
10 INTEGRATED T1/E1/J1 TRANSCEIVER ........................................................................................ 72
10.1 T1/E1/J1 CLOCKS ........................................................................................................................ 72
10.2 PER-CHANNEL OPERATION............................................................................................................ 73
10.3 T1/E1/J1 TRANSCEIVER INTERRUPTS ............................................................................................ 73
10.4 T1 FRAMER/FORMATTER CONTROL AND STATUS ........................................................................... 74
10.4.1 T1 Transmit Transparency....................................................................................................................74
10.4.2 AIS-CI and RAI-CI Generation and Detection ......................................................................................74
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................75
10.5 E1 FRAMER/FORMATTER CONTROL AND STATUS........................................................................... 76
10.5.1 Automatic Alarm Generation.................................................................................................................77
10.6 PER-CHANNEL LOOPBACK ............................................................................................................. 77
10.7 ERROR COUNTERS........................................................................................................................ 78
10.7.1 Line-Code Violation Counter (TR.LCVCR)...........................................................................................78
10.7.2 Path Code Violation Count Register (TR.PCVCR)...............................................................................79
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) ..............................................................................80
10.7.4 E-Bit Counter (TR.EBCR).....................................................................................................................80
10.8 DS0 MONITORING FUNCTION ........................................................................................................ 81
10.9 SIGNALING OPERATION ................................................................................................................. 82
10.9.1 Processor-Based Receive Signaling ....................................................................................................82
10.9.2 Hardware-Based Receive Signaling.....................................................................................................83
10.9.3 Processor-Based Transmit Signaling ...................................................................................................84
10.9.4 Hardware-Based Transmit Signaling....................................................................................................85
10.10 PER-CHANNEL IDLE CODE GENERATION ........................................................................................86
10.10.1 Idle-Code Programming Examples.......................................................................................................87
10.11 CHANNEL BLOCKING REGISTERS ...................................................................................................88
10.12 ELASTIC STORES OPERATION........................................................................................................ 88
10.12.1 Receive Elastic Store............................................................................................................................88
10.12.2 Transmit Elastic Store...........................................................................................................................89
10.12.3 Elastic Stores Initialization....................................................................................................................89
10.12.4 Minimum Delay Mode...........................................................................................................................89
10.13 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)............................................................ 90
10.14 T1 BIT-ORIENTED CODE (BOC) CONTROLLER ............................................................................... 91
10.14.1 Transmit BOC.......................................................................................................................................91
10.15 RECEIVE BOC .............................................................................................................................. 91
10.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)........................................... 92
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................92
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe.......................................................92
10.17 ADDITIONAL HDLC CONTROLLERS IN T1/E1/J1 TRANSCEIVER ....................................................... 93
10.17.1 HDLC Configuration..............................................................................................................................93
10.17.2 FIFO Control.........................................................................................................................................95
10.17.3 HDLC Mapping......................................................................................................................................95
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.17.4 FIFO Information...................................................................................................................................96
10.17.5 Receive Packet-Bytes Available...........................................................................................................96
10.18 LEGACY FDL SUPPORT (T1 MODE) ............................................................................................... 97
10.18.1 Overview...............................................................................................................................................97
10.18.2 Receive Section....................................................................................................................................97
10.18.3 Transmit Section...................................................................................................................................98
10.19 D4/SLC-96 OPERATION................................................................................................................ 98
10.20 PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............................................ 99
10.21 LINE INTERFACE UNIT (LIU)......................................................................................................... 100
10.21.1 LIU Operation......................................................................................................................................100
10.21.2 Receiver..............................................................................................................................................100
10.21.3 Transmitter..........................................................................................................................................102
10.22 MCLK PRESCALER ..................................................................................................................... 103
10.23 JITTER ATTENUATOR................................................................................................................... 103
10.24 CMI (CODE MARK INVERSION) OPTION........................................................................................ 103
10.25 RECOMMENDED CIRCUITS ........................................................................................................... 104
10.26 T1/E1/J1 TRANSCEIVER BERT FUNCTION ...........................................................................108
10.26.1 BERT Status .......................................................................................................................................108
10.26.2 BERT Mapping....................................................................................................................................108
10.26.3 BERT Repetitive Pattern Set..............................................................................................................110
10.26.4 BERT Bit Counter................................................................................................................................110
10.26.5 BERT Error Counter............................................................................................................................110
10.26.6 BERT Alternating Word-Count Rate...................................................................................................110
10.27 PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) ...........................................................111
10.27.1 Number-of-Errors Registers................................................................................................................111
10.28 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER..................................................................... 112
10.29 FRACTIONAL T1/E1 SUPPORT ..................................................................................................... 112
10.30 T1/E1/J1 TRANSMIT FLOW DIAGRAMS ......................................................................................... 113
11 DEVICE REGISTERS..................................................................................................................... 117
11.1 REGISTER BIT MAPS ................................................................................................................... 118
11.1.1 Global Ethernet Mapper Register Bit Map..........................................................................................118
11.1.2 Arbiter Register Bit Map......................................................................................................................119
11.1.3 BERT Register Bit Map.......................................................................................................................119
11.1.4 Serial Interface Register Bit Map........................................................................................................120
11.1.5 Ethernet Interface Register Bit Map....................................................................................................122
11.1.6 MAC Register Bit Map ........................................................................................................................123
11.2 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER............................................................ 134
11.3 ARBITER REGISTERS ................................................................................................................... 143
11.3.1 Arbiter Register Bit Descriptions.........................................................................................................143
11.4 BERT REGISTERS ...................................................................................................................... 144
11.5 SERIAL INTERFACE REGISTERS.................................................................................................... 151
11.5.1 Serial Interface Transmit and Common Registers..............................................................................151
11.5.2 Serial Interface Transmit Register Bit Descriptions............................................................................151
11.5.3 Transmit HDLC Processor Registers..................................................................................................152
11.5.4 X.86 Registers.....................................................................................................................................159
11.5.5 Receive Serial Interface......................................................................................................................161
11.6 ETHERNET INTERFACE REGISTERS .............................................................................................. 174
11.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................174
11.6.2 MAC Registers....................................................................................................................................186
11.7 T1/E1/J1 TRANSCEIVER REGISTERS ........................................................................................... 201
11.7.1 Number-of-Errors Left Register...........................................................................................................299
12 FUNCTIONAL TIMING................................................................................................................... 300
12.1 FUNCTIONAL SERIAL I/O TIMING .................................................................................................. 300
12.2 MII AND RMII INTERFACES .......................................................................................................... 301
12.3 TRANSCEIVER T1 MODE FUNCTIONAL TIMING .............................................................................. 303
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
12.4 E1 MODE.................................................................................................................................... 308
13 OPERATING PARAMETERS ........................................................................................................ 313
13.1 THERMAL CHARACTERISTICS ....................................................................................................... 314
13.2 MII INTERFACE............................................................................................................................ 315
13.3 RMII INTERFACE ......................................................................................................................... 317
13.4 MDIO INTERFACE ....................................................................................................................... 319
13.5 TRANSMIT WAN INTERFACE ........................................................................................................ 320
13.6 RECEIVE WAN INTERFACE .......................................................................................................... 321
13.7 SDRAM TIMING.......................................................................................................................... 322
13.8 MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................... 324
13.9 AC CHARACTERISTICS: RECEIVE-SIDE ........................................................................................ 327
13.10 AC CHARACTERISTICS: BACKPLANE CLOCK TIMING ..................................................................... 331
13.11 AC CHARACTERISTICS: TRANSMIT SIDE....................................................................................... 332
13.12 JTAG INTERFACE TIMING ............................................................................................................ 335
14 JTAG INFORMATION.................................................................................................................... 336
14.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION............................................................. 337
14.2 INSTRUCTION REGISTER.............................................................................................................. 339
14.3 JTAG ID CODES......................................................................................................................... 341
14.4 TEST REGISTERS ........................................................................................................................ 341
14.4.1 Boundary Scan Register.....................................................................................................................341
14.4.2 Bypass Register..................................................................................................................................341
14.4.3 Identification Register .........................................................................................................................341
14.5 JTAG FUNCTIONAL TIMING ......................................................................................................... 342
15 PACKAGE INFORMATION............................................................................................................ 343
15.1 PACKAGE OUTLINE DRAWING OF 256-BGA (VIEW FROM BOTTOM OF DEVICE).............................. 343
16 DOCUMENT REVISION HISTORY ................................................................................................ 344
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17
Figure 6-1. Main Block Diagram ................................................................................................................................20
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver ................................................................................................. 21
Figure 6-3. Receive and Transmit T1/E1/J1 LIU ....................................................................................................... 22
Figure 6-4. Receive and Transmit T1/E1/J1 Framer ................................................................................................. 23
Figure 6-5. T1/E1/J1 Backplane Interface ................................................................................................................. 24
Figure 7-1. 256-Ball BGA Pinout ............................................................................................................................... 40
Figure 9-1. Clocking for the DS33R11....................................................................................................................... 44
Figure 9-2. Device Interrupt Information Flow Diagram ............................................................................................ 49
Figure 9-3. Flow Control Using Pause Control Frame .............................................................................................. 55
Figure 9-4. IEEE 802.3 Ethernet Frame .................................................................................................................... 56
Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode ........................................................... 58
Figure 9-6. DS33R11 Configured as a DCE in MII Mode.......................................................................................... 59
Figure 9-7. RMII Interface.......................................................................................................................................... 61
Figure 9-8. MII Management Frame.......................................................................................................................... 62
Figure 9-9. PRBS Synchronization State Diagram.................................................................................................... 63
Figure 9-10. Repetitive Pattern Synchronization State Diagram............................................................................... 64
Figure 9-11. HDLC Encapsulation of MAC Frame .................................................................................................... 67
Figure 9-12. LAPS Encoding of MAC Frames Concept ............................................................................................ 68
Figure 9-13. X.86 Encapsulation of the MAC frame.................................................................................................. 69
Figure 10-1. T1/E1/J1 Clock Map.............................................................................................................................. 72
Figure 10-2. Simplified Diagram of Receive Signaling Path...................................................................................... 82
Figure 10-3. Simplified Diagram of Transmit Signaling Path..................................................................................... 84
Figure 10-4. CRC-4 Recalculate Method .................................................................................................................. 90
Figure 10-5. Typical Monitor Application ................................................................................................................. 101
Figure 10-6. CMI Coding ......................................................................................................................................... 103
Figure 10-7. Basic Interface..................................................................................................................................... 104
Figure 10-8. E1 Transmit Pulse Template............................................................................................................... 105
Figure 10-9. T1 Transmit Pulse Template ............................................................................................................... 105
Figure 10-10. Jitter Tolerance ................................................................................................................................. 106
Figure 10-11. Jitter Tolerance (E1 Mode)................................................................................................................ 106
Figure 10-12. Jitter Attenuation (T1 Mode).............................................................................................................. 107
Figure 10-13. Jitter Attenuation (E1 Mode) ............................................................................................................. 107
Figure 10-14. Optional Crystal Connections ........................................................................................................... 108
Figure 10-15. Simplified Diagram of BERT in Network Direction............................................................................ 109
Figure 10-16. Simplified Diagram of BERT in Backplane Direction ........................................................................ 109
Figure 10-17. T1/J1 Transmit Flow Diagram........................................................................................................... 113
Figure 10-18. E1 Transmit Flow Diagram................................................................................................................ 115
Figure 12-1. Tx Serial Interface Functional Timing ................................................................................................. 300
Figure 12-2. Rx Serial Interface Functional Timing ................................................................................................. 300
Figure 12-3. Transmit Byte Sync Functional Timing ............................................................................................... 301
Figure 12-4. Receive Byte Sync Functional Timing ................................................................................................ 301
Figure 12-5. MII Transmit Functional Timing........................................................................................................... 301
Figure 12-6. MII Transmit Half Duplex with a Collision Functional Timing.............................................................. 302
Figure 12-7. MII Receive Functional Timing............................................................................................................ 302
Figure 12-8. RMII Transmit Interface Functional Timing ......................................................................................... 302
Figure 12-9. RMII Receive Interface Functional Timing .......................................................................................... 303
Figure 12-10. Receive-Side D4 Timing ................................................................................................................... 303
Figure 12-11. Receive-Side ESF Timing ................................................................................................................. 303
Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled).................................................................. 304
Figure 12-13. Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................. 304
Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................. 305
Figure 12-15. Transmit-Side D4 Timing .................................................................................................................. 305
Figure 12-16. Transmit-Side ESF Timing ................................................................................................................ 306
Figure 12-17. Transmit-Side Boundary Timing (with Elastic Store Disabled) ......................................................... 306
Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)................................................ 307
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................ 307
Figure 12-20. Receive-Side Timing ......................................................................................................................... 308
Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) .......................................................... 308
Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled)................................... 309
Figure 12-23. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (E-Store Enabled)................................... 309
Figure 12-24. G.802 Timing, E1 Mode Only............................................................................................................ 310
Figure 12-25. Transmit-Side Timing ........................................................................................................................ 310
Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled)................................................................. 311
Figure 12-27. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) ......................... 311
Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) .......................... 312
Figure 13-1. Transmit MII Interface Timing ............................................................................................................. 315
Figure 13-2. Receive MII Interface Timing .............................................................................................................. 316
Figure 13-3. Transmit RMII Interface Timing........................................................................................................... 317
Figure 13-4. Receive RMII Interface Timing............................................................................................................ 318
Figure 13-5. MDIO Interface Timing ........................................................................................................................ 319
Figure 13-6. Transmit WAN Interface Timing.......................................................................................................... 320
Figure 13-7. Receive WAN Interface Timing........................................................................................................... 321
Figure 13-8. SDRAM Interface Timing .................................................................................................................... 323
Figure 13-9. Intel Bus Read Timing (MODEC = 00)................................................................................................ 325
Figure 13-10. Intel Bus Write Timing (MODEC = 00).............................................................................................. 325
Figure 13-11. Motorola Bus Read Timing (MODEC = 01) ...................................................................................... 326
Figure 13-12. Motorola Bus Write Timing (MODEC = 01)....................................................................................... 326
Figure 13-13. Receive-Side Timing ......................................................................................................................... 328
Figure 13-14. Receive-Side Timing, Elastic Store Enabled .................................................................................... 329
Figure 13-15. Receive Line Interface Timing .......................................................................................................... 330
Figure 13-16. Receive Timing Delay RCLKO to BPCLK......................................................................................... 331
Figure 13-17. Transmit-Side Timing ........................................................................................................................ 333
Figure 13-18. Transmit-Side Timing, Elastic Store Enabled ................................................................................... 334
Figure 13-19. Transmit Line Interface Timing ......................................................................................................... 334
Figure 13-20. JTAG Interface Timing Diagram ....................................................................................................... 335
Figure 14-1. JTAG Functional Block Diagram......................................................................................................... 336
Figure 14-2. TAP Controller State Diagram............................................................................................................. 339
Figure 14-3. JTAG Functional Timing...................................................................................................................... 342
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LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 25
Table 9-1. Clocking Options for the Ethernet Interface ............................................................................................. 43
Table 9-2. Reset Functions........................................................................................................................................ 46
Table 9-3. Registers Related to Connections and Queues....................................................................................... 52
Table 9-4. Options for Flow Control........................................................................................................................... 53
Table 9-5. Registers Related to Setting the Ethernet Port ........................................................................................ 57
Table 9-6. MAC Control Registers............................................................................................................................. 60
Table 9-7. MAC Status Registers .............................................................................................................................. 60
Table 10-1. T1/E1/J1 Transmit Clock Source ........................................................................................................... 73
Table 10-2. T1 Alarm Criteria .................................................................................................................................... 75
Table 10-3. E1 Sync/Resync Criteria ........................................................................................................................ 76
Table 10-4. E1 Alarm Criteria .................................................................................................................................... 77
Table 10-5 T1 Line Code Violation Counting Options ............................................................................................... 78
Table 10-6. E1 Line-Code Violation Counting Options.............................................................................................. 78
Table 10-7. T1 Path Code Violation Counting Arrangements ................................................................................... 79
Table 10-8. T1 Frames Out-of-Sync Counting Arrangements .................................................................................. 80
Table 10-9. Time Slot Numbering Schemes.............................................................................................................. 85
Table 10-10. Idle-Code Array Address Mapping ....................................................................................................... 86
Table 10-11. Elastic Store Delay After Initialization .................................................................................................. 89
Table 10-12. HDLC Controller Registers................................................................................................................... 94
Table 10-13. Transformer Specifications................................................................................................................. 104
Table 10-14. Transmit Error-Insertion Setup Sequence.......................................................................................... 111
Table 10-15. Error Insertion Examples.................................................................................................................... 111
Table 11-1. Register Address Map.......................................................................................................................... 117
Table 11-2. Global Ethernet Mapper Register Bit Map ........................................................................................... 118
Table 11-3. Arbiter Register Bit Map ....................................................................................................................... 119
Table 11-4. BERT Register Bit Map ........................................................................................................................ 119
Table 11-5. Serial Interface Register Bit Map.......................................................................................................... 120
Table 11-6. Ethernet Interface Register Bit Map ..................................................................................................... 122
Table 11-7. MAC Indirect Register Bit Map ............................................................................................................. 123
Table 11-8. T1/E1/J1 Transceiver Register Bit Map (Active when CST = 0) .......................................................... 125
Table 13-1. Recommended DC Operating Conditions............................................................................................ 313
Table 13-2. DC Electrical Characteristics................................................................................................................ 313
Table 13-3. Thermal Characteristics ....................................................................................................................... 314
Table 13-4. Theta-JA vs. Airflow ............................................................................................................................. 314
Table 13-5. Transmit MII Interface .......................................................................................................................... 315
Table 13-6. Receive MII Interface ........................................................................................................................... 316
Table 13-7. Transmit RMII Interface........................................................................................................................ 317
Table 13-8. Receive RMII Interface......................................................................................................................... 318
Table 13-9. MDIO Interface ..................................................................................................................................... 319
Table 13-10. Transmit WAN Interface ..................................................................................................................... 320
Table 13-11. Receive WAN Interface ...................................................................................................................... 321
Table 13-12. SDRAM Interface Timing.................................................................................................................... 322
Table 13-13. AC Characteristics—Microprocessor Bus Timing .............................................................................. 324
Table 13-14. AC Characteristics: Receive Side ...................................................................................................... 327
Table 13-15. AC Characteristics: Backplane Clock Synthesis................................................................................ 331
Table 13-16. AC Characteristics: Transmit Side ..................................................................................................... 332
Table 13-17. JTAG Interface Timing ....................................................................................................................... 335
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture .................................................................................. 340
Table 14-2. ID Code Structure................................................................................................................................. 341
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
1 DESCRIPTION
The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet
Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports,
Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver. The packet interface consists of a MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The
T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet ports. Access is provided to the signals between the Serial port and the integrated T1/E1/J1 Transceiver.
The device includes a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul
applications. The transceiver is composed of an LIU, framer, and two additional HDLC controllers. The transceiver
is software compatible with the DS2155 and DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible
for generating the necessary waveshapes for driving the network and providing the correct source impedance
depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line
build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax
and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the
network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB
or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be
placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for
interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up
and loop-down code generation and detection.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data
through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a
time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of
processor overhead required to manage the flow of data. In addition, built-in support for reducing the processor
time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface).
An 8-bit parallel microcontroller port provides access for control and configuration of all the features of the device.
The internal 100MHz SDRAM controller interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer
the data from the Ethernet and WAN ports for transport. The external SDRAM can accommodate up to 8192
frames with a maximum frame size of 2016 bytes. Diagnostic capabilities include SDRAM BIST, loopbacks, PRBS
pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection. The DS33R11
operates with a 1.8V core supply and 3.3V I/O supply.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethernet mapper. There are a few things
to note when porting a DS33Z11 application to this device:
• The SPI and hardware modes are not supported.
• RSER has been renamed to RSERI.
• RCLK has been renamed to RCLKI.
• TSER has been renamed to TSERO.
• TCLK has been renamed to TCLKE.
The integrated T1/E1/J1 transceiver is software compatible with the DS2155 T1/E1/J1 transceiver. There are a few
things to note when porting a DS2155 application to this device:
• The Facilities Data Link (FDL) support is available through software only. The TLINK, RLINK, TLCLK,
RLCLK pins are not available on the DS33R11.
• Multiplexed Microprocessor Bus mode is not supported on the DS33R11.
• The Extended System Information Bus (ESIB) is not supported on the DS33R11.
• The MODEC pins serve the function of the DS2155’s BTS pin.
• The interim LIU/Framer clock signals RCLKI, RCLKO have been renamed to RDCLKI, RDCLKO to avoid
confusion with the receive clock connections between the transceiver and the Ethernet mapper.
• The interim LIU/Framer clock signals TCLKI, TCLKO have been renamed to TDCLKI, TDCLKO to avoid
confusion with the receive clock connections between the transceiver and the Ethernet mapper.
• RSER has been renamed RSERO.
• RCLK has been renamed RCLKO.
• TSER has been renamed TSERI.
• TCLK has been renamed TCLKT.
10 of 344
2 FEATURE HIGHLIGHTS
2.1 General
• 256-pin, 27mm BGA package
• 1.8V and 3.3V supplies
• IEEE 1149.1 JTAG boundary scan
• Software access to device ID and silicon revision
• Development support includes evaluation kit, driver source code, and reference designs
• Reference design routes on a two-layer PC board
• Programmable output clocks for fractional T1, E1, H0, and H12 applications
2.2 Microprocessor Interface
• Parallel control port with 8-bit data bus
• Nonmultiplexed Intel and Motorola timing modes
• Internal software reset and external hardware reset-input pin
• Supports polled or interrupt-driven environments
• Software access to device ID and silicon revision
• Global interrupt-output pin
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.3 HDLC Ethernet Mapping
• Dedicated HDLC controller engine for protocol encapsulation
• Compatible with polled or interrupt driven environments
• Programmable FCS insertion and extraction
• Programmable FCS type
• Supports FCS error insertion
• Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)
• Supports bit stuffing/destuffing
• Selectable packet scrambling/descrambling (X
• Separate FCS errored packet and aborted packet counts
• Programmable inter-frame fill for transmit HDLC
43
+1)
2.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping
• Programmable X.86 address/control fields for transmit and receive
• Programmable 2-byte protocol (SAPI) field for transmit and receive
• 32 bit FCS
• Transmit transparency processing—7E is replaced by 7D, 5E
• Transmit transparency processing—7D replaced by 7D, 5D
• Receive rate adaptation (7D, DD) is deleted.
• Receive transparency processing—7D, 5E is replaced by 7E
• Receive transparency processing—7D, 5D is replaced by 7D
• Receive abort sequence the LAPS packet is dropped if 7D7E is detect
• Self-synchronizing X
• Frame indication due to bad address/control/SAPI, FCS error, abort sequence or frame size longer
than preset max
43
+1 payload scrambling.
11 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver
• Two additional independent HDLC controllers
• Fast load and unload features for FIFOs
• SS7 support for FISU transmit and receive
• Independent 128-byte Rx and Tx buffers with interrupt support
• Access FDL, Sa, or single/multiple DS0 channels
• DS0 access includes Nx64 or Nx56
• Compatible with polled or interrupt driven environments
• Bit-oriented code (BOC) support
2.6 Committed Information Rate (CIR) Controller
• CIR Rate controller limits transmission of data from the Ethernet interface to the serial interface
• CIR granularity at 512kbit/s
• CIR averaging for smoothing traffic peaks
2.7 SDRAM Interface
• Interface for 128Mb, 32-bit-wide SDRAM
• SDRAM Interface speed up to 100MHz
• Auto refresh timing
• Automatic precharge
• Master clock provided to the SDRAM
• No external components required for SDRAM connectivity
2.8 MAC Interface
• MAC port with standard MII (less TX_ER) or RMII
• 10Mbps and 100Mbps Data rates
• Configurable DTE or DCE modes
• Facilitates auto-negotiation by host microprocessor
• Programmable half and full-duplex modes
• Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes
• Programmable Maximum MAC frame size up to 2016 bytes
• Minimum MAC frame size: 64 bytes
• Discards frames greater than programmed maximum MAC frame size and runt, nonoctet bounded, or
bad-FCS frames upon reception
• Configurable for promiscuous broadcast-discard mode.
• Programmable threshold for SDRAM queues to initiate flow control and status indication
• MAC loopback support for transmit data looped to receive data at the MII/RMII interface
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2.9 T1/E1/J1 Line Interface
• Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz
for T1 operation
• Fully software configurable
• Short-haul and long-haul applications
• Automatic receive sensitivity adjustments
• Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1
applications
• Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
• Internal receive termination option for 75Ω, 100Ω, and 120Ω lines
• Internal transmit termination option for 75Ω, 100Ω, and 120Ω lines
• Monitor application gain settings of 20dB, 26dB, and 32dB
• G.703 receive synchronization-signal mode
• Flexible transmit waveform generation
• T1 DSX-1 line build-outs
• T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
• E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
• AIS generation independent of loopbacks
• Alternating ones and zeros generation
• Square-wave output
• Open-drain output option
• NRZ format option
• Transmitter power-down
• Transmitter 50mA short-circuit limiter with current-limit-exceeded indication
• Transmit open-circuit-detected indication
• Line interface function can be completely decoupled from the framer/formatter
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.10 Clock Synthesizer
• Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
• Derived from recovered receive clock
2.11 Jitter Attenuator
• 32-bit or 128-bit crystal-less jitter attenuator
• Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz
for T1 operation
• Can be placed in either the receive or transmit path or disabled
• Limit trip indication
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2.12 T1/E1/J1 Framer
• Fully independent transmit and receive functionality
• Full receive and transmit path transparency
• T1 framing formats include D4 (SLC-96) and ESF
• Detailed alarm and status reporting with optional interrupt support
• Large path and line error counters for:
o T1: BPV, CV, CRC6, and framing bit errors
o E1: BPV, CV, CRC4, E-bit, and frame alignment errors
• Timed or manual update modes
• DS1 idle code generation on a per-channel basis in both transmit and receive paths
o User-defined
o Digital milliwatt
• ANSI T1.403-1998 Support
• RAI-CI detection and generation
• AIS-CI detection and generation
• E1 ETS 300 011 RAI generation
• G.965 V5.2 link detect
• Ability to monitor one DS0 channel in both the transmit and receive paths
• In-band repeating pattern generators and detectors
o Three independent generators and detectors
o Patterns from 1 to 8 bits or 16 bits in length
• RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state
• Flexible signaling support
o Software or hardware based
o Interrupt generated on change of signaling data
o Receive signaling freeze on loss-of-sync, carrier loss, or frame slip
• Addition of hardware pins to indicate carrier loss and signaling freeze
• Automatic RAI generation to ETS 300 011 specifications
• Access to Sa and Si bits
• Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
• Japanese J1 support
o
Ability to calculate and check CRC6 according to the Japanese standard
o
Ability to generate Yellow Alarm according to the Japanese standard
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.13 TDM Bus
• Dual two-frame independent receive and transmit elastic stores
o Independent control and clocking
o Controlled slip capability with status
o Minimum delay mode supported
• Programmable output clocks for fractional T1, E1, H0, and H12 applications
• Hardware signaling capability
o Receive signaling reinsertion to a backplane multiframe sync
o Availability of signaling in a separate PCM data stream
o Signaling freezing
• Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
• Access to the data streams in between the framer/formatter and the elastic stores
• User-selectable synthesized clock output
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2.14 Test and Diagnostics
• IEEE 1149.1 support
• Programmable on-chip bit error-rate tester (BERT)
• Pseudorandom patterns including QRSS
• User-defined repetitive patterns
• Daly pattern
• Error insertion single and continuous
• Total bit and errored bit counts
• Payload error insertion
• Error insertion in the payload portion of the T1 frame in the transmit path
• Errors can be inserted over the entire frame or selected channels
• Insertion options include continuous and absolute number with selectable insertion rates
• F-bit corruption for line testing
• Loopbacks: remote, local, analog, and per-channel loopback
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2.15 Specifications Compliance
The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications
and relevant sections that are applicable to the DS33R11.
Table 2-1. T1-Related Telecommunications Specifications
IEEE 802.3-2002—CSMA/CD access method and physical layer specifications.
RFC1662—PPP in HDLC-like Framing
RFC2615—PPP over SONET/SDH
X.86—Ethernet over LAPS
RMII—Industry Implementation Agreement for “Reduced MII Interface,” Sept 1997
ANSI: T1.403-1995, T1.231–1993, T1.408
AT&T: TR54016, TR62411
ITU-T: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161,
Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification
ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4
Japanese: JTG.703, JTI.431, JJ-20.11 (CMI Coding Only)
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
3 APPLICATIONS
The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery
over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4.
For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet LAN to
Unframed T1/E1 WAN Bridge, available on our website at
Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing)
www.maxim-ic.com/telecom.
T1/E1/J1
Stream
Inter-Building
LAN Extension
SDRAM
RMII, MII
10 Base T
100 Base T
EthernetDS33R11
Clock
Sources
17 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
4 ACRONYMS AND GLOSSARY
• BERT: Bit Error-Rate Tester
• DCE: Data Communication Interface
• DTE: Data Terminating Interface
• FCS: Frame Check Sequence
• HDLC: High-Level Data Link Control
• MAC: Media Access Control
• MII: Media Independent Interface
• RMII: Reduced Media Independent Interface
• WAN: Wide Area Network
Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
The register names have been allowed to remain with a “SU.” prefix to avoid register renaming.
Note 2: Previous versions of this document used the term “Line” to refer to the Serial Interface. The register names
have been allowed to remain with a “LI.” prefix to avoid register renaming.
Note 3: The terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
Note 4: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125μs frame
there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1.
Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first.
Bit number 8 is the LSB and is transmitted last. The term “locked” is used to refer to two clock signals that are
phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz
clock if they share the same 8kHz component). Throughout this data sheet, the following abbreviations are used:
B8ZS Bipolar with 8 Zero Substitution
BOC Bit-Oriented Code
CRC Cyclical Redundancy Check
D4 Superframe (12 frames per multiframe) Multiframe Structure
ESF Extended Superframe (24 frames per multiframe) Multiframe Structure
FDL Facility Data Link
FPS Framing Pattern Sequence in ESF
Fs Signaling Framing Pattern in D4
Ft Terminal Framing Pattern in D4
HDLC High-Level Data Link Control
MF Multiframe
SLC–96 Subscriber Loop Carrier—96 Channels
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
5 MAJOR OPERATING MODES
Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the
features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86
encapsulation.
The integrated transceiver can be software configured for T1, E1, or J1 operation. It is composed of a line interface
unit (LIU), framer, two additional HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit
parallel port configured for Intel or Motorola bus operations.
The LIUs are composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for
both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be
programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications) and can be placed in either transmit or receive data paths.
More information on microprocessor control is available in Section
8.1.
19 of 344
s
K
K
C
WR RD I
S
S
S
E
K
JTAG Pins
6 BLOCK DIAGRAMS
Figure 6-1. Main Block Diagram
TTIP
TRING
RTIP
RRING
MCLK
TDCLKI
TDCLKO
TPOSI
TPOSO
TNEGI
TNEGO TCHBLK
CLAD
MUX
LIU
TRANSMIT
TRANSMIT
HDLC
BERT
HDLC
MUX
LIU
RECEIVE
RECEIVIE
JTAG2 JTAG1
TCHCLK
TCLKT
FRAMER
T1/E1/J1
FRAMER
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TSERI
TSERO
TCLKE
TDEN
ST CS
A0-A9
D0-D7
NT
μP Port
CLAD
SYSCLKI
(RMII MODE)
PORT
SERIAL
TRANSMIT
CIR
PACKET
HDLC/X.86
CONTROLLER
RXD[0:1]
RX_CLK
CRS_DV
RX_ERR
REF_CLK
REF_CLKO
ETHERNET MAC
MAPPER
TRANSCEIVER
ETHERNET
ARBITER
BERT
TX_EN
TXD[0:1]
MDC
PORT
SERIAL
RECEIVE
PACKET
HDLC/X.86
MDIO
LIUC
RPOSI
RNEGI
RDCLKI
JTAG Pin
NOTE: SOME PINS NOT SHOWN. THE BLOCK IN THE DIAGRAM LABELED “T1/E1/J1 TRANSCEIVER” IS
DIVIDED INTO THREE FUNCTIONAL BLOCKS: LIU, FRAMER, AND BACKPLANE INTERFACE OUTLINED IN
THE FOLLOWING DIAGRAMS.
RPOSO
RDCLKO
RNEGO
RCHBL
RCLKO
RSERO
RCHCL
RSERI
20 of 344
RDEN
RCLKI
SDRAM PORT
SDC
SRA
SCA
SW
SBA[0:1]
SDATA[0:32]
]
SDCL
SDMASK[0:4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-2. Block Diagram of T1/E1/J1 Transceiver
CLOCK
CLOCK
ADAPTER
EXTERNAL ACCESS
TO RECEIVE SIGNALS
BACKPLANE
CLOCK SYNTH
BACKPLANE
RX
LIU
MUX
HDB3 / B8ZS
SYNC
SINGALING
ALARM DET
HDLCs
INTERFACE
T1/E1/J1
NETWORK
TX
LIU
LIU
LOCAL LOOPBACK
JITTER ATTENUATOR
EXTERNAL ACCESS
TO TRANSMIT SIGNALS
REMOTE LOOPBACK
MUX
FRAMER LOOPBACK
FRAMER
SINGALING
ALARM GEN
HDLCs
CRC GEN
HDB3 / B8ZS
PAYLOAD LOOPBACK
FRAMER BACKPLANE
CIRCUIT
BACKPLANE
INTERFACE
JTAG ESIB
HOST INTERFACE
21 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-3. Receive and Transmit T1/E1/J1 LIU
XTALD
MCLK
8XCLK
RPOSO
RDCLKO
RNEGO
RDCLKI
RNEGI
RPOSI
RCL
RRING
RTIP
TRING
TTIP
VCO / PLL
MUX
32.768MHz
RECEIVE
LINE I/F
LOCAL LOOPBACK
JITTER ATTENUATOR
OR RECEIVE PATH
TRANSMIT
REMOTE LOOPBACK
JACLK
RPOS
RCLK
RNEG
TRANSMIT
LINE I/F
TNEG
TCLK
TPOS
INTERNAL
MUX
SIGNALS
TO
FRAMER
LIUC
TNEGO
TPOSI
TNEGI
TDCLKI
TPOSO
TDCLKO
22 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-4. Receive and Transmit T1/E1/J1 Framer
REC
HDLC #1
128 Byte
FIFO
REC
HDLC #2
128 Byte
FIFO
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
INTERNAL
SIGNALS
FROM
LIU
DATA
FRAMER LOOPBACK
RECEIVE
FRAMER
TRANSMIT
FRAMER
CLOCK
SYNC
SYNC
CLOCK
DATA
MAPPER MAPPER
MAPPER
MAPPER
PAYLOAD LOOPBACK
DATA
CLOCK
SYNC
SYNC
CLOCK
DATA
INTERNAL
XMIT
HDLC #1
128 Byte
FIFO
XMIT
HDLC #2
128 Byte
FIFO
SIGNALS
TO
BACKPLANE
INTERFACE
23 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 6-5. T1/E1/J1 Backplane Interface
DATA
CLOCK
SYNC
INTERNAL
SIGNALS
FROM
FRAMER
SYNC
DATA
Sa/FDL
INSERT
ELASTIC
STORE
Sa BIT/FDL
EXTRACTION
SIGNALING
BUFFER
ELASTIC
STORE
CHANNEL
TIMING
SIGNALING
BUFFER
RLINK
RLCLK
RSIG
RSIGFR
RSYSCLK
RSERO
RCLKO
RSYNC
RMSYNC
RFSYNC
RDATA
RCHCLK
RCHBLK
TSERI
TSIG
TSSYNC
CLOCK
JACLK
CHANNEL
TIMING
24 of 344
TSYSCLK
TSYNC
TESO
TDATA
TLCLK
TLINK
TCHCLK
TCHBLK
TCLK
MUX
TCLKT
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
7 PIN DESCRIPTIONS
7.1 Pin Functional Description
Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG
patterns.
LEGEND: I = input, O = output, Ipu = input with pullup, Oz = output with tri-state, IO = bidirectional pin, IOz = bidirectional pin with tri-state.
Table 7-1. Detailed Pin Descriptions
NAME PIN TYPE FUNCTION
MICROPROCESSOR PORT
A0 A18 I
A1 B18 I
A2 C18 I
A3 A17 I
A4 B17 I
A5 C17 I
A6 A16 I
A7 B16 I
A8 C16 I
A9 C15 I
D0 A14 IOZ
D1 B14 IOZ
D2 C14 IOZ
D3 A13 IOZ
D4 B13 IOZ
D5 C13 IOZ
D6 A12 IOZ
D7 B12 IOZ
WR/RW
C11 I
Address Bit 0: Address bit 0 of the microprocessor interface.
Least Significant Bit.
Address Bit 1: Address bit 1 of the microprocessor interface.
Address Bit 2: Address bit 2 of the microprocessor interface.
Address Bit 3: Address bit 3 of the microprocessor interface.
Address Bit 4: Address bit 4 of the microprocessor interface.
Address Bit 5: Address bit 5 of the microprocessor interface.
Address Bit 6: Address bit 6 of the microprocessor interface.
Address Bit 7: Address bit 7 of the microprocessor interface.
Address Bit 8: Address bit 8 of the microprocessor interface.
Address Bit 9: Address bit 9 of the microprocessor interface.
Data Bit 0: Bidirectional data bit 0 of the microprocessor interface.
Least Significant Bit. Not driven when CS =1 or RST = 0.
Data Bit 1: Bidirectional data bit 1 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 2: Bidirectional data bit 2 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 3: Bidirectional data bit 3 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 4: Bidirectional data bit 4 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 5: Bidirectional data bit 5 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 6: Bidirectional data bit 6 of the microprocessor interface.
Not driven when CS = 1 or RST = 0.
Data Bit 7: Bidirectional data bit 7 of the microprocessor interface.
Most Significant Bit. Not driven when CS = 1 or RST = 0.
Write (Intel Mode): The DS33R11 captures the contents of the
data bus (D0-D7) on the rising edge of WR and writes them to the
addressed register location. CS must be held low during write
operations.
Read Write (Motorola Mode): Used to indicate read or write
operation. RW must be set high for a register read cycle and low for
a register write cycle.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Read Data Strobe (Intel Mode): The DS33R11 drives the data bus
(D0-D7) with the contents of the addressed register while RD and
CS are both low.
RD/DS
B11 I
Data Strobe (Motorola Mode): Used to latch data through the
microprocessor interface. DS must be low during read and write
operations.
Chip Select for Protocol Conversion Device: This pin must be
CS
A11 I
taken low for read/write operations. When CS is high, the RD/DS
and WR signals are ignored.
CST
D7 I
Chip Select for the T1/E1/J1 Transceiver: Must be low to read or
write the T1/E1/J1 transceiver.
Interrupt Output: Outputs a logic zero when an unmasked
interrupt event is detected. INT is deasserted when all interrupts
INT
A10 OZ
have been acknowledged and serviced. Active low. Inactive state is
programmable in register
GL.CR1. is deasserted when all
interrupts have been acknowledged and serviced. Active low.
Inactive state is programmable in register
GL.CR1.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
MII/RMII PHY PORT
Collision Detect (MII): Asserted by the MAC PHY to indicate that a
COL_DET N18 I
collision is occurring. In DCE Mode this signal should be connected
to ground. This signal is only valid in half duplex mode, and is
ignored in full duplex mode.
Receive Carrier Sense (MII): Should be asserted (high) when data
from the PHY (RXD[3:0) is valid. For each clock pulse 4 bits arrive
from the PHY. Bit 0 is the least significant bit. In DCE mode,
RX_CRS/
CRS_DV
M19 I
connect to V
DD
.
Carrier Sense/Receive Data Valid (RMII): This signal is asserted
(high) when data is valid from the PHY. For each clock pulse 2 bits
arrive from the PHY. In DCE mode, this signal must be grounded.
Receive Clock (MII): Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency
RX_CLK M20 IO
is 25MHz for 100Mbit/s operation and 2.5MHz for 10Mbit/s
operation. In DTE mode, this is a clock input provided by the PHY.
In DCE mode, this is an output derived from REF_CLK providing
2.5MHz (10Mbit/s operation) or 25MHz (100Mbit/s operation).
Receive Data 0 through 3 (MII): Four bits of received data,
RXD[0] L18
sampled synchronously with the rising edge of RX_CLK. For every
clock cycle, the PHY transfers 4 bits to the DS33R11. RXD[0] is the
RXD[1] L19
O
RXD[2] L20
least significant bit of the data. Data is not considered valid when
RX_DV is low.
Receive Data 0 through 1 (RMII): Two bits of received data,
sampled synchronously with REF_CLK with 100Mbit/s mode.
RXD[3] M18
Accepted when CRS_DV is asserted. When configured for
10Mbit/s mode, the data is sampled once every 10 clock periods.
Receive Data Valid (MII): This active high signal indicates valid
RX_DV K19 I
data from the PHY. The data RXD is ignored if RX_DV is not
asserted high.
Receive Error (MII): Asserted by the MAC PHY for one or more
RX_CLK periods indicating that an error has occurred. Active High
indicates Receive code group is invalid. If CRS_DV is low,
RX_ERR K18 I
RX_ERR has no effect. This is synchronous with RX_CLK. In DCE
mode, this signal must be grounded.
Receive Error (RMII): Signal is synchronous to REF_CLK.
Transmit Clock (MII): Timing reference for TX_EN and TXD[3:0].
The TX_CLK frequency is 25MHz for 100Mbit/s operation and
2.5MHz for 10Mbit/s operation.
TX_CLK H19 IO
In DTE mode, this is a clock input provided by the PHY. In DCE
mode, this is an output derived from REF_CLK providing 2.5MHz
(10Mbit/s operation) or 25MHz (100Mbit/s operation).
27 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
TXD[0] F19
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is the least
TXD[1] F18
TXD[2] E20
TXD[3] E19
O
significant bit of the data. When TX_EN is low the data on TXD
should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD [1:0]
presented synchronously with the rising edge of REF_CLK.
Transmit Enable (MII): This pin is asserted high when data TXD
[3:0] is being provided by the DS33R11. The signal is deasserted
prior to the first nibble of the next frame. This signal is synchronous
TX_EN F20 O
with the rising edge TX_CLK. It is asserted with the first bit of the
preamble.
Transmit Enable (RMII): When this signal is asserted, the data on
TXD [1:0] is valid. This signal is synchronous to the REF_CLK.
Reference Clock (RMII and MII): When in RMII mode, all signals
from the PHY are synchronous to this clock input for both transmit
and receive. This required clock can be up to 50MHz and should
have ±100ppm accuracy.
REF_CLK A19 I
When in MII mode in DCE operation, the DS33R11 uses this input
to generate the RX_CLK and TX_CLK outputs as required for the
Ethernet PHY interface. When the MII interface is used with DTE
operation, this clock is not required and should be tied low.
In DCE and RMII modes, this input must have a stable clock input
before setting the RST pin high for normal operation.
Reference Clock Output (RMII and MII): A derived clock output
up to 50MHz, generated by internal division of the SYSCLKI signal.
REF_CLKO A20 O
Frequency accuracy of the REF_CLKO signal will be proportional
to the accuracy of the user-supplied SYSCLKI signal. See Section
9.1.1 for more information.
DCE or DTE Selection: The user must set this pin high for DCE
Mode selection or low for DTE Mode. In DCE Mode, the DS33R11
MAC port can be directly connected to another MAC. In DCE
DCEDTES G20 I
Mode, the Transmit clock (TX_CLK) and Receive clock (RX_CLK)
are output by the DS33R11. Note that there is no software bit
selection of DCEDTES. Note that DCE Mode is only relevant when
the MAC interface is in MII mode.
RMIIMIIS G19 I
RMII or MII Selection: Set high to configure the MAC for RMII
interfacing. Set low for MII interfacing.
28 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
PHY MANAGEMENT BUS
Management Data Clock (MII): Clocks management data between
MDC C19 O
the PHY and DS33R11. The clock is derived from theSYSCLKI,
with a maximum frequency is 1.67MHz. The user must leave this
pin unconnected in the DCE Mode.
MII Management data IO (MII): Data path for control information
between the PHY and DS33R11. When not used, pull to logic high
externally through a 10kΩ resistor. The MDC and MDIO pins are
MDIO C20 IO
used to write or read up to 32 Control and Status Registers in 32
PHY Controllers. This port can also be used to initiate AutoNegotiation for the PHY. The user must leave this pin unconnected
in the DCE Mode.
SDRAM INTERFACE
SDRAM Column Address Strobe: Active-low output, used to latch
SCAS
W7 O
the column address on the rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDRAM Row Address Strobe: Active-low output, used to latch
SRAS
W9 O
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode Register Write.
SDCS
V10 O
SDRAM Chip Select: Active-low output enables SDRAM access.
SWE
W10 O
SBA[0] Y11
SBA[1] V11
SDRAM Write Enable: This active-low output enables write
operation and auto precharge.
SDRAM Bank Select: These 2 bits select 1 of 4 banks for the
read/write/precharge operations.
O
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
29 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
SDATA[0] W2
SDATA[1] Y4
SDATA[2] Y2
SDATA[3] Y5
SDATA[4] Y3
SDATA[5] W5
SDATA[6] V5
SDATA[7] W6
SDATA[8] V6
SDATA[9] W4
SDATA[10] V4
SDATA[11] V2
SDATA[12] V3
SDATA[13] V1
SDATA[14] W3
SDATA[15] W1
SDATA[16] Y16
SDATA[17] Y17
SDATA[18] V18
O
SDRAM Data Bus Bits 0 to 31: The 32 pins of the SDRAM data
bus are inputs for read operations and outputs for write operations.
At all other times, these pins are high-impedance.
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
SDATA[19] Y19
SDATA[20] V19
SDATA[21] Y20
SDATA[22] U19
SDATA[23] W20
SDATA[24] U20
SDATA[25] T19
SDATA[26] T20
SDATA[27] Y18
SDATA[28] W19
SDATA[29] V17
SDATA[30] W17
SDATA[31] W16
SDA[0] W14
SDA[1] W12
SDA[2] Y15
SDA[3] W15
SDA[4] Y14
SDA[5] V13
SDA[6] W13
SDA[7] Y12
SDA[8] V12
SDA[9] Y10
O
SDRAM Address Bus 0 to 11: The 12 pins of the SDRAM address
bus output the row address first, followed by the column address.
The row address is determined by SDA0 to SDA11 at the rising
edge of clock. Column address is determined by SDA0-SDA9 and
SDA11 at the rising edge of the clock. SDA10 is used as an autoprecharge signal.
Note: All SDRAM operations are controlled entirely by the
DS33R11. No user programming for SDRAM buffering is required.
SDA[10] V14
SDA[11] W11
SDMASK[0] Y6
SDMASK[1] V7
SDMASK[2] V16
SDMASK[3] V15
SDCLKO Y8
O
O
(4mA)
SDRAM Mask 0 through 3: When high, a write is done for that
byte. The least significant byte is SDATA7 to SDATA0. The most
significant byte is SDATA31 to SDATA24.
SDRAM CLK Out: System clock output to the SDRAM. This clock
is a buffered version of SYSCLKI.
30 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
T1/E1/J1 ANALOG LINE INTERFACE
Transmit Analog Tip Output for the T1/E1/J1 Transceiver:
TTIP R1, R2 O
Analog line-driver outputs. Two connections are provided to
improve signal quality. These pins connect via a 1:2 step-up
transformer to the network. See Section
Transmit Analog Ring Output for the T1/E1/J1 Transceiver:
TRING T1,T2 O
Analog line-driver outputs. Two connections are provided to
improve signal quality. These pins connect via a 1:2 step-up
transformer to the network. See Section
Receive Analog Tip Input for the T1/E1/J1 Transceiver: Analog
RTIP K1 I
input for clock recovery circuitry. These pins connect via a 1:1
transformer to the network. See Section
Receive Analog Ring Input for the T1/E1/J1 Transceiver:
RRING M1 I
Analog input for clock recovery circuitry. These pins connect via a
1:1 transformer to the network. See Section
T1/E1/J1 TRANSMIT FRAMER INTERFACE
Transmit Serial Data Input to the T1/E1/J1 Framer: Transmit
TSERI E3 I
NRZ serial data. Sampled on the falling edge of TCLKT when the
transmit-side elastic store is disabled. Sampled on the falling edge
of TSYSCLK when the transmit-side elastic store is enabled.
Transmit Clock for the T1/E1/J1 Transceiver: 1.544MHz or a
TCLKT D2 I
2.048MHz primary clock. Used to clock data from the TSERI pin
through the transmit-side formatter.
Transmit Channel Block for the T1/E1/J1 Transceiver: A userprogrammable output that can be forced high or low during any of
the channels. Synchronous with TCLKT when the transmit-side
TCHBLK A2 O
elastic store is disabled. Synchronous with TSYSCLK when the
transmit-side elastic store is enabled. Useful for locating individual
channels in drop-and-insert applications, for external per-channel
loopback, and for per-channel conditioning.
Transmit Channel Clock for the T1/E1/J1 Transceiver: A
192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB
of each channel. Can also be programmed to output a gated
TCHCLK G1 O
transmit-bit clock for fractional T1/E1 applications. Synchronous
with TCLKT when the transmit-side elastic store is disabled.
Synchronous with TSYSCLK when the transmit-side elastic store is
enabled. Useful for parallel-to-serial conversion of channel data.
Transmit System Sync for the T1/E1/J1 Transceiver: Only used
when the transmit-side elastic store is enabled. A pulse at this pin
TSSYNC A5 I
will establish either frame or multiframe boundaries for the transmit
side. Should be tied low in applications that do not use the transmitside elastic store.
Transmit Sync for the T1/E1/J1 Transceiver: A pulse at this pin
will establish either frame or multiframe boundaries for the transmit
TSYNC C1 I/O
side. Can be programmed to output either a frame or multiframe
pulse. If this pin is set to output pulses at frame boundaries, it can
also be set via TR.IOCR1.3 to output double-wide pulses at
signaling frames in T1 mode.
Transmit System Clock for the T1/E1/J1 Transceiver:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock.
TSYSCLK E4 I
Only used when the transmit-side elastic-store function is enabled.
Should be tied low in applications that do not use the transmit-side
elastic store.
10.24 for details.
10.24 for details.
10.24 for details
10.24 for details
31 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Transmit Signaling Input for the T1/E1/J1 Transceiver: When
enabled, this input will sample signaling bits for insertion into
TSIG B4 I
outgoing PCM data stream. Sampled on the falling edge of TCLKT
when the transmit-side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit-side elastic store is
enabled.
ETHERNET MAPPER TRANSMIT SERIAL INTERFACE
Transmit Serial Data Output from Ethernet Mapper: Output on
TSERO E2 O
the rising edge of TCLKE. Selective clock periods can be skipped
for output of TSERO with a gapped clock input on TCLKE. The
maximum data rate is 52Mbit/s.
Serial Interface Transmit Clock Input to Ethernet Mapper: The
TCLKE F1 I
clock reference for TSERO, which is output on the rising edge of
the clock. TCLKE supports gapped clocking, up to a maximum
frequency of 52MHz.
Transmit Data Enable (Input): The transmit data enable is
programmable to selectively block/enable the transmit data. The
TDEN signal must occur one clock edge prior to the affected data
bit. The active polarity of TDEN is programmable in register
LI.TSLCR. It is recommended for both T1/E1 and T3/E3
TDEN/
TBSYNC
D5 IO
applications that use gapped clocks. The TDEN signal is provided
for interfacing to framers that do not have a gapped clock facility.
Transmit Byte Sync (Output): This output can be used by an
external Serial to Parallel to convert TSERO stream to byte wide
data. This output indicates the last bit of the byte data sent serially
on TSERO. This signal is only active in the X.86 Mode.
T1/E1/J1 RECEIVE FRAMER INTERFACE
Receive Serial Data for T1/E1/J1 Transceiver: Received NRZ
RSERO H2 O
serial data. Updated on rising edges of RCLKO when the receiveside elastic store is disabled. Updated on the rising edges of
RSYSCLK when the receive-side elastic store is enabled.
Receive Clock Output from the T1/E1/J1 Framer: 1.544MHz (T1)
RCLKO G3 O
or 2.048MHz (E1) clock that is used to clock data through the
receive-side framer. Normally connected to the RCLKI input.
Receive Channel Block for the T1/E1/J1 Transceiver: A userprogrammable output that can be forced high or low during any of
the 24 T1 or 32 E1 channels. Synchronous with RCLKO when the
RCHBLK A1 O
receive-side elastic store is disabled. Synchronous with RSYSCLK
when the receive-side elastic store is enabled. Also useful for
locating individual channels in drop-and-insert applications, for
external per-channel loopback, and for per-channel conditioning.
See the Channel Blocking Registers section.
Receive Channel Clock for the T1/E1/J1 Transceiver: A 192kHz
(T1) or 256kHz (E1) clock that pulses high during the LSB of each
channel can also be programmed to output a gated receive-bit
RCHCLK G2 O
clock for fractional T1/E1 applications. Synchronous with RCLKO
when the receive-side elastic store is disabled. Synchronous with
RSYSCLK when the receive-side elastic store is enabled. Useful
for parallel-to-serial conversion of channel data.
32 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Receive Sync for the T1/E1/J1 Transceiver: An extracted pulse,
one RCLKO wide, is output at this pin, which identifies either frame
(TR.IOCR1.5 = 0) or multiframe (TR.IOCR1.5 = 1) boundaries. If
RSYNC G4 I/O
set to output-frame boundaries then via TR.IOCR1.6, RSYNC can
also be set to output double-wide pulses on signaling frames in T1
mode. If the receive-side elastic store is enabled, then this pin can
be enabled to be an input via TR.IOCR1.4 at which a frame or
multiframe boundary pulse is applied.
Receive System Clock for the Transceiver: 1.544MHz,
RSYSCLK F4 I
2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the
receive-side elastic-store function is enabled. Should be tied low in
applications that do not use the receive-side elastic store.
Receive Frame Sync (Pre Receive Elastic Store) for T1/E1/J1
RFSYNC A3 O
Transceiver: An extracted 8kHz pulse, one RCLKO wide, is output
at this pin, which identifies frame boundaries.
Receive Multiframe Sync for the T1/E1/J1 Transceiver: An
RMSYNC U3 O
extracted pulse, one RCLKO wide (elastic store disabled) or one
RSYSCLK wide (elastic store enabled), is output at this pin, which
identifies multiframe boundaries.
Receive Signaling Output: Outputs signaling bits in a PCM
RSIG L3 O
format. Updated on rising edges of RCLKO when the receive-side
elastic store is disabled. Updated on the rising edges of RSYSCLK
when the receive-side elastic store is enabled.
33 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
ETHERNET MAPPER RECEIVE SERIAL INTERFACE
Receive Serial Data Input to Ethernet Mapper: Receive Serial
RSERI H1 I
data arrives on the rising edge of RCLKI. Normally connected to
RSERO.
Serial Interface Receive Clock Input to the Ethernet Mapper:
RCLKI F2 I
Reference clock for receive serial data on RSERI. Gapped clocking
is supported, up to the maximum RCLKI frequency of 52 MHz.
Receive Data Enable for the Ethernet Mapper: The receive data
enable is programmable to block the receive data. The RDEN must
be coincident with the RSERI data bit to be blocked or enabled.
The active polarity of RDEN is programmable in register
It is recommended for both T1/E1 and T3/E3 applications that use
gapped clocks. The RDEN signal is provided for interfacing to
framers that do not have a gapped clock facility.
RDEN/
RBSYNC
P2 I
Receive Byte Synchronization Input: Provides byte
synchronization input to X.86 decoder. This signal will go high at
the last bit of the byte as it arrives. This signal can occur at
maximum rate every 8 bits. Note that a long as the R11 receives
one RBSYNC indicator. The X.86 receiver will determine the byte
boundary. Hence the R11 does not require a continuous 8 bit sync
indicator. A new sync pulse is required if the byte boundary
changes.
T1/E1/J1 FRAMER/LIU INTERIM SIGNALS
Receive Clock Input to the T1/E1/J1 Framer: Clock used to clock
RDCLKI M4 I
data through the receive-side framer. This pin is normally
connected to RDCLKO. Can be internally connected to RDCLKO
by connecting the LIUC pin high.
Receive Clock Output from the T1/E1/J1 LIU: Buffered
RDCLKO M3 O
recovered clock from the network. This pin is normally connected to
RDCLKI.
Receive Negative-Data Input: Sampled on the falling edge of
RDCLKI for data to be clocked through the receive-side framer.
RNEGI L4 I
RPOSI and RNEGI can be connected together for an NRZ
interface. Can be internally connected to RNEGO by connecting
the LIUC pin high.
Receive Negative Data Output from the T1/E1/J1 LIU: Updated
RNEGO N2 O
on the rising edge of RDCLKO with the bipolar data out of the line
interface. This pin is normally tied to RNEGI.
Receive Positive-Data Input to the T1/E1/J1 Framer: Sampled
on the falling edge of RDCLKI for data to be clocked through the
RPOSI J3 I
receive-side framer. RPOSI and RNEGI can be connected together
for an NRZ interface. Can be internally connected to RPOSO by
connecting the LIUC pin high.
Receive Positive-Data Output from the T1/E1/J1 LIU: Updated
RPOSO N3 O
on the rising edge of RDCLKO with bipolar data out of the line
interface. This pin is normally connected to RPOSI.
Receive Data from the T1/E1/J1 Framer: Updated on the rising
RDATA H3 O
edge of RCLKO with the data out of the receive-side framer, before
passing through the Elastic Store.
Serial Interface Transmit Clock Input for the T1/E1/J1 LIU: Line
TDCLKI D1 I
interface transmit clock. This pin is normally tied to TCLKO. Can be
internally connected to TCLKO by connecting the LIUC pin high.
LI.RSLCR.
34 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Transmit Clock Output from the T1/E1/J1 Framer: Buffered
TDCLKO C2 O
clock that is used to clock data through the transmit-side formatter
(either TCLKT or RDCLKI). This pin is normally tied to TDCLKI.
Transmit Negative-Data Input: Sampled on the falling edge of
TNEGI C3 I
TDCLKI for data to be transmitted out onto the T1 line. Can be
internally connected to TNEGO by connecting the LIUC pin high.
TPOSI and TNEGI can be connected together in NRZ applications.
Transmit Negative-Data Output: Updated on the rising edge of
TNEGO D3 O
TCLKO with the bipolar data out of the transmit-side formatter. This
pin is normally connected to TNEGI.
Transmit Positive-Data Input: Sampled on the falling edge of
TPOSI B3 I
TDCLKI for data to be transmitted out onto the T1 line. Can be
internally connected to TPOSO by connecting the LIUC pin high.
TPOSI and TNEGI can be connected together in NRZ applications.
Transmit Positive-Data Output: Updated on the rising edge of
TPOSO E1 O
TCLKO with the bipolar data out of the transmit-side formatter. Can
be programmed to source NRZ data by the output data format
(TR.IOCR1.0) control bit. This pin is normally connected to TPOSI.
Transmit Data: Sampled on the falling edge of TCLKT with data to
TDATA A4 I
be clocked through the transmit-side formatter. This pin is normally
connected to TESO.
Transmit Elastic Store Output: Updated on the rising edge of
TESO D4 O
TCLKT with data out of the transmit-side elastic store whether the
elastic store is enabled or not. This pin is normally connected to
TDATA.
35 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
HARDWARE AND STATUS PINS
Line Interface Unit Connect: When a logic low is present on this
input pin, the T1/E1/J1 Framer and LIU are not internally
connected. The line interface circuitry will be separated from the
framer/formatter circuitry and the TPOSI, TNEGI, TDCLKI, RPOSI,
RNEGI, and RDCLKI input pins will be active.
LIUC B2 I
When a logic high is present on this input pin, the T1/E1/J1 Framer
is internally connected to the LIU. The TPOSI, TNEGI, TDCLKI,
RPOSI, RNEGI, RDCLKI input pins are deactivated. When LIUC is
connected high, the TPOSI, TNEGI, TDCLKI, RPOSI, RNEGI, and
RDCLKI pins should be tied low.
Reset for the Ethernet Mapper: An active low signal on this pin
resets the internal registers and logic of the protocol conversion
RST
A8 I
device. This pin should remain low until power, SYSCLKI, RX_CLK,
and TX_CLK are stable, then set high for normal operation. This
input requires a clean edge with a rise time of 25ns or less to
properly reset the device.
Test/Reset for the T1/E1/J1 Transceiver: A dual-function pin. A
zero-to-one transition issues a hardware reset to the transceiver
TSTRST C4 I
register set. A reset clears all configuration registers. Configuration
register contents are set to zero. Leaving TSTRST high will tri-state
all output and I/O pins (including the parallel control port). Set low
for normal operation. Useful in board-level testing.
Mode Control for Processor Interface:
MODEC[0],
MODEC[1]
B19,
B20
I
00 = Read/Write Strobe Used (Intel Mode)
01 = Data Strobe Used (Motorola Mode)
10 = Reserved. Do not use.
11 = Reserved. Do not use.
Queue Overflow for Ethernet Mapper: This pin goes high when
QOVF H18 O
the transmit or receive queue has overflowed. This pin will go low
when the high watermark is reached again.
T1/E1/J1 Receive Loss-of-Sync/Loss-of-Transmit Clock: A dual
function output that is controlled by the CCR1.0 control bit. This pin
RLOS/LTC N1 O
can be programmed to either toggle high when the synchronizer is
searching for the frame and multiframe or to toggle high if the
TCLKT pin has not been toggled for 5μs.
RCL B5 O
T1/E1/J1 Receive Carrier Loss: Set high when the T1/E1/J1 line
interface detects a carrier loss.
T1/E1/J1 Receive Signaling-Freeze Output: Set high when the
RSIGF P3 O
signaling data is frozen by either automatic or manual intervention.
Used to alert downstream equipment of the condition.
36 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
SYSTEM CLOCKS
System Clock In for Ethernet Mapper: 100MHz System Clock
input to the DS33R11, used for internal operation. This clock is
SYSCLKI V8 I
buffered and provided at SDCLKO for the SDRAM interface. The
DS33R11 also provides a divided version output at the REF_CLKO
pin. A clock supply with ±100ppm frequency accuracy is suggested.
Master Clock Input for the T1/E1/J1 Transceiver: A (50ppm)
clock source. This clock is used internally for both clock/data
MCLK H4 I
recovery and for the jitter attenuator for both T1 and E1 modes.
The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz. When using the transceiver in T1-only operation a
1.544MHz (50ppm) clock source can be used.
Backplane Clock from T1/E1/J1 Transceiver: A user-selectable
BPCLK B1 O
synthesized clock output that is referenced to the clock that is
output at the RCLKO pin.
Eight Times Clock from the T1/E1/J1 Transceiver: An 8x clock
that is locked to the recovered network clock provided from the
8XCLK K4 O
clock/data recovery block (if the jitter attenuator is enabled on the
receive side) or from the TDCLKI pin (if the jitter attenuator is
enabled on the transmit side).
Quartz Crystal Driver for the T1/E1/J1 Transceiver: A quartz
XTALD J4 O
crystal of 2.048MHz (optional 1.544MHz in T1-only operation) can
be applied across MCLK and XTALD instead of a clock source at
MCLK. Leave open circuited if a clock source is applied at MCLK.
37 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
JTAG INTERFACE
JTAG Clock 1 for the Ethernet Mapper: This signal is used to
JTCLK1 A7 Ipu
shift data into JTDI1 on the rising edge and out of JTDO1 on the
falling edge.
JTAG Data In 1 for the Ethernet Mapper: Test instructions and
JTDI1 C9 Ipu
data are clocked into this pin on the rising edge of JTCLK1. This
pin has a 10kΩ pullup resistor.
JTAG Data Out 1 for the Ethernet Mapper: Test instructions and
JTDO1 B7 Oz
data are clocked out of this pin on the falling edge of JTCLK1. If not
used, this pin should be left unconnected.
JTAG Mode Select 1 for the Ethernet Mapper: This pin is
JTMS1 C8 Ipu
sampled on the rising edge of JTCLK1 and is used to place the test
access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Reset 1 for the Ethernet Mapper: JTRST1 is used to
asynchronously reset the test access port controller. After power
up, a rising edge on JTRST1 will reset the test port and cause the
JTRST1
C7 Ipu
device I/O to enter the JTAG DEVICE ID mode. Pulling JTRST1
low restores normal device operation. JTRST1 is pulled HIGH
internally via a 10kΩ resistor operation. If boundary scan is not
used, this pin should be held low.
JTAG Clock 2 for the T1/E1/J1 Transceiver: This signal is used
JTCLK2 A6 Ipu
to shift data into JTDI1 on the rising edge and out of JTDO1 on the
falling edge.
JTAG Data In 2 for the T1/E1/J1 Transceiver: Test instructions
JTDI2 B6 Ipu
and data are clocked into this pin on the rising edge of JTCLK2.
This pin has a 10kΩ pullup resistor.
JTAG Data Out 2 for the T1/E1/J1 Transceiver: Test instructions
JTDO2 C5 Oz
and data are clocked out of this pin on the falling edge of JTCLK2.
If not used, this pin should be left unconnected.
JTAG Mode Select 2 for the T1/E1/J1 Transceiver: This pin is
JTMS2 B9 Ipu
sampled on the rising edge of JTCLK2 and is used to place the
test-access port into the various defined IEEE 1149.1 states. This
pin has a 10kΩ pullup resistor.
JTAG Reset 2 for the T1/E1/J1 Transceiver: JTRST2 is used to
asynchronously reset the test access port controller. After power-
JTRST2
B8 Ipu
up, JTRST2 must be toggled from low to high. This action will set
the device into the JTAG DEVICE ID mode. Normal device
operation is restored by pulling JTRST2 low. JTRST2 is pulled HIGH
internally via a 10kΩ resistor operation.
38 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
POWER SUPPLIES
RVDD K3, L1 —
RVSS
J1, J2, K2,
L2, M2
—
TVDD U1 –
TVSS
DVDD
DVSS
P1, R3, T3,
U2
D1–D17,
E17
N4, P4, R4,
T4
–
—
—
Receive Analog Positive Supply: Connect to 3.3V power supply.
Receive Analog Signal Ground: Connect to the common supply
ground.
Transmit Analog Positive Supply: Connect to 3.3V power supply.
Transmit Analog Signal Ground: Connect to the common supply
ground.
Digital Positive Supply: Connect to 3.3V power supply.
Digital Signal Ground: Connect to the common supply ground.
B10, B15,
C12, F3,
VDD1.8
J18, J20,
P18, P19,
I
VDD1.8: Connect to 1.8V power supply.
R19, R20,
V9, Y9, Y13
D20, F17,
G17, G18,
H17, J17,
VDD3
K17, L17,
M17, N17,
I
VDD3.3: Connect to 3.3V power supply.
P17, R17,
R18, T17,
T18, U17
A15, C10,
D8, D9,
D10, D18,
D19, E18,
H20, J19,
VSS
K20, N19,
I
VSS: Connect to the common supply ground.
N20, P20,
U4–U16,
U18, V20,
W8, W18,
Y1, Y7
N.C. A9, C6, D6 —
No Connection. Do not connect these pins. Leave these pins
open.
39 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 7-1. 256-Ball BGA Pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RCHBLK TCHBLK RFSYNC T DATA TSSYNC JTCLK2 JTCLK1
A
BPCLK LIUC T POSI TSIG RCL JTDI2 JTDO1
B
TSYNC TDCLKO TNEGI T STRST JTDO2 N.C.
C
SDATA
[10]
SDATA
[9]
SDATA
[1]
TDEN/
TBSYNC
SDATA
[6]
SDATA
[5]
SDATA
[3]
TDCLKI TCLKT TNEGO TESO
D
TPOSO TSERO TSERI TSYSCLK DVDD VSS
E
TCLKE RCLKI VDD1.8 RSYSCLK VDD3
F
TCHCLK RCHCLK RCLKO RSYNC VDD3 VDD3 RMIIMIIS
G
RSERI RSERO RDATA MCLK VDD3 QOVF TX_CLK VSS
H
RVSS RVSS RPOSI XTALD VDD3 VDD1.8 VSS VDD1.8
J
RTIP RVSS RVDD 8XCLK VDD3 RX_ERR RX_DV VSS
K
RVDD RVSS RSIG RNEGI VDD3
L
RRING RVSS RDCLKO RDCLKI VDD3
M
RLOS/
N
P
R
T
U
V
W
Y
RNEGO RPOSO DVSS VDD3 COL_DEt VSS VSS
LTC
RDEN/
TVSS
TTIP TTIP TVSS DVSS VDD3 VDD3 VDD1.8 VDD1.8
TRING TRING TVSS DVSS VDD3 VDD3
TVDD T VSS RMSYNC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD3 VSS
SDATA
[13]
SDATA
[15]
VSS
RSIGF DVSS VDD3 VDD1.8 VDD1.8 VSS
RBSYNC
SDATA
SDATA
[11]
[12]
SDATA
SDATA
[0]
[14]
SDATA
SDATA
[2]
[4]
JTRST1
N.C.
CST
SDATA
SDMASK
[8]
[1]
SDATA
SCAS
[7]
SDMASK
VSS SDCLKO VDD1.8
[0]
N.C.
RST
JTRST2
JTMS1 JTDI1 VSS
VSS VSS VSS DVDD DVDD DVDD DVDD DVDD DVDD DVDD VSS VSS VDD3
SYSCLKI VDD1.8
VSS
INT CS
JTMS2 VDD1.8
SDCS
SRAS SWE
SDA
[9]
D6 D3 D0 VSS A6 A3 A0 REF_CLK
D7 D4 D1 VDD1.8 A7 A4 A1
RD/DS
VDD1.8 D5 D2 A9 A8 A5 A2 MDC MDIO
WR/RW
TXD
[1]
RXD
[0]
RXD
RX_CRS /
[3]
SBA
SDA
SDA
SDA
SDMASK
SDMASK
SDATA
[1]
SDA
[11]
SBA
[0]
[8]
SDA
[1]
SDA
[7]
[5]
SDA
[6]
VDD1.8
[10]
SDA
[0]
SDA
[4]
[3]
SDA
[3]
SDA
[2]
[2]
SDATA
[31]
SDATA
[16]
[29]
SDATA
[30]
SDATA
[17]
SDATA
[18]
VSS
SDATA
[27]
MODEC
[0]
TXD
[3]
TXD
[0]
RXD
[1]
CRS_DV
SDATA
[25]
SDATA
[22]
SDATA
[20]
SDATA
[28]
SDATA
[19]
REF_
CLKO
MODEC
[1]
TXD
[2]
TX_EN
DCE
DTES
RXD
[2]
RX_CLK
SDATA
[26]
SDATA
[24]
VSS
SDATA
[23]
SDATA
[21]
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
8 FUNCTIONAL DESCRIPTION
The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1/E1/J1
WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet
arbiter, committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM interface, control ports,
bit error-rate tester (BERT), and integrated T1/E1/J1 transceiver. The packet interface consists of a MII/RMII
Ethernet PHY interface. The Ethernet interface can be configured for 10Mbit/s or 100Mbit/s service. The DS33R11
encapsulates Ethernet traffic with HDLC or X.86 (LAPS) encoding to be transmitted over a T1, E1, or J1 line. The
T1/E1/J1 interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet ports. Access is provided to the signals between the serial port and the integrated T1/E1/J1 transceiver.
The Ethernet packet interface supports MII and RMII interfaces, allowing the DSZ33R11 to connect to
commercially available Ethernet PHY and MAC devices. The Ethernet interface can be configured for 10Mbit/s or
100Mbit/s service, in DTE and DCE configurations. The DS33R11 MAC interface rejects frames with bad FCS and
short frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33R11 SDRAM controller enables
connection to a 128Mb SDRAM without external glue logic, at clock frequencies up to 100MHz. The SDRAM is
used for both the transmit and receive data queues. The receive queue stores data to be sent from the packet
interface to the WAN serial interface. The transmit queue stores data to be sent from the WAN serial interface to
the Ethernet LAN packet interface. The external SDRAM can accommodate up to 8192 frames with a maximum
frame size of 2016 bytes. The sizing of the queues can be adjusted by software. The user can also program high
and low watermarks for each queue that can be used for automatic or manual flow control. The packet data stored
in the SDRAM is encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The device also
provides the capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN serial port can operate with a gapped clock, and is designed to be connected to the
integrated T1/E1/J1 transceiver for transmission.
The DS33R11 can be configured through an 8-bit microprocessor interface port. Diagnostic capabilities include
loopbacks, PRBS pattern generation/detection, and 16-bit loop-up/loop-down code generation and detection. The
DS33R11 provides two on-board clock dividers for the system-clock input and reference-clock input for the 802.3
interfaces, further reducing the need for ancillary devices.
The integrated transceiver is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and
long-haul applications. The transceiver is composed of an LIU, framer, HDLC controllers, and a TDM backplane
interface, and is controlled by the 8-bit parallel port. The transceiver is software compatible with the DS2155 and
DS2156.
The LIU is composed of transmit and receive interfaces and a jitter attenuator. The transmit interface is responsible
for generating the necessary waveshapes for driving the network and providing the correct source impedance
depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line
build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75Ω coax
and 120Ω twisted cables. The receive interface provides network termination and recovers clock and data from the
network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0 to 43dB
or 0 to 12dB for E1 applications and 0 to 30dB or 0 to 36dB for T1 applications. The jitter attenuator removes
phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be
placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for
interfacing to optical networks.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Both the transmit and receive path of the integrated T1/E1/J1 transceiver also have two HDLC controllers. The
HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to
any time slot, group of time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte
FIFOs, thus reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time is required in SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface).
8.1 Processor Interface
Microprocessor control of the DS33R11 is accomplished through the interface pins of the microprocessor port. The
8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0] pins.
When MODEC[1:0] = 00, bus timing is in Intel mode, as shown in
MODEC[1:0] = 01, bus timing is in Motorola mode, as shown in
is mapped through the use of 10 address lines, A0-A9. Multiplexed Mode is not supported on the processor
interface. See the timing diagrams in AC Electrical Characteristics in Section
The Chip Select (CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port. With Intel timing selected, the Read (RD) and Write (WR) pins are used to indicate read and write operations
and latch data through the interface. With Motorola timing selected, the Read-Write (RW) pin is used to indicate
read and write operations while the Data Strobe (DS) pin is used to latch data through the interface.
Figure 13-11 and Figure 13-12. The address space
Figure 13-9 and Figure 13-10. When
13 for more details.
The interrupt output pin (INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The register
map is shown in
Table 11-1.
8.1.1 Read-Write/Data Strobe Modes
The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC[1:0] =
00 the read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a negative pulse
on WR performs a write cycle. When MODEC[1:0] pins = 01 the data strobe mode is enabled and a negative pulse
on DS when RW is high performs a read cycle, and a negative pulse on DS when RW is low performs a write cycle.
The read-write strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the
“Motorola” mode.
8.1.2 Clear on Read
The latched status registers will clear on a read access. It is important to note that in a multi-task software
environment, the user should handle all status conditions of each register at the same time to avoid inadvertently
clearing status conditions. The latched status register bits are carefully designed so that an event occurrence
cannot collide with a user read access.
8.1.3 Interrupt and Pin Modes
The interrupt (INT) pin is configurable to drive high or float when not active. The INTM bit controls the pin
configuration, when it is set the INT pin will drive high when not active. After reset, the INT pin is in high-impedance
mode until an interrupt source is active and enabled to drive the interrupt pin.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9 ETHERNET MAPPER
9.1 Ethernet Mapper Clocks
The DS33R11 clocks sources and functions are as follows:
• Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from
the serial interface. These clocks can be continuous or gapped.
• System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A
clock supply with ±100ppm frequency accuracy is suggested. A buffered version of this clock is provided
on the SDCLKO pin for the operation of the SDRAM. A divided and buffered version of this clock is
provided on REF_CLKO for the RMII/MII interface.
• Packet Interface Reference clock (REF_CLK) input that can be 25MHz or 50MHz. This clock is used as
the timing reference for the RMII/MII interface.
• The Transmit and Receive clocks for the MII Interface (TX_CLK and RX_CLK). In DTE mode, these are
input pins and accept clocks provided by an Ethernet PHY. In the DCE mode, these are output pins and
will output an internally generated clock to the Ethernet PHY. The output clocks are generated by internal
division of REF_CLK. In RMII mode, only the REF_CLK input is used.
• REF_CLKO is an output clock that is generated by dividing the 100MHz System clock (SYSCLKI) by 2 or
4.
• A Management Data Clock (MDC) output is derived from SYSCLKI and is used for information transfer
between the internal Ethernet MAC and external PHY. The MDC clock frequency is 1.67MHz.
Clocking of the integrated T1/E1/J1 tansceiver is discussed in Section
different clocking options for the Ethernet interface.
10.1. The following table provides the
Table 9-1. Clocking Options for the Ethernet Interface
RMIIMIIS
PIN
0 (MII) 10 Mbps DTE 25MHz
0 (MII) 10 Mbps DCE 25MHz
0 (MII) 100 Mbps DCE 25MHz
1 (RMII) 10 Mbps — 50MHz
1 (RMII) 100 Mbps — 50MHz
SPEED DCE/ DTE
REF_CLKO
OUTPUT
REF_CLK
INPUT
25MHz
±100ppm
25MHz
±100ppm
25MHz
±100ppm
50MHz
±100ppm
50MHz
±100ppm
RX_CLK TX_CLK
Input from
PHY
2.5MHz
(Output)
25MHz
(Output)
Not
Applicable
Not
Applicable
Input from
PHY
2.5MHz
(Output)
25MHz
(Output)
Not
Applicable
Not
Applicable
MDC
OUTPUT
1.67MHz
1.67MHz
1.67MHz
1.67MHz
1.67MHz
43 of 344
K
K
K
K
Figure 9-1. Clocking for the DS33R11
MCLK
XTALD
8XCLK
TRING
RRING
TTIP
RTIP
BPCLK TDCLKI
CLAD
LIU
TRANSMIT
LIU
RECEIVE
JTAG2 JTAG1
MUX
MUX
TDCLKO
BERT
TSYSCLK
TCHBLK
FRAMER
TRANSMIT
HDLC
HDLC
FRAMER
RECEIVIE
TCHCLK
TCLKT
T1/E1/J1
TRANSCEIVER
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TCLKE
TDEN
μP Port
CLAD
SYSCLKI
REF_CLKO
PORT
SERIAL
TRANSMIT
CIR
PACKET
HDLC/X.86
CONTROLLER
RX_CLK
REF_CLK
BERT
MAPPER
ETHERNET
ARBITER
ETHERNET MAC
TX_CLK
MDC
PORT
SERIAL
RECEIVE
PACKET
HDLC/X.86
SDRAM PORT
RDEN
JTCLK2
NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1.
RDCLKI
RDCLKO
RSYSCL
RCLKO
RCHBL
RCHCL
RCLKI
SDCL
JTCLK1
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.1.1 Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation.
Table 9-1 outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is
generated by division of the 100MHz system clock input by the user on SYSCLKI. The frequency of the
REF_CLKO pin is automatically determined by the DS33R11 based on the state of the RMIIMIIS pin. The
REF_CLKO function can be turned off with the
GL.CR1.RFOO bit. Note that in DCE and RMII operating modes,
the REF_CLKO signal should not be used to provide an input to REF_CLK, due to the reset requirements in these
operating modes.
In RMII mode, receive and transmit timing is always synchronous to a 50 MHz clock input on the REF_CLK pin.
The source of REF_CLK is expected to be the external PHY. The user has the option of using the 50MHz
REF_CLKO output as the timing source for the PHY. More information on RMII mode can be found in
Section
9.15.2.
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to
be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and
RX_CLK) are output by the DS33R11, and are derived from the 25MHz REF_CLK input. More information on MII
mode can be found in Section
9.15.1.
9.1.2 Serial Interface Clock Modes
The serial interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLKE and
RCLKI) are inputs, and can be gapped.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.2 Resets and Low Power Modes
The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the
resets all the other flops to their reset values. The processor bus output signals are also placed in high-impedance
mode when the RST pin is active (low). The global reset bit (
is reset to zero when the external RST pin is active or when a zero is written to it. Allow 5ms after initiating a reset
condition for the reset operation to complete.
The Serial Interface reset bit in LI.RSTPD resets all the status and control registers on the serial interface to their
default values, except for the
encoder and decoder and the corresponding serial port. The serial interface reset bit (
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
LI.RSTPD.RST bit. The serial interface includes the HDLC encoder/decoder, X86
GL.CR1.RST) stays set after a one is written to it, but
GL.CR1.RST bit) to their default values and
LI.RSTPD.RST) stays set
Table 9-2. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset GL.CR1 Writing to this bit resets the device.
Serial Interface Reset LI.RSTPD Writing to this bit resets the Serial Interface.
Queue Pointer Reset GL.C1QPR Writing to this bit resets the Queue Pointers.
There are several features in the DS33R11 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the RST pin or
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization and
configuration. For the lowest possible standby current, clocks may be externally gated.
The T1/E1/J1 transceiver contains an on-chip power-up reset function that automatically clears the writeable
register space immediately after power is supplied to the transceiver. The user can issue a chip reset at any time.
Issuing a reset disrupts traffic flowing through the transceiver until the device is reprogrammed. The reset can be
issued through hardware using the TSTRST pin or through software using the SFTRST function in the master
mode register. The LIRST (TR.LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. (It takes
the transceiver about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and
RSYSCLK inputs are stable, the receive and transmit elastic stores should be reset (this step can be skipped if the
elastic stores are disabled).
RST Pin
JTRST Pin
Transition from a logic 0 to a logic 1 resets the device.
Resets the JTAG test port.
GL.CR1.RST bit may be held in reset
46 of 344
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.3 Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Apply 3.3V supplies, then apply 1.8V supplies.
STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits
outlined in Section
STEP 3: Reset the integrated T1/E1/J1 Transceiver through hardware using the TSTRST pin or through software
using the SFTRST function in the master mode register.
STEP 4: The LIRST (TR.LIC2.6) should be toggled from 0 to 1 to reset the line interface circuitry. Allow 40ms for
the reset recovery.
9.2. Clear all reset bits. Allow 5ms for the reset recovery.
STEP 5: Check the Ethernet Mapper Device ID in the
STEP 6: Check the T1/E1/J1 Transceiver Device ID in the TR.IDR register.
STEP 7: Configure the system clocks. Allow the clock system to properly adjust.
STEP 8: Initialize the entire remainder of the register space with 00h (or otherwise if specifically noted in the
register’s definition), including the reserved bits and reserved register locations.
STEP 9: Write FFFFFFFFh to the MAC indirect addresses 010Ch through 010Fh.
STEP 10: Setup connection in the GL.CON1 register.
STEP 11: Configure the Serial Port register space as needed.
STEP 12: Configure the Ethernet Port register space as needed.
STEP 13: Configure the Ethernet MAC indirect registers as needed.
STEP 14: Configure the T1/E1/J1 Framer as needed.
STEP 15: Configure the T1/E1/J1 LIU as needed.
STEP 16: Configure the external Ethernet PHY through the MDIO interface.
STEP 17: Clear all counters and latched status bits.
STEP 18: Set the queue size in the Arbiter and reset the queue pointers for the Ethernet and serial interfaces.
STEP 19: After the TSYSCLK and RSYSCLK inputs to the T1/E1/J1 transceiver are stable, the receive and
transmit elastic stores should be reset (this step can be skipped if the elastic stores are disabled).
STEP 20: Enable Interrupts as needed.
GL.IDRL and GL.IDRH registers.
STEP 21: Begin handling interrupts and latched status events.
9.4 Global Resources
In order to maintain software compatibility with the multiport devices in the product family, a set of global registers
are located at 0F0h-0FFh. The global registers include Global resets, global interrupt status, interrupt masking,
clock configuration, and the Device ID registers. See the Global Register Definitions in
9.5 Per-Port Resources
Multiport devices in this product family share a common set of global registers, BERT, and arbiter. All other
resources are per-port.
Table 11-2.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.6 Device Interrupts
Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global
Latched Status registers
The host can then read the
further identify the source of the interrupt(s). In order to maintain software compatibility with the multiport devices in
the product family, the global interrupt status and interrupt enable registers have been preserved, but do not need
to be used. If
GL.TRQIS is determined to be the interrupt source, the host will then read the LI.TPPSRL and
LI.RPPSRL registers for the cause of the interrupt. If GL.LIS is determined to be the interrupt source, the host will
then read the
LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, and LI.RX86S registers for the source of the interrupt. If
GL.SIS is the source, the host will then read the SU.QCRLS register for the source of the interrupt. If GL.BIS is the
source, the host will then read the BSRL register for the source of the interrupt. All Global Interrupt Status Register
bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as long as no
additional, enabled interrupt conditions are present in the associated status register. All Latched Status bits must
be cleared by the host writing a “1” to the bit location of the interrupt condition that has been serviced. In order for
individual status conditions to transmit their status to the next level of interrupt logic, they must be enabled by
placing a “1” in the associated bit location of the correct Interrupt Enable Register. The Interrupt enable registers
LI.TPPSRIE, LI.RPPSRIE, LI.RX86LSIE, BSRIE, SU.QRIE, GL.LIE, GL.SIE, GL.BIE, and GL.TRQIE. Latched
are
Status bits that have been enabled via Interrupt Enable registers are allowed to pass their interrupt conditions to
the Global Interrupt Status Registers. The Interrupt enable registers allow individual Latched Status conditions to
generate an interrupt, but when set to zero, they do not prevent the Latched Status bits from being set. Therefore,
when servicing interrupts, the user should AND the Latched Status with the associated Interrupt Enable Register in
order to exclude bits for which the user wished to prevent interrupt service. This architecture allows the application
host to periodically poll the latched status bits for noninterrupt conditions, while using only one set of registers.
Note the bit-orders of SU.QRIE and SU.QCRLS are different.
GL.LIS, GL.SIS, GL.BIS, and GL.TRQIS to initially determine the source of the interrupt.
LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, LI.RX86S, SU.QCRLS, or BSRL registers to
Note that the inactive state of the interrupt output pin is configurable. The INTM bit in
GL.CR1 controls the inactive
state of the interrupt pin, allowing selection of a pull-up resistor or active driver.
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
latched status bits for the interrupting entity must be read to clear the interrupt. Also reading the latched status bit
will reset all bits in that register. During a reset condition, interrupts cannot be generated. The interrupts from any
source can be blocked at a global level by the placing a zero in the global interrupt enable registers (
GL.LIE,
GL.SIE, GL.BIE, and GL.TRQIE). Reading the Latched Status bit for all interrupt generating events will clear the
interrupt status bit and Interrupt signal will be de-asserted.
Note that the integrated T1/E1/J1 transceiver also generates interrupts, as discussed in Section 10.3.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 9-2. Device Interrupt Information Flow Diagram
Receive FCS Errored Packet
Receive Aborted Packet
Receive Invalid Packet Detected
Receive Small Packet Detected
Receive Large Packet Detected
Receive FCS Errored Packet Count
Receive Aborted Packet Count
Receive Size Violation Packet Count
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Transmit Errored Packet Insertion Finished
<Reserved>
<Reserved>
<Reserved>
<Reserved>
SAPI High is not equal to LI.TRX86SAPIH
SAPI Low is not equal to LI.TRX86SAPIL
Control is not equal to LI.TRX8C
Address is not equal to LI.TRX86A
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Transmit Queue FIFO Overflowed
Transmit Queue Overflow
Transmit Queue for Connection Exceeded Low Threshold
Transmit Queue for Connection Exceeded High
Threshold
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Receive Queue FIFO Overflowed
Receive Queue Overflow
Receive Queue for Connection Exceeded Low Threshold
Receive Queue for Connection Exceeded High Threshold
<Reserved>
<Reserved>
<Reserved>
<Reserved>
Performance Monitor Update
Bit Error Detected
Bit Error Count
Out Of Synchronization
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
LI.RPPSL
LI.RPPSRIE
LI.TPPSRL
LI.TPPSRIE
LI.RX86S
LI.RX86LSIE
LI.TQTIE
LI.TQCTLS
SU.QRIE
SU.QCRLS
BSRL
BSRIE
Drawing Legend:
Interrupt Status
Registers
Register Name
Interrupt
Enable
Registers
Register Name
6
5
4
3
2
GL.TRQIS
1
0
6
5
4
3
2
1
0
GL.TRQIE
GL.LIS
GL.LIE
Interrupt Pin
GL.SIS
GL.SIE
GL.BIS
GL.BIE
Interrupts from
T1/E1/J1 Transceiver
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9.7 Interrupt Information Registers
The interrupt information registers provide an indication of which status registers (SR1 through SR9) are
generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR2 to quickly identify which
of the nine status registers are causing the interrupt.
9.8 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit
in a status register is set to a 1. All of the status registers operate in a latched fashion. This means that if an event
or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An event bit is cleared when it is
read and it is not set again until the event has occurred again. Condition bits such as RBL, RLOS, etc., remain set
if the alarm is still present.
The user always proceeds a read of any of the status registers with a write. The byte written to the register informs
the device which bits the user wishes to read and have cleared. The user writes a byte to one of these registers,
with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user does not wish to obtain the
latest information on. When a 1 is written to a bit location, the read register is updated with the latest information.
When a 0 is written to a bit position, the read register is not updated and the previous value is held. A write to the
status registers is immediately followed by a read of the same register. This write-read scheme allows an external
microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register.
This operation is key in controlling the device with higher order languages.
Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically network
conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the one-second timer,
elastic store slip, etc. Each status register bit is labeled as a condition or event bit. Some of the status registers
have bits for both the detection of a condition and the clearance of the condition. For example, TR.SR2 has a bit
that is set when the device goes into a loss-of-sync state (TR.SR2.0, a condition bit) and a bit that is set
(TR.SR2.4, an event bit) when the loss-of-sync condition clears (goes in sync). Some of the status register bits
(condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce
interrupts on both edges, setting and clearing. These bits are marked as double interrupt bits. An interrupt is
produced when the condition occurs and when it clears.
9.9 Information Registers
Information registers operate the same as status registers except they cannot cause interrupts. They are all
latched except for TR.INFO7 and some of the bits in TR.INFO5 and TR.INFO6. TR.INFO7 register is a read-only
register. It reports the status of the E1 synchronizer in real time. TR.INFO7 and some of the bits in TR.INFO6 and
TR.INFO5 are not latched and it is not necessary to precede a read of these bits with a write.
9.10 Serial Interface
The Serial (WAN) interface is intended to be connected to the integrated T1/E1/J1 Transceiver. However, the
interface supports time-division multiplexed, serial data input and output up to 52 Mbit/s. The Serial interface
receives and transmits encapsulated Ethernet packets. The Serial Interface block consists of the physical serial
port and HDLC / X.86 engine. The physical interface consists of a Transmit Data, Transmit Clock, Transmit Enable,
Receive Data, Receive Clock, and Receive Enable. The WAN serial port can operate with a gapped clock, and can
be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier transceiver for transmission to the
WAN.
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9.11 Connections and Queues
The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet
ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device
to provide software compatibility with multi-port devices. The connection will have an associated transmit and
receive queue. Note that the terms “Transmit Queue” and “Receive Queue” are with respect to the Ethernet
Interface. The Receive queue is for data arriving from Ethernet interface to be transmitted to the WAN interface.
The Transmit queue is for data arriving from the WAN to be transmitted to the Ethernet interface. Hence the
transmit and receive direction terminology is the same as is used for the Ethernet MAC port.
The user can define the connection and the size of the transmit and receive queues. The size is adjustable in units
of 32 (by 2048 byte) packets. The external SDRAM can hold up to 8192 packets of data. The user must ensure
that all the connection queues do no exceed this limit. The user also must ensure that the transmit and receive
queues do not overlap each other. Unidirectional connections are not supported.
When the user changes the queue sizes, the connection must be torn down and re-established. When a
connection is disconnected all transmit and receive queues associated with the connection are flushed and a “1’ is
sourced towards the Serial transmit and the HDLC receiver. The clocks to the HDLC are sourced a “0”.
The user can also program high and low watermarks. If the queue size grows past the High watermark, an
interrupt is generated if enabled. The registers of relevance are described in
provides the size of the transmit queue for the connection. The high watermark will set a latched status bit. The
latched status bit will clear when the register is read. The status bit is indicated by
can be enabled on the latched bit events by
LI.TQTIE. A latched status bit (LI.TQCTLS.TQLTS) is also set when
the queue crosses a low watermark.
Table 9-3. The AR.TQSC1 size
LI.TQCTLS.TQHTS. Interrupts
The Receive Queue functions in a similar manner. Note that the user must ensure that sizes and watermarks are
set in accordance with the configuration speed of the Ethernet and Serial interfaces. The DS33R11 does not
provide error indication if the user creates a connection and queue that overwrites data for another connection
queue. The user must take care in setting the queue sizes and watermarks. The registers of relevance are
AR.RQSC1and SU.QCRLS. Queue size should never be set to 0.
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It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must
be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be
transmitted. The proper procedure for setting up a connection follows:
• Set up the queue sizes for both transmit and receive queue (
• Set up the high/low thresholds and interrupt enables if desired (
• Reset all the pointers for the connection desired (
• Set up the connections (
• If a connection is disconnected, reset the queue pointers after the disconnection.
GL.CON1).
GL.C1QPR).
AR.TQSC1 and AR.RQSC1).
GL.TRQIE, LI.TQTIE, SU.QRIE).
Table 9-3. Registers Related to Connections and Queues
REGISTER FUNCTION
GL.CON1
AR.TQSC1 Size for the Transmit Queue in Number of 32—2K packets.
AR.RQSC1 Size for the Receive Queue in Number of 32—2K packets.
GL.TRQIE Interrupt enable for items related to the connections at the global level
GL.TRQIS Interrupt enable status for items related to the connections at the global level
LI.TQTIE Enables for the Transmit queue crossing high and low thresholds
LI.TQCTLS Latched status bits for connection high and low thresholds for the transmit queue.
SU.QRIE Enables for the receive queue crossing high and low thresholds
Enables connection between the Ethernet Interface and the Serial Interface. Note that once
connection is set up, then the queues and thresholds can be setup for that connection.
SU.QCRLS Latched status bits for receive queue high and low thresholds.
GL.C1QPR Resets the connection pointer.
9.12 Arbiter
The Arbiter manages the transport between the Ethernet port and the Serial port. It is responsible for queuing and
dequeuing packets to a single external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer
data to and from the SDRAM.
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9.13 Flow Control
Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11
allows for optional flow control based on the queue high watermark or through host processor intervention. There
are 2 basic mechanisms that are used for flow control:
• In half duplex mode, a jam sequence is sent that causes collisions at the far end. The collisions cause the
transmitting node to reduce the rate of transmission.
• In full duplex mode, flow control is initiated by the receiving node sending a pause frame. The pause frame
has a timer parameter that determines the pause timeout to be used by the transmitting node.
Note that the terms “transmit queue” and “receive queue” are with respect to the Ethernet Interface. The Receive
Queue is the queue for the data that arrives on the MII/RMII interface, is processed by the MAC and stored in the
SDRAM. Transmit queue is for data that arrives from the Serial port, is processed by the HDLC and stored in the
SDRAM to be sent to the MAC transmitter.
The following flow control options are possible:
• Automatic flow control can be enabled in software mode with the
does not have control over
pause or jam is dependent only on the receive queue high threshold.
• Manual flow control can be performed through software when SU.GCR.ATFLOW=0. The host processor
must monitor the receive queues and generate pause frames (full duplex) and/or jam bytes through the
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR.FCE bits.
Note that in order to use flow control, the receive queue size (in AR.RQSC1) must be 02h or greater. The receive
queue high threshold (in
threshold is set to the same value as the queue size, automatic flow control will not be effective. The high threshold
must always be set to less than the corresponding queue size.
The following table provides all the options on flow control mechanism for DS33R11.
SU.RQHT) must be set to 01h or greater, but must be less than the queue size. If the high
SU.MACFCR.FCE and FCB bits if ATFLOW is set. The mechanism of sending
SU.GCR.ATFLOW bit. Note that the user
Table 9-4. Options for Flow Control
TYPE MODE
Full Duplex;
Automatic Flow
Control
Controlled
Automatically
Controlled
Automatically
Configuration
ATFLOW Bit
JAME Bit
FCB Bit
(Pause)
FCE Bit
Half Duplex; Manual
Flow Control
0 1 0 1
Controlled By User
N/A N/A Controlled by User
Controlled By User
Half Duplex;
Automatic Flow
Control
Controlled
Automatically
Controlled
Automatically
Full Duplex; Manual
Flow Control
N/A N/A
Controlled By User
Pause Timer
N/A N/A Programmed by User Programmed by User
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.13.1 Full Duplex Flow Control
Automatic flow control is enabled by default. The host processor can disable this functionality with
SU.GCR.ATFLOW. The flow control mechanism is governed by the high watermarks (SU.RQHT). The SU.RQLT
low threshold can be used as indication that the network congestion is clearing up. The value of
not affect the flow control. When the connection queue high threshold is exceeded the DS33R11 will send a pause
frame with the timer value programmed by the user. See
Table 9-6 for more information. It is recommended that 80
slots (80 by 64 bytes or 5120 bytes) be used as the standard timer value.
The pause frame causes the distant transmitter to “pause for a time” before starting transmission again. The pause
command has a multicast address 01-80-62-00-00-01. The high and low thresholds for the receive queue are
configurable by the user but it is recommended that the high threshold be set approximately 96 packets from the
maximum size of the queue and the low threshold 96 packets lower than the high threshold. The DS33R11 will
send a pause frame as the queue has crossed the high threshold and a frame is received. Pause is sent every
time a frame is received in the “high threshold state”. Pause control will only take care of temporary congestion.
Pause control does not take care of systems where the traffic throughput is too high for the queue sizes selected. If
the flow control is not effective the receive queue will eventually overflow. This is indicated by
SU.QCRLS.RQOVFL latched bit. If the receive queue is overflowed any new frames will not be received.
The user has the option of not enabling automatic flow control. In this case the thresholds and corresponding
interrupt mechanism to send pause frame by writing to flow control busy bit in the MAC flow control registers
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR. This allows the user to set not only the watermarks but also
to decide when to send a pause frame or not based on watermark crossings.
On the receive side the user has control over whether to respond to the pause frame sent by the distant end (PCF
bit). Note that if automatic flow control is enabled the user cannot modify the FCE bit in the MAC flow control
register. On the Transmit queue the user has the option of setting high and low thresholds and corresponding
interrupts. There is no automatic flow control mechanism for data received from the Serial side waiting for
transmission over the Ethernet interface during times of heavy Ethernet congestion.
SU.RQLT does
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 9-3. Flow Control Using Pause Control Frame
8
Receive Queue Low
Water
Rx
Data
Receive Queue
Growth
Receive Queue High
Water Mark
Initiate Flow control
9.13.2 Half Duplex Flow Control
Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving
node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant
end. In both 100Mbit/s and 10Mbit/s MII/RMII modes, 4 bytes are jammed upon reception of a new frame. Note
that the jamming mechanism does not jam the current frame that is being received during the watermark crossing,
but will wait to jam the next frame after the
received frames will continue to be jammed. This jam sequence is stopped when the queue falls below the high
threshold.
SU.RQHT bit is set. If the queue remains above the high threshold,
9.13.3 Host-Managed Flow Control
Although automatic flow control is recommended, flow control by the host processor is also possible. By utilizing
the high watermark interrupts, the host processor can manually issue pause frames or jam incoming packets to
exert backpressure on the transmitting node. Pause frames can be initiated with SU.MACFCR.FCB bit. Jam
sequences can be initiated be setting SU.GCR.JAME. The host can detect pause frames by monitoring
SU.RFSB3.UF and SU.RFSB3.CF. Jammed frames will be indistinguishable from packet collisions.
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9.14 Ethernet Interface Port
The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a
10/100Mbit/s MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains seven signals with
a reference clock of 50 MHz. In MII operation, the interface contains 17 signals and a clock reference of 25MHz.
The DS33R11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured for
MII in DCE mode, REF_CLK must be 25MHz. The DS33R11 will internally generate the TX_CLK and RX_CLK
outputs (at 25MHz for 100Mbps, 2.5MHz for 10Mbps) required for DCE mode from the REF_CLK input. In MII
mode with DTE operation, the TX_CLK and RX_CLK signals are generated by the PHY and are inputs to the
DS33R11. For more information on clocking the Ethernet Interface, see Section
The data received from the MII or RMII interface is processed by the internal IEEE 802.3 compliant Ethernet MAC.
The user can select the maximum frame size (up to 2016 bytes) that is received with the
SU.RMFSRL registers. The maximum frame length (in bits) is the number specified in SU.RMFSRH and
SU.RMFSRL multiplied by 8. Any programmed value greater than 2016 bytes will result in unpredictable
behavior and should be avoided. The maximum frame size is shown in
destination address, source address, VLAN tag (2 bytes), type length field, data and CRC32. The frame size is
different than the 802.3 “type length field.”
Frames from the Ethernet PHY or received from the packet processor are rejected if greater than the maximum
frame size specified. Each Ethernet frame sent or received generates status bits (
SU.RFSB0 to SU.RFSB3). These are real-time status registers and will change as each frame is sent or received.
Hence they are useful to the user only when one frame is sent or received and the status is associated with the
frame sent or received.
9.1.
SU.RMFSRH and
Figure 9-4. The length includes only
SU.TFSH and SU.TFSL and
Figure 9-4. IEEE 802.3 Ethernet Frame
Preamble SFD Destination Adrs Source Address
7 1 6 6 2 46-1500
Max Frame Length
Encapsulated Frame
The distant end will normally reject the sent frames if jabber timeout, Loss of carrier, excessive deferral, late
collisions, excessive collisions, under run, deferred or collision errors occur. Transmission of a frame under any of
theses errors will generate a status bit in SU.TFSL, SU.TFSH. The DS33R11 provides user the option to
automatically retransmit the frame if any of the errors have occurred through the bit settings in
frames and heartbeat fail have separate resend control bits (
SU.TFRC.TFBFCB and SU.TFRC.TPRHBC). If there
is no carrier (indicated by the MAC Transmit Packet Status), the transmit queue (data from the Serial Interface to
the SDRAM to Ethernet Interface) can be selectively flushed. This is controlled by
Type
Lenght
Data CRC32
4
SU.TFRC. Deferred
SU.TFRC.NCFQ.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by
SU.RFSB0 to SU.RFSB3. Note the frame status is the “real time” status and hence the value will change as new
frames are received. Hence the real time status reflects the status in time and may not correspond to the current
received frame being processed. This is also true for the transmitted frames.
Frames with errors are usually rejected by the DS33R11. The user has the option of accepting frames by settings
in Receive Frame Rejection Control register (
SU.RFRC). The user can program whether to reject or accept frames
with the following errors:
• MII error asserted during the reception of the frame
• Dribbling bits occurred in the frame
• CRC error occurred
• Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes
received
• Control frame was received. The mode must be full duplex
• Unsupported control frame was received
Note that frames received that are runt frames or frames with collision will automatically be rejected.
Table 9-5. Registers Related to Setting the Ethernet Port
REGISTER NAME FUNCTION
Transmit Frame Resend
Control
Transmit Frame Status Low
and Transmit Frame Status
High
Receive Frame Status Byte 0
to 3
Receive Frame Rejection
Control
Receiver Maximum Frame
High and Receiver Maximum
Frame Low
SU.TFRC
SU.TFSL and
SU.TFSH
SU.RFSB0 to 3
SU.RFRC
SU.RMFSRH and
SU.RMFSRL
This register determines if the current frame is retransmitted
due to various transmit errors.
These two registers provide the real-time status of the
transmit frame. Only apply to the last frame transmitted.
These registers provide the real-time status for the received
frame. Only apply to the last frame received.
This register provides settings for reception or rejection of
frame based on errors detected by the MAC.
The settings for this register provide the maximum size of
frames to be accepted from the MII/RMII receive interface.
MAC Control SU.MACCR This register provides configuration control for the MAC.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.14.1 DTE and DCE Mode
The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE
Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices
other than an Ethernet PHY. The DTE/DCE connections for the DS33R11 in MII mode are shown in the following
two figures.
In DCE Mode, the DS33R11 transmitter is connected to an external receiver and DS33R11 receiver is connected
to an external MAC transmitter. The selection of DTE or DCE mode is done by the hardware pin DCEDTES.
Figure 9-5. Configured as DTE Connected to an Ethernet PHY in MII Mode
DS33R11
MAC
Rx
DTE
Tx
RXDV
RX_CLK
RX_CRS
COL_DET
TXD[3:0] TXD[3:0]
TX_CLK
TX_EN
MDIO
MDC
RXD[3:0]RXD[3:0]
RXDV
RX_CLK
RX_ERRRX_ERR
RX_CRS
COL_DET
TX_CLK
TX_EN
MDIO
MDC
Ethernet Phy
Rx
DCE
Tx
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 9-6. DS33R11 Configured as a DCE in MII Mode
DS33Z11
9.15 Ethernet MAC
MAC
DCE
Rx Tx
RXD[3:0]
RXDV
RX_CRS
COL_DET COL_DET
TXD[3:0] RXD[3:0]
Tx
TX_CLK
TX_EN
MDIO
MDC
TXD[3:0]
TX_EN
TX_CLKRX_CLK
TX_ERRRX_ERR
RX_CRS
RX_CLK
RXDV
MDIO
MDC
DTE
MAC
Rx
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address for the write operation must be written to
SU.MACAWL and SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one
SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33R11 when the operation is complete.
to
Reading from the MAC registers requires the SU.MACRADH and SU.MACRADL registers to be written with the
address for the read operation. A read command is issued by writing a one to
SU.MACRWC.MCRW and a zero to
SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33R11 when the operation is complete. After MCS is
clear, valid data is available in
SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated (read or
write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been cleared by the
device. The MAC registers are detailed in the following table.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Table 9-6. MAC Control Registers
ADDRESS REGISTER DESCRIPTION
MAC Control Register. This register is used for programming full
0000h-0003h SU.MACCR
0014h-0017h SU.MACMIIA
0018h-001Bh SU.MACMIID
001Ch-001Fh SU.MACFCR MAC Flow Control Register
0100h-0103h SU.MMCCTRL MAC MMC Control Register. Bit 0 for resetting the status counters.
duplex, half duplex, promiscuous mode, and back-off limit for half
duplex. The transmit and receive enable bits must be set for the MAC
to operate.
MAC MII Management (MDIO) Address Register. The address for
PHY access through the MDIO interface.
MAC MII (MDIO) Data Register. Data to be written to (or read from)
the PHY through MDIO interface.
Table 9-7. MAC Status Registers
ADDRESS REGISTER DESCRIPTION
0200h-0203h SU.RxFrmCtr All frames received counter.
0204h-0207h SU.RxFrmOkCtr Number of received frames that are good.
0300h-0303h SU.TxFrmCtr Number of frames transmitted.
0308h-030Bh SU.TxBytesCtr Number of bytes transmitted.
030Ch-030Fh SU.TxBytesOkCtr Number of bytes transmitted with good frames.
0334h-0337h SU.TxFrmUndr Transmit FIFO underflow counter.
0338h-033Bh SU.TxBdFrmCtr Transmit number of frames aborted.
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9.15.1 MII Mode Options
The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII
interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section
Diagrams of system connections for MII operation are shown in
Figure 9-5 and Figure 9-6.
9.1.
9.15.2 RMII Mode
The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high. RMII
interface operates synchronously from the external 50MHz reference (REF_CLK). Only seven signals are required.
The following figure shows the RMII architecture. Note that DCE mode is not supported for RMII mode and RMII is
valid only for full duplex operation.
Figure 9-7. RMII Interface
DS33R11 MAC External PHY
TXD[1:0]
TX_EN
CRS_DV
RXD[1:0]
REF_CLK
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9.15.3 PHY MII Management Block and MDIO Interface
The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block
communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for
data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management
Interface is shown
Figure 9-8. The read/write control of the MII Management is accomplished through the indirect
SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data
Register. These indirect registers are accessed through the MAC Control Registers defined in
Table 9-6. The MDC
clock is internally generated and runs at 1.67MHz.
Figure 9-8. MII Management Frame
Preamble Start
32 bits 2 bits
Opco
Phy Adrs Phy Reg
de
2 bits 5 bits
5 bits
Turn
Aroun
d
2 bits
Data
16
bits
Idle
1
Bit
READ
WRITE
111...111 01
111...111 PHYA[4:0] PHYR[4:0] PHYD[15:0]
1001PHYA[4:0] PHYR[4:0] ZZ10ZZZZZZZZZ Z
01
Z
9.16 BERT in the Ethernet Mapper
The BERT in the Ethernet Mapper can be used for generation and detection of BERT patterns. The BERT is a
software programmable test pattern generator and monitor capable of meeting most error performance
requirements for digital transmission equipment. The following restrictions are related to the BERT:
• The RDEN and TDEN are inputs that can be used to “gap” bits.
• BERT will transmit even when the device is set for X.86 mode and TDEN is configured as an output.
• The normal traffic flow is halted while the BERT is in operation.
• If the BERT is enabled for a Serial port, it will override the normal connection.
• If there is a connection overridden by the BERT, when BERT operation is terminated the normal operation is
restored.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test
pattern payload for the programmable test pattern.
BERT Features
• PRBS and QRSS patterns of 29-1, 215-1 223-1 and QRSS pattern support.
• Programmable repetitive pattern. The repetitive pattern length and pattern are programmable.
[length n = 1 to 32 and pattern = 0 to (2
• 24-bit error count and 32-bit bit count registers.
• Programmable bit error insertion. Errors can be inserted individually.
n
– 1)].
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9.16.1 Receive Data Interface
9.16.1.1 Receive Pattern Detection
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x
n
+ xy + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to one if the
next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is
forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection
performs either PRBS synchronization or repetitive pattern synchronization.
9.16.1.2 PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least is incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
resynchronization is initiated. Automatic pattern resynchronization can be disabled.
Figure 9-9. PRBS Synchronization State Diagram
Sync
6
o
rs
rro
e
t
u
o
h
t
i
w
s
t
i
b
2
3
1 bit error
f
6
4
b
i
t
s
w
it
h
e
r
r
o
rs
LoadVerify
32 bits loaded
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.16.2 Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least sis incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be
disabled.
Figure 9-10. Repetitive Pattern Synchronization State Diagram
Sync
6
o
rs
rro
e
t
u
o
h
t
i
w
s
t
i
b
2
3
f
6
4
b
i
t
s
w
it
h
e
r
r
o
rs
1 bit error
MatchVerify
Pattern Matches
9.16.3 Pattern Monitoring
Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and
counts the incoming bits. An OOS condition is declared when the synchronization state machine is not in the
“Sync” state. An OOS condition is terminated when the synchronization state machine is in the “Sync” state.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they
do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit
count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.
9.16.4 Pattern Generation
Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable. The output of the receive pattern generator is the feedback. If QRSS is enabled,
the feedback is an XOR of bits 17 and 20, and the output is forced to one if the next 14 bits are all zeros. QRSS is
programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to one if bits 1 through 31 are all
zeros. When a new pattern is loaded, the pattern generator is loaded with a pattern value before pattern generation
starts. The pattern value is programmable (0 – 2
n
- 1). When PRBS and QRSS patterns are generated the seed
value is all ones.
n
+ xy + 1), the
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.16.4.1 Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error
insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream is
inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
9.16.4.2 Performance Monitoring Update
All counters stop counting at their maximum count. A counter register is updated by asserting (low to high
transition) the performance monitoring update signal (PMU). During the counter register update process, the
performance monitoring status signal (PMS) is de-asserted. The counter register update process consists of
loading the counter register with the current count, resetting the counter, forcing the zero count status indication
low for one clock cycle, and then asserting PMS. No events shall be missed during an update procedure.
9.17 Transmit Packet Processor
The Transmit Packet Processor accepts data from the Transmit FIFO, performs bit reordering, FCS processing,
packet error insertion, stuffing, packet abort sequence insertion, inter-frame padding, and packet scrambling. The
data output from the Transmit Packet Processor to the Transmit Serial Interface is a serial data stream (bit
synchronous mode). HDLC processing can be disabled (clear channel enable). Disabling HDLC processing
disables FCS processing, packet error insertion, stuffing, packet abort sequence insertion, and inter-frame
padding. Only bit reordering and packet scrambling are not disabled.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output from the Transmit FIFO with the MSB in
TFD[7] (or 15, 23, or 31) and the LSB in TFD[0] (or 8, 16, or 24) of the transmit FIFO data TFD[7:0] 15:8, 23:16, or
31:24). If bit reordering is enabled, the outgoing 8-bit data stream DT[1:8] is output from the Transmit FIFO with the
MSB in TFD[0] and the LSB in TFD[7] of the transmit FIFO data TFD[7:0]. In bit synchronous mode, DT [1] is the
first bit transmitted.
FCS processing calculates an FCS and appends it to the packet. FCS calculation is a CRC-16 or CRC-32
calculation over the entire packet. The polynomial used for FCS-16 is x
FCS-32 is x
32
+ x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1. The FCS is inverted after
16
+ x12 + x5 + 1. The polynomial used for
calculation. The FCS type is programmable. If FCS append is enabled, the calculated FCS is appended to the
packet. If FCS append is disabled, the packet is transmitted without an FCS. The FCS append mode is
programmable. If packet processing is disabled, FCS processing is not performed.
Packet error insertion inserts errors into the FCS bytes. A single FCS bit is corrupted in each errored packet. The
FCS bit corrupted is changed from errored packet to errored packet. Error insertion can be controlled by a register
or by the manual error insertion input (
LI.TMEI.TMEI). The error insertion initiation type (register or input) is
programmable. If a register controls error insertion, the number and frequency of the errors are programmable. If
FCS append is disabled, packet error insertion will not be performed. If packet processing is disabled, packet error
insertion is not performed.
Stuffing inserts control data into the packet to prevent packet data from mimicking flags. A packet start indication is
received, and stuffing is performed until, a packet end indication is received. Bit stuffing consists of inserting a '0'
directly following any five contiguous '1's. If packet processing is disabled, stuffing is not performed.
There is at least one flag plus a programmable number of additional flags between packets. The inter-frame fill can
be flags or all '1's followed by a start flag. If the inter-frame fill is all '1's, the number of '1's between the end and
start flags does not need to be an integer number of bytes, however, there must be at least 15 consecutive '1's
between the end and start flags. The inter-frame padding type is programmable. If packet processing is disabled,
inter-frame padding is not performed.
Packet abort insertion inserts a packet abort sequences as necessary. If a packet abort indication is detected, a
packet abort sequence is inserted and inter-frame padding is done until a packet start flag is detected. The abort
sequence is FFh. If packet processing is disabled, packet abort insertion is not performed.
The packet scrambler is a x
43
+ 1 scrambler that scrambles the entire packet data stream. The packet scrambler
runs continuously, and is never reset. In bit synchronous mode, scrambling is performed one bit at a time. In byte
synchronous mode, scrambling is performed 8 bits at a time. Packet scrambling is programmable.
Once all packet processing has been completed serial data stream is passed on to the Transmit Serial Interface.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.18 Receive Packet Processor
The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling,
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial
data stream. Packet processing can be disabled (clear channel enable). Disabling packet processing disables
packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error
monitoring, and FCS byte extraction. Only packet descrambling and bit reordering are not disabled.
The packet descrambler is a self-synchronous x
Packet descrambling is programmable. The descrambler runs continuously, and is never reset. The descrambling
is performed one bit at a time. Packet descrambling is programmable. If packet processing is disabled, the serial
data stream is demultiplexed in to an 8-bit data stream before being passed on.
If packet processing is disabled, a packet boundary is arbitrarily chosen and the data is divided into "packets" of
programmable size (dependent on maximum packet size setting). These packets are then passed on to bit
reordering with packet start and packet end indications. Data then bypasses packet delineation, inter-frame fill
filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, and FCS byte extraction.
Packet delineation determines the packet boundary by identifying a packet start or end flag. Each time slot is
checked for a flag sequence (7Eh). Once a flag is found, it is identified as a start/end flag and the packet boundary
is set. The flag check is performed one bit at a time. If packet processing is disabled, packet delineation is not
performed.
Inter-frame fill filtering removes the inter-frame fill between packets. When a packet end flag is detected, all data is
discarded until a packet start flag is detected. The inter-frame fill can be flags or all '1's. The number of '1's
between flags does not need to be an integer number of bytes, and if at least 7 '1's are detected in the first 16 bits
after a flag, all data after the flag is discarded until a start flag is detected. There may be only one flag between
packets. When the inter-frame fill is flags, the flags may have a shared zero (011111101111110). If there is less
than 16 bits between two flags, the data is discarded. If packet processing is disabled, inter-frame fill filtering is not
performed.
43
+ 1 descrambler that descrambles the entire packet data stream.
Packet abort detection searches for a packet abort sequence. Between a packet start flag and a packet end flag, if
an abort sequence is detected, the packet is marked with an abort indication, the aborted packet count is
incremented, and all subsequent data is discarded until a packet start flag is detected. The abort sequence is
seven consecutive ones. If packet processing is disabled, packet abort detection is not performed.
Destuffing removes the extra data inserted to prevent data from mimicking a flag or an abort sequence. A start flag
is detected, a packet start is set, the flag is discarded, destuffing is performed until an end flag is detected, a
packet end is set, and the flag is discarded. In bit synchronous mode, bit destuffing is performed. Bit destuffing
consists of discarding any '0' that directly follows five contiguous '1's. After destuffing is completed, the serial bit
stream is demultiplexed into an 8-bit parallel data stream and passed on with packet start, packet end, and packet
abort indications. If there is less than eight bits in the last byte, an invalid packet flag is raised, the packet is tagged
with an abort indication, and the packet size violation count is incremented. If packet processing is disabled,
destuffing is not performed.
Packet size checking checks each packet for a programmable maximum and programmable minimum size. As the
packet data comes in, the total number of bytes is counted. If the packet length is below the minimum size limit, the
packet is marked with an aborted indication, and the packet size violation count is incremented. If the packet length
is above the maximum size limit, the packet is marked with an aborted indication, the packet size violation count is
incremented, and all packet data is discarded until a packet start is received. The minimum and maximum lengths
include the FCS bytes, and are determined after destuffing has occurred. If packet processing is disabled, packet
size checking is not performed.
FCS error monitoring checks the FCS and aborts errored packets. If an FCS error is detected, the FCS errored
packet count is incremented and the packet is marked with an aborted indication. If an FCS error is not detected,
the receive packet count is incremented. The FCS type (16-bit or 32-bit) is programmable. If FCS processing or
packet processing is disabled, FCS error monitoring is not performed.
FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted from the
packet and discarded. If FCS extraction is disabled, the FCS bytes are stored in the receive FIFO with the packet.
If FCS processing or packet processing is disabled, FCS byte extraction is not performed.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7]
(or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or
31:24). If bit reordering is enabled, the incoming 8-bit data stream DT[1:8] is output to the Receive FIFO with the
MSB in RFD[0] and the LSB in RFD[7] of the receive FIFO data RFD[7:0]. DT[1] is the first bit received from the
incoming data stream.
Once all of the packet processing has been completed, The 8-bit parallel data stream is demultiplexed into a 32-bit
parallel data stream. The Receive FIFO data is passed on to the Receive FIFO with packet start, packet end,
packet abort, and modulus indications. At a packet end, the 32-bit word may contain 1, 2, 3, or 4 bytes of data
depending on the number of bytes in the packet. The modulus indications indicate the number of bytes in the last
data word of the packet.
Figure 9-11. HDLC Encapsulation of MAC Frame
Number of Bytes
Flag(0x7E)
Destination Adrs(DA)
Source Adrs(SA)
Length/Type
MAC Client Data
PAD
FCS for MAC
FCS for HDLC
Flag(0x7E)
MSB LSB
1
6
6
2
46-1500
4
0 / 2 / 4
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.19 X.86 Encoding and Decoding
X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type framing
structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to send data onto a
SONET/SDH network. The DS33R11 expects a byte synchronization signal to provide the byte boundary for the
X.86 receiver. This is provided by the RBSYNC pin. The functional timing is shown in
Figure 12-4. The X.86
transmitter provides a byte boundary indicator with the signal TBSYNC. The functional timing is shown in
Figure 12-3. Note that in some cases, additional logic may be required to meet RSYNC/TSYNC sychronization
timing requirements when operating in X.86 mode.
Figure 9-12. LAPS Encoding of MAC Frames Concept
IEEE
802.3 MAC Frame
LAPS
Rate Adaption
SDH
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Figure 9-13. X.86 Encapsulation of the MAC frame
Number of Bytes
Flag(0x7E)
Address(0x04)
Control(0x03)
1st Octect of SAPI(0xfe)
2nd Octect of SAPI(0x01)
Destination Adrs(DA)
Source Adrs(SA)
Length/Type
MAC Client Data
PAD
FCS for MAC
FCS for LAPS
Flag(0x7E)
1
1
1
1
1
6
6
2
46-1500
4
4
MSB LSB
The DS33R11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured
for X.86 mode in the register
LI.TX86E. The DS33R11 provides the following functions:
• Control Registers for Address, Control, SAPIH, SAPIL.
• 32 bit FCS enabled.
• Programmable X
43
+1 scrambling.
The sequence of processing performed by the receiver is as follows:
• Programmable octets X
43
+1 descrambling.
• Detect the Start Flag (7E).
• Remove Rate adaptation octets 7d, dd.
• Perform transparency-processing 7d, 5e is converted to 7e and 7d, 5d is converted to 7d.
• Check for a valid Address, Control and SAPI fields (
LI.TRX86A to LI.TRX86SAPIL).
• Perform FCS checking.
• Detect the closing flag.
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The X86 received frame is aborted if:
• If 7d,7E is detected. This is an abort packet sequence in X.86.
• Invalid FCS is detected.
• The received frame has less than 6 octets.
• Control, SAPI and address field are mismatched to the programmed value.
• Octet 7d and octet other than 5d,5e,7e or dd is detected.
For the transmitter if X.86 is enabled the sequence of processing is as follows:
• Construct frame including start flag, SAPI, Control and MAC frame.
• Calculate FCS.
• Perform transparency processing - 7E is translated to 7D5E, 7D is translated to 7D5D.
• Append the end flag(7E).
• Scramble the sequence X
43
+1.
Note that the serial transmit and receive registers apply to the X.86 implementations with specific exceptions. The
exceptions are outlined in the serial interface transmit and receive register sections.
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9.20 Committed Information Rate Controller
The DS33R11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC
data to a programmable rate. The CIR location is shown in the
the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN. The
user must set the CIR register to control the amount of data throughput from the MAC to HDLC transmit. The CIR
register is in granularity of 500kbit/s with a range of 0 to 52Mbit/s. The operation of the CIR is as follows:
• The CIR block counts the credits that are accumulated at the end of every 125ms.
• If data is received and stored in the SDRAM to be sent to the Serial Interface, the interface will request the
data if there is a positive credit balance. If the credit balance is negative, transmit interface does not
request data.
• New credit balance is calculated credit balance = old credit balance – frame size in bytes after the frame
is sent.
• The credit balance is incremented every 125ms by CIR/8.
• Credit balances not used in 250ms are reset to 0.
• The maximum value of CIR can not exceed the transmit line rate.
• If the data rate received from the Ethernet interface is higher than the CIR, the receive queue buffers will fill
and the high threshold water mark will invoke flow control to reduce the incoming traffic rate.
Figure 6-1. The CIR will restrict the data flow from
• The CIR function is only available for software mode of operation only.
• CIR function is only available in data received at the Ethernet Interface to be sent to WAN. There is not
CIR functionality for data arriving from the WAN to be sent to the Ethernet Interface.
• Negative credits are not allowed, if there is not a credit balance, no frames are sent until there is a credit
balance again.
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10 INTEGRATED T1/E1/J1 TRANSCEIVER
10.1 T1/E1/J1 Clocks
Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are
shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator,
which can be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 10-1. T1/E1/J1 Clock Map
RXCLK
TO
LIU
TXCLK
The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR.CCR1 register and the state of
the TCLKT pin.
MCLKS = 0
2.048 TO 1.544
SYNTHESIZER
RCL = 1
RCL = 0
MCLK
MCLKS = 1
PRE-SCALER
LOCAL
LOOPBACK
LLB = 0
LLB = 1
TR.LIC4.MPS0
TR.LIC4.MPS1
TR.LIC2.3
JITTER ATTENUATOR
SEE TR.LIC1
REGISTER
LTCA
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
LTCA
REMOTE
LOOPBACK
RLB = 1
RLB = 0
DJA = 1
DJA = 0
FRAMER
LOOPBACK
FLB = 0
FLB = 1
RECEIVE
FRAMER
TRANSMIT
FORMATTER
8 x PLL
PAYLOAD
LOOPBACK
(SEE NOTES)
PLB = 1
PLB = 0
BPCLK
SYNTH
BA
TCLKT
MUX
C
TSYSCLK
8XCLK
BPCLK
RCLK
TCLKT
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Table 10-1. T1/E1/J1 Transmit Clock Source
TCSS1 TCSS0 TRANSMIT CLOCK SOURCE
0 0 The TCLKT pin (C) is always the source of transmit clock.
0 1
1 0
1 1
Switch to the recovered clock (B) when the signal at the TCLKT pin
fails to transition after one channel time.
Use the scaled signal (A) derived from MCLK as the transmit clock.
The TCLKT pin is ignored.
Use the recovered clock (B) as the transmit clock. The TCLKT pin is
ignored.
10.2 Per-Channel Operation
Some of the features described in the data sheet that operate on a per-channel basis use a special method for
channel selection. There are five registers involved: per-channel pointer register (TR.PCPR) and per-channel data
registers 1–4 (TR.PCDR1–4). The user selects which function or functions are to be applied on a per-channel
basis by setting the appropriate bit(s) in the TR.PCPR register. The user then writes to the TR.PCDR registers to
select the channels for that function. The following is an example of mapping the transmit and receive BERT
function to channels 9–12, 20, and 21.
Write 11h to TR.PCPR
Write 00h to TR.PCDR1
Write 0fh to TR.PCDR2
Write 18h to TR.PCDR3
Write 00h to TR.PCDR4
The user may write to the TR.PCDR1-4 with multiple functions in the TR.PCPR register selected, but can only read
the values from the TR.PCDR1-4 registers for a single function at a time. More information about how to use these
per-channel features can be found in the
TR.PCPR register.
10.3 T1/E1/J1 Transceiver Interrupts
Various alarms, conditions, and events in the T1/E1/J1 transceiver can cause interrupts. For simplicity, these are
all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each
status register has an associated interrupt mask register. For example, TR.SR1 (status register 1) has an interrupt
control register called TR.IMR1 (interrupt mask register 1). Status registers are the only sources of interrupts in the
device. On power-up, all writeable registers of the T1/E1/J1 transceiver are automatically cleared. Since bits in the
TR.IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until
the host selects which events are to product interrupts. Since there are potentially many sources of interrupts on
the device, several features are available to help sort out and identify which event is causing an interrupt. When an
interrupt occurs, the host should first read the TR.IIR1 and TR.IIR2 registers (interrupt information registers) to
identify which status register (or registers) is producing the interrupt. Once that is determined, the individual status
register or registers can be examined to determine the exact source.
Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (TR.CCR3.6) to stop further
activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine
should re-enable interrupts by setting the INTDIS bit = 0.
Note that the integrated Ethernet Mapper also generates interrupts, as discussed in Section 9.6.
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10.4 T1 Framer/Formatter Control and Status
The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the transceiver has been initialized, the
control registers only need to be accessed when there is a change in the system configuration. There are two
receive control registers (TR.T1RCR1 and TR.T1RCR2), two transmit control registers (TR.T1TCR1 and
TR.T1TCR2), and a common control register (TR.T1CCR1). Each of these registers is described in this section.
10.4.1 T1 Transmit Transparency
The software signaling insertion-enable registers, TR.SSIE1–TR.SSIE4, can be used to select signaling insertion
from the transmit signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows
signaling data to be sourced from the signaling registers for that channel.
In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the
channels. If a DS0 is programmed to be clear, no robbed-bit signaling is inserted nor does the channel have bit 7
stuffing performed. However, in the D4 framing mode, bit 2 is overwritten by a 0 when a Yellow Alarm is
transmitted. Also, the user has the option to globally override the TR.SSIEx registers from determining which
channels are to have bit 7 stuffing performed. If the TR.T1TCR1.3 and TR.T1TCR2.0 bits are set to 1, then all 24
T1 channels have bit 7 stuffing performed on them, regardless of how the TR.SSIEx registers are programmed. In
this manner, the TR.SSIEx registers are only affecting the channels that are to have robbed-bit signaling inserted
into them.
10.4.2 AIS-CI and RAI-CI Generation and Detection
The device can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with
and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI
T1.403.
The AIS-CI code (alarm indication signal-customer installation) is the same for both ESF and D4 operation. Setting
the TAIS-CI bit in the TR.T1CCR1 register and the TBL bit in the TR.T1TCR1 register causes the device to
transmit the AIS-CI code. The RAIS-CI status bit in the TR.SR4 register indicates the reception of an AIS-CI signal.
The RAI-CI (remote alarm indication-customer installation) code for T1 ESF operation is a special form of the ESF
Yellow Alarm (an unscheduled message). Setting the RAIS-CI bit in the TR.T1CCR1 register causes the device to
transmit the RAI-CI code. The RAI-CI code causes a standard Yellow Alarm to be detected by the receiver. When
the host processor detects a Yellow Alarm, it can then test the alarm for the RAI-CI state by checking the BOC
detector for the RAI-CI flag. That flag is a 011111 code in the 6-bit BOC message.
The RAI-CI code for T1 D4 operation is a 10001011 flag in all 24 time slots. To transmit the RAI-CI code the host
sets all 24 channels to idle with a 10001011 idle code. Since this code meets the requirements for a standard T1
D4 Yellow Alarm, the host can use the receive channel monitor function to detect the 100001011 code whenever a
standard Yellow Alarm is detected.
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10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation
Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers
(TR.T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be
overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a
1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the TR.T1RDMRx registers represents a particular
channel. If a bit is set to a 1, then the receive data in that channel is replaced with the digital-milliwatt code. If a bit
is set to 0, no replacement occurs.
Table 10-2. T1 Alarm Criteria
ALARM SET CRITERIA CLEAR CRITERIA
Blue Alarm (AIS)
(Note 1)
Yellow Alarm (RAI)
D4 Bit 2 Mode
(TR.T1RCR2.0 = 0)
D4 12th F-Bit Mode
(TR.T1RCR2.0 = 1; this mode is
also referred to as the “Japanese
Yellow Alarm”)
When over a 3ms window, five or
fewer 0s are received
When bit 2 of 256 consecutive
channels is set to 0 for at least 254
occurrences
When the 12th framing bit is set to 1
for two consecutive occurrences
ESF Mode When 16 consecutive patterns of
00FF appear in the FDL
When over a 3ms window, six or
more 0s are received
When bit 2 of 256 consecutive
channels is set to 0 for fewer than
254 occurrences
When the 12th framing bit is set to
0 for two consecutive occurrences
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in
the FDL
Red Alarm (LRCL)
(Also referred to as loss of signal)
Note 1: The definition of Blue Alarm (or AIS) is an unframed all-ones signal. Blue Alarm detectors should be able to operate properly in the
presence of a 10E-3 error rate and they should not falsely trigger on a framed all-1s signal. Blue Alarm criteria in the device has been
set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.
Note 2: ANSI specifications use a different nomenclature than this document. The following terms are equivalent:
RBL = AIS
RCL = LOS
RLOS = LOF
RYEL = RAI
When 192 consecutive 0s are
received
When 14 or more 1s out of 112
possible bit positions are received
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10.5 E1 Framer/Formatter Control and Status
The E1 framer portion of the transceiver is configured by a set of four control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the device has been initialized, the control
registers need only to be accessed when there is a change in the system configuration. There are two receive
control registers (TR.E1RCR1 and TR.E1RCR2) and two transmit control registers (TR.E1TCR1 and TR.E1TCR2).
There are also four status and information registers. Each of these eight registers is described in this section.
Table 10-3. E1 Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
FAS
CRC4
CAS
SYNC CRITERIA RESYNC CRITERIA ITU SPEC.
Three consecutive incorrect
FAS received
FAS present in frame N and
N + 2; FAS not present in
frame N + 1
Alternate: (TR.E1RCR1.2 = 1)
The above criteria is met or
G.706
4.1.1
4.1.2
three consecutive incorrect bit
2 of non-FAS received
Two valid MF alignment
words found within 8ms
915 or more CRC4 codewords
out of 1000 received in error
G.706
4.2 and 4.3.2
Valid MF alignment word
found and previous time slot
16 contains code other than
Two consecutive MF alignment
words received in error
G.732
5.2
all 0s
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10.5.1 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (TR.E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following
conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive
carrier (or signal). The framer forces either an AIS or remote alarm if any one or more of these conditions is
present.
When automatic RAI generation is enabled (TR.E1TCR2.0 = 1), the framer monitors the receive side to determine
if any of the following conditions are present: loss-of-receive-frame synchronization, AIS alarm (all ones) reception,
loss-of-receive carrier (or signal), or if CRC4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC4 is enabled). If any one or more of these conditions is present, then the framer transmits
an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted
if the device cannot find CRC4 multiframe synchronization within 400ms as per G.706.
Note: It is an invalid state to have both automatic AIS generation and automatic remote alarm generation enabled
at the same time.
Table 10-4. E1 Alarm Criteria
ALARM SET CRITERIA CLEAR CRITERIA
An RLOS condition exists on power-up
prior to initial synchronization, when a
RLOS
RCL
RRA
RUA1
RDMA
V52LNK Two out of three Sa7 bits are 0 G.965
resync criteria has been met, or when a
manual resync has been initiated by
TR.E1RCR1.0
255 or 2048 consecutive 0s received as
determined by TR.E1RCR2.0
Bit 3 of nonalign frame set to 1 for three
consecutive occasions
Fewer than three 0s in two frames (512
bits)
Bit 6 of time slot 16 in frame 0 has been set
for two consecutive multiframes
At least 32 1s in 255-bit times
are received
Bit 3 of nonalign frame set to
0 for three consecutive
occasions
More than two 0s in two
frames (512 bits)
SPECIFICATION
ITU
G.775/G.962
O.162
2.1.4
O.162
1.6.1.2
10.6 Per-Channel Loopback
The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be
replaced with the data from the receive side or, i.e., off of the T1 or E1 line. If this loopback is enabled, then
transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this is to connect
RCLKO to TCLKT and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on
how many channels can be looped back.
Each of the bit positions in the per-channel loopback registers (TR.PCLR1/TR.PCLR2/TR.PCLR3/TR.PCLR4)
represents a DS0 channel in the outgoing frame. When these bits are set to a 1, data from the corresponding
receive channel replaces the data on TSERI for that channel.
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10.7 Error Counters
The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and
synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1
mode only), or manual. See Error-Counter Configuration Register (TR.ERCNT). When updated automatically, the
user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at
their respective maximum counts, and they do not roll over. Note: Only the line-code violation count register has
the potential to overflow, but the bit error would have to exceed 10E-2 before this would occur.
10.7.1 Line-Code Violation Counter (TR.LCVCR)
In T1 mode, code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for
the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during
receive loss-of-synchronization (RLOS = 1) conditions.
Table 10-5 shows what the LCVCRs count.
Table 10-5 T1 Line Code Violation Counting Options
COUNT EXCESSIVE
ZEROS?
(TR.ERCNT.0)
No No BPVs
Yes No BPVs + 16 consecutive 0s
No Yes BPVs (B8ZS codewords not counted)
Yes Yes BPVs + 8 consecutive 0s
In E1 mode, either bipolar violations or code violations can be counted. Bipolar violations are defined as
consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receive side, then HDB3
codewords are not counted as BPVs. If TR.ERCNT.3 is set, then the LVC counts code violations as defined in ITU
O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the
framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3
code. This counter increments at all times and is not disabled by loss-of-sync conditions. The counter saturates at
65,535 and does not roll over. The bit-error rate on an E1 line would have to be greater than 10
would saturate (
Table 10-6).
B8ZS ENABLED?
(TR.T1RCR2.5)
COUNTED IN THE LCVCRs
-2
before the VCR
Table 10-6. E1 Line-Code Violation Counting Options
E1 CODE VIOLATION SELECT
(TR.ERCNT.3)
0 BPVs
1 CVs
COUNTED IN THE LCVCRs
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10.7.2 Path Code Violation Count Register (TR.PCVCR)
In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive
side of a framer is set to operate in the T1 ESF framing mode, TR.PCVCR records errors in the CRC6 codewords.
When set to operate in the T1 D4 framing mode, TR.PCVCR counts errors in the Ft framing bit position. Through
the TR.ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The
TR.PCVCR is disabled during receive loss-of-synchronization (RLOS = 1) conditions.
Table 10-7 shows what
errors the TR.PCVCR counts.
Table 10-7. T1 Path Code Violation Counting Arrangements
FRAMING MODE COUNT Fs ERRORS?
COUNTED
IN THE PCVCRs
D4 No Errors in the Ft pattern
D4 Yes Errors in both the Ft and Fs patterns
ESF Don’t Care Errors in the CRC6 codewords
In E1 mode, the path code violation-count register records CRC4 errors. Since the maximum CRC4 count in a onesecond period is 1000, this counter cannot saturate. The counter is disabled during loss-of-sync at either the FAS
or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level.
Path code violation-count register 1 (TR.PCVCR1) is the most significant word and TR.PCVCR2 is the least
significant word of a 16-bit counter that records path violations (PVs).
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10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR)
In T1 mode, TR.FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync.
This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and
ESF error events as described in AT&T publication TR54016. When TR.FOSCR is operated in this mode, it is not
disabled during receive loss-of-synchronization (RLOS = 1) conditions. TR.FOSCR has an alternate operating
mode whereby it counts either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern
(in the ESF mode). When TR.FOSCR is operated in this mode, it is disabled during receive loss-of-synchronization
(RLOS = 1) conditions.
Table 10-8 shows what the FOSCR is capable of counting.
Table 10-8. T1 Frames Out-of-Sync Counting Arrangements
FRAMING MODE
(TR.T1RCR1.3)
D4 MOS Number of multiframes out-of-sync
D4 F-Bit Errors in the Ft pattern
ESF MOS Number of multiframes out-of-sync
ESF F-Bit Errors in the FPS pattern
In E1 mode, TR.FOSCR counts word errors in the FAS in time slot 0. This counter is disabled when RLOS is high.
FAS errors are not counted when the framer is searching for FAS alignment and/or synchronization at either the
CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this
counter cannot saturate.
The frames out-of-sync count register 1 (TR.FOSCR1) is the most significant word and TR.FOSCR2 is the least
significant word of a 16-bit counter that records frames out-of-sync.
COUNT MOS OR
F-BIT ERRORS
(TR.ERCNT.1)
COUNTED IN THE FOSCRs
10.7.4 E-Bit Counter (TR.EBCR)
This counter is only available in E1 mode. E-bit count register 1 (TR.EBCR1) is the most significant word and
TR.EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in
the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers increment once
each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this
counter cannot saturate. The counter is disabled during loss-of-sync at either the FAS or CRC4 level; it continues
to count if loss-of-multiframe sync occurs at the CAS level.
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10.8 DS0 Monitoring Function
The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel
in the receive direction at the same time. In the transmit direction, the user determines which channel is to be
monitored by properly setting the TCM0 to TCM4 bits in the TR.TDS0SEL register. In the receive direction, the
RCM0 to RCM4 bits in the TR.RDS0SEL register need to be properly set. The DS0 channel pointed to by the
TCM0 to TCM4 bits appear in the transmit DS0 monitor (TR.TDS0M) register. The DS0 channel pointed to by the
RCM0 to RCM4 bits appear in the receive DS0 (TR.RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0
bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24
map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example,
if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored,
then the following values would be programmed into TR.TDS0SEL and TR.RDS0SEL:
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
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A
10.9 Signaling Operation
There are two methods to access receive signaling data and provide transmit signaling data, processor-based
(software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling
registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be
used simultaneously.
Figure 10-2. Simplified Diagram of Receive Signaling Path
PER-CHANNEL
CONTROL
T1/E1 DATA STREAM
SIGNALING
EXTRACTION
RECEIVE SIGNALING
REGISTERS
CHANGE-OF-STATE
INDICATION
REGISTERS
LL-ONES
REINSERTION
CONTROL
SIGNALING
BUFFERS
RSERO
RSYNC
RSIG
10.9.1 Processor-Based Receive Signaling
The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into
the receive signaling registers, RS1–RS16. In T1 mode, only RS1–RS12 are used. The signaling information in
these registers is always updated on multiframe boundaries. This function is always enabled.
10.9.1.1 Change-of-State
To avoid constant monitoring of the receive signaling registers, the transceiver can be programmed to alert the
host when any specific channel or channels undergo a change of their signaling state. TR.RSCSE1–TR.RSCSE4
for E1 and TR.RSCSE1–TR.RSCSE3 for T1 are used to select which channels can cause a change-of-state
indication. The change-of-state is indicated in status register 5 (TR.SR1.5). If signaling integration (TR.CCR1.5) is
enabled, then the new signaling state must be constant for three multiframes before a change-of-state is indicated.
The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the TR.IMR1.5 bit.
The signaling integration mode is global and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change-of-state by reading the TR.RSINFO1–
TR.RSINFO4 registers. The information from these registers inform the user which TR.RSx register to read for the
new signaling data. All changes are indicated in the TR.RSINFO1–TR.RSINFO4 registers regardless of the
TR.RSCSE1–TR.RSCSE4 registers.
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10.9.2 Hardware-Based Receive Signaling
In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a
signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1
robbed bit or E1 TS16, is still present in the original data stream at RSERO. The signaling buffer provides signaling
data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different
alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can
be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either
1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble
of each channel. The RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing
mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6
contain the same data as bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe
(1.5ms) unless a freeze is in effect. See the timing diagrams in Section
10.9.2.1 Receive Signaling Reinsertion at RSERO
In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data is reinserted based on
this alignment. In T1 mode, this results in two copies of the signaling data in the RSERO data stream, the original
signaling data and the realigned data. This is of little consequence in voice channels. Reinsertion can be avoided
in data channels since this feature is activated on a per-channel basis. In this mode, the elastic store must be
enabled; however, the backplane clock can be either 1.544MHz or 2.048MHz.
Signaling reinsertion can be enabled on a per-channel basis by setting the RSRCS bit high in the TR.PCPR
register. The channels that will have signaling reinserted are selected by writing to the TR.PCDR1–TR.PCDR3
registers for T1 mode and TR.PCDR1–TR.PCDR4 registers for E1 mode. In E1 mode, the user generally selects
all channels or none for reinsertion. In E1 mode, signaling reinsertion on all channels can be enabled with a single
bit, TR.SIGCR.7 (GRSRE). This bit allows the user to reinsert all signaling channels without having to program all
channels through the per-channel function.
10.9.2.2 Force Receive Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to a 1 by using the
per-channel register (Section
10.2). The user sets the BTCS bit in the TR.PCPR register. The channels that will be
forced to 1 are selected by writing to the TR.PCDR1–TR.PCDR3 registers.
10.9.2.3 Receive Signaling Freeze
The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore TR–TSY–
000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit (TR.SIGCR.4) should be set
high. The user can force a freeze by setting the RFF control bit (TR.SIGCR.3) high. The RSIGF output pin provides
a hardware indication that a freeze is in effect. The four-multiframe buffer provides a three-multiframe delay in the
signaling bits provided at the RSIG pin (and at the RSERO pin if receive signaling reinsertion is enabled). When
freezing is enabled (RFE = 1), the signaling data is held in the last-known good state until the corrupting error
condition subsides. When the error condition subsides, the signaling data is held in the old state for at least an
additional 9ms (or 4.5ms in D4 framing mode) before updating with new signaling data.
12 for some examples.
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Figure 10-3. Simplified Diagram of Transmit Signaling Path
T1/E1 DATA
STREAM
0
1
B7
ONLY APPLIES TO T1 MODE
PER-CHANNEL
CONTROL
TR.SSIE1 TR.SSIE4
TRANSMIT
SIGNALING
REGISTERS
1
0
0
1
TR.T1TCR1.4
PER-CHANNEL
CONTROL
TR.PCPR.3
SIGNALING
BUFFERS
TSER
TSIG
10.9.3 Processor-Based Transmit Signaling
In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host
interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in
the appropriate bit position in the outgoing data stream. The user can employ the transmit multiframe interrupt in
status register 4 (TR.SR4.4) to know when to update the signaling bits. The user need not update any transmit
signaling register for which there is no change-of-state for that register.
Each transmit signaling register contains the robbed-bit signaling (T1) or TS16 CAS signaling (E1) for two time
slots that are inserted into the outgoing stream, if enabled to do so through TR.T1TCR1.4 (T1 mode) or
TR.E1TCR1.6 (E1 mode). In T1 mode, only TS1–TS12 are used.
Signaling data can be sourced from the TR.TS registers on a per-channel basis by using the software signaling
insertion enable registers, TR.SSIE1–TRSSIE4.
10.9.3.1 T1 Mode
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a full
multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1
D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. In
D4 mode, two multiframes of signaling data can be loaded into TS1–TS12. The framer loads the contents of TS1–
TS12 into the outgoing shift register every other D4 multiframe. In D4 mode, the host should load new contents into
TS1–TS12 on every other multiframe boundary and no later than 120μs after the boundary. In T1 mode, only
registers TR.SSIE1–TR.SSIE3 are used since there are only 24 channels in a T1 frame.
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10.9.3.2 E1 Mode
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel
signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel
number schemes in E1. In “Channel” numbering, TS0–TS31 are labeled channels 1 through 32. In “Phone
Channel” numbering, TS1–TS15 are labeled channel 1 through channel 15 and TS17–TS31 are labeled channel
15 through channel 30. In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the
transmit signaling registers along with the signaling data.
Table 10-9. Time Slot Numbering Schemes
TS
Channel
Phone
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Channel
10.9.4 Hardware-Based Transmit Signaling
In hardware-based mode, signaling data is input through the TSIG pin. This signaling PCM stream is buffered and
inserted to the data stream being input at the TSERI pin.
Signaling data can be inserted on a per-channel basis by the transmit hardware-signaling channel-select (THSCS)
function. The user has the ability to control which channels are to have signaling data from the TSIG pin inserted
into them on a per-channel basis. See Section
signaling insertion capabilities of the framer are available whether the transmit-side elastic store is enabled or
disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz.
Also, if the elastic is enabled in conjunction with transmit hardware signaling, CCR3.7 must be set = 0.
10.2 for details on using this per-channel (THSCS) feature. The
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10.10 Per-Channel Idle Code Generation
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When
operated in the T1 mode, only the first 24 channels are used by the device, the remaining channels, CH25–CH32,
are not used.
The device contains a 64-byte idle code array accessed by the idle array address register (TR.IAAR) and the perchannel idle code register (TR.PCICR). The contents of the array contain the idle codes to be substituted into the
appropriate transmit or receive channels. This substitution can be enabled and disabled on a per-channel basis by
the transmit-channel idle code-enable registers (TR.TCICE1–4) and receive-channel idle code-enable registers
(TR.RCICE1–4).
To program idle codes, first select a channel by writing to the TR.IAAR register. Then write the idle code to the
TR.PCICR register. For successive writes there is no need to load the TR.IAAR with the next consecutive address.
The TR.IAAR register automatically increments after a write to the TR.PCICR register. The auto increment feature
can be used for read operations as well. Bits 6 and 7 of the TR.IAAR register can be used to block write a common
idle code to all transmit or receive positions in the array with a single write to the TR.PCICR register. Bits 6 and 7
of the TR.IAAR register should not be used for read operations. TR.TCICE1–4 and TR.RCICE1–4 are used to
enable idle code replacement on a per-channel basis.
Table 10-10. Idle-Code Array Address Mapping
BITS 0 to 5 OF IAAR
REGISTER
0 Transmit Channel 1
1 Transmit Channel 2
2 Transmit Channel 3
— —
— —
30 Transmit Channel 31
31 Transmit Channel 32
32 Receive Channel 1
33 Receive Channel 2
34 Receive Channel 3
— —
— —
62 Receive Channel 31
63 Receive Channel 32
MAPS TO CHANNEL
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10.10.1 Idle-Code Programming Examples
Example 1
Sets transmit channel 3 idle code to 7Eh
Write TR.IAAR = 02h ;select channel 3 in the array
Write TR.PCICR = 7Eh ;set idle code to 7Eh
Example 2
Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels.
Write TR.IAAR = 02h ;select channel 3 in the array
Write TR.PCICR = 7Eh ;set channel 3 idle code to 7Eh
Write TR.PCICR = 7Eh ;set channel 4 idle code to 7Eh
Write TR.PCICR = 7Eh ;set channel 5 idle code to 7Eh
Write TR.PCICR = 7Eh ;set channel 6 idle code to 7Eh
Write TR.TCICE1 = 3Ch ;enable transmission of idle codes for channels 3,4,5, and 6
Example 3
Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh, EEh, FFh, and 7Eh, respectively.
Write TR.IAAR = 02h
Write TR.PCICR = 7Eh
Write TR.PCICR = EEh
Write TR.PCICR = FFh
Write TR.PCICR = 7Eh
Example 4
Sets all transmit idle codes to 7Eh.
Write TR.IAAR = 4xh
Write TR.PCICR = 7Eh
Example 5
Sets all receive and transmit idle codes to 7Eh and enables idle code substitution in all E1 transmit and receive
channels.
Write TR.IAAR = Cxh ;enable block write to all transmit and receive positions in the array
Write TR.PCICR = 7Eh ;7Eh is idle code
Write TR.TCICE1 = FEh ;enable idle code substitution for transmit channels 2 through 8
Write TR.TCICE2 = FFh ;enable idle code substitution for transmit channels 9 through 16
Write TR.TCICE3 = FEh ;enable idle code substitution for transmit channels 18 through 24
Write TR.TCICE4 = FFh ;enable idle code substitution for transmit channels 25 through 32
Write TR.RCICE1 = FEh ;enable idle code substitution for receive channels 2 through 8
Write TR.RCICE2 = FFh ;enable idle code substitution for receive channels 9 through 16
Write TR.RCICE3 = FEh ;enable idle code substitution for receive channels 18 through 24
Write TR.RCICE4 = FFh ;enable idle code substitution for receive channels 25 through 32
;Although an idle code was programmed for channel 1 by the block write
;function above, enabling it for channel 1 would step on the frame
;alignment, alarms, and Sa bits
;Although an idle code was programmed for channel 17 by the block write
;function above, enabling it for channel 17 would step on the CAS frame
;alignment, and signaling information
The transmit-channel idle-code enable registers (TR.TCICE1/2/3/4) are used to determine which of the 24 T1 or 32
E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel
code array.
The receive-channel idle-code enable registers (TR.RCICE1/2/3/4) are used to determine which of the 24 T1 or 32
E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel
code array.
.
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10.11 Channel Blocking Registers
The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel
blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low
during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI
applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins are held high during the
entire corresponding channel time. Channels 25 through 32 are ignored when the device is operated in the T1
mode.
10.12 Elastic Stores Operation
The device contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction.
Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled
independently of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/
8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store is interfacing to.
The elastic stores have two main purposes. Firstly, they can be used for rate conversion. When the device is in the
T1 mode, the elastic stores can rate-convert the T1 data stream to a 2.048MHz backplane. In E1 mode, the elastic
store can rate-convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the
differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked)
backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate difference
and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the
network and the backplane. The elastic stores can also be used to multiplex T1 or E1 data streams into higher
backplane rates.
10.12.1 Receive Elastic Store
See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. If the receive-side
elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin.
The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin
provide a pulse on frame/multiframe boundaries. If signaling reinsertion is enabled, signaling data in TS16 is
realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a
simple frame boundary by the elastic store. The framer always indicates frame boundaries on the network side of
the elastic store by the RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries are
always indicated by the RMSYNC output. If the elastic store is enabled, then RMSYNC outputs the multiframe
boundary on the backplane side of the elastic store.
10.12.1.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then the data output at RSERO is forced to all
1s every fourth channel and the F-bit is passed into the MSB of TS0. Hence, channels 1 (bits 1–7), 5, 9, 13, 17, 21,
25, and 29 [time slots 0 (bits 1–7), 4, 8, 12, 16, 20, 24, and 28] are forced to a 1. Also, in 2.048MHz applications,
the RCHBLK output is forced high during the same channels as the RSERO pin. This is useful in T1-to-E1
conversion applications. If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer
empties, then a full frame of data is repeated at RSERO, and the TR.SR5.0 and TR.SR5.1 bits are set to a 1. If the
buffer fills, then a full frame of data is deleted, and the TR.SR5.0 and TR.SR5.2 bits are set to a 1.
10.12.1.2 E1 Mode
If the elastic store is enabled, then either CAS or CRC4 multiframe boundaries are indicated through the RMSYNC
output. If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data is deleted and an F-bit position, which is forced to 1, is inserted. Hence, channels 1, 5, 9, 13, 17,
21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are deleted from the received E1 data stream. Also, in
1.544MHz applications, the RCHBLK output is not active in channels 25 through 32 (i.e., RCBR4 is not active). If
the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, then a full frame of
data is repeated at RSERO, and the TR.SR5.0 and TR.SR5.1 bits are set to a 1. If the buffer fills, then a full frame
of data is deleted, and the TR.SR5.0 and TR.SR5.2 bits are set to a 1.
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10.12.2 Transmit Elastic Store
See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. The operation of
the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled, a 1.544MHz
or 2.048MHz clock can be applied to the TSYSCLK input. Controlled slips in the transmit elastic store are reported
in the TR.SR5.3 bit, and the direction of the slip is reported in the TR.SR5.4 and TR.SR5.5 bits. If hardware
signaling insertion is not enabled, TR.CCR3.7 should be set = 1.
10.12.2.1 T1 Mode
If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSERI is ignored every
fourth channel. Therefore channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are
ignored. The user can supply frame or multiframe sync pulse to the TSSYNC input. Also, in 2.048MHz
applications, the TCHBLK output is forced high during the channels ignored by the framer.
10.12.2.2 E1 Mode
A 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. The user must supply a frame sync pulse or
a multiframe sync pulse to the TSSYNC input.
10.12.3 Elastic Stores Initialization
There are two elastic store initializations that can be used to improve performance in certain applications, elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLKO/TCLKT,
respectively) (
Table 10-11).
Table 10-11. Elastic Store Delay After Initialization
INITIALIZATION REGISTER BIT DELAY
Receive Elastic Store Reset
Transmit Elastic Store Reset
Receive Elastic Store Align
Transmit Elastic Store Align
10.12.4 Minimum Delay Mode
Elastic store minimum delay mode can be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLKO locked to RSYSCLK for the receive side and TCLKT locked to TSYSCLK for the transmit side).
TR.ESCR.5 and TR.ESCR.1 enable the transmit and receive elastic store minimum delay modes. When enabled,
the elastic stores are forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is
useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay
mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the
receive elastic store is in minimum delay mode; TSYNC must be configured as an output when transmit minimum
delay mode is enabled. In a typical application, RSYSCLK and TSYSCLK are locked to RCLKO, and RSYNC
(frame output mode) is connected to TSSYNC (frame input mode). All of the slip contention logic in the framer is
disabled (since slips cannot occur). On power-up, after the RSYSCLK and TSYSCLK signals have locked to their
respective network clock signals, the elastic store reset bits (TR.ESCR.2 and TR.ESCR.6) should be toggled from
a 0 to a 1 to ensure proper operation.
TR.ESCR.2
TR.ESCR.6
TR.ESCR.3
TR.ESCR.7
8 Clocks < Delay < 1 Frame
1 Frame < Delay < 2 Frames
½ Frame < Delay < 1 ½ Frames
½ Frame < Delay < 1 ½ Frames
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10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
The device can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled,
the data stream presented at TSERI already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4
checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify
the CRC-4 checksum. This modification, however, does not corrupt any error information the original CRC-4
checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode. The data at
TSERI must be aligned to the TSYNC signal. If TSYNC is an input, then the user must assert TSYNC aligned at
the beginning of the multiframe relative to TSERI. If TSYNC is an output, the user must multiframe-align the data
presented to TSERI.
Figure 10-4. CRC-4 Recalculate Method
TPOSO/TNEGO
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
TSER
+
CRC-4
CALCULATOR
XOR
MODIFY
Sa BIT
POSITIONS
NEW Sa BIT
DATA
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10.14 T1 Bit-Oriented Code (BOC) Controller
The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC
function is available only in T1 mode.
10.14.1 Transmit BOC
Bits 0 to 5 in the TR.TFDL register contain the BOC message to be transmitted. Setting TR.BOCC.0 = 1 causes
the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The
transmit BOC controller automatically provides the abort sequence. BOC messages are transmitted as long as
TR.BOCC.0 is set.
10.14.1.1 Transmit a BOC
1) Write 6-bit code into the TR.TFDL register.
2) Set the SBOC bit in TR.BOCC = 1.
10.14.2 Receive BOC
The receive BOC function is enabled by setting TR.BOCC.4 = 1. The TR.RFDL register now operates as the
receive BOC message and information register. The lower six bits of the TR.RFDL register (BOC message bits)
are preset to all 1s. When the BOC bits change state, the BOC change-of-state indicator, TR.SR8.0, alerts the
host. The host then reads the TR.RFDL register to get the BOC status and message. A change-of-state occurs
when either a new BOC code has been present for a time determined by the receive BOC filter bits RBF0 and
RBF1 in the TR.BOCC register, or a nonvalid code is being received.
10.14.2.1 Receive a BOC
1) Set integration time through TR.BOCC.1 and TR.BOCC.2.
2) Enable the receive BOC function (TR.BOCC.4 = 1).
3) Enable interrupt (TR.IMR8.0 = 1).
4) Wait for interrupt to occur.
5) Read the TR.RFDL register.
6) If TR.SR2.7 = 1, then a valid BOC message was received. The lower six bits of the TR.RFDL register
comprise the message.
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10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only)
When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The
first method involves using the internal TR.RAF/TR.RNAF and TR.TAF/TR.TNAF registers (Section
second method, which is covered in Section
10.15.2, involves an expanded version of the first method.
10.15.1 Method 1: Internal Register Scheme Based on Double-Frame
On the receive side, the TR.RAF and TR.RNAF registers always report the data as it received in the Sa and Si bit
locations. The TR.RAF and TR.RNAF registers are updated on align-frame boundaries. The setting of the receive
align frame bit in Status Register 4 (TR.SR4.0) indicates that the contents of the TR.RAF and TR.RNAF have been
updated. The host can use the TR.SR4.0 bit to know when to read the TR.RAF and TR.RNAF registers. The host
has 250μs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TR.TAF and TR.TNAF registers with the setting of the transmit align
frame bit in Status Register 4 (TR.SR4.3). The host can use the TR.SR4.3 bit to know when to update the TR.TAF
and TR.TNAF registers. It has 250μs to update the data or else the old data is retransmitted. If the TR.TAF and
TR.TNAF registers are only being used to source the align frame and nonalign frame-sync patterns, then
the host need only write once to these registers. Data in the Si bit position is overwritten if either the framer is
(1) programmed to source the Si bits from the TSERI pin, (2) in the CRC4 mode, or (3) has automatic E-bit
insertion enabled. Data in the Sa bit position is overwritten if any of the TR.E1TCR2.3 to TR.E1TCR2.7 bits are set
to 1.
10.15.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe
The receive side contains a set of eight registers (TR.RSiAF, TR.RSiNAF, TR.RRA, and TR.RSa4–TR.RSa8) that
report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4
multiframe bit in Status Register 2 (TR.SR4.1). The host can use the TR.SR4.1 bit to know when to read these
registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first received. See
the following register descriptions for more details.
The transmit side also contains a set of eight registers (TR.TSiAF, TR.TSiNAF, TR.TRA, and TR.TSa4–TR.TSa8)
that, through the transmit Sa bit control register (TR.TSACR), can be programmed to insert Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Status Register 2 (TR.SR4.4). The
host can use the TR.SR4.4 bit to know when to update these registers. It has 2ms to update the data or else the
old data is retransmitted. The MSB of each register is the first bit transmitted. See the register descriptions for
more details.
10.15.1). The
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10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver
This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use
with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte buffers in
the transmit and receive paths. When used with time slots, the user can select any time slot or multiple time slots,
contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the HDLC controllers.
The user must not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode, map both
controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and therefore the following operational
description refers only to a singular controller.
The HDLC controller performs the entire necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 128-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and FIFOs.
Table 10-12 lists these registers by group.
10.16.1 HDLC Configuration
The TR.HxTC and TR.HxRC registers perform the basic configuration of the HDLC controllers. Operating features
such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle flags are selected
here. These registers also reset the HDLC controllers.
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Table 10-12. HDLC Controller Registers
REGISTER FUNCTION
CONTROL AND CONFIGURATION
TR.H1TC, HDLC #1 Transmit Control Register
TR.H2TC, HDLC #2 Transmit Control Register
TR.H1RC, HDLC #1 Receive Control Register
TR.H2RC, HDLC #2 Receive Control Register
TR.H1FC, HDLC #1 FIFO Control Register
TR.H2FC, HDLC #2 FIFO Control Register
STATUS AND INFORMATION
TR.SR6, HDLC #1 Status Register
TR.SR7, HDLC #2 Status Register
TR.IMR6, HDLC #1 Interrupt Mask Register
TR.IMR7, HDLC #2 Interrupt Mask Register
TR.INFO4, HDLC #1 and #2 Information Register
TR.INFO5, HDLC #1 Information Register
TR.INFO6, HDLC #2 Information Register
TR.H1RPBA, HDLC #1 Receive Packet Bytes Available
TR.H2RPBA, HDLC #2 Receive Packet Bytes Available
TR.H1TFBA, HDLC #1 Transmit FIFO Buffer Available
TR.H2TFBA, HDLC #2 Transmit FIFO Buffer Available
MAPPING
TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4,
HDLC #1 Receive Channel Select Registers
TR.H2RCS1, TR.H2RCS2, TR.H2RCS3, TR.H2RCS4,
HDLC #2 Receive Channel Select Registers
TR.H1RTSBS, HDLC #1 Receive TS/Sa Bit Select
TR.H2RTSBS, HDLC #2 Receive TS/Sa Bit Select
TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4,
HDLC #1 Transmit Channel Select Registers
TR.H2TCS1, TR.H2TCS2, TR.H2TCS3, TR.H2TCS4,
HDLC #2 Transmit Channel Select Registers
TR.H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select
TR.H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select
FIFOs
TR.H1RF, HDLC #1 Receive FIFO Register
TR.H2RF, HDLC #1 Receive FIFO Register
TR.H1TF, HDLC #1 Transmit FIFO Register
TR.H2TF, HDLC #2 Transmit FIFO Register
General control over the transmit HDLC controllers
General control over the receive HDLC controllers
Sets high watermark for receiver and low
watermark for transmitter
Key status information for both transmit and
receive directions
Selects which bits in the status registers (SR7 and
SR8) cause interrupts
Information about HDLC controller
Indicates the number of bytes that can be read
from the receive FIFO
Indicates the number of bytes that can be written to
the transmit FIFO
Selects which channels are mapped to the receive
HDLC controller
Selects which bits in a channel are used or which
Sa bits are used by the receive HDLC controller
Selects which channels are mapped to the transmit
HDLC controller
Selects which bits in a channel are used or which
Sa bits are used by the transmit HDLC controller
Access to 128-byte receive FIFO
Access to 128-byte transmit FIFO
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10.16.2 FIFO Control
The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3,
4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register
TR.SR6 or TR.SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO’s read pointer is
below the watermark. If enabled, this condition can also cause an interrupt through the INT pin.
When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status register is
set. RHWM is a real-time bit and remains set as long as the receive FIFO’s write pointer is above the watermark. If
enabled, this condition can also cause an interrupt through the INT pin.
10.16.3 HDLC Mapping
The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data.
The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If mapped to channels, then
any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When
assigned to a channel(s), any combination of bits within the channel(s) can be avoided.
The TR.HxRCS1 – TR.HxRCS4 registers are used to assign the receive controllers to channels 1–24 (T1) or
1–32 (E1) according to the following table:
REGISTER CHANNELS
TR.HxRCS1 1–8
TR.HxRCS2 9–16
TR.HxRCS3 17–24
TR.HxRCS4 25–32
The TR.HxTCS1 – TR.HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or
1–32 (E1) according to the following table.
REGISTER CHANNELS
TR.HxTCS1 1–8
TR.HxTCS2 9–16
TR.HxTCS3 17–24
TR.HxTCS4 25–32
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10.16.4 FIFO Information
The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO.
The count form this register informs the host as to how many bytes can be written into the transmit FIFO without
overflowing the buffer.
10.16.5 Receive Packet-Bytes Available
The lower 7 bits of the receive packet-bytes available register indicates the number of bytes (0 through 127) that
can be read from the receive FIFO. The value indicated by this register (lower seven bits) informs the host as to
how many bytes can be read from the receive FIFO without going past the end of a message. This value refers to
one of four possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a
complete packet. After reading the number of bytes indicated by this register, the host then checks the HDLC
information register for detailed message status.
If the value in the TR.HxRPBA register refers to the beginning portion of a message or continuation of a message,
then the MSB of the TR.HxRPBA register returns a value of 1. This indicates that the host can safely read the
number of bytes returned by the lower seven bits of the TR.HxRPBA register, but there is no need to check the
information register since the packet has not yet terminated (successfully or otherwise).
10.16.5.1 Receive HDLC Code Example
The following is an example of a receive HDLC routine:
1) Reset receive HDLC controller.
2) Set HDLC mode, mapping, and high watermark.
3) Start new message buffer.
4) Enable RPE and RHWM interrupts.
5) Wait for interrupt.
6) Disable RPE and RHWM interrupts.
7) Read TR.HxRPBA register. N = TR.HxRPBA (lower 7 bits are byte count, MSB is status).
8) Read (N and 7Fh) bytes from receive FIFO and store in message buffer.
9) Read TR.INFO5 register.
10) If PS2, PS1, PS0 = 000, then go to Step 4.
11) If PS2, PS1, PS0 = 001, then packet terminated OK, save present message buffer.
12) If PS2, PS1, PS0 = 010, then packet terminated with CRC error.
13) If PS2, PS1, PS0 = 011, then packet aborted.
14) If PS2, PS1, PS0 = 100, then FIFO overflowed.
15) Go to Step 3.
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10.17 Legacy FDL Support (T1 Mode)
10.17.1 Overview
To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that
existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC
controllers and BOC controller described in Section
10.17.2 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the receive FDL register
(TR.RFDL). Because the TR.RFDL is 8 bits in length, it fills up every 2ms (8 x 250μs). The framer signals an
external microcontroller that the buffer has filled through the TR.SR8.3 bit. If enabled through TR.IMR8.3, the INT
pin toggles low, indicating that the buffer has filled and needs to be read. The user has 2ms to read this data
before it is lost. If the byte in the TR.RFDL matches either of the bytes programmed into the TR.RFDLM1 or
TR.RFDLM2 registers, then the TR.SR8.1 bit is set to a 1 and the INT pin toggles low if enabled through
TR.IMR8.1. This feature allows an external microcontroller to ignore the FDL or Fs pattern until an important event
occurs.
The framer also contains a zero destuffer, which is controlled through the TR.T1RCR2.3 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD protocol states that
no more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled through TR.T1RCR2.3, the device automatically looks for five
1s in a row, followed by a 0. If it finds such a pattern, it automatically removes the zero. If the zero destuffer sees
six or more 1s in a row followed by a 0, the 0 is not removed. The TR.T1RCR2.3 bit should always be set to a 1
when the device is extracting the FDL. Refer to Application Note 335: DS2141A, DS2151 Controlling the FDL for
information about using the device in FDL applications in this legacy support mode.
10.14 and 10.16 are used.
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10.17.3 Transmit Section
The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in
the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new value is written to TR.TFDL,
it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits have
been shifted out, the framer signals the host microcontroller by setting the TR.SR8.2 bit to a 1 that the buffer is
empty and that more data is needed. The INT also toggles low if enabled through TR.IMR8.2. The user has 2ms to
update TR.TFDL with a new value. If TR.TFDL is not updated, the old value in TR.TFDL is transmitted once again.
The framer also contains a zero stuffer that is controlled through the TR.T1TCR2.5 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of an LAPD protocol. The LAPD protocol states that no
more than five 1s should be transmitted in a row so that the data does not resemble an opening or closing flag
(01111110) or an abort signal (11111111). If enabled through TR.T1TCR2.5, the framer automatically looks for five
1s in a row. If it finds such a pattern, it automatically inserts a 0 after the five 1s. The TR.T1TCR2.5 bit should
always be set to a 1 when the framer is inserting the FDL.
10.18 D4/SLC-96 Operation
In the D4 framing mode, the framer uses the TR.TFDL register to insert the Fs framing pattern. To allow the device
to properly insert the Fs framing pattern, the TR.TFDL register at address C1h must be programmed to 1Ch and
the following bits must be programmed as shown:
TR.T1TCR1.2 = 0 (source Fs data from the TR.TFDL register)
TR.T1TCR2.6 = 1 (allow the TR.TFDL register to load on multiframe boundaries)
Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields through the
TR.TFDL and TR.RFDL registers. Refer to Application Note 345: DS2141A, DS2151, DS2152 SLC-96 for a
detailed description about implementing an SLC-96 function.
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10.19 Programmable In-Band Loop Code Generation and Detection
The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in
length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the
transmit code-definition registers (TR.TCD1 and TR.TCD2) and selects the proper length of the pattern by setting
the TC0 and TC1 bits in the in-band code control (TR.IBCC) register. When generating a 1-, 2-, 4-, 8-, or 16-bit
pattern, both transmit code-definition registers must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7bit pattern only requires TR.TCD1 to be filled. Once this is accomplished, the pattern is transmitted as long as the
TLOOP control bit (TR.T1CCR1.0) is enabled. Normally (unless the transmit formatter is programmed to not insert
the F-bit position) the framer overwrites the repeating pattern once every 193 bits to send the F-bit position.
For example, to transmit the standard “loop-up” code for CSUs, which is a repeating pattern of ...10000100001... ,
set TR.TCD1 = 80h, TR.IBCC = 0, and TR.T1CCR1.0 = 1.
The framer has three programmable pattern detectors. Typically two of the detectors are used for “loop-up” and
“loop-down” code detection. The user programs the codes to be detected in the receive up-code definition
(TR.RUPCD1 and TR.RUPCD2) registers and the receive down-code definition (TR.RDNCD1 and TR.RDNCD2)
registers, and the length of each pattern is selected through the TR.IBCC register. There is a third detector (spare)
that is defined and controlled through the TR.RSCD1/ TR.RSCD2 and TR.RSCC registers. When detecting a 16-bit
pattern, both receive code-definition registers are used together to form a 16-bit register. For 8-bit patterns, both
receive code-definition registers are filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern
only requires the first receive code-definition register to be filled. The framer detects repeating pattern codes in
both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors are capable of
handling both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the receive codedefinition register resets the integration period for that detector. The code detector has a nominal integration period
of 36ms. Hence, after about 36ms of receiving a valid code, the proper status bit (LUP at TR.SR3.5, LDN at
TR.SR3.6, and LSPARE at TR.SR3.7) is set to a 1. Normally codes are sent for a period of five seconds. It is
recommended that the software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the
code is continuously present.
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10.20 Line Interface Unit (LIU)
The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that
waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line
interface control registers (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1
mode-select bit and can operate independently of the framer function.
The transceiver can switch between T1 or E1 networks without changing external components on the transmit or
receive side.
transceiver can connect to T1, J1, or E1 (75Ω or 120Ω) without component changes. The receiver can adjust the
120Ω termination to 100Ω or 75Ω. The transmitter can adjust its output impedance to provide high return-loss
characteristics for 120Ω, 100Ω, and 75Ω lines. Other components can be added to this configuration to meet
safety and network protection requirements (Section
10.20.1 LIU Operation
The analog AMI/HDB3 waveform off the E1 line or the AMI/B8ZS waveform off of the T1 line is transformercoupled into the RTIP and RRING pins of the device. The user has the option to use internal termination, software
selectable for 75Ω/100Ω/120Ω applications, or external termination. The LIU recovers clock and data from the
analog signal and passes it through the jitter-attenuation mux outputting the received line clock at RDCLKO and
bipolar or NRZ data at RPOSO and RNEGO. The transceiver contains an active filter that reconstructs the analogreceived signal for the nonlinear losses that occur in transmission. The receive circuitry also is configurable for
various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB
for T1, which allow the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length.
Data input at TPOSI and TNEGI is sent through the jitter-attenuation mux to the waveshaping circuitry and line
driver. The transceiver drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The
line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.
Figure 10-7 shows a network connection using minimal components. In this configuration, the
10.24).
10.20.2 Receiver
The receiver contains a digital clock recovery system. The device couples to the receive E1 or T1 twisted pair (or
coaxial cable in 75Ω E1 applications) through a 1:1 transformer. See
device has the option of using software-selectable termination requiring only a single fixed pair of termination
resistors.
The transceiver’s LIU is designed to be fully software selectable for E1 and T1, requiring no change to any external
resistors for the receive side. The receive side allows the user to configure the transceiver for 75Ω, 100Ω, or 120Ω
receive termination by setting the RT1 (TR.LIC4.1) and RT0 (TR.LIC4.0) bits. When using the internal termination
feature, the resistors labeled R in
should be set to 0 and the resistors labeled R in
the line impedance.
There are two ranges of user-selectable receive sensitivity for T1 and E1. The EGL bit of TR.LIC1 (TR.LIC1.4)
selects the full or limited sensitivity. The resultant E1 or T1 clock derived from MCLK is multiplied by 16 through an
internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to
form a 16-times over-sampler that is used to recover the clock and data. This over-sampling technique offers
outstanding performance to meet jitter tolerance specifications shown in
Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the
case in most applications), the jitter attenuator restores the RCLKO to an approximate 50% duty cycle. If the jitter
attenuator is either placed in the transmit path or is disabled, the RCLKO output can exhibit slightly shorter high
cycles of the clock. This is because of the highly over-sampled digital-clock recovery circuitry. See the Receive AC
Timing Characteristics in Section
carrier loss (RCL) condition occurs and the RCLKO is derived from the JACLK source.
Figure 10-7 should be 60Ω each. If external termination is used, RT1 and RT0
Figure 10-7 should be 37.5Ω, 50Ω, or 60Ω each, depending on
13.9 for more details. When no signal is present at RTIP and RRING, a receive
Table 10-13 for transformer details. The
Figure 10-10.
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