MAXIM DS3065W User Manual
General Description
The DS3065W consists of a static RAM, a nonvolatile
(NV) controller, a year 2000-compliant real-time clock
(RTC), and an internal rechargeable manganese lithium
(ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint.
Whenever VCCis applied to the module, it recharges
the ML battery, powers the clock and SRAM from the
external power source, and allows the contents of the
clock registers or SRAM to be modified. When V
CC
is
powered down or out-of-tolerance, the controller writeprotects the memory contents and powers the clock
and SRAM from the battery. The DS3065W also contains a power-supply monitor output (RST), as well as a
user-programmable interrupt output (IRQ/FT).
Applications
RAID Systems and Servers Gaming
POS Terminals Fire Alarms
Industrial Controllers PLCs
Data-Acquisition Systems Routers/Switches
Features
♦ Single-Piece, Reflowable, 27mm x 27mm BGA
Package Footprint
♦ Internal Manganese Lithium Battery and Charger
♦ Integrated Real-Time Clock
♦ Unconditionally Write-Protects the Clock and
SRAM when VCCis Out-of-Tolerance
♦ Automatically Switches to Battery Supply when
VCCPower Failures Occur
♦ Reset Output can be Used as a CPU Supervisor
♦ Interrupt Output can be Used as a CPU Watchdog
Timer
♦ Industrial Temperature Range (-40°C to +85°C)
♦ UL Recognized
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
______________________________________________ Maxim Integrated Products 1
CE
DATA
ADDRESS
INT
RST
A0–19
DQ0–7
CE
20 BITS
8 BITS
MICROPROCESSOR
OR DSP
DS3065W
1024k x 8
NV SRAM
AND RTC
WR WE
RD OE
INT
IRQ/FT
CS CS
Typical Operating Circuit
Rev 2; 10/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
Pin Configuration appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE SPEED SUPPLY VOLTAGE
DS3065W-100#
-40°C to +85°C 256-ball 27mm x 27mm BGA Module 100ns 3.3V ±0.3V
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements.
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
(TA= -40°C to +85°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ...............................-40°C to +85°C
Soldering Temperature Range..........See IPC/JEDEC J-STD-020
PARAMETER
CONDITIONS
UNITS
Supply Voltage V
CC
3.0 3.3 3.6 V
Input Logic 1 V
IH
2.2
V
Input Logic 0 V
IL
0.0 0.4 V
PIN CAPACITANCE
(TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
Input Capacitance C
IN
Not production tested 15 pF
Input/Output Capacitance C
OUT
Not production tested 15 pF
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V ±0.3V, TA = -40°C to +85°C.)
PARAMETER
CONDITIONS
UNITS
Input Leakage Current I
IL
µA
I/O Leakage Current I
IO
CE = CS = V
CC
µA
Output-Current High I
OH
At 2.4V
mA
Output-Current Low I
OL
At 0.4V 2.0 mA
Output-Current Low RST
At 0.4V (Note 1) 8.0 mA
Output-Current Low IRQ/FT
At 0.4V (Note 1) 7.0 mA
I
CCS1
CE = CS = 2.2V 0.5 7
Standby Current
I
CCS2
CE = CS = V
CC
- 0.2V 0.2 5
mA
Operating Current I
CCO1tRC
= 200ns, outputs open 50 mA
Write Protection Voltage V
TP
2.8 2.9 3.0 V
SYMBOL
SYMBOL
MIN TYP MAX
V
CC
MIN TYP MAX
-1.0 +1.0
-1.0 +1.0
-1.0
IOL RST
IOL IRQ/FT
SYMBOL
MIN TYP MAX
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
_____________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V ±0.3V, TA = -40°C to +85°C.)
DS3065W-100
PARAMETER
CONDITIONS
MIN MAX
UNITS
Read Cycle Time
t
RC
100 ns
Access Time
t
ACC
100 ns
OE to Output Valid
t
OE
50 ns
RTC OE to Output Valid
t
OEC
60 ns
CE or CS to Output Valid
t
CO
100 ns
t
COE
(Note 2) 5 ns
Output High Impedance from
Deselection
t
OD
(Note 2) 40 ns
Output Hold from Address t
OH
5ns
Write Cycle Time
t
WC
100 ns
Write Pulse Width
t
WP
(Note 3) 75 ns
Address Setup Time
t
AW
0ns
t
WR1
(Note 4) 5
Write Recovery Time
t
WR2
(Note 5) 20
ns
Output High Impedance
from WE
t
ODW
(Note 2) 40 ns
Output Active from WE
t
OEW
(Note 2) 5 ns
Data Setup Time
t
DS
(Note 6) 40 ns
t
DH1
(Note 4) 0
Data Hold Time
t
DH2
(Note 5) 20
ns
Chip-to-Chip Setup Time
t
CCS
40 ns
POWER-DOWN/POWER-UP TIMING
(TA = -40°C to +85°C.)
PARAMETER
CONDITIONS
UNITS
VCC Fail Detect to CE, CS, and
WE Inactive
t
PD
(Note 7) 1.5 µs
VCC Slew from VTP to 0V
t
F
µs
VCC Slew from 0V to V
TP
t
R
µs
VCC Valid to CE, CS, and WE
Inactive
t
PU
2ms
VCC Valid to End of Write
Protection
t
REC
ms
VCC Fail Detect to RST Active
t
RPD
(Note 1) 3.0 µs
VCC Valid to RST Inactive
t
RPU
(Note 1) 40 350
ms
SYMBOL
OE or CE or CS to Output Active
SYMBOL
MIN TYP MAX
150
150
125
525
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
4 _____________________________________________________________________
Note 1: IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these
pins to realize a logic-high level.
Note 2: These parameters are sampled with a 5pF load and are not 100% tested.
Note 3: t
WP
is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. tWPis measured from
the latter of the two related edges going low to the earlier of the two related edges going high.
Note 4: t
WR1
and t
DH1
are measured from WE going high.
Note 5: t
WR2
and t
DH2
are measured from CE going high for SRAM writes or CS going high for RTC writes.
Note 6: t
DS
is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for
RTC writes.
Note 7: In a power-down condition, the voltage on any pin may not exceed the voltage on V
CC
.
Note 8: The expected t
DR
is defined as accumulative time in the absence of VCCstarting from the time power is first applied by the
user. Minimum expected data-retention time is based upon a maximum of two +230°C convection reflow exposures, followed by a fully charged cell. Full charge occurs with the initial application of V
CC
for a minimum of 96 hours. This parame-
ter is assured by component selection, process control, and design. It is not measured directly during production testing.
Note 9: WE is high for any read cycle.
Note 10: OE = V
IH
or VIL. If OE = VIHduring write cycle, the output buffers remain in a high-impedance state.
Note 11: If the CE or CS low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a
high-impedance state during this period.
Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a
high-impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output
buffers remain in a high-impedance state during this period.
DATA RETENTION
(TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
Expected Data-Retention Time
(Per Charge)
t
DR
(Notes 7, 8) 2 3
years
AC TEST CONDITIONS
Input Pulse Levels: VIL= 0.0V, VIH= 2.7V
Input Pulse Rise and Fall Times: 5ns
Input and Output Timing Reference Level: 1.5V
Output Load: 1 TTL Gate + C
L
(100pF) including scope and jig
SYMBOL
MIN TYP MAX
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
_____________________________________________________________________ 5
Read Cycle
OUTPUT
DATA VALID
t
RC
t
ACC
t
CO
t
OE
t
OEC
t
OH
t
OD
t
OD
t
COE
t
COE
V
IH
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IL
V
IH
ADDRESSES
CE
OR
CS
OE
D
OUT
(SEE NOTE 9.)
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
DS3065W
3.3V Single-Piece 8Mb Nonvolatile SRAM
with Clock
6 _____________________________________________________________________
Write Cycle 1
DATA IN STABLE
ADDRESSES
WE
D
OUT
D
IN
t
WC
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
HIGH
IMPEDANCE
V
IH
V
IH
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
t
AW
t
WP
t
OEW
t
DH1
t
DS
t
ODW
t
WR1
(SEE NOTES 2, 3, 4, 6, 10–13.)
CE
OR
CS
Write Cycle 2
t
WC
t
AW
t
DH2
t
DS
t
COE
t
ODW
t
WP
t
WR2
V
IH
V
IL
V
IH
ADDRESSES
WE
D
OUT
D
IN
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
DATA IN STABLE
V
IL
V
IH
V
IL
(SEE NOTES 2, 3, 5, 6, 10–13.)
CE
OR
CS
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