MAXIM DS28E04-100 Technical data
PX.Y
µC
R
PUP
V
CC
IO V
CC
POL
P1
P0
GND
A0
A6
DS28E04 #1
IO V
CC
POL
P1
P0
GND
A0
A6
DS28E04 #7
RST1 RST 0
LED
PART
TEMP RANGE
PIN-PACKAGE
DS28E04S-100+
-40°C to +85°C
16 SO
16 SO
(2.5k pieces)
Commands, Registers, and Modes are capitalized for
DS28E04-100
Wire EEPROM with PIO
19-6134; Rev 12/11
4096-Bit Addressable 1-
GENERAL DESCRIPTION
The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM
chip with seven address inputs. The address inputs
are directly mapped into the 1-Wire 64-bit Device ID
Number to easily enable the host system to identify
the physical location or functional association of the
DS28E04-100 in a multidevice 1-Wire network environment. The 4096-bit EEPROM array is configured
as 16 pages of 32 bytes with a 32 byte scratchpad to
perform write operations. EEPROM memory pages
can be individually write protected or put in EPROMemulation mode, where bits can only be changed
from a 1 to a 0 state. In addition to the memory, the
DS28E04-100 has two general-purpose I/O ports that
can be used for input or to generate level and/or
pulse outputs. Activity registers also capture port
activity for state change monitoring. The DS28E04100 communicates over the single-contact 1-Wire
bus. The communication follows the standard Maxim
1-Wire protocol.
APPLICATIONS
Autoconfiguration of Modular Systems such as
Central-Office Switches, Cellular Base Stations,
Access Products, Optical Network Units, and
PBXs
Accessory/PCB Identification
TYPICAL OPERATING CIRCUIT
FEATURES
• 4096 bits of EEPROM Memory Partitioned into
16 Pages of 256 Bits
• Seven Address Inputs for Physical Location
Configuration
• Two General-Purpose PIO Pins with Pulse-
Generation Capability
Individual Memory Pages can be Permanently
Write-Protected or put in OTP EPROMEmulation Mode (“Write to 0”)
Communicates to Host with a Single Digital
Signal at 15.3kbps or 111kbps Using 1-Wire
Protocol
Parasitic or V
Powered
CC
Conditional Search Based on PIO Status or PIO
Activity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40°C to +85°C
16-Pin, 150-mil SO Package
ORDERING INFORMATION
DS28E04S-100+T -40°C to +85°C
+ Indicates lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PIN CONFIGURATION
1 of 37
SO (150 mils)
clarity.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
All Pins: Voltage to GND
-0.5V, +6V
All Pins: Sink Current
20mA
Operating Temperature Range
-40°C to +85°C
Junction Temperature
+150°C
Storage Temperature Range
-55°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Soldering Temperature (reflow)
+260°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Ground Current
I
GND
(Notes 1, 2, 3)
20
mA
Supply Current
I
CC
VCC = V
(Note 3)
1
mA
Standby Supply Current
I
CCS
Device idle; A0 to A6 not connected
11
µA
PINS A0 TO A6
Input Low Voltage
V
ILA
(Note 1)
0.30
V
VX -
0.3V
Input Load Current
I
LA
Pin at GND (Note 4)
-1.1
µA
POL PIN
Input Low Voltage
V
ILPOL
(Note 1)
0.30
V
VX -
0.3V
Leakage Current
I
LKPOL
Pin at 5.25V
1
µA
PIO PINS
Input Low Voltage
V
ILP
(Note 1)
0.30
V
VX -
0.3V
Output Low Voltage at
4mA
Leakage Current
I
LKP
Pin at 5.25V
1
µA
Minimum Sensed PIO
Pulse
Output Pulse Duration
t
PULSE
(Note 7)
250 1000
ms
IO PIN GENERAL DATA
1-Wire Pullup Resistance
R
PUP
(Notes 1, 8)
0.3 2.2
kΩ
Input Capacitance
CIO
(Notes 3, 9)
100
800
pF
IO pin at V
, A0 to A6 not connected,
V
CC
at GND
IO pin at V
, A0 to A6 not connected,
V
CC
at V
PUP
High-to-Low Switching
Threshold
Input Low Voltage
V
IL
(Notes 1, 12)
0.3
V
VX -
0.3V
Low-to-High Switching
Threshold
Switching Hysteresis
V
HY
(Notes 3, 10, 14)
0.21
1.70
V
Output Low Voltage
V
OL
At 4mA Current Load (Note 5)
0.4
V
Standard speed, R
PUP
= 2.2kΩ
5
Overdrive speed, R
PUP
= 2.2kΩ
2
Overdrive speed, directly prior to reset
pulse; R
PUP
= 2.2kΩ
Rising-Edge Hold-Off Time
(Note 3)
Standard speed (Note 16)
0.5 5.0
Overdrive speed
Not applicable (0)
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute max imum rating conditions for extended periods may affect dev ice reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.8V to 5.25V, VCC = V
PUP
, not connected or grounded, TA = -40°C to +85°C.)
PUP
PUP
Input High Voltage V
Input High Voltage V
Input High Voltage V
V
t
PWM IN
Input Load Current I
IHA
IHPOL
IHP
OLP
VX = max(V
VX = max(V
VX = max(V
(Note 5) 0.4 V
, VCC) (Note 1)
PUP
, VCC) (Note 1)
PUP
, VCC) (Note 1)
PUP
V
V
V
(Note 6) 1 10 µs
PUP
L
V
TL
(Notes 3, 10, 11) 0.46 4.40 V
PUP
0.05 11.00
0.05 8.25
µA
Input High Voltage V
Recovery Time
(Notes 1, 15)
2 of 37
V
TH
t
REC
t
REH
IH
VX = max(V
, VCC) (Note 1)
PUP
V
(Notes 3, 10, 13) 1.0 4.9 V
µs
5
µs
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Time Slot Duration
(Note 1)
Standard speed
65
Overdrive speed
9
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed, V
PUP
> 4.5V
480 640
Standard speed (Note 17)
504 640
Overdrive speed, V
PUP
> 4.5V
48 80
Overdrive speed (Note 17)
53 80
Presence-Detect High
Time
Standard speed
15 60
Overdrive speed (Note 17)
2 7
Standard speed, V
PUP
> 4.5V
1.10
3.75
Standard speed
1.1 7.0
Overdrive speed
0 1.1
Standard speed
60 240
Overdrive speed, V
PUP
> 4.5V
8 24
Overdrive speed (Note 17)
8 26
Standard speed, V
PUP
> 4.5V
64 75
Standard speed
67 75
Overdrive speed
8.1 10
IO PIN, 1-Wire WRITE
Write-0 Low Time
(Notes 1, 19)
Standard speed
60 120
Overdrive speed (Note 17)
7 16
Write-1 Low Time
(Notes 1, 19)
Standard speed
5 15
Overdrive speed
1 2
IO PIN, 1-Wire READ
Read Low Time
(Notes 1, 20)
Standard speed
5
15 - δ
Overdrive speed
1
2 - δ
Read Sample Time
(Notes 1, 20)
Standard speed
tRL + δ 15
Overdrive speed
tRL + δ 2
EEPROM
Programming Current
I
PROG
(Note 21) 1 mA
Programming Time
t
PROG
(Note 22)
10
ms
Write/Erase Cycles
(Endurance) (Note 23)
At +25°C
200k
At +85°C (worst case)
50k
Data Retention
(Notes 23, 24)
Note 1:
System requir ement.
Note 2:
Maximum instantaneous pulldown current through all pins combined.
Note 3:
Guaranteed by design, simulation only. Not production tested.
Note 4:
This load current is caused by the internal weak pullup, which ass erts a logical 1 to address pins that are not connected. The
which these bits are relevant.
Note 5:
The I-V characteristic is linear for voltages less than 1V.
Note 6:
Width of the narrowest puls e that trips the activity latch. Back t o back pulses that are active for < t
(max) and that have an
intermediate inactive time < t
PWMIN
(max) are not guaranteed to be filtered.
Note 7:
The Puls e function requires that VCC power is available; otherwise the command will not be executed.
Note 8:
Maximum allowable pullup resistance is a function of the number of 1 -Wire devices in the system and 1-Wire recovery times. The
loaded s ystems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 9:
Capacitance on the data pin could be 800pF when V
is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs
after V
PUP
has been applied the parasite capacitance will not aff ect normal communications.
Note 10:
VTL, VTH, and V
are a function of the internal supply voltage, which in parasit e power mode, is a function of V
and the 1-W ire
recovery times. The VTH and VTL maximum specifications are valid at VCC = V
PUP
= 5.25V. In any case, VTL < VTH < V
PUP
.
Note 11:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 12:
The voltage on IO needs to be less than or equal to V
ILM AX
whenever the master drives the line low.
Note 13:
Voltage above whic h, during a rising edge on IO, a logic 1 is detected.
Note 14:
After VTH is crossed dur ing a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.
Note 15:
Applies to a single DS28E04-100 without VCC supply, attached to a 1-Wire line.
Note 16:
The earliest recognition of a negative edge is possible at t
REH
after VTH has been previously reached.
Note 17:
Highlighted numbers are NOT in complianc e with legacy 1-W ire product standards. See comparison table.
Note 18:
Interval during the negative edge on IO at the beginning of a Presence Detect puls e between the time at which the voltage is
80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
Reset Low Time (Note 1) t
Presence-Detect Fall Time
(Notes 3, 18)
Presence-Detect Low
Time
Presence-Detect Sample
Time (Note 1)
t
SLOT
RSTL
t
PDH
t
FPD
t
PDL
t
MSP
t
W0L
t
W1L
t
RL
t
MSR
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
N
CY
tDR At +85°C (worst case) 40 years
logical state of the address pins must not change during the execution of ROM function commands during those time slots in
PWMIN
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
PUP
HY
PUP
3 of 37
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Note 19:
ε in Figur e 16 represents the time requir ed for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum
duration for the master to pull the line low is t
W1LMAX
+ tF - ε and t
W0LMAX
+ tF - ε respectively.
Note 20:
δ in Figure 16 represents the time requir ed for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold
of the bus master. T he actu al maximum duration for the master to pull the line low is t
RLM AX
+ tF.
Note 21:
Current drawn during the EEPROM programming interval. If the device does not get VCC power, the pullup circuit on IO during the
Vpup(min) then a low-impedance bypass of R
PUP
that can be activated during programming may need to be added.
Note 22:
The t
interval begins t
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid C opy Scratchpad
device has returned from I
PROG
to IL or I
CCS
, r espectively.
Note 23:
Not production tested. Guaranteed by design or characterization.
Note 24:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at elevated temperatures
is not recommended; the device c an lose its write capability after 10 years at +125°C or 40 years at +85°C.
LEGACY VALUES
DS28E04-100 VALUES
PARAMETER
STANDARD SPEED
OVERDRIVE SPEED
STANDARD SPEED
OVERDRIVE SPEED
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
SLOT
(incl. t
REC)
61µs
(undef)
7µs
(undef)
65µs1)
(undef)
9µs
(undef)
t
RSTL
480µs
(undef)
48µs
80µs
504µs
640µs
53µs
80µs
t
PDH
15µs
60µs
2µs
6µs
15µs
60µs
2µs
7µs
t
PDL
60µs
240µs
8µs
24µs
60µs
240µs
8µs
26µs
t
W0L
60µs
120µs
6µs
16µs
60µs
120µs
7µs
16µs
PIN
NAME
FUNCTION
1
A3
Address bit input (place value = 8), with weak pullup.
2
A2
Address bit input (place value = 4), with weak pullup.
3
A1
Address bit input (place value = 2), with weak pullup.
4
A0
Least significant address bit input (place value = 1), with weak pullup.
5, 12
GND
Ground Reference
6, 11
N.C.
Not Connected
7
VCC
Optional power supply for the chip; leave unconnected or ground if VCC power
is not available.
8
POL
Power-up polarity (logical state) for P0 and P1; pin has a weak pulldown.
9
P0
Remote-controlled I/O pin, open drain with weak pulldown.
10
P1
Remote-controlled I/O pin, open drain with weak pulldown.
13
A6
Address bit input (place value = 64), with weak pullup.
14
A5
Address bit input (place value = 32), with weak pullup.
15
A4
Address bit input (place value = 16), with weak pullup.
16
IO
1-Wire Bus Interface. Open drain, requires external pullup resistor.
programming interval should be such that the voltage at IO is greater than or equal to V
PROG
sequence. Interval ends onc e the device's self-timed EEPRO M programming cycle is c omplete and the current drawn by the
REHmax
1)
Intentional change, longer recovery time requirement due t o modified 1-W ire front end.
PIN DESCRIPTION
(min). If V
PUP
in the system is close to
PUP
DETAILED DESCRIPTION
The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven
external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as opendrain and provide an on-resistance of 100Ω max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the
scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the
scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory
location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this
number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number
guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The
DS28E04-100 has an optional V
parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of
the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of
modular systems such as central-office switches, cellular base stations, access products, optical network units, and
PBXs, and accessory/PC board identification.
supply connection. When an external supply is absent, device power is supplied
CC
4 of 37
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
1-Wire Network
Device ID
Number Register
1-Wire
Function Control
Memory
Function
Control Unit
Special Function
Registers
32-
Byte
Scratchpad
Data Memory
16 Pages of
32 Bytes Each
CRC16
Generator
A0
A6
IO
Internal VDD
PIO
Control Registers
P0
VCC
P1
POL
Internal VDD
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte
scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the eight
ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip
ROM, 6) Resume, 7) Overdrive-Skip ROM or 8) Overdrive-Match ROM. Upon completion of an Overdrive ROM
command byte executed at standard speed, the device enters Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is described in
Figure 14. After a ROM function command is successfully executed, the memory/control functions become
accessible and the master may provide any one of the nine Memory/Control Function commands. The protocol for
these commands is described in Figure 9. All data is read and written least significant bit first.
Figure 1. Block Diagram
5 of 37
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
DS28E04-100
Available
Commands:
Command
Level:
Data Field
Affected:
1-Wire ROM Function
Commands (see Figure 14)
DS28E04
-Specific
Memory/Control Function
Commands (see Figure 9)
Read ROM
Match ROM
Search ROM
Conditional Search
ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Device ID, RC-Flag
Device ID, RC
-Flag
Device ID, RC-Flag
Device ID, RC-Flag, PIO Status,
cond. Search Settings
RC-Flag
RC-Flag
RC-Flag, OD-Flag
Device ID, RC-Flag, OD-Flag
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
PIO Access Read
PIO Access Write
PIO Access Pulse
Reset Act. Latch
Write Register
32-byte Scratchpad, Flags
32-byte Scratchpad
Data Memory, Register Page
Data Memory, Registers
PIO Pins
PIO Pins, Activity Latch
PIO Pins, Activity Latch
Activity Latch
Conditional Search and Control
Registers
MSB
LSB
8-Bit External
A6 A5 A4 A3 A2 A1 A
0
MSB LSB
MSB LSB
MSB LSB
MSB LSB
Figure 2. Hierarchical Structure for 1-Wire Protocol
64-BIT DEVICE ID NUMBER (NETWORK ADDRESS)
Each DS28E04-100 has a unique device ID number that is 64 bits long, as shown in Figure 3. The first 8 bits are a
1-Wire family code. The next 8 bits are an external address byte, of which the lower 7 bits are connected to the
address input pins A0 to A6. This allows the user to set a portion of the Device ID Number by connecting some of
these pins to GND (logic 0) or to V
number. Even if multiple DS28E04-100 are used in a 1-Wire network and all address inputs are wired to the same
state or left open (unconnected), the unique 40-bit serialization field will prevent any address conflict, allowing to
communicate with each device individually. The last 8 bits are a lasered CRC (Cyclic Redundancy Check) of the
first 56 bits, assuming that the address input pins A0 to A6 are at logic 1. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X
4
X
+ 1. Further information on the Device ID CRC is found in section CRC Generation near the end of this
document.
Figure 3. 64-Bit Device ID Number
8-Bit CRC
Code
40-Bit Lasered Serial Number
(logic 1) or leaving them open (logic 1). The next 40 bits are a lasered serial
CC
8
+ X5 +
Address Input
0
8-Bit Family Code
(1Ch)
6 of 37
Figure 4. 1-Wire CRC Generator
X0X
1
X
2
X
3X4
X
5
X
6
X
7
X
8
Polynomial = X8 + X5 + X
4
+ 1
1
st
STAGE
2
nd
STAGE
3
rd
STAGE
4
th
STAGE
6
th
STAGE
5
th
STAGE
7
th
STAGE
8
th
STAGE
INPUT DATA
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
MEMORY
The DS28E04-100 EEPROM array consists of 17 pages of 32 bytes each, starting at address 0000h and ending at
address 021Fh. All memory addresses in this range have unrestricted read access. The data memory consists of
16 pages of 32 bytes each. The register page consists of 32 bytes starting at address 0200h. It contains 16 page
protection control bytes (one for each data memory page), the register page lock byte, the factory bytes, and the
reserved bytes. The reserved bytes are for future use by the factory and should be not be used. They have no
effect on device operation.
The protection control registers, along with the register page lock byte, determine whether write protection, EPROM
mode, or copy protection is enabled for each of the 16 data memory pages. A value of 55h sets write protection for
the associated memory page. A value of AAh sets EPROM mode. A value of 55h or AAh for the register page lock
byte sets copy protection for all write-protected data memory pages, as well as the register page. EPROM mode
pages are not affected. The protection control registers and the register page lock byte write protect themselves if
set to 55h or AAh. Any other setting leaves them open for unrestricted write access.
In addition to the EEPROM, the device has a 32-byte volatile scratchpad. Writes to the EEPROM array are a twostep process. First, data is written to the scratchpad through the Write Scratchpad command, and then copied into
the main array through the Copy Scratchpad command. The user can verify the data written to the scratchpad
through the Read Scratchpad command prior to copying into the main array.
If a memory location is write protected, data sent by the master to the associated address during a Write
Scratchpad command is not loaded into the scratchpad. Instead, it is replaced by the data in EEPROM located at
the target address. If a memory location is in EPROM mode, the scratchpad is loaded with the logical AND of the
data sent by the master and the data in EEPROM at the target address. Copy Scratchpad commands to writeprotected or EPROM mode memory locations are allowed. This allows write-protected data in the device to be
refreshed, i.e., reprogrammed with the current data.
If a memory location is copy protected, a Copy Scratchpad command to that location will be blocked, which is
indicated by FFh success bytes. Copy protection is used for a higher level of security, and should only be used
after all write-protected pages and their associated protection control bytes are set to their final values. Copy
protection as implemented with this device does not prevent copying data from one device to another; it only blocks
the execution of the copy scratchpad command with a target address of a copy-protected memory page.
7 of 37
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Selection Mask
Figure 5. Memory Map
Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile.
ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES (NOTES)
0000h to 001Fh R/(W) Data Memory Page 0 (Protection controlled by address 0200h)
0020h to 003Fh R/(W) Data Memory Page 1 (Protection controlled by address 0201h)
0040h to 005Fh R/(W) Data Memory Page 2 (Protection controlled by address 0202h)
0060h to 007Fh R/(W) Data Memory Page 3 (Protection controlled by address 0203h)
0080h to 009Fh R/(W) Data Memory Page 4 (Protection controlled by address 0204h)
00A0h to 00BFh R/(W) Data Memory Page 5 (Protection controlled by address 0205h)
00C0h to 0DFh R/(W) Data Memory Page 6 (Protection controlled by address 0206h)
00E0h to 00FFh R/(W) Data Memory Page 7 (Protection controlled by address 0207h)
0100h to 011Fh R/(W) Data Memory Page 8 (Protection controlled by address 0208h)
0120h to 013Fh R/(W) Data Memory Page 9 (Protection controlled by address 0209h)
0140h to 015Fh R/(W) Data Memory Page 10 (Protection controlled by address 020Ah)
0160h to 017Fh R/(W) Data Memory Page 11 (Protection controlled by address 020Bh)
0180h to 019Fh R/(W) Data Memory Page 12 (Protection controlled by address 020Ch)
01A0h to 01BFh R/(W) Data Memory Page 13 (Protection controlled by address 020Dh)
01C0h to 01DFh R/(W) Data Memory Page 14 (Protection controlled by address 020Eh)
01E0h to 01FFh R/(W) Data Memory Page 15 (Protection controlled by address 020Fh)
0200h1) to 020Fh1) R/(W)
Protection Control Pages 0
to 15
0210h1) R/(W) Register Page Lock (See text)
0211h R Factory Byte (Reads 55h or AAh)
0212h to 021Dh N/A Reserved
021Eh to 021Fh R Factory Bytes (Undefined value)
55h: Write Protected; AAh: EPROM mode.
Address 0200h is associated with memory
page 0, address 0201h with page 1, etc.
220h R PIO Logic State (The lower two bits are valid)
221h R PIO Output Latch State (The lower two bits are valid)
222h R PIO Activity Latch State (The lower two bits are valid)
223h R/W2) Conditional Search PIO
224h R/W2) Conditional Search Polarity
225h R/W2) Conditional Search Control
1)
Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither
write-protect the address nor activate any function.
2)
Limited write access through Write Register command
Selection
and Status Register
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PIO Output
Latch
PIO Activity
Latch
Edge
Detector
Port
Function
Control
To Activity Latch
State Register
To PIO Logic
State Register
To PIO Output
Latch State Reg.
R
Q D D
Q
Q
Q
"1"
CLR ACT LATCH
P0, P1
DATA
CLOCK
POWER ON
RESET
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0220h
1 1 1 1 1 1 P1
P0
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0221h
1 1 1 1 1 1 PL1
PL0
PIO-RELATED REGISTERS
Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in
the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when the device is
powered down. All PIO-related registers can be read like any data memory. There are special commands to control
the PIOs for input (read), output (write), pulse-generation, and to reset the activity latches.
Figure 6. PIO Simplified Logic Diagram
PIO Logic State Register
The logic state of the PIO pins can be obtained by reading this register using the Read Memory command. This
register is read-only. Each bit is associated with the pin of the respective PIO channel. Bits 2 to 7 have no function;
they always read 1. The data in this register reflects the PIO state at the last (most significant) bit of the byte that
proceeds reading the first (least significant) bit of this register. See the PIO Access Read command description for
details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIOs through the PIO Access Write command.
This register is read using the Read Memory command. This register is not affected if the device re-initializes itself
after an ESD hit. This register is read-only. Each bit is associated with the output latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 1. The flip-flops of this register power up as specified by the
state of the POL pin. If the chip has to power up with all PIO channels off, the POL pin must be connected to a logic
"1".
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0222h
0 0 0 0 0 0 AL1
AL0
AL1
P1
PLS
SP0
SM0
CT
SM1
SP1
AL0
P0
CSR
Channel 0
Channel 1
PORL
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0223h
0 0 0 0 0 0 SM1
SM0
PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using the Read
Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 0. A state transition on a PIO pin, HighLow or
LowHigh, of a duration greater than t
causes the associated bit in the register to be set to a 1. This register
PW MI N
is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command.
The next three registers control the device's participation a Conditional Search ROM sequence. The interaction of
the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7.
There is a selection mask, SM, to select the participating PIOs, a polarity selection SP to specify for each channel
whether the channel signal needs to be 1 or 0 to qualify, and a PLS bit to select either the activity latches or PIO
pins as inputs. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally
selects the ANDed or ORed result as the conditional search response signal CSR. If CT is 0, the channel signal of
at least one of the selected channels must match the corresponding polarity. If CT is 1, the channel signals of all
selected channels must match the corresponding polarity.
Figure 7. CONDITIONAL SEARCH LOGIC
Conditional Search Channel Selection Mask Register
The data in this register controls whether a PIO channel qualifies for participation in the conditional search
command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1.
This register can only be written through the Write Register command. This register is read/write. Each bit is
associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0
and cannot be changed to 1. This register is cleared to 00h by a power-on reset.
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0224h
0 0 0 0 0 0 SP1
SP0
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0225h
VCCP
POL 0 0
PORL
0
CT
PLS
BIT DESCRIPTION
BIT(S)
DEFINITION
1: activity latch selected
Specifies whether the data of two channels needs to be ORed or
1: bitwise AND
Search ROM sequence.
Reports the state of the POL pin. The state of the POL pin specifies
1: PIO powers up 1
1: VCC-powered operation
Conditional Search Channel Polarity Selection Register
The data in this register specifies the polarity of each selected PIO channel for the device to respond to the
conditional search command. This register can only be written through the W rite Registers command. Within a PIO
channel, the data source may be either the channel's input pin or the channel's activity latch, as specified by the
PLS bit in the Control/Status register at address 0225h. This register is read/write. Each bit is associated with the
respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0 and cannot be
changed to 1. This register is cleared to 00h at power-up.
Control/Status Register
The data in this register reports status information and further configures the device for conditional search. This
register can only be written through the Write Registers command. This register is read/write. The power-up state
of the PORL bit is "1". CT and PLS power up as "0". The functional assignments of the individual bits are explained
in the table below. Bits 2, 4, and 5 have no function; they always read 0 and cannot be set to 1.
Control/Status Register Details
PLS: Pin or Activity
Latch Select
CT: Conditional Search
Logical Term
PORL: Power-On Reset
Latch
POL: PIO Default
Polarity (Read-Only)
VCCP: VCC Power
Status (Read-Only)
b0
b1
b3
b6
b7
Selects either the PIO pins or the PIO activity latches as input for the
conditional search.
0: pin selected (default)
AND’ed to meet the qualifying condition for the device to respond to
a conditional search. If only a single channel is selected in the
channel selection mask (0223h) this bit is a don't care.
0: bitwise OR (default)
Specifies whether the device has performed a power-on reset. This
bit can only be cleared to 0 by writing to the Control/Status Register.
As long as this bit is 1 the device will always respond to a Conditional
whether the PIO pins P0 and P1 power up high or low. The polarity
of a pulse generated at a PIO pin is the opposite of the pin's powerup state.
0: PIO powers up 0
For VCC-powered operation, the VCC pin needs to be connected to a
voltage source equal to V
0: V
power not available
CC
PUP
.
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Ending Address with
(Read Only)
ADDRESS REGISTERS AND TRANSFER STATUS
The DS28E04-100 employs three address registers, called TA1, TA2, and E/S (Figure 8). Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data is read. Register E/S is
a read-only transfer-status register, used to verify data integrity of write commands. The lower five bits of the E/S
register indicate the Ending Offset within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the
number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due
to a loss of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. Note
that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate
storage of data will begin. This address is called byte offset. If the target address (TA1) for a Write command is
03CH for example, then the scratchpad stores incoming data beginning at the byte offset 1CH and is full after only
four bytes. The corresponding ending offset in this example is 1FH. For maximum data bandwidth, the target
address for writing should point to the beginning of a new page, i.e., the byte offset is 0. Thus the full 32-byte
capacity of the scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write
one or several contiguous bytes somewhere within a page. The ending offset together with the partial flag support
the master checking the data integrity after a Write command. The highest valued bit of the E/S register, called AA
is valid only if the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. Writing data to the scratchpad
clears the AA flag.
Figure 8. Address Registers
Bit # 7 6 5 4 3 2 1 0
Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0
Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8
Data Status (E/S)
AA 0 PF E4 E3 E2 E1 E0
WRITING WITH VERIFICATION
To write data to the DS28E04-100 EEPROM sections, the scratchpad has to be used as intermediate storage. First
the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be
written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address (actual address sent), and data (as sent by the master) at the end of the
Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has
calculated to decide whether the communication was successful and proceed to the Copy Scratchpad command. If
the master could not receive the CRC16, it should use the Read Scratchpad command to verify data integrity. As a
preamble to the scratchpad data, the DS28E04-100 repeats the target address TA1 and TA2 and sends the
contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss
of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a
new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the
device did not recognize the Write command. If everything went correctly, both flags are cleared and the ending
offset indicates the address of the last byte written to the scratchpad. Now the master can continue reading and
verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master
should obtain the contents of these registers by reading the scratchpad.
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