MAXIM DS26524 User Manual
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www.maxim-ic.com
DS26524
Quad T1/E1/J1 Transceive
GENERAL DESCRIPTION
The DS26524 is a single-chip 4-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
TYPICAL OPERATING CIRCUIT
T1/E1/J1
NETWORK
DS26524
T1/J1/E1
Transceiver
x4
BACKPLANE
TDM
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS26524G
DS26524G+
DS26524GN
DS26524GN+
+ Denotes lead-free/RoHS compliant device.
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
FEATURES
Four Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section 2
.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9
1.1 MAJOR OPERATING MODES .............................................................................................................9
2. FEATURE HIGHLIGHTS ..................................................................................................10
2.1 GENERAL ......................................................................................................................................10
2.2 LINE INTERFACE ............................................................................................................................ 10
2.3 CLOCK SYNTHESIZER ....................................................................................................................10
2.4 JITTER ATTENUATOR .....................................................................................................................10
2.5 FRAMER/FORMATTER .................................................................................................................... 10
2.6 SYSTEM INTERFACE ......................................................................................................................11
2.7 HDLC CONTROLLERS ...................................................................................................................12
2.8 TEST AND DIAGNOSTICS ................................................................................................................ 12
2.9 CONTROL PORT ............................................................................................................................12
3. APPLICATIONS ...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE ...................................................................................14
5. ACRONYMS AND GLOSSARY .......................................................................................16
6. BLOCK DIAGRAMS.........................................................................................................17
7. PIN DESCRIPTIONS ........................................................................................................19
7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19
8. FUNCTIONAL DESCRIPTION .........................................................................................26
8.1 PROCESSOR INTERFACE................................................................................................................ 26
8.2 CLOCK STRUCTURE....................................................................................................................... 26
8.2.1 Backplane Clock Generation ............................................................................................................... 26
8.3 RESETS AND POWER-DOWN MODES..............................................................................................28
8.4 INITIALIZATION AND CONFIGURATION..............................................................................................29
8.4.1 Example Device Initialization Sequence.............................................................................................. 29
8.5 GLOBAL RESOURCES ....................................................................................................................29
8.6 PER-PORT RESOURCES ................................................................................................................29
8.7 DEVICE INTERRUPTS .....................................................................................................................29
8.8 SYSTEM BACKPLANE INTERFACE ................................................................................................... 31
8.8.1 Elastic Stores ....................................................................................................................................... 31
8.8.2 IBO Multiplexer..................................................................................................................................... 34
8.8.3 H.100 (CT Bus) Compatibility .............................................................................................................. 40
8.8.4 Receive and Transmit Channel Blocking Registers............................................................................. 41
8.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
8.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
8.9 FRAMERS......................................................................................................................................42
8.9.1 T1 Framing........................................................................................................................................... 42
8.9.2 E1 Framing........................................................................................................................................... 45
8.9.3 T1 Transmit Synchronizer .................................................................................................................... 47
8.9.4 Signaling .............................................................................................................................................. 48
8.9.5 T1 Data Link......................................................................................................................................... 52
8.9.6 E1 Data Link......................................................................................................................................... 54
8.9.7 Maintenance and Alarms ..................................................................................................................... 55
8.9.8 E1 Automatic Alarm Generation .......................................................................................................... 58
8.9.9 Error-Count Registers .......................................................................................................................... 59
8.9.10 DS0 Monitoring Function...................................................................................................................... 61
8.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 62
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8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 62
8.9.13 Per-Channel Loopback ........................................................................................................................ 62
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 62
8.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 63
8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................ 64
8.9.17 Framer Payload Loopbacks ................................................................................................................. 65
8.10 HDLC CONTROLLERS ................................................................................................................ 66
8.10.1 Receive HDLC Controller..................................................................................................................... 66
8.10.2 Transmit HDLC Controller.................................................................................................................... 69
8.11 LINE INTERFACE UNITS (LIUS) ....................................................................................................71
8.11.1 LIU Operation....................................................................................................................................... 74
8.11.2 Transmitter ........................................................................................................................................... 75
8.11.3 Receiver ............................................................................................................................................... 78
8.11.4 Jitter Attenuator.................................................................................................................................... 81
8.11.5 LIU Loopbacks ..................................................................................................................................... 82
8.12 BIT-ERROR-RATE TEST (BERT) FUNCTION ................................................................................84
8.12.1 BERT Repetitive Pattern Set ............................................................................................................... 85
8.12.2 BERT Error Counter............................................................................................................................. 85
9. DEVICE REGISTERS .......................................................................................................86
9.1 REGISTER LISTINGS ...................................................................................................................... 86
9.1.1 Global Register List.............................................................................................................................. 88
9.1.2 Framer Register List............................................................................................................................. 89
9.1.3 LIU and BERT Register List................................................................................................................. 96
9.2 REGISTER BIT MAPS......................................................................................................................97
9.2.1 Global Register Bit Map ....................................................................................................................... 97
9.2.2 Framer Register Bit Map ...................................................................................................................... 98
9.2.3 LIU Register Bit Map .......................................................................................................................... 106
9.2.4 BERT Register Bit Map...................................................................................................................... 106
9.3 GLOBAL REGISTER DEFINITIONS .................................................................................................. 107
9.4 FRAMER REGISTER DEFINITIONS ................................................................................................. 122
9.4.1 Receive Register Definitions.............................................................................................................. 122
9.4.2 Transmit Register Definitions............................................................................................................. 181
9.5 LIU REGISTER DEFINITIONS.........................................................................................................216
9.6 BERT REGISTER DEFINITIONS.....................................................................................................225
10. FUNCTIONAL TIMING ...................................................................................................233
10.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................233
10.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................238
10.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................243
10.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................245
11. OPERATING PARAMETERS.........................................................................................248
11.1 THERMAL CHARACTERISTICS ....................................................................................................249
11.2 LINE INTERFACE CHARACTERISTICS..........................................................................................249
12. AC TIMING CHARACTERISTICS ..................................................................................250
12.1 MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................250
12.2 JTAG INTERFACE TIMING.........................................................................................................259
12.3 SYSTEM CLOCK AC CHARACTERISTICS ....................................................................................260
13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................261
13.1 TAP CONTROLLER STATE MACHINE .........................................................................................262
13.1.1 Test-Logic-Reset................................................................................................................................ 262
13.1.2 Run-Test-Idle ..................................................................................................................................... 262
13.1.3 Select-DR-Scan ................................................................................................................................. 262
13.1.4 Capture-DR ........................................................................................................................................ 262
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13.1.5 Shift-DR.............................................................................................................................................. 262
13.1.6 Exit1-DR............................................................................................................................................. 262
13.1.7 Pause-DR........................................................................................................................................... 262
13.1.8 Exit2-DR............................................................................................................................................. 262
13.1.9 Update-DR ......................................................................................................................................... 262
13.1.10 Select-IR-Scan ............................................................................................................................... 262
13.1.11 Capture-IR ...................................................................................................................................... 263
13.1.12 Shift-IR............................................................................................................................................ 263
13.1.13 Exit1-IR........................................................................................................................................... 263
13.1.14 Pause-IR......................................................................................................................................... 263
13.1.15 Exit2-IR........................................................................................................................................... 263
13.1.16 Update-IR ....................................................................................................................................... 263
13.2 INSTRUCTION REGISTER........................................................................................................... 265
13.2.1 SAMPLE:PRELOAD .......................................................................................................................... 265
13.2.2 BYPASS............................................................................................................................................. 265
13.2.3 EXTEST ............................................................................................................................................. 265
13.2.4 CLAMP............................................................................................................................................... 265
13.2.5 HIGHZ ................................................................................................................................................ 265
13.2.6 IDCODE ............................................................................................................................................. 265
13.3 JTAG ID CODES......................................................................................................................266
13.4 TEST REGISTERS ..................................................................................................................... 266
13.4.1 Boundary Scan Register .................................................................................................................... 266
13.4.2 Bypass Register ................................................................................................................................. 266
13.4.3 Identification Register......................................................................................................................... 266
14. PIN CONFIGURATION...................................................................................................271
15. PACKAGE INFORMATION............................................................................................272
15.1 256-BALL TE-CSBGA (56-G6028-001) ...................................................................................272
16. DOCUMENT REVISION HISTORY ................................................................................273
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LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 27
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 30
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 35
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 36
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 37
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 40
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 41
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 62
Figure 8-9. Receive HDLC Example.......................................................................................................................... 68
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 70
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal Protection ............................. 72
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 76
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 77
Figure 8-14. Typical Monitor Application ................................................................................................................... 79
Figure 8-15. Jitter Attenuation ................................................................................................................................... 81
Figure 8-16. Analog Loopback................................................................................................................................... 82
Figure 8-17. Local Loopback ..................................................................................................................................... 82
Figure 8-18. Remote Loopback ................................................................................................................................. 83
Figure 8-19. Dual Loopback ...................................................................................................................................... 83
Figure 9-1. Register Memory Map for the DS26524.................................................................................................. 87
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 233
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 233
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 234
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 234
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 235
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 236
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 237
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 238
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 238
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 239
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 239
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 240
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 241
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 242
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 243
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 243
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 245
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 245
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 247
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 251
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 251
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 252
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Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 252
Figure 12-5. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 254
Figure 12-6. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 255
Figure 12-7. Receive Framer Timing—Line Side .................................................................................................... 255
Figure 12-8. Transmit Formatter Timing—Backplane ............................................................................................. 257
Figure 12-9. Transmit Formatter Timing, Elastic Store Enabled ............................................................................. 258
Figure 12-10. BPCLK Timing................................................................................................................................... 258
Figure 12-11. Transmit Formatter Timing—Line Side ............................................................................................. 258
Figure 12-12. JTAG Interface Timing Diagram........................................................................................................ 259
Figure 13-1. JTAG Functional Block Diagram ......................................................................................................... 261
Figure 13-2. TAP Controller State Diagram............................................................................................................. 264
Figure 14-1. Pin Configuration—256-Ball TE-CSBGA ............................................................................................ 271
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LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19
Table 8-1. Reset Functions........................................................................................................................................ 28
Table 8-2. Registers Related to the Elastic Store...................................................................................................... 31
Table 8-3. Elastic Store Delay After Initialization....................................................................................................... 32
Table 8-4. Registers Related to the IBO Multiplexer ................................................................................................. 34
Table 8-5. RSER Output Pin Definitions.................................................................................................................... 38
Table 8-6. RSIG Output Pin Definitions..................................................................................................................... 38
Table 8-7. TSER Input Pin Definitions....................................................................................................................... 39
Table 8-8. TSIG Input Pin Definitions ........................................................................................................................ 39
Table 8-9. RSYNC Input Pin Definitions.................................................................................................................... 39
Table 8-10. D4 Framing Mode................................................................................................................................... 42
Table 8-11. ESF Framing Mode ................................................................................................................................ 43
Table 8-12. SLC-96 Framing ..................................................................................................................................... 43
Table 8-13. E1 FAS/NFAS Framing .......................................................................................................................... 45
Table 8-14. Registers Related to Setting Up the Framer .......................................................................................... 46
Table 8-15. Registers Related to the Transmit Synchronizer.................................................................................... 47
Table 8-16. Registers Related to Signaling ............................................................................................................... 48
Table 8-17. Registers Related to SLC-96.................................................................................................................. 51
Table 8-18. Registers Related to T1 Transmit BOC.................................................................................................. 52
Table 8-19. Registers Related to T1 Receive BOC................................................................................................... 53
Table 8-20. Registers Related to T1 Transmit FDL................................................................................................... 53
Table 8-21. Registers Related to T1 Receive FDL.................................................................................................... 54
Table 8-22. Registers Related to E1 Data Link ......................................................................................................... 54
Table 8-23. Registers Related to Maintenance and Alarms...................................................................................... 56
Table 8-24. T1 Alarm Criteria .................................................................................................................................... 58
Table 8-25. T1 Line Code Violation Counting Options .............................................................................................. 59
Table 8-26. E1 Line Code Violation Counting Options.............................................................................................. 60
Table 8-27. T1 Path Code Violation Counting Arrangements ................................................................................... 60
Table 8-28. T1 Frames Out of Sync Counting Arrangements ................................................................................... 60
Table 8-29. Registers Related to DS0 Monitoring ..................................................................................................... 61
Table 8-30. Registers Related to T1 In-Band Loop Code Generator........................................................................ 63
Table 8-31. Registers Related to T1 In-Band Loop Code Detection......................................................................... 64
Table 8-32. Registers Related to Framer Payload Loopbacks.................................................................................. 65
Table 8-33. Registers Related to the HDLC .............................................................................................................. 66
Table 8-34. Recommended Supply Decoupling ........................................................................................................ 73
Table 8-35. Registers Related to Control of DS26524 LIU ....................................................................................... 74
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters .......................................... 75
Table 8-37. Transformer Specifications..................................................................................................................... 75
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications .......................................... 79
Table 8-39. Jitter Attenuator Standards Compliance................................................................................................. 81
Table 8-40. Registers Related to BERT Configure, Control, and Status................................................................... 84
Table 9-1. Register Address Ranges (in Hex)........................................................................................................... 86
Table 9-2. Global Register List .................................................................................................................................. 88
Table 9-3. Framer Register List ................................................................................................................................. 89
Table 9-4. LIU Register List ....................................................................................................................................... 96
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Table 9-5. BERT Register List ................................................................................................................................... 96
Table 9-6. Global Register Bit Map............................................................................................................................ 97
Table 9-7. Framer Register Bit Map .......................................................................................................................... 98
Table 9-8. LIU Register Bit Map .............................................................................................................................. 106
Table 9-9. BERT Register Bit Map .......................................................................................................................... 106
Table 9-10. Global Register Set .............................................................................................................................. 107
Table 9-11. Backplane Reference Clock Select ...................................................................................................... 111
Table 9-12. Master Clock Input Selection................................................................................................................ 112
Table 9-13. Device ID Codes in this Product Family ............................................................................................... 115
Table 9-14. LIU Register Set ................................................................................................................................... 216
Table 9-15. Transmit Load Impedance Selection.................................................................................................... 217
Table 9-16. Transmit Pulse Shape Selection .......................................................................................................... 217
Table 9-17. Receive Level Indication....................................................................................................................... 222
Table 9-18. Receive Impedance Selection.............................................................................................................. 223
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 224
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 224
Table 9-21. BERT Register Set ............................................................................................................................... 225
Table 9-22. BERT Pattern Select ............................................................................................................................ 227
Table 9-23. BERT Error Insertion Rate ................................................................................................................... 228
Table 9-24. BERT Repetitive Pattern Length Select ............................................................................................... 228
Table 11-1. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-2. Capacitance.......................................................................................................................................... 248
Table 11-3. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-4. Thermal Characteristics........................................................................................................................ 249
Table 11-5. Transmitter Characteristics................................................................................................................... 249
Table 11-6. Receiver Characteristics....................................................................................................................... 249
Table 12-1. AC Characteristics—Microprocessor Bus Timing ................................................................................ 250
Table 12-2. Receiver AC Characteristics ................................................................................................................ 253
Table 12-3. Transmit AC Characteristics................................................................................................................. 256
Table 12-4. JTAG Interface Timing.......................................................................................................................... 259
Table 12-5. System Clock AC Charateristics .......................................................................................................... 260
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 265
Table 13-2. ID Code Structure................................................................................................................................. 266
Table 13-3. Boundary Scan Control Bits ................................................................................................................. 266
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DS26524 Quad T1/E1/J1 Transceiver
1. DETAILED DESCRIPTION
The DS26524 is a 4-port monolithic device featuring independent transceivers that can be software configured for
T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic
store, and a TDM backplane interface. The DS26524 is controlled via an 8-bit parallel port. Internal impedance
matching is provided for both transmit and receive paths, reducing external component count.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes
for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be
placed in either transmit or receive data paths.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane
interface section.
Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives
data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot, or to FDL
(T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). The interleave bus option (IBO) is provided to allow up to eight transceivers to share a
high-speed backplane. The DS26524 also contains an internal clock adapter useful for the creation of a
synchronous, high-frequency backplane timing source.
The parallel port provides access for configuration and status of all the DS26524’s features. Diagnostic capabilities
include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
1.1 Major Operating Modes
The DS26524 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is
configured in the LIU Transmit Receive Control register (LTRCR
configured in the Transmit Master Mode register (TMMR
). J1 operation is a special case of T1 operating mode.
). The mode of operation for the framer is
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2. FEATURE HIGHLIGHTS
2.1 General
Member of the TEX-series transceiver family of devices. Software compatible with the DS26521 single,
DS26522 dual, and DS26528 octal transceivers
256-pin TE-CSBGA package (17mm x 17mm, 1.00mm pitch)
3.3V supply with 5V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Development support includes evaluation kit, driver source code, and reference designs
2.2 Line Interface
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,
2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz
Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to
30dB, 0dB to 20dB, and 0dB to -15dB for T1
Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB
increments
Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
Analog loss-of-signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current-limit-exceeded indication
Transmit open-circuit-detected indication
2.3 Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from user-selected recovered receive clock
2.4 Jitter Attenuator
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
2.5 Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
10 of 273
DS26524 Quad T1/E1/J1 Transceiver
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
− T1: BPV, CV, CRC-6, and framing bit errors
− E1: BPV, CV, CRC-4, E-bit, and frame alignment errors
− Timed or manual update modes
DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
− User defined
− Digital Milliwatt
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
− Three independent generators and detectors
− Patterns from 1 to 8 bits or 16 bits in length
Bit-oriented code (BOC) support
Flexible signaling support
− Software or hardware based
− Interrupt generated on change of signaling data
− Optional receive-signaling freeze on loss of frame, loss of signal, or frame slip
− Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock
(LOTC), or signaling freeze condition
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC-6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1-to-E1 conversion
2.6 System Interface
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
Receive-signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
User-selectable synthesized clock output
11 of 273
DS26524 Quad T1/E1/J1 Transceiver
2.7 HDLC Controllers
One HDLC controller engine for each T1/E1 port
Independent 64-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single DS0 channel
Compatible with polled or interrupt driven environments
2.8 Test and Diagnostics
IEEE 1149.1 support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
2.9 Control Port
8-bit parallel control port
Intel or Motorola nonmultiplexed support
Flexible status registers support polled, interrupt, or hybrid program environments
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
12 of 273
3. APPLICATIONS
The DS26524 is useful in applications such as:
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
DS26524 Quad T1/E1/J1 Transceiver
13 of 273
DS26524 Quad T1/E1/J1 Transceiver
4. SPECIFICATIONS COMPLIANCE
The DS26524 LIU meets all the latest relevant telecommunications specifications. Table 4-1 and Table 4-2 provide
the T1 and E1 specifications and relevant sections that are applicable to the DS26524.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102: Digital Hierarchy Electrical Interface
AMI Coding
B8ZS Substitution Definition
DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6V peak; power level between
12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is
greater than -26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cables of 1000 feet.
ANSI T1.231: Digital Hierarchy—Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition.
ANSI T1.403: Network and Customer Installation Interface—DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100Ω. Pulse shape and template compliance
according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB, and -15dB. Line rate is ±32ppm. Pulse Amplitude
is 2.4V to 3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26524 functions with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different, specifically at Times 0.61, -0.27, -34, and
0.77. The DS26524 is compliant to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter the G.823.
(ANSI) “Digital Hierarchy—Electrical Interfaces”
(ANSI) “Digital Hierarchy—Formats Specification”
(ANSI) “Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces—DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super
Frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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DS26524 Quad T1/E1/J1 Transceiver
Table 4-2. E1-Related Telecommunications Specifications
ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to-
peak space voltage is ±0.237V; nominal pulse width is 244ns.
Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse template for E1 is defined in G.703.
ITU-T G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps
The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps
The DS26524 jitter attenuator is complaint with jitter transfer curve for sinusoidal jitter input.
ITU-T G.772
This specification provides the method for using receiver for transceiver 0 as a monitor for the remaining seven
transmitter/receiver combinations.
ITU-T G.775
An LOS detection criterion is defined.
ITU-T G.823 The control of jitter and wander within digital networks that are based on 2.048kbps hierarchy.
G.823 Provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and
100kHz.
ETS 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.
(ITU-T) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
(ITU-T) “Characteristics of Primary PCM Multiplex Equipment Operating at 2048kbps”
(ITU-T) Characteristics of a Synchronous Digital Multiplex Equipment Operating at 2048kbps”
(ITU-T) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
(ITU-T) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy”
(ITU-T) “Primary Rate User-Network Interface—Layer 1 Specification”
(ITU-T) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”
(ITU-T) “In-Service Code Violation Monitors for Digital Systems”
(ETS) “Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface (UNI); Part 1/Layer 1
Specification”
(ETS) “Transmission and Multiplexing; Physical/Electrical Characteristics of Hierarchical Digital Interfaces for
Equipment Using the 2048kbps-Based Plesiochronous or Synchronous Digital Hierarchies”
(ETS) “Integrated Services Digital Network (ISDN); Access Digital Section for ISDN Primary Rate”
(ETS) “Integrated Services Digital Network (ISDN); Attachment Requirements for Terminal Equipment to Connect
to an ISDN Using ISDN Primary Rate Access”
(ETS) “Business Telecommunications (BT); Open Network Provision (ONP) Technical Requirements; 2048kbps
Digital Unstructured Leased Lines (D2048U) Attachment Requirements for Terminal Equipment Interface”
(ETS) “Business Telecommunications (BTC); 2048kbps Digital Structured Leased Lines (D2048S); Attachment
Requirements for Terminal Equipment Interface”
(ITU-T) “Synchronous Frame Structures Used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
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DS26524 Quad T1/E1/J1 Transceiver
5. ACRONYMS AND GLOSSARY
This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1
frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. For T1 and E1, each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is
transmitted first. Bit 8, the LSB, is transmitted last.
Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
Table 5-1. Time Slot Numbering Schemes
TS
Channel
Phone
Channel
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 of 273
6. BLOCK DIAGRAMS
A
Figure 6-1. Block Diagram
DS26524
DS26524 Quad T1/E1/J1 Transceiver
RTIP
RRING
TTIP
TRING
X4
LIU #4
LIU #3
LIU #2
LINE
INTERFACE
UNIT
MICRO PROCESSOR
INTERFACE
CONTROLLER
PORT
FRAMER #4
FRAMER #3
FRAMER #2
T1/E1 FRAMER
HDLC
BERT
JTAG PORT
TEST
PORT
INTERFACE #4
INTERFACE #3
INTERFACE #2
BACKPLANE
INTERFACE
ELASTIC
STORES
CLOCK
GENERATION
CLOCK
ADAPTER
RECEIVE
BACKPLANE
SIGNALS
TRANSMIT
BACKPLANE
SIGNALS
HARDWARE
LARM
INDICATORS
X4
17 of 273
Figure 6-2. Detailed Block Diagram
JITTER ATTENUATOR
ENABLE
C
C
A
A[
]
[
]
C
R
/
W
/
I
J
R
g
g
(
)
DS26524 Quad T1/E1/J1 Transceiver
TTIPn
TRINGn
RTIPn
RRINGn
TRANSCEIVER #1 of 4:
TRANSMIT
LB
TRANSMIT
LIU
Waveform
Shaper/Line
Driver
RECEIVE
LIU
Clock/Data
Recovery
DS26524
MICROPROCESSOR
INTERFACE
Tx
BERT
Tx FRAMER:
B8ZS/
HDB3
Encode
LLB
FLB
RLB
Rx FRAMER:
B8ZS/
HDB3
Decode
Rx
BERT
JTAG
PORT
RESET
BLOCK
Elastic
Store
Elastic
Store
Tx
HDLC
Rx
HDLC
System IF
PLB
System IF
PRESCALER
PLL
BA
KPLANE INTERFA
E
Tx Signaling/
Channel Blockin
TCLKn
TSERn
TSYNCn
TSSYNCIO
TSYSCLK
RSYSCLK
RSYNCn
RSERn
RCLKn
Rx Signaling/
Channel Blockin
MCLK
TSSYNCIO
Output Mode
BPCLK
REFCLK
NTB
BTS
RB
RWB
DB
DSB
SB
D
7:0
12:0
TRST
JTCLK
JTMS
JTDI
JTDO
ESETB
BACKPLANE
CLOCK
GENERATOR
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DS26524 Quad T1/E1/J1 Transceiver
7. PIN DESCRIPTIONS
7.1 Pin Functional Description
Table 7-1. Detailed Pin Descriptions
NAME PIN TYPE FUNCTION
ANALOG TRANSMIT
TTIP1 A1, A2
TTIP2 H1, H2
TTIP3 J1 J2
TTIP4 T1, T2
TRING1 A3, B3
TRING2 G3, H3
TRING3 J3, K3
TRING4 R3, T3
Impedance
Impedance
Analog
Output,
High
Analog
Output,
High
Transmit Bipolar Tip for Transceiver 1 to 4. These pins are differential line
driver tip outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω , E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar tip (e.g., pins A1 and A2 for
TTIP1) should be tied together.
Transmit Bipolar Ring for Transceiver 1 to 4. These pins are differential line
driver ring outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar ring (e.g., pins A3 and B3 for
TRING1) should be tied together.
TXENABLE L13 I
RTIP1 C1
RTIP2 F1
RTIP3 L1
RTIP4 P1
RRING1 C2
RRING2 F2
RRING3 L2
RRING4 P2
TSER1 F6
TSER2 E7
TSER3 R4
TSER4 N7
Analog
Input
Analog
Input
I
Transmit Enable. If this pin is pulled low, all transmitter outputs (TTIP and
TRING) are high impedance. The register settings for tri-state control of
TTIP/TRING are ignored if TXENABLE is low. If TXENABLE is high, the particular
driver can be tri-stated by the register settings.
ANALOG RECEIVE
Receive Bipolar Tip for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR
Receive Bipolar Ring for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR
TRANSMIT FRAMER
Transmit NRZ Serial Data. These pins are sampled on the falling edge of TCLK
when the transmit-side elastic store is disabled. These pins are sampled on the
falling edge of TSYSCLK when the transmit-side elastic store is enabled.
In IBO mode, data for multiple framers can be used in high-speed multiplexed
scheme. This is described in Section 8.8.2
combination of framer data for each of the streams.
TSYSCLK is used as a reference when IBO is invoked.
. The table there presents the
).
).
19 of 273
DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
TCLK1 C5
TCLK2 D7
TCLK3 P5
I
TCLK4 L8
TSYSCLK P13 I
TSYNC1 B4
TSYNC2 F7
TSYNC3 M6
TSYNC4 M7
TSSYNCIO N13 I/O
I/O
Transmit Clock. A 1.544MHz or a 2.048MHz primary clock. Used to clock data
through the transmit side of the transceiver. TSER data is sampled on the falling
edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled
or IBO is not used.
When the elastic store is enabled, TCLKn is used as the internal transmit clock for
the framer side or the elastic store, including the transmit framer and LIU. With the
elastic store enabled, TCLKn can be either synchronous or asynchronous to
TSYSCLKn, which either prevents or allows for slips. In addition, when IBO mode
is enabled, TCLKn must be synchronous to TSYSCLKn, which prevents slips in the
elastic store.
Note: This clock must be provided for proper device operation. The only exception
is when the TCR3 register is configured to source TCLK internally from RCLK.
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz clock. Only used when the transmit-side elastic store function is
enabled. Should be tied low in applications that do not use the transmit-side elastic
store. This is a common clock that is used for the transmitters. The clock can be
4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
Transmit Synchronization. A pulse at these pins establishes either frame or
multiframe boundaries for the transmit side. These signals can also be
programmed to output either a frame or multiframe pulse. If these pins are set to
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signaling frames in T1 mode. The operation of these signals is
synchronous with TCLK.
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for all four transmitters. Should be tied low
in applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26524
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG1 D5
TSIG2 A6
TSIG3 T4
TSIG4 R6
TCHBLK/
CLK1
TCHBLK/
CLK2
TCHBLK/
CLK3
TCHBLK/
CLK4
A5
C7
L7
P7
O
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
I
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams
can run up to 16.384MHz.
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for perchannel conditioning.
TCHCLK. TCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, TCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, TCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, TCHCLKn is synchronous with
TCLKn when the receive-side elastic store is disabled or it is synchronous with
TSYSCLKn when the receive-side elastic store is enabled. The mode of TCHCLKn
is determined by the TGCLKEN bit in the TESCR register.
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
RECEIVE FRAMER
RSER1 E5
RSER2 D6
RSER3 N4
RSER4 N6
RCLK1 F4
RCLK2 G4
RCLK3 L4
RCLK4 M4
RSYSCLK L12 I
RSYNC1 A4
RSYNC2 B6
RSYNC3 N5
RSYNC4 T6
RMSYNC1/
RFSYNC1
RMSYNC2/
RFSYNC2
RMSYNC3/
RFSYNC3
RMSYNC4/
RFSYNC4
RSIG1 D4
RSIG2 E6
RSIG3 M5
RSIG4 R5
AL/
RSIGF/
FLOS1
AL/
RSIGF/
FLOS2
AL/
RSIGF/
FLOS3
AL/
RSIGF/
FLOS4
RLF/
LTC1
RLF/
LTC2
RLF/
LTC3
RLF/
LTC4
C4
C6
P4
P6
C3
F3
L3
P3
D3
E3
M3
N3
O
O
I/O
O
O
O
O
Received Serial Data. Received NRZ serial data. Updated on rising edges of
RCLK when the receive-side elastic store is disabled. Updated on the rising edges
of RSYSCLK when the receive-side elastic store is enabled.
When IBO mode is used, the RSER pins can output data for multiple framers. The
RSER data is synchronous to RSYSCLK. This is described in Section 8.8.2
Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock
data through the receive-side framer. This clock is recovered from the signal at
RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used
to output RSER when the elastic store is not enabled or IBO is not used. When the
elastic store is enabled or IBO is used, the RSER is clocked by RSYSCLK.
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receiveside elastic store. Multiple of 2.048MHz is expected when the IBO mode is used.
Note that RSYSCLK is used for all four transceivers.
Receive Synchronization. If the receive-side elastic store is enabled, then this
signal is used to input a frame or multiframe boundary pulse. If set to output frame
boundaries, then RSYNC can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNC out can be used to indicate
CAS and CRC-4 multiframe. The DS26524 can accept H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR
Receive Multiframe/Frame Synchronization. A dual function pin to indicate
frame or multiframe synchronization. RFSYNC is an extracted 8kHz pulse, one
RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one
RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled),
that identifies multiframe boundaries. When the receive elastic store is enabled,
the RMSYNC signal indicates the multiframe sync on the system (backplane) side
of the elastic store. In E1 mode, this pin can indicate either the CRC-4 or CAS
multiframe as determined by the RSMS2 control bit in the Receive I/O
Configuration register (RIOCR
Receive Signaling. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.
Analog Loss/Receive-Signaling Freeze/Framer LOS. Analog LOS reflects the
LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS
detection by the corresponding framer; the same pins can reflect receive-signaling
freeze indications. This selection can be made by settings in the Global
Transceiver Clock Control register (GTCCR
If framer LOS is selected, this pin can be programmed to toggle high when the
framer detects an LOS condition, or when the signaling data is frozen via either
automatic or manual intervention. The indication is used to alert downstream
equipment of the condition.
Receive Loss of Frame/Loss of Transmit Clock. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe,
or to toggle high if the TCLK pin has not been toggled for approximately three clock
periods.
.1).
.2 register.
).
.
21 of 273
DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
RCHBLK/
CLK1
RCHBLK/
CLK2
RCHBLK/
CLK3
RCHBLK/
CLK4
BPCLK E8 O
A12 C8
A11 A8
A10 B8
A9 F8
A8 B9
A7 A9
A6 C9
A5 D9
A4 E9
A3 F9
A2 B10
A1 A10
A0 C10
D7 T9
D6 N9
D5 M9
D4 R8
D3 T8
D2 P8
D1 L9
D0 N8
CSB
E4
B5
L6
T5
T7 I
O
I
I
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a userprogrammable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in dropand-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
MICROPROCESSOR INTERFACE
Address [12:0]. This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
RDB/
DSB
WRB/
RWB
M8 I
R7 I
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Interrupt Bar. This active-low, open-drain output is asserted when an unmasked
INTB
BTS M13 I
MCLK B7 I
RESETB
REFCLKIO A7 I/O
R9 U
J12 I
interrupt event is detected. INTB will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global lev el,
framer, LIU, and BERT level.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins.
SYSTEM INTERFACE
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLK must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See Table 9-12
Reset Bar. Active-low reset. This input forces the complete DS26524 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference
clock. This allows for multiple DS26524s to share the same reference for
generation of the backplane clock. Hence, in a system consisting of multiple
DS26524s, one can be a master and others a slave using the same reference
clock.
TEST
.
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
DIGIOEN D8 I, Pullup
JTRST
JTMS K4 I, Pullup
JTCLK F5 I
JTDI H4 I, Pullup
JTDO J4
L5 I, Pullup
O, High
impedance
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
for normal operation.
DD
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
POWER SUPPLIES
ATVDD1 B1
ATVDD2 G1
ATVDD3 K1
ATVDD4 R1
ATVDD5 R16
—
ATVDD6 K16
ATVDD7 G16
ATVDD8 B16
ATVSS1 B2
ATVSS2 G2
ATVSS3 K2
ATVSS4 R2
ATVSS5 R15
—
ATVSS6 K15
ATVSS7 G15
ATVSS8 B15
ARVDD1 D1
ARVDD2 E1
ARVDD3 M1
ARVDD4 N1
ARVDD5 N16
—
ARVDD6 M16
ARVDD7 E16
ARVDD8 D16
ARVSS1 D2
ARVSS2 E2
ARVSS3 M2
ARVSS4 N2
ARVSS5 N15
—
ARVSS6 M15
ARVSS7 E15
ARVSS8 D15
ACVDD H7 —
3.3V Analog Transmit Power Supply. These V
LIU sections of the DS26524.
Analog Transmit V
. These pins are used for transmit analog VSS.
SS
3.3V Analog Receive Power Supply. These V
LIU sections of the DS26524.
Analog Receive V
Analog Clock Conversion V
. These pins are used for analog VSS for the receivers.
SS
. This VDD input is used for the clock conversion
DD
unit of the DS26524.
inputs are used for the transmit
DD
inputs are used for the receive
DD
ACVSS J7 —
DVDD
DVDDIO
G5–G12,
H8, H9
H5, H6,
H10, H11
—
—
Analog Clock V
3.3V Power Supply for Digital Framers
3.3V Power Supply for I/Os
. This pin is used for clock converter analog VSS.
SS
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
A11, A13,
B11, B13,
C11, C13,
D12, D13,
E10, F10,
H12, H13,
DVSS
DVSSIO
N.C.
J8, J9,
K5–K12,
L10, L11,
M10, N10,
N11, P12,
R10, R12,
T10, T12
J5, J6,
J10, J11
A12, A14,
A15, A16,
B12, B14,
C12, C14,
C15, C16,
D10, D11,
D14,
E11–E14,
F11–F16,
G13, G14,
H14, H15,
H16,
J13–J16,
K13, K14,
L14, L15,
L16, M11,
M12, M14
N12, N14,
P9, P10,
P11, P14,
P15, P16,
R11, R13,
R14, T11,
T13–T16
-—
—
—
Digital Ground for the Framers
Digital Ground for the I/Os
No Connection. These pins must not be connected to V
or VSS.
DD
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DS26524 Quad T1/E1/J1 Transceiver
8. FUNCTIONAL DESCRIPTION
8.1 Processor Interface
Microprocessor control of the DS26524 is accomplished through the 28 hardware pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 12-1
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 12-3 and Figure 12-4. The
address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the readwrite bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The device has
a bulk write mode that allows a microprocessor to write all four internal transceivers with each bus write cycle. By
setting the BWE bit (GTCR1
The BWE bit must be cleared before normal write operation is resumed. This function is useful for device
initialization. The register map is shown in Figure 9-1
.2), each port write cycle will write to all four framers, LIUs, or BERTs at the same time.
.
and Figure 12-2.
8.2 Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
8.2.1 Backplane Clock Generation
The DS26524 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 8-1). The Global Transceiver Clock Control register (GTCCR) is used to control the backplane clock
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can output MCLKT1
or MCLKE1 as shown in Figure 8-1
This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26524 and other IBO-equipped devices
as an IBO bus master. Hence, the DS26524 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock.
This can be used by the link layer devices and frames connected to the IBO bus.
.
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Figure 8-1. Backplane Clock Generation
BPREFSEL3:0
RCLK1
RCLK2
RCLK3
RCLK4
Pre
MCLK
Scaler
PLL
MCLKT1
MCLKE1
DS26524 Quad T1/E1/J1 Transceiver
BPCLK1:0
BFREQSEL
Multiplexor
Clock
CLK
GEN
REFCLKIO
TSSYNCIO
BPCLK
REFCLKIO
The reference clock for the backplane clock generator can be as follows:
• External Master Clock. A prescaler can be used to generate T1 or E1 frequency.
• External Reference Clock REFCLKIO. This allows for multiple DS26524s to use the backplane clock from
a common reference.
• Internal LIU recovered RCLKs 1 to 4.
• The clock generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
for the IBO.
• If MCLK or RCLK are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
clock for external use.
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DS26524 Quad T1/E1/J1 Transceiver
8.3 Resets and Power-Down Modes
A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs,
and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be
reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing
reserved locations to 00h.
The DS26524 has several features included to reduce power consumption. The LIU transmitters can be powered
down by setting the TPDE bit in the LIU Maintenance Control register (LMCR
transmit LIU results in a high-impedance state for the corresponding TTIP and TRING pins and reduced operating
current. The RPDE bit in the LMCR
register can be used to power down the LIU receiver.
). Note that powering down the
The TE (transmit enable) bit in the LMCR
them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for
equipment protection-switching applications.
register can be used to disable the TTIP and TRING outputs and place
Table 8-1. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset
Hardware JTAG Reset
Global Framer and BERT Reset GFSRR.0:3
Global LIU Reset GLSRR.0:3 Writing to these bits resets the associated LIU.
Framer Receive Reset RMMR.1 Writing to this bit resets the receive framer.
Framer Transmit Reset TMMR.1 Writing to this bit resets the transmit framer.
HDLC Receive Reset RHC.6 Writing to this bit resets the receive HDLC controller.
HDLC Transmit Reset THC1.5 Writing to this bit resets the transmit HDLC controller.
Elastic Store Receive Reset RESCR.2 Writing to this bit resets the receive elastic store.
Elastic Store Transmit Reset TESCR.2 Writing to this bit resets the transmit elastic store.
Bit Oriented Code Receive Reset T1RBOCC.7 Writing to this bit resets the receive BOC controller.
RESETB
JTRST
Transition to a logic 0 level resets the DS26524.
Resets the JTAG test port.
Writing to these bits resets the framer and BERT (transmit
and receive).
Loop Code Integration Reset
Spare Code Integration Reset T1RSCD1
T1RDNCD1
T1RUPCD1
,
Writing to these registers resets the programmable in-band
code integration period.
Writing to this register resets the programmable in-band
code integration period.
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DS26524 Quad T1/E1/J1 Transceiver
8.4 Initialization and Configuration
8.4.1 Example Device Initialization Sequence
STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software
reset bits outlined in Section 8.3
. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the device ID in the Device Identification register (IDR
STEP 3: Write the GTCCR
this write with at least a 300ns delay to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR
registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit
signaling in E1 mode, program the E1TAF
Control registers (TCR1
T1RCR2/E1RCR2, RCR3). Configure other framer features as appropriate.
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE bit to turn on the
TTIP and TRING outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
STEP 8: Set the INIT_DONE bit in the TMMR
register to correctly configure the system clocks. If supplying a 1.544MHz MCLK, follow
and E1TNAF registers as required. Configure the framer Transmit
:TCR4). Configure the Framer Receive Control registers (RCR1 (T1)/RCR1 (E1),
and RMMR registers for each framer.
).
and RMMR
register.
8.5 Global Resources
All four framers share a common microprocessor port. All ports share a common MCLK, and there is a common
software-configurable BPCLK output. A set of global registers are located at 0F0h–0FFh and include global resets,
global interrupt status, interrupt masking, clock configuration, and the device ID registers. See the global register
definitions in Table 9-2
. A common JTAG controller is used.
8.6 Per-Port Resources
Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the
per-port functions has its own register space.
8.7 Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR
interrupt(s). The host can then read the specific transceiver’s interrupt information registers (TIIR
latched status registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source,
the host will then read the transmit-latched status or the receive-latched status registers for the source of the
interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
register. The host must clear all latched status bits by writing a 1 to the bit location of the interrupt condition that
has been serviced. Latched status bits that have been masked by the interrupt mask registers are masked from the
interrupt information registers. The interrupt mask register bits prevent individual latched status conditions from
generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing
interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude bits for
which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll
the latched status bits for noninterrupt conditions, while using only one set of registers.
, GLISR, and GBISR to identify which of the four transceivers is causing the
, RIIR) and the
29 of 273
Figure 8-2. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear 7
Receive Alarm Condition Clear 6
Receive Loss of Signal Clear 5
Receive Loss of Frame Clear 4
Receive Remote Alarm Indication 3
Receive Alarm Condition 2
Receive Loss of Signal 1
Receive Loss of Frame 0
Receive Signal All Ones 3
Receive Signal All Zeros 2
Receive CRC-4 Multiframe 1
Receive Align Frame 0
Loss of Receive Clock Clear/Loss of Receive Clock Clear 7
Spare Code Detected Condition Clear 6
Loop-Down Code Clear/V52 Link Clear 5
Loop-Up Code Clear/Receive Distant MF Alarm Clear 4
Loss of Receive Clock/Loss of Receive Clock 3
Spare Code Detect 2
Loop-Down Detect/V52 Link Detect 1
Loop-Up Detect/Receive Distant MF Alarm Detect 0
Receive Elastic Store Full 7
Receive Elastic Store Empty 6
Receive Elastic Store Slip 5
Receive Signaling Change of State (Enable in RSCSE1:4) 3
One-Second Timer 2
Timer 1
Receive Multiframe 0
Receive FIFO Overrun 5
Receive HDLC Opening Byte 4
Receive Packet End 3
Receive Packet Start 2
Receive Packet High Watermark 1
Receive FIFO Not Empty 0
Receive RAI-CI 5
Receive AIS-CI 4
Receive SLC-96 Alignment 3
Receive FDL Register Full 2
Receive BOC Clear 1
Receive BOC 0
Transmit Elastic Store Full 7
Transmit Elastic Store Empty 6
Transmit Elastic Store Slip 5
Transmit SLC-96 Multiframe 4
Transmit Pulse Density Violation/Transmit Align Frame 3
Transmit Multiframe 2
Loss of Transmit Clock Clear 1
Loss of Transmit Clock 0
Transmit FDL Register Empty 4
Transmit FIFO Underrun 3
Transmit Message End 2
Transmit FIFO Below Low Watermark 1
Transmit FIFO Not Full Set 0
— —
— —
Loss of Frame 1
Loss of Frame Synchronization 0
Jitter Attenuator Limit Trip Clear 7
Open-Circuit Detect Clear 6
Short-Circuit Detect Clear 5
Loss of Signal Detect Clear 4
Jitter Attenuator Limit Trip 3
Open-Circuit Detect 2
Short-Circuit Detect 1
Loss of Signal Detect 0
BERT Bit-Error Detected 6
BERT Bit Counter Overflow 5
BERT Error Counter Overflow 4
BERT Receive All Ones 3
BERT Receive All Zeros 2
BERT Receive Loss of Synchronization 1
BERT in Synchronization 0
RLS1
RLS2
RLS3
RLS4
RLS5
RLS7
TLS1
TLS2
TLS3
LLSR
BLSR
0
1
2
RIIR
3
4
5
2
TIIR
1
DS26524 Quad T1/E1/J1 Transceiver
DRAWING LEGEND:
INTERRUPT
STATUS
REGISTERS
INTERRUPT MASK
REGISTERS
6
5
4
3
2
FRAMERS 2–4 LIUs 2–4 BERTs 2–4
1
0
REGISTER NAME
REGISTER NAME
GFIMR
GFISR1
GLIMR
GLISR1
GBISR1
GBIMR
GTCR1.0
INTERRUPT PIN
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