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DS26524
Quad T1/E1/J1 Transceive
GENERAL DESCRIPTION
The DS26524 is a single-chip 4-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
TYPICAL OPERATING CIRCUIT
T1/E1/J1
NETWORK
DS26524
T1/J1/E1
Transceiver
x4
BACKPLANE
TDM
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS26524G
DS26524G+
DS26524GN
DS26524GN+
+ Denotes lead-free/RoHS compliant device.
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
256 TE-CSBGA
FEATURES
Four Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
Features Continued in Section 2
.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 112907
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DS26524 Quad T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9
1.1 MAJOR OPERATING MODES .............................................................................................................9
2. FEATURE HIGHLIGHTS ..................................................................................................10
2.1 GENERAL ......................................................................................................................................10
2.2 LINE INTERFACE ............................................................................................................................ 10
2.3 CLOCK SYNTHESIZER ....................................................................................................................10
2.4 JITTER ATTENUATOR .....................................................................................................................10
2.5 FRAMER/FORMATTER .................................................................................................................... 10
2.6 SYSTEM INTERFACE ......................................................................................................................11
2.7 HDLC CONTROLLERS ...................................................................................................................12
2.8 TEST AND DIAGNOSTICS ................................................................................................................ 12
2.9 CONTROL PORT ............................................................................................................................12
3. APPLICATIONS ...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE ...................................................................................14
5. ACRONYMS AND GLOSSARY .......................................................................................16
6. BLOCK DIAGRAMS.........................................................................................................17
7. PIN DESCRIPTIONS ........................................................................................................19
7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19
8. FUNCTIONAL DESCRIPTION .........................................................................................26
8.1 PROCESSOR INTERFACE................................................................................................................ 26
8.2 CLOCK STRUCTURE....................................................................................................................... 26
8.2.1 Backplane Clock Generation ............................................................................................................... 26
8.3 RESETS AND POWER-DOWN MODES..............................................................................................28
8.4 INITIALIZATION AND CONFIGURATION..............................................................................................29
8.4.1 Example Device Initialization Sequence.............................................................................................. 29
8.5 GLOBAL RESOURCES ....................................................................................................................29
8.6 PER-PORT RESOURCES ................................................................................................................29
8.7 DEVICE INTERRUPTS .....................................................................................................................29
8.8 SYSTEM BACKPLANE INTERFACE ................................................................................................... 31
8.8.1 Elastic Stores ....................................................................................................................................... 31
8.8.2 IBO Multiplexer..................................................................................................................................... 34
8.8.3 H.100 (CT Bus) Compatibility .............................................................................................................. 40
8.8.4 Receive and Transmit Channel Blocking Registers............................................................................. 41
8.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
8.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
8.9 FRAMERS......................................................................................................................................42
8.9.1 T1 Framing........................................................................................................................................... 42
8.9.2 E1 Framing........................................................................................................................................... 45
8.9.3 T1 Transmit Synchronizer .................................................................................................................... 47
8.9.4 Signaling .............................................................................................................................................. 48
8.9.5 T1 Data Link......................................................................................................................................... 52
8.9.6 E1 Data Link......................................................................................................................................... 54
8.9.7 Maintenance and Alarms ..................................................................................................................... 55
8.9.8 E1 Automatic Alarm Generation .......................................................................................................... 58
8.9.9 Error-Count Registers .......................................................................................................................... 59
8.9.10 DS0 Monitoring Function...................................................................................................................... 61
8.9.11 Transmit Per-Channel Idle Code Insertion........................................................................................... 62
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8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 62
8.9.13 Per-Channel Loopback ........................................................................................................................ 62
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)................................................................... 62
8.9.15 T1 Programmable In-Band Loop Code Generator............................................................................... 63
8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................ 64
8.9.17 Framer Payload Loopbacks ................................................................................................................. 65
8.10 HDLC CONTROLLERS ................................................................................................................ 66
8.10.1 Receive HDLC Controller..................................................................................................................... 66
8.10.2 Transmit HDLC Controller.................................................................................................................... 69
8.11 LINE INTERFACE UNITS (LIUS) ....................................................................................................71
8.11.1 LIU Operation....................................................................................................................................... 74
8.11.2 Transmitter ........................................................................................................................................... 75
8.11.3 Receiver ............................................................................................................................................... 78
8.11.4 Jitter Attenuator.................................................................................................................................... 81
8.11.5 LIU Loopbacks ..................................................................................................................................... 82
8.12 BIT-ERROR-RATE TEST (BERT) FUNCTION ................................................................................84
8.12.1 BERT Repetitive Pattern Set ............................................................................................................... 85
8.12.2 BERT Error Counter............................................................................................................................. 85
9. DEVICE REGISTERS .......................................................................................................86
9.1 REGISTER LISTINGS ...................................................................................................................... 86
9.1.1 Global Register List.............................................................................................................................. 88
9.1.2 Framer Register List............................................................................................................................. 89
9.1.3 LIU and BERT Register List................................................................................................................. 96
9.2 REGISTER BIT MAPS......................................................................................................................97
9.2.1 Global Register Bit Map ....................................................................................................................... 97
9.2.2 Framer Register Bit Map ...................................................................................................................... 98
9.2.3 LIU Register Bit Map .......................................................................................................................... 106
9.2.4 BERT Register Bit Map...................................................................................................................... 106
9.3 GLOBAL REGISTER DEFINITIONS .................................................................................................. 107
9.4 FRAMER REGISTER DEFINITIONS ................................................................................................. 122
9.4.1 Receive Register Definitions.............................................................................................................. 122
9.4.2 Transmit Register Definitions............................................................................................................. 181
9.5 LIU REGISTER DEFINITIONS.........................................................................................................216
9.6 BERT REGISTER DEFINITIONS.....................................................................................................225
10. FUNCTIONAL TIMING ...................................................................................................233
10.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................233
10.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................238
10.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ..........................................................................243
10.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ....................................................................245
11. OPERATING PARAMETERS.........................................................................................248
11.1 THERMAL CHARACTERISTICS ....................................................................................................249
11.2 LINE INTERFACE CHARACTERISTICS..........................................................................................249
12. AC TIMING CHARACTERISTICS ..................................................................................250
12.1 MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................250
12.2 JTAG INTERFACE TIMING.........................................................................................................259
12.3 SYSTEM CLOCK AC CHARACTERISTICS ....................................................................................260
13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................261
13.1 TAP CONTROLLER STATE MACHINE .........................................................................................262
13.1.1 Test-Logic-Reset................................................................................................................................ 262
13.1.2 Run-Test-Idle ..................................................................................................................................... 262
13.1.3 Select-DR-Scan ................................................................................................................................. 262
13.1.4 Capture-DR ........................................................................................................................................ 262
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DS26524 Quad T1/E1/J1 Transceiver
13.1.5 Shift-DR.............................................................................................................................................. 262
13.1.6 Exit1-DR............................................................................................................................................. 262
13.1.7 Pause-DR........................................................................................................................................... 262
13.1.8 Exit2-DR............................................................................................................................................. 262
13.1.9 Update-DR ......................................................................................................................................... 262
13.1.10 Select-IR-Scan ............................................................................................................................... 262
13.1.11 Capture-IR ...................................................................................................................................... 263
13.1.12 Shift-IR............................................................................................................................................ 263
13.1.13 Exit1-IR........................................................................................................................................... 263
13.1.14 Pause-IR......................................................................................................................................... 263
13.1.15 Exit2-IR........................................................................................................................................... 263
13.1.16 Update-IR ....................................................................................................................................... 263
13.2 INSTRUCTION REGISTER........................................................................................................... 265
13.2.1 SAMPLE:PRELOAD .......................................................................................................................... 265
13.2.2 BYPASS............................................................................................................................................. 265
13.2.3 EXTEST ............................................................................................................................................. 265
13.2.4 CLAMP............................................................................................................................................... 265
13.2.5 HIGHZ ................................................................................................................................................ 265
13.2.6 IDCODE ............................................................................................................................................. 265
13.3 JTAG ID CODES......................................................................................................................266
13.4 TEST REGISTERS ..................................................................................................................... 266
13.4.1 Boundary Scan Register .................................................................................................................... 266
13.4.2 Bypass Register ................................................................................................................................. 266
13.4.3 Identification Register......................................................................................................................... 266
14. PIN CONFIGURATION...................................................................................................271
15. PACKAGE INFORMATION............................................................................................272
15.1 256-BALL TE-CSBGA (56-G6028-001) ...................................................................................272
16. DOCUMENT REVISION HISTORY ................................................................................273
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LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 27
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 30
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 35
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 36
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 37
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 40
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 41
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 62
Figure 8-9. Receive HDLC Example.......................................................................................................................... 68
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 70
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal Protection ............................. 72
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 76
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 77
Figure 8-14. Typical Monitor Application ................................................................................................................... 79
Figure 8-15. Jitter Attenuation ................................................................................................................................... 81
Figure 8-16. Analog Loopback................................................................................................................................... 82
Figure 8-17. Local Loopback ..................................................................................................................................... 82
Figure 8-18. Remote Loopback ................................................................................................................................. 83
Figure 8-19. Dual Loopback ...................................................................................................................................... 83
Figure 9-1. Register Memory Map for the DS26524.................................................................................................. 87
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 233
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 233
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 234
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 234
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 235
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 236
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 237
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 238
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 238
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 239
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 239
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 240
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 241
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 242
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 243
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 243
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 244
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 245
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 245
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 246
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 247
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 251
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 251
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 252
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DS26524 Quad T1/E1/J1 Transceiver
Figure 12-4. Motorola Bus Write Timing (BTS = 1) ................................................................................................. 252
Figure 12-5. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 254
Figure 12-6. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 255
Figure 12-7. Receive Framer Timing—Line Side .................................................................................................... 255
Figure 12-8. Transmit Formatter Timing—Backplane ............................................................................................. 257
Figure 12-9. Transmit Formatter Timing, Elastic Store Enabled ............................................................................. 258
Figure 12-10. BPCLK Timing................................................................................................................................... 258
Figure 12-11. Transmit Formatter Timing—Line Side ............................................................................................. 258
Figure 12-12. JTAG Interface Timing Diagram........................................................................................................ 259
Figure 13-1. JTAG Functional Block Diagram ......................................................................................................... 261
Figure 13-2. TAP Controller State Diagram............................................................................................................. 264
Figure 14-1. Pin Configuration—256-Ball TE-CSBGA ............................................................................................ 271
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LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19
Table 8-1. Reset Functions........................................................................................................................................ 28
Table 8-2. Registers Related to the Elastic Store...................................................................................................... 31
Table 8-3. Elastic Store Delay After Initialization....................................................................................................... 32
Table 8-4. Registers Related to the IBO Multiplexer ................................................................................................. 34
Table 8-5. RSER Output Pin Definitions.................................................................................................................... 38
Table 8-6. RSIG Output Pin Definitions..................................................................................................................... 38
Table 8-7. TSER Input Pin Definitions....................................................................................................................... 39
Table 8-8. TSIG Input Pin Definitions ........................................................................................................................ 39
Table 8-9. RSYNC Input Pin Definitions.................................................................................................................... 39
Table 8-10. D4 Framing Mode................................................................................................................................... 42
Table 8-11. ESF Framing Mode ................................................................................................................................ 43
Table 8-12. SLC-96 Framing ..................................................................................................................................... 43
Table 8-13. E1 FAS/NFAS Framing .......................................................................................................................... 45
Table 8-14. Registers Related to Setting Up the Framer .......................................................................................... 46
Table 8-15. Registers Related to the Transmit Synchronizer.................................................................................... 47
Table 8-16. Registers Related to Signaling ............................................................................................................... 48
Table 8-17. Registers Related to SLC-96.................................................................................................................. 51
Table 8-18. Registers Related to T1 Transmit BOC.................................................................................................. 52
Table 8-19. Registers Related to T1 Receive BOC................................................................................................... 53
Table 8-20. Registers Related to T1 Transmit FDL................................................................................................... 53
Table 8-21. Registers Related to T1 Receive FDL.................................................................................................... 54
Table 8-22. Registers Related to E1 Data Link ......................................................................................................... 54
Table 8-23. Registers Related to Maintenance and Alarms...................................................................................... 56
Table 8-24. T1 Alarm Criteria .................................................................................................................................... 58
Table 8-25. T1 Line Code Violation Counting Options .............................................................................................. 59
Table 8-26. E1 Line Code Violation Counting Options.............................................................................................. 60
Table 8-27. T1 Path Code Violation Counting Arrangements ................................................................................... 60
Table 8-28. T1 Frames Out of Sync Counting Arrangements ................................................................................... 60
Table 8-29. Registers Related to DS0 Monitoring ..................................................................................................... 61
Table 8-30. Registers Related to T1 In-Band Loop Code Generator........................................................................ 63
Table 8-31. Registers Related to T1 In-Band Loop Code Detection......................................................................... 64
Table 8-32. Registers Related to Framer Payload Loopbacks.................................................................................. 65
Table 8-33. Registers Related to the HDLC .............................................................................................................. 66
Table 8-34. Recommended Supply Decoupling ........................................................................................................ 73
Table 8-35. Registers Related to Control of DS26524 LIU ....................................................................................... 74
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters .......................................... 75
Table 8-37. Transformer Specifications..................................................................................................................... 75
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications .......................................... 79
Table 8-39. Jitter Attenuator Standards Compliance................................................................................................. 81
Table 8-40. Registers Related to BERT Configure, Control, and Status................................................................... 84
Table 9-1. Register Address Ranges (in Hex)........................................................................................................... 86
Table 9-2. Global Register List .................................................................................................................................. 88
Table 9-3. Framer Register List ................................................................................................................................. 89
Table 9-4. LIU Register List ....................................................................................................................................... 96
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DS26524 Quad T1/E1/J1 Transceiver
Table 9-5. BERT Register List ................................................................................................................................... 96
Table 9-6. Global Register Bit Map............................................................................................................................ 97
Table 9-7. Framer Register Bit Map .......................................................................................................................... 98
Table 9-8. LIU Register Bit Map .............................................................................................................................. 106
Table 9-9. BERT Register Bit Map .......................................................................................................................... 106
Table 9-10. Global Register Set .............................................................................................................................. 107
Table 9-11. Backplane Reference Clock Select ...................................................................................................... 111
Table 9-12. Master Clock Input Selection................................................................................................................ 112
Table 9-13. Device ID Codes in this Product Family ............................................................................................... 115
Table 9-14. LIU Register Set ................................................................................................................................... 216
Table 9-15. Transmit Load Impedance Selection.................................................................................................... 217
Table 9-16. Transmit Pulse Shape Selection .......................................................................................................... 217
Table 9-17. Receive Level Indication....................................................................................................................... 222
Table 9-18. Receive Impedance Selection.............................................................................................................. 223
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 224
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 224
Table 9-21. BERT Register Set ............................................................................................................................... 225
Table 9-22. BERT Pattern Select ............................................................................................................................ 227
Table 9-23. BERT Error Insertion Rate ................................................................................................................... 228
Table 9-24. BERT Repetitive Pattern Length Select ............................................................................................... 228
Table 11-1. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-2. Capacitance.......................................................................................................................................... 248
Table 11-3. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-4. Thermal Characteristics........................................................................................................................ 249
Table 11-5. Transmitter Characteristics................................................................................................................... 249
Table 11-6. Receiver Characteristics....................................................................................................................... 249
Table 12-1. AC Characteristics—Microprocessor Bus Timing ................................................................................ 250
Table 12-2. Receiver AC Characteristics ................................................................................................................ 253
Table 12-3. Transmit AC Characteristics................................................................................................................. 256
Table 12-4. JTAG Interface Timing.......................................................................................................................... 259
Table 12-5. System Clock AC Charateristics .......................................................................................................... 260
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 265
Table 13-2. ID Code Structure................................................................................................................................. 266
Table 13-3. Boundary Scan Control Bits ................................................................................................................. 266
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DS26524 Quad T1/E1/J1 Transceiver
1. DETAILED DESCRIPTION
The DS26524 is a 4-port monolithic device featuring independent transceivers that can be software configured for
T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic
store, and a TDM backplane interface. The DS26524 is controlled via an 8-bit parallel port. Internal impedance
matching is provided for both transmit and receive paths, reducing external component count.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is
responsible for generating the necessary waveshapes for driving the network and providing the correct source
impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well
as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes
for both 75Ω coax and 120Ω twisted cables. The receive interface provides network termination and recovers clock
and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be
programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1
applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter
attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be
placed in either transmit or receive data paths.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane
interface section.
Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives
data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot, or to FDL
(T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). The interleave bus option (IBO) is provided to allow up to eight transceivers to share a
high-speed backplane. The DS26524 also contains an internal clock adapter useful for the creation of a
synchronous, high-frequency backplane timing source.
The parallel port provides access for configuration and status of all the DS26524’s features. Diagnostic capabilities
include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and
detection.
1.1 Major Operating Modes
The DS26524 has two major modes of operation: T1 mode and E1 mode. The mode of operation for the LIU is
configured in the LIU Transmit Receive Control register (LTRCR
configured in the Transmit Master Mode register (TMMR
). J1 operation is a special case of T1 operating mode.
). The mode of operation for the framer is
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DS26524 Quad T1/E1/J1 Transceiver
2. FEATURE HIGHLIGHTS
2.1 General
Member of the TEX-series transceiver family of devices. Software compatible with the DS26521 single,
DS26522 dual, and DS26528 octal transceivers
256-pin TE-CSBGA package (17mm x 17mm, 1.00mm pitch)
3.3V supply with 5V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Development support includes evaluation kit, driver source code, and reference designs
2.2 Line Interface
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,
2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz
Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to
30dB, 0dB to 20dB, and 0dB to -15dB for T1
Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB
increments
Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
Analog loss-of-signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current-limit-exceeded indication
Transmit open-circuit-detected indication
2.3 Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from user-selected recovered receive clock
2.4 Jitter Attenuator
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
2.5 Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
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DS26524 Quad T1/E1/J1 Transceiver
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
− T1: BPV, CV, CRC-6, and framing bit errors
− E1: BPV, CV, CRC-4, E-bit, and frame alignment errors
− Timed or manual update modes
DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
− User defined
− Digital Milliwatt
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
− Three independent generators and detectors
− Patterns from 1 to 8 bits or 16 bits in length
Bit-oriented code (BOC) support
Flexible signaling support
− Software or hardware based
− Interrupt generated on change of signaling data
− Optional receive-signaling freeze on loss of frame, loss of signal, or frame slip
− Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock
(LOTC), or signaling freeze condition
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC-6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1-to-E1 conversion
2.6 System Interface
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
Receive-signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
User-selectable synthesized clock output
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DS26524 Quad T1/E1/J1 Transceiver
2.7 HDLC Controllers
One HDLC controller engine for each T1/E1 port
Independent 64-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single DS0 channel
Compatible with polled or interrupt driven environments
2.8 Test and Diagnostics
IEEE 1149.1 support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
2.9 Control Port
8-bit parallel control port
Intel or Motorola nonmultiplexed support
Flexible status registers support polled, interrupt, or hybrid program environments
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
12 of 273
3. APPLICATIONS
The DS26524 is useful in applications such as:
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
DS26524 Quad T1/E1/J1 Transceiver
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DS26524 Quad T1/E1/J1 Transceiver
4. SPECIFICATIONS COMPLIANCE
The DS26524 LIU meets all the latest relevant telecommunications specifications. Table 4-1 and Table 4-2 provide
the T1 and E1 specifications and relevant sections that are applicable to the DS26524.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102: Digital Hierarchy Electrical Interface
AMI Coding
B8ZS Substitution Definition
DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6V peak; power level between
12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is
greater than -26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cables of 1000 feet.
ANSI T1.231: Digital Hierarchy—Layer 1 in Service Performance Monitoring
BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition.
ANSI T1.403: Network and Customer Installation Interface—DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100Ω. Pulse shape and template compliance
according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB, and -15dB. Line rate is ±32ppm. Pulse Amplitude
is 2.4V to 3.6V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26524 functions with up to -36dB cable loss.
Note that the pulse template defined by T1.403 and T1.102 are different, specifically at Times 0.61, -0.27, -34, and
0.77. The DS26524 is compliant to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter the G.823.
(ANSI) “Digital Hierarchy—Electrical Interfaces”
(ANSI) “Digital Hierarchy—Formats Specification”
(ANSI) “Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring”
(ANSI) “Network and Customer Installation Interfaces—DS1 Electrical Interface”
(AT&T) “Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super
Frame Format”
(AT&T) “High Capacity Digital Service Channel Interface Specification”
(TTC) “Frame Structures on Primary and Secondary Hierarchical Digital Interfaces”
(TTC) “ISDN Primary Rate User-Network Interface Layer 1 Specification”
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DS26524 Quad T1/E1/J1 Transceiver
Table 4-2. E1-Related Telecommunications Specifications
ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to-
peak space voltage is ±0.237V; nominal pulse width is 244ns.
Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB.
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse template for E1 is defined in G.703.
ITU-T G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps
The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps
The DS26524 jitter attenuator is complaint with jitter transfer curve for sinusoidal jitter input.
ITU-T G.772
This specification provides the method for using receiver for transceiver 0 as a monitor for the remaining seven
transmitter/receiver combinations.
ITU-T G.775
An LOS detection criterion is defined.
ITU-T G.823 The control of jitter and wander within digital networks that are based on 2.048kbps hierarchy.
G.823 Provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and
100kHz.
ETS 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications.
The jitter transfer characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.
(ITU-T) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
(ITU-T) “Characteristics of Primary PCM Multiplex Equipment Operating at 2048kbps”
(ITU-T) Characteristics of a Synchronous Digital Multiplex Equipment Operating at 2048kbps”
(ITU-T) “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
(ITU-T) “The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy”
(ITU-T) “Primary Rate User-Network Interface—Layer 1 Specification”
(ITU-T) “Error Performance Measuring Equipment Operating at the Primary Rate and Above”
(ITU-T) “In-Service Code Violation Monitors for Digital Systems”
(ETS) “Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface (UNI); Part 1/Layer 1
Specification”
(ETS) “Transmission and Multiplexing; Physical/Electrical Characteristics of Hierarchical Digital Interfaces for
Equipment Using the 2048kbps-Based Plesiochronous or Synchronous Digital Hierarchies”
(ETS) “Integrated Services Digital Network (ISDN); Access Digital Section for ISDN Primary Rate”
(ETS) “Integrated Services Digital Network (ISDN); Attachment Requirements for Terminal Equipment to Connect
to an ISDN Using ISDN Primary Rate Access”
(ETS) “Business Telecommunications (BT); Open Network Provision (ONP) Technical Requirements; 2048kbps
Digital Unstructured Leased Lines (D2048U) Attachment Requirements for Terminal Equipment Interface”
(ETS) “Business Telecommunications (BTC); 2048kbps Digital Structured Leased Lines (D2048S); Attachment
Requirements for Terminal Equipment Interface”
(ITU-T) “Synchronous Frame Structures Used at 1544, 6312, 2048, 8488, and 44736kbps Hierarchical Levels”
(ITU-T) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures
Defined in Recommendation G.704”
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DS26524 Quad T1/E1/J1 Transceiver
5. ACRONYMS AND GLOSSARY
This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1
frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by
channel 1. For T1 and E1, each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is
transmitted first. Bit 8, the LSB, is transmitted last.
Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
Table 5-1. Time Slot Numbering Schemes
TS
Channel
Phone
Channel
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 of 273
6. BLOCK DIAGRAMS
A
Figure 6-1. Block Diagram
DS26524
DS26524 Quad T1/E1/J1 Transceiver
RTIP
RRING
TTIP
TRING
X4
LIU #4
LIU #3
LIU #2
LINE
INTERFACE
UNIT
MICRO PROCESSOR
INTERFACE
CONTROLLER
PORT
FRAMER #4
FRAMER #3
FRAMER #2
T1/E1 FRAMER
HDLC
BERT
JTAG PORT
TEST
PORT
INTERFACE #4
INTERFACE #3
INTERFACE #2
BACKPLANE
INTERFACE
ELASTIC
STORES
CLOCK
GENERATION
CLOCK
ADAPTER
RECEIVE
BACKPLANE
SIGNALS
TRANSMIT
BACKPLANE
SIGNALS
HARDWARE
LARM
INDICATORS
X4
17 of 273
Figure 6-2. Detailed Block Diagram
JITTER ATTENUATOR
ENABLE
C
C
A
A[
]
[
]
C
R
/
W
/
I
J
R
g
g
(
)
DS26524 Quad T1/E1/J1 Transceiver
TTIPn
TRINGn
RTIPn
RRINGn
TRANSCEIVER #1 of 4:
TRANSMIT
LB
TRANSMIT
LIU
Waveform
Shaper/Line
Driver
RECEIVE
LIU
Clock/Data
Recovery
DS26524
MICROPROCESSOR
INTERFACE
Tx
BERT
Tx FRAMER:
B8ZS/
HDB3
Encode
LLB
FLB
RLB
Rx FRAMER:
B8ZS/
HDB3
Decode
Rx
BERT
JTAG
PORT
RESET
BLOCK
Elastic
Store
Elastic
Store
Tx
HDLC
Rx
HDLC
System IF
PLB
System IF
PRESCALER
PLL
BA
KPLANE INTERFA
E
Tx Signaling/
Channel Blockin
TCLKn
TSERn
TSYNCn
TSSYNCIO
TSYSCLK
RSYSCLK
RSYNCn
RSERn
RCLKn
Rx Signaling/
Channel Blockin
MCLK
TSSYNCIO
Output Mode
BPCLK
REFCLK
NTB
BTS
RB
RWB
DB
DSB
SB
D
7:0
12:0
TRST
JTCLK
JTMS
JTDI
JTDO
ESETB
BACKPLANE
CLOCK
GENERATOR
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DS26524 Quad T1/E1/J1 Transceiver
7. PIN DESCRIPTIONS
7.1 Pin Functional Description
Table 7-1. Detailed Pin Descriptions
NAME PIN TYPE FUNCTION
ANALOG TRANSMIT
TTIP1 A1, A2
TTIP2 H1, H2
TTIP3 J1 J2
TTIP4 T1, T2
TRING1 A3, B3
TRING2 G3, H3
TRING3 J3, K3
TRING4 R3, T3
Impedance
Impedance
Analog
Output,
High
Analog
Output,
High
Transmit Bipolar Tip for Transceiver 1 to 4. These pins are differential line
driver tip outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω , E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar tip (e.g., pins A1 and A2 for
TTIP1) should be tied together.
Transmit Bipolar Ring for Transceiver 1 to 4. These pins are differential line
driver ring outputs. These pins can be high impedance if:
If TXENABLE is low, the TTIP/TRING will be high impedance. Note that if
TXENABLE is low, the register settings for control of the TTIP/TRING are ignored
and output is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal matched
impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω. The user has the option
of turning off internal termination.
Note: The two pins shown for each transmit bipolar ring (e.g., pins A3 and B3 for
TRING1) should be tied together.
TXENABLE L13 I
RTIP1 C1
RTIP2 F1
RTIP3 L1
RTIP4 P1
RRING1 C2
RRING2 F2
RRING3 L2
RRING4 P2
TSER1 F6
TSER2 E7
TSER3 R4
TSER4 N7
Analog
Input
Analog
Input
I
Transmit Enable. If this pin is pulled low, all transmitter outputs (TTIP and
TRING) are high impedance. The register settings for tri-state control of
TTIP/TRING are ignored if TXENABLE is low. If TXENABLE is high, the particular
driver can be tri-stated by the register settings.
ANALOG RECEIVE
Receive Bipolar Tip for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR
Receive Bipolar Ring for Transceiver 1 to 4. The differential inputs of RTIPn and
RRINGn can provide internal matched impedance for E1 75Ω, E1 120Ω, T1 100Ω,
or J1 110Ω. The user has the option of turning off internal termination via the LIU
Receive Impedance and Sensitivity Monitor register (LRISMR
TRANSMIT FRAMER
Transmit NRZ Serial Data. These pins are sampled on the falling edge of TCLK
when the transmit-side elastic store is disabled. These pins are sampled on the
falling edge of TSYSCLK when the transmit-side elastic store is enabled.
In IBO mode, data for multiple framers can be used in high-speed multiplexed
scheme. This is described in Section 8.8.2
combination of framer data for each of the streams.
TSYSCLK is used as a reference when IBO is invoked.
. The table there presents the
).
).
19 of 273
DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
TCLK1 C5
TCLK2 D7
TCLK3 P5
I
TCLK4 L8
TSYSCLK P13 I
TSYNC1 B4
TSYNC2 F7
TSYNC3 M6
TSYNC4 M7
TSSYNCIO N13 I/O
I/O
Transmit Clock. A 1.544MHz or a 2.048MHz primary clock. Used to clock data
through the transmit side of the transceiver. TSER data is sampled on the falling
edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled
or IBO is not used.
When the elastic store is enabled, TCLKn is used as the internal transmit clock for
the framer side or the elastic store, including the transmit framer and LIU. With the
elastic store enabled, TCLKn can be either synchronous or asynchronous to
TSYSCLKn, which either prevents or allows for slips. In addition, when IBO mode
is enabled, TCLKn must be synchronous to TSYSCLKn, which prevents slips in the
elastic store.
Note: This clock must be provided for proper device operation. The only exception
is when the TCR3 register is configured to source TCLK internally from RCLK.
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz clock. Only used when the transmit-side elastic store function is
enabled. Should be tied low in applications that do not use the transmit-side elastic
store. This is a common clock that is used for the transmitters. The clock can be
4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
Transmit Synchronization. A pulse at these pins establishes either frame or
multiframe boundaries for the transmit side. These signals can also be
programmed to output either a frame or multiframe pulse. If these pins are set to
output pulses at frame boundaries, they can also be set to output double-wide
pulses at signaling frames in T1 mode. The operation of these signals is
synchronous with TCLK.
Transmit System Synchronization In. Only used when the transmit-side elastic
store is enabled. A pulse at this pin establishes either frame or multiframe
boundaries for the transmit side. Note that if the elastic store is enabled, frame or
multiframe boundary will be established for all four transmitters. Should be tied low
in applications that do not use the transmit-side elastic store. The operation of this
signal is synchronous with TSYSCLK.
Transmit System Synchronization Out. If configured as an output, an 8kHz
pulse synchronous to the BPCLK will be generated. This pulse in combination with
BPCLK can be used as an IBO master. The BPCLK can be sourced to RSYSCLK,
TSYSCLK, and TSSYNCIO as a source to RSYNC, and TSSYNCIO of DS26524
or RSYNC and TSSYNC of other Dallas Semiconductor parts.
TSIG1 D5
TSIG2 A6
TSIG3 T4
TSIG4 R6
TCHBLK/
CLK1
TCHBLK/
CLK2
TCHBLK/
CLK3
TCHBLK/
CLK4
A5
C7
L7
P7
O
Transmit Signaling. When enabled, this input samples signaling bits for insertion
into outgoing PCM data stream. Sampled on the falling edge of TCLK when the
I
transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK
when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams
can run up to 16.384MHz.
Transmit Channel Block/Transmit Channel Block Clock. A dual function pin.
TCHBLK is a user-programmable output that can be forced high or low during any
of the channels. It is synchronous with TCLK when the transmit-side elastic store is
disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is
enabled. It is useful for blocking clocks to a serial UART or LAPD controller in
applications where not all channels are used such as Fractional T1, Fractional E1,
384kbps (H0), 768kbps, or ISDN-PRI. Also useful for locating individual channels
in drop-and-insert applications, for external per-channel loopback, and for perchannel conditioning.
TCHCLK. TCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, TCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, TCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, TCHCLKn is synchronous with
TCLKn when the receive-side elastic store is disabled or it is synchronous with
TSYSCLKn when the receive-side elastic store is enabled. The mode of TCHCLKn
is determined by the TGCLKEN bit in the TESCR register.
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
RECEIVE FRAMER
RSER1 E5
RSER2 D6
RSER3 N4
RSER4 N6
RCLK1 F4
RCLK2 G4
RCLK3 L4
RCLK4 M4
RSYSCLK L12 I
RSYNC1 A4
RSYNC2 B6
RSYNC3 N5
RSYNC4 T6
RMSYNC1/
RFSYNC1
RMSYNC2/
RFSYNC2
RMSYNC3/
RFSYNC3
RMSYNC4/
RFSYNC4
RSIG1 D4
RSIG2 E6
RSIG3 M5
RSIG4 R5
AL/
RSIGF/
FLOS1
AL/
RSIGF/
FLOS2
AL/
RSIGF/
FLOS3
AL/
RSIGF/
FLOS4
RLF/
LTC1
RLF/
LTC2
RLF/
LTC3
RLF/
LTC4
C4
C6
P4
P6
C3
F3
L3
P3
D3
E3
M3
N3
O
O
I/O
O
O
O
O
Received Serial Data. Received NRZ serial data. Updated on rising edges of
RCLK when the receive-side elastic store is disabled. Updated on the rising edges
of RSYSCLK when the receive-side elastic store is enabled.
When IBO mode is used, the RSER pins can output data for multiple framers. The
RSER data is synchronous to RSYSCLK. This is described in Section 8.8.2
Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock
data through the receive-side framer. This clock is recovered from the signal at
RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used
to output RSER when the elastic store is not enabled or IBO is not used. When the
elastic store is enabled or IBO is used, the RSER is clocked by RSYSCLK.
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or
16.384MHz receive backplane clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receiveside elastic store. Multiple of 2.048MHz is expected when the IBO mode is used.
Note that RSYSCLK is used for all four transceivers.
Receive Synchronization. If the receive-side elastic store is enabled, then this
signal is used to input a frame or multiframe boundary pulse. If set to output frame
boundaries, then RSYNC can be programmed to output double-wide pulses on
signaling frames in T1 mode. In E1 mode, RSYNC out can be used to indicate
CAS and CRC-4 multiframe. The DS26524 can accept H.100-compatible
synchronization signal. The default direction of this pin at power-up is input, as
determined by the RSIO control bit in the RIOCR
Receive Multiframe/Frame Synchronization. A dual function pin to indicate
frame or multiframe synchronization. RFSYNC is an extracted 8kHz pulse, one
RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one
RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled),
that identifies multiframe boundaries. When the receive elastic store is enabled,
the RMSYNC signal indicates the multiframe sync on the system (backplane) side
of the elastic store. In E1 mode, this pin can indicate either the CRC-4 or CAS
multiframe as determined by the RSMS2 control bit in the Receive I/O
Configuration register (RIOCR
Receive Signaling. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.
Analog Loss/Receive-Signaling Freeze/Framer LOS. Analog LOS reflects the
LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS
detection by the corresponding framer; the same pins can reflect receive-signaling
freeze indications. This selection can be made by settings in the Global
Transceiver Clock Control register (GTCCR
If framer LOS is selected, this pin can be programmed to toggle high when the
framer detects an LOS condition, or when the signaling data is frozen via either
automatic or manual intervention. The indication is used to alert downstream
equipment of the condition.
Receive Loss of Frame/Loss of Transmit Clock. This pin can be programmed to
either toggle high when the synchronizer is searching for the frame and multiframe,
or to toggle high if the TCLK pin has not been toggled for approximately three clock
periods.
.1).
.2 register.
).
.
21 of 273
DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
RCHBLK/
CLK1
RCHBLK/
CLK2
RCHBLK/
CLK3
RCHBLK/
CLK4
BPCLK E8 O
A12 C8
A11 A8
A10 B8
A9 F8
A8 B9
A7 A9
A6 C9
A5 D9
A4 E9
A3 F9
A2 B10
A1 A10
A0 C10
D7 T9
D6 N9
D5 M9
D4 R8
D3 T8
D2 P8
D1 L9
D0 N8
CSB
E4
B5
L6
T5
T7 I
O
I
I
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a userprogrammable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in dropand-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLKn is a dual function pin that can output either a gapped clock or
a channel clock. In gapped clock mode, RCHCLKn is a N x 64kHz fractional clock
that is software programmable for 0 to 24 channels and the F-bit (T1) or 0 to 32
channels (E1). In channel clock mode, RCHCLKn is a 192kHz (T1) or 256kHz (E1)
clock that pulses high during the LSB of each channel. It is useful for parallel-toserial conversion of channel data. In either mode, RCHCLK is synchronous with
RCLKn when the receive-side elastic store is disabled or it is synchronous with
RSYSCLKn when the receive-side elastic store is enabled. The mode of
RCHCLKn is determined by the RGCLKEN bit in the RESCR register.
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from external
source or T1J1E1 recovered clock or the MCLK oscillator.
MICROPROCESSOR INTERFACE
Address [12:0]. This bus selects a specific register in the DS26524 during
read/write access. A12 is the MSB and A0 is the LSB.
Data [7:0]. This 8-bit, bidirectional data bus is used for read/write access of the
DS26524 information and control registers. D7 is the MSB and D0 is the LSB.
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
RDB/
DSB
WRB/
RWB
M8 I
R7 I
Read-Data Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies
read access to one of the DS26524 registers. The DS26524 drives the data bus
with the contents of the addressed register while RDB and CSB are low.
Write-Read Bar/Read-Write Bar. This active-low signal along with CSB qualifies
write access to one of the DS26524 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low.
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
Interrupt Bar. This active-low, open-drain output is asserted when an unmasked
INTB
BTS M13 I
MCLK B7 I
RESETB
REFCLKIO A7 I/O
R9 U
J12 I
interrupt event is detected. INTB will be deasserted when all interrupts have been
acknowledged and serviced. Extensive mask bits are provided at the global lev el,
framer, LIU, and BERT level.
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins.
SYSTEM INTERFACE
Master Clock. This is an independent free-running clock whose input can be a
multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is
available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be
internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to
2.048MHz. Note that TCLK must be 2.048MHz for E1 and 1.544MHz for T1/J1
operation. See Table 9-12
Reset Bar. Active-low reset. This input forces the complete DS26524 reset. This
includes reset of the registers, framers, and LIUs.
Reference Clock Input/Output
Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate
the backplane clock. This allows for the users to synchronize the system
backplane with the reference clock. The other options for the backplane clock
reference are LIU-received clocks or MCLK.
Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference
clock. This allows for multiple DS26524s to share the same reference for
generation of the backplane clock. Hence, in a system consisting of multiple
DS26524s, one can be a master and others a slave using the same reference
clock.
TEST
.
Digital Enable. When this pin and JTRST are pulled low, all digital I/O pins are
DIGIOEN D8 I, Pullup
JTRST
JTMS K4 I, Pullup
JTCLK F5 I
JTDI H4 I, Pullup
JTDO J4
L5 I, Pullup
O, High
impedance
placed in a high-impedance state. If this pin is high the digital I/O pins operate
normally. This pin must be connected to V
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up, JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores
normal device operation. JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10kΩ pullup resistor.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10kΩ pullup resistor.
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
for normal operation.
DD
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
POWER SUPPLIES
ATVDD1 B1
ATVDD2 G1
ATVDD3 K1
ATVDD4 R1
ATVDD5 R16
—
ATVDD6 K16
ATVDD7 G16
ATVDD8 B16
ATVSS1 B2
ATVSS2 G2
ATVSS3 K2
ATVSS4 R2
ATVSS5 R15
—
ATVSS6 K15
ATVSS7 G15
ATVSS8 B15
ARVDD1 D1
ARVDD2 E1
ARVDD3 M1
ARVDD4 N1
ARVDD5 N16
—
ARVDD6 M16
ARVDD7 E16
ARVDD8 D16
ARVSS1 D2
ARVSS2 E2
ARVSS3 M2
ARVSS4 N2
ARVSS5 N15
—
ARVSS6 M15
ARVSS7 E15
ARVSS8 D15
ACVDD H7 —
3.3V Analog Transmit Power Supply. These V
LIU sections of the DS26524.
Analog Transmit V
. These pins are used for transmit analog VSS.
SS
3.3V Analog Receive Power Supply. These V
LIU sections of the DS26524.
Analog Receive V
Analog Clock Conversion V
. These pins are used for analog VSS for the receivers.
SS
. This VDD input is used for the clock conversion
DD
unit of the DS26524.
inputs are used for the transmit
DD
inputs are used for the receive
DD
ACVSS J7 —
DVDD
DVDDIO
G5–G12,
H8, H9
H5, H6,
H10, H11
—
—
Analog Clock V
3.3V Power Supply for Digital Framers
3.3V Power Supply for I/Os
. This pin is used for clock converter analog VSS.
SS
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DS26524 Quad T1/E1/J1 Transceiver
NAME PIN TYPE FUNCTION
A11, A13,
B11, B13,
C11, C13,
D12, D13,
E10, F10,
H12, H13,
DVSS
DVSSIO
N.C.
J8, J9,
K5–K12,
L10, L11,
M10, N10,
N11, P12,
R10, R12,
T10, T12
J5, J6,
J10, J11
A12, A14,
A15, A16,
B12, B14,
C12, C14,
C15, C16,
D10, D11,
D14,
E11–E14,
F11–F16,
G13, G14,
H14, H15,
H16,
J13–J16,
K13, K14,
L14, L15,
L16, M11,
M12, M14
N12, N14,
P9, P10,
P11, P14,
P15, P16,
R11, R13,
R14, T11,
T13–T16
-—
—
—
Digital Ground for the Framers
Digital Ground for the I/Os
No Connection. These pins must not be connected to V
or VSS.
DD
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DS26524 Quad T1/E1/J1 Transceiver
8. FUNCTIONAL DESCRIPTION
8.1 Processor Interface
Microprocessor control of the DS26524 is accomplished through the 28 hardware pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select
(BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 12-1
When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 12-3 and Figure 12-4. The
address space is mapped through the use of 13 address lines, A[12:0]. Multiplexed mode is not supported on the
processor interface.
The chip-select bar (CSB) pin must be brought to a logic-low level to gain read and write access to the
microprocessor port. With Intel timing selected, the read-data bar (RDB) and write-read bar (WRB) pins are used to
indicate read and write operations and latch data through the interface. With Motorola timing selected, the readwrite bar (RWB) pin is used to indicate read and write operations while the data-strobe bar (DSB) pin is used to
latch data through the interface.
The interrupt output pin (INTB) is an open-drain output that asserts a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The device has
a bulk write mode that allows a microprocessor to write all four internal transceivers with each bus write cycle. By
setting the BWE bit (GTCR1
The BWE bit must be cleared before normal write operation is resumed. This function is useful for device
initialization. The register map is shown in Figure 9-1
.2), each port write cycle will write to all four framers, LIUs, or BERTs at the same time.
.
and Figure 12-2.
8.2 Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
8.2.1 Backplane Clock Generation
The DS26524 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see
Figure 8-1). The Global Transceiver Clock Control register (GTCCR) is used to control the backplane clock
generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can output MCLKT1
or MCLKE1 as shown in Figure 8-1
This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26524 and other IBO-equipped devices
as an IBO bus master. Hence, the DS26524 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock.
This can be used by the link layer devices and frames connected to the IBO bus.
.
26 of 273
Figure 8-1. Backplane Clock Generation
BPREFSEL3:0
RCLK1
RCLK2
RCLK3
RCLK4
Pre
MCLK
Scaler
PLL
MCLKT1
MCLKE1
DS26524 Quad T1/E1/J1 Transceiver
BPCLK1:0
BFREQSEL
Multiplexor
Clock
CLK
GEN
REFCLKIO
TSSYNCIO
BPCLK
REFCLKIO
The reference clock for the backplane clock generator can be as follows:
• External Master Clock. A prescaler can be used to generate T1 or E1 frequency.
• External Reference Clock REFCLKIO. This allows for multiple DS26524s to use the backplane clock from
a common reference.
• Internal LIU recovered RCLKs 1 to 4.
• The clock generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
for the IBO.
• If MCLK or RCLK are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
clock for external use.
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DS26524 Quad T1/E1/J1 Transceiver
8.3 Resets and Power-Down Modes
A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs,
and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be
reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing
reserved locations to 00h.
The DS26524 has several features included to reduce power consumption. The LIU transmitters can be powered
down by setting the TPDE bit in the LIU Maintenance Control register (LMCR
transmit LIU results in a high-impedance state for the corresponding TTIP and TRING pins and reduced operating
current. The RPDE bit in the LMCR
register can be used to power down the LIU receiver.
). Note that powering down the
The TE (transmit enable) bit in the LMCR
them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for
equipment protection-switching applications.
register can be used to disable the TTIP and TRING outputs and place
Table 8-1. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset
Hardware JTAG Reset
Global Framer and BERT Reset GFSRR.0:3
Global LIU Reset GLSRR.0:3 Writing to these bits resets the associated LIU.
Framer Receive Reset RMMR.1 Writing to this bit resets the receive framer.
Framer Transmit Reset TMMR.1 Writing to this bit resets the transmit framer.
HDLC Receive Reset RHC.6 Writing to this bit resets the receive HDLC controller.
HDLC Transmit Reset THC1.5 Writing to this bit resets the transmit HDLC controller.
Elastic Store Receive Reset RESCR.2 Writing to this bit resets the receive elastic store.
Elastic Store Transmit Reset TESCR.2 Writing to this bit resets the transmit elastic store.
Bit Oriented Code Receive Reset T1RBOCC.7 Writing to this bit resets the receive BOC controller.
RESETB
JTRST
Transition to a logic 0 level resets the DS26524.
Resets the JTAG test port.
Writing to these bits resets the framer and BERT (transmit
and receive).
Loop Code Integration Reset
Spare Code Integration Reset T1RSCD1
T1RDNCD1
T1RUPCD1
,
Writing to these registers resets the programmable in-band
code integration period.
Writing to this register resets the programmable in-band
code integration period.
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DS26524 Quad T1/E1/J1 Transceiver
8.4 Initialization and Configuration
8.4.1 Example Device Initialization Sequence
STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software
reset bits outlined in Section 8.3
. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the device ID in the Device Identification register (IDR
STEP 3: Write the GTCCR
this write with at least a 300ns delay to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register
locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR
registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using software transmit
signaling in E1 mode, program the E1TAF
Control registers (TCR1
T1RCR2/E1RCR2, RCR3). Configure other framer features as appropriate.
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE bit to turn on the
TTIP and TRING outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
STEP 8: Set the INIT_DONE bit in the TMMR
register to correctly configure the system clocks. If supplying a 1.544MHz MCLK, follow
and E1TNAF registers as required. Configure the framer Transmit
:TCR4). Configure the Framer Receive Control registers (RCR1 (T1)/RCR1 (E1),
and RMMR registers for each framer.
).
and RMMR
register.
8.5 Global Resources
All four framers share a common microprocessor port. All ports share a common MCLK, and there is a common
software-configurable BPCLK output. A set of global registers are located at 0F0h–0FFh and include global resets,
global interrupt status, interrupt masking, clock configuration, and the device ID registers. See the global register
definitions in Table 9-2
. A common JTAG controller is used.
8.6 Per-Port Resources
Each port has an associated framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller. Each of the
per-port functions has its own register space.
8.7 Device Interrupts
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR
interrupt(s). The host can then read the specific transceiver’s interrupt information registers (TIIR
latched status registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source,
the host will then read the transmit-latched status or the receive-latched status registers for the source of the
interrupt. All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been
serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status
register. The host must clear all latched status bits by writing a 1 to the bit location of the interrupt condition that
has been serviced. Latched status bits that have been masked by the interrupt mask registers are masked from the
interrupt information registers. The interrupt mask register bits prevent individual latched status conditions from
generating an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing
interrupts, the user should XOR the latched status with the associated interrupt mask in order to exclude bits for
which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll
the latched status bits for noninterrupt conditions, while using only one set of registers.
, GLISR, and GBISR to identify which of the four transceivers is causing the
, RIIR) and the
29 of 273
Figure 8-2. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear 7
Receive Alarm Condition Clear 6
Receive Loss of Signal Clear 5
Receive Loss of Frame Clear 4
Receive Remote Alarm Indication 3
Receive Alarm Condition 2
Receive Loss of Signal 1
Receive Loss of Frame 0
Receive Signal All Ones 3
Receive Signal All Zeros 2
Receive CRC-4 Multiframe 1
Receive Align Frame 0
Loss of Receive Clock Clear/Loss of Receive Clock Clear 7
Spare Code Detected Condition Clear 6
Loop-Down Code Clear/V52 Link Clear 5
Loop-Up Code Clear/Receive Distant MF Alarm Clear 4
Loss of Receive Clock/Loss of Receive Clock 3
Spare Code Detect 2
Loop-Down Detect/V52 Link Detect 1
Loop-Up Detect/Receive Distant MF Alarm Detect 0
Receive Elastic Store Full 7
Receive Elastic Store Empty 6
Receive Elastic Store Slip 5
Receive Signaling Change of State (Enable in RSCSE1:4) 3
One-Second Timer 2
Timer 1
Receive Multiframe 0
Receive FIFO Overrun 5
Receive HDLC Opening Byte 4
Receive Packet End 3
Receive Packet Start 2
Receive Packet High Watermark 1
Receive FIFO Not Empty 0
Receive RAI-CI 5
Receive AIS-CI 4
Receive SLC-96 Alignment 3
Receive FDL Register Full 2
Receive BOC Clear 1
Receive BOC 0
Transmit Elastic Store Full 7
Transmit Elastic Store Empty 6
Transmit Elastic Store Slip 5
Transmit SLC-96 Multiframe 4
Transmit Pulse Density Violation/Transmit Align Frame 3
Transmit Multiframe 2
Loss of Transmit Clock Clear 1
Loss of Transmit Clock 0
Transmit FDL Register Empty 4
Transmit FIFO Underrun 3
Transmit Message End 2
Transmit FIFO Below Low Watermark 1
Transmit FIFO Not Full Set 0
— —
— —
Loss of Frame 1
Loss of Frame Synchronization 0
Jitter Attenuator Limit Trip Clear 7
Open-Circuit Detect Clear 6
Short-Circuit Detect Clear 5
Loss of Signal Detect Clear 4
Jitter Attenuator Limit Trip 3
Open-Circuit Detect 2
Short-Circuit Detect 1
Loss of Signal Detect 0
BERT Bit-Error Detected 6
BERT Bit Counter Overflow 5
BERT Error Counter Overflow 4
BERT Receive All Ones 3
BERT Receive All Zeros 2
BERT Receive Loss of Synchronization 1
BERT in Synchronization 0
RLS1
RLS2
RLS3
RLS4
RLS5
RLS7
TLS1
TLS2
TLS3
LLSR
BLSR
0
1
2
RIIR
3
4
5
2
TIIR
1
DS26524 Quad T1/E1/J1 Transceiver
DRAWING LEGEND:
INTERRUPT
STATUS
REGISTERS
INTERRUPT MASK
REGISTERS
6
5
4
3
2
FRAMERS 2–4 LIUs 2–4 BERTs 2–4
1
0
REGISTER NAME
REGISTER NAME
GFIMR
GFISR1
GLIMR
GLISR1
GBISR1
GBIMR
GTCR1.0
INTERRUPT PIN
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DS26524 Quad T1/E1/J1 Transceiver
8.8 System Backplane Interface
The DS26524 provides a versatile backplane interface that can be configured to the following:
• Transmit and receive two-frame elastic stores
• Mapping of T1 channels into a 2.048MHz backplane
• IBO mode for multiple framers to share the backplane signals
• Transmit and receive channel-blocking capability
• Fractional T1/E1/J1 support
• Hardware-based (through the backplane interface) or processor-based signaling
• Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz
• Backplane clock and frame pulse (TSSYNCIOn) generator
8.8.1 Elastic Stores
The DS26524 contains dual two-frame elastic stores for each framer: one for the receive direction and one for the
transmit direction. Both elastic stores are fully independent. The transmit- and receive-side elastic stores can be
enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a
1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic
store. Since the DS26524 has a common TSYSCLK and RSYSCLK for all four ports, the backplane signals in each
direction must be synchronous for all ports on which the elastic stores are enabled. However, the transmit and
receive signals are not required to be synchronous to each other. The TIOCR and RIOCR settings should be
identical for all ports on which the elastic stores are enabled.
The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26524 is in
the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the
elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Second, the elastic stores can be used
to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not
locked) backplane clock, which can be 1.544MHz or 2.048MHz. In this mode, the elastic stores manage the rate
difference and perform controlled slips, deleting or repeating frames of data to manage the difference between the
network and the backplane.
If the elastic store is enabled while in E1 mode, then either CAS or CRC-4 multiframe boundaries are indicated via
the RMSYNC output as controlled by the RSMS2 control bit (RIOCR
clock to the RSYSCLK pin, then the Receive Blank Channel Select registers (RBCS1:RBCS4) registers determine
which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the
RSER data and set to 1. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 to
32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip
occurs. If the buffer empties, a full frame of data is repeated at RSER and the RLS4
If the buffer fills, a full frame of data is deleted and the RLS4
The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the
Interleave Bus Option (IBO), which is discussed in Section 8.8.2
elastic stores.
.5 and RLS4.7 bits are set to 1.
.1). If the user selects to apply a 1.544MHz
.5 and RLS4.6 bits are set to 1.
. Table 8-2 shows the registers related to the
Table 8-2. Registers Related to the Elastic Store
REGISTER
Receive I/O Configuration Register (RIOCR) 084h Sync and clock selection for the receiver.
Receive Elastic Store Control Register
(RESCR
Receive Latched Status Register 4 (RLS4) 093h Receive elastic store empty full status.
Receive Interrupt Mask Register 4 (RIM4) 0A3h Receive interrupt mask for elastic store.
Transmit Elastic Store Control Register
(TESCR
Transmit Latched Status Register 1 (TLS1) 190h Transmit elastic store latched status.
Transmit Interrupt Mask Register 1 (TIM1) 1A0h Transmit elastic store interrupt mask.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h), where n = 2 to 4 for Framers 2 to 4.
)
)
FRAMER
ADDRESSES
085h Receive elastic store control.
185h
31 of 273
FUNCTION
Transmit elastic control such as minimum
mode.
DS26524 Quad T1/E1/J1 Transceiver
8.8.1.1 Elastic Stores Initialization
There are two elastic store initializations that can be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK,
respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align
bit is used to “center” the read/write pointers to the extent possible.
Table 8-3. Elastic Store Delay After Initialization
INITIALIZATION REGISTER BIT DELAY
Receive Elastic Store Reset RESCR.2 N bytes < Delay < 1 Frame + N bytes
Transmit Elastic Store Reset TESCR.2 N bytes < Delay < 1 Frame + N bytes
Receive Elastic Store Align RESCR.3 1/2 Frame < Delay < 1 1/2 Frames
Transmit Elastic Store Align TESCR.3 1/2 Frame < Delay < 1 1/2 Frames
N = 9 for RSZS = 0; N = 2 for RSZS = 1.
8.8.1.2 Minimum Delay Mode
Elastic store minimum-delay mode can be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side).
RESCR
maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that
interface to a 2.048MHz bus. Certain restrictions apply when minimum-delay mode is used. In addition to the
restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in
minimum-delay mode and TSYNC must be configured as an output when transmit minimum-delay mode is
enabled. In this mode the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a
typical application, RSYSCLK and TSYSCLK are locked to RCLK and RSYNC (frame-output mode) is connected to
TSSYNCIO (frame-input mode). The slip zone select bit (RSZS at RESCR
contention logic in the framer is disabled (since slips cannot occur). On power-up, after the RSYSCLK and
TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR
should be toggled from a 0 to 1 to ensure proper operation
.1 enables the receive elastic store minimum-delay mode. When enabled, the elastic stores are forced to a
.4) must be set to 1. All the slip
.2)
8.8.1.3 Additional Receive Elastic Store Information
If the receive-side elastic store is enabled, the user must provide either a 1.544MHz or 2.048MHz clock at the
RSYSCLK pin. See Section 8.8.2
for higher rate system-clock applications. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe
boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync
input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the
elastic store. The framer always indicates frame boundaries on the network side of the elastic store via the
RFSYNC output, whether the elastic store is enabled or not. Multiframe boundaries arel always indicated via the
RMSYNC output. If the elastic store is enabled, RMSYNC outputs the multiframe boundary on the backplane side
of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the
RMSYNC signal outputs the T1 multiframe boundaries as delayed through the elastic store. When the device is
receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal outputs the E1 multiframe
boundaries as delayed through the elastic store.
If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, the user can use the Receive Blank Channel
Select registers (RBCS1
:RBCS4) to determine which channels will have the data output at RSER forced to all
ones.
32 of 273
8.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
DS26524 Quad T1/E1/J1 Transceiver
Setting the TSCLKM bit (TIOCR
.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on TSER will be mapped into
the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1
:TBCS4). A logic 1 in the
associated bit location forces the transmit elastic store to ignore backplane data for that channel. Typically the user
will want to program eight channels to be ignored. The default (power-up) configuration ignores channels 25 to 32,
so that the first 24 backplane channels are mapped into the T1 transmit data stream.
For example, if the user desired to transmit data from the 2.048MHz backplane channels 2 to 16 and 18 to 26, the
TBCS1
:TBCS4 registers should be programmed as follows:
TBCS1
TBCS2
= 01h :: ignore backplane channel 1 ::
= 00h
TBCS3 = 01h :: ignore backplane channel 17 ::
TBCS4 = FCh :: ignore backplane channels 27 to 32 ::
8.8.1.5 Mapping T1 Channels onto a 2.048MHz Backplane
Setting the RSCLKM bit (RIOCR
.4) enables the receive elastic store to operate with a 2.048MHz backplane (32
time slots/frame). In this mode the user can choose which of the backplane channels on RSER receive the T1 data
by programming the Receive Blank Channel Select registers (RBCS1
:RBCS4). A logic 1 in the associated bit
location forces RSER high for that backplane channel. Typically the user will want to program eight channels to be
blanked. The default (power-up) configuration blanks channels 25 to 32, so that the 24 T1 channels are mapped
into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting
RBCS1
.0 = 1, the F-bit will be passed into the MSB of TS0 on RSER.
For example, if:
RBCS1
= 01h
RBCS2 = 00h
RBCS3
= 01h
RBCS4 = FCh
Then on RSER:
Channel 1 (MSB) = F-bit
Channel 1 (bits 1 to 7) = all ones
Channels 2 to 16 = T1 channels 1 to 15
Channel 17 = all ones
Channels 18 to 26 = T1 channels 16 to 24
Channels 27 to 32 = all ones
Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should
be set to 0. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29), the RSZS bit can be set to 1,
which can provide a lower occurrence of slips in certain applications.
If the two-frame elastic buffer either fills or empties, a controlled slip occurs. If the buffer empties, a full frame of
data is repeated at RSER and the RLS4
deleted and the RLS4
.5 and RLS4.7 bits are set to 1.
.5 and RLS4.6 bits are set to 1. If the buffer fills, a full frame of data is
8.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
The user can use the TSCLKM bit in TIOCR
.4 to enable the transmit elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will have allones data inserted by programming the Transmit Blank Channel Select registers (TBCS1
:TBCS4). A logic 1 in the
associated bit location causes the elastic store to force all ones at the outgoing E1 data for that channel. Typically
the user will want to program eight channels to be blanked. The default (power-up) configuration blanks channels
25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane.
33 of 273
8.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
DS26524 Quad T1/E1/J1 Transceiver
The user can use the RSCLKM bit (RIOCR
.4) to enable the receive elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be
ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers
(RBCS1
:RBCS4). A logic 1 in the associated bit location causes the elastic store to ignore the incoming E1 data for
that channel. Typically the user will want to program eight channels to be ignored. The default (power-up)
configuration will ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the
1.544MHz backplane. In this mode the F-bit location at RSER is always set to 1.
For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS16 (channel 17), the RBCS1
:RBCS4
registers would be programmed as follows:
RBCS1
= 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4
= FCh
8.8.2 IBO Multiplexer
The Interleaved Bus Operation (IBO) multiplexer is used in conjunction with the IBO function located within each
framer/formatter block (controlled by the RIBOC
simplifies user interface by connecting bus signals internally. The IBO multiplexer eliminates the need for ganged
external wiring and tri-state output drivers on the RSER and RSIG pins. This option provides a more controlled,
cleaner, and lower power mode of operation.
Note that the channel block signals TCHBLK and RCHBLK are output at the rate of the of IBO selection. Hence, a
4.096MHz IBO would have the channel blocks (if programmed active at the rate of 4.096MHz). The particular
blocking channel would be active for a duration of the channel if programmed.
The DS26524 also supports the traditional mode of IBO operation by allowing complete access to individual
framers, and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This mode of
operation is enabled per framer in the associated RIBOC
disabled (IBOMS0 = 0 and IBOMS1 = 0).
and TIBOC registers). When enabled, the IBO multiplexer
and TIBOC registers, while leaving the IBO multiplexer is
Figure 8-3
, Figure 8-4, and Figure 8-5 show the equivalent internal circuit for each IBO mode. Table 8-4 describes
the pin function changes for each mode of the IBO multiplexer.
Table 8-4. Registers Related to the IBO Multiplexer
REGISTER
Global Transceiver Control Register 1
(GTCR1
)
Receive Interleave Bus Operation
Control Register (RIBOC)
Transmit Interleave Bus Operation
Control Register (TIBOC
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated by using the following: Framer n = (Framer 1
address + (n - 1) x 200h), where n = 2 to 4 for Framers 2 to 4.
)
FRAMER
ADDRESSES
0F0h
088h
188h
This is a global register for all four framers. It can be
used to specify ganged operation for the IBO.
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the receiver.
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the transmitter.
FUNCTION
34 of 273
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz
RSER
RSIG
Port # 1
Backplane
Interface
Port # 2
Backplane
Interface
Port # 3
Backplane
Interface
Port # 4
Backplane
Interface
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
DS26524 Quad T1/E1/J1 Transceiver
RSER1
RSIG1
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER3
RSIG3
RSYNC3
RSYSCLK
TSER3
TSIG3
TSSYNCIO
TSYSCLK
35 of 273
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz
DS26524 Quad T1/E1/J1 Transceiver
RSER1
DS26524 #1
Port # 1
Backplane
Interface
DS26524 #1
Port # 2
Backplane
Interface
DS26524 #1
Port # 3
Backplane
Interface
DS26524 #1
Port # 4
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSSYNC
TSYSCLK
TSER
TSIG
RSIG1
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
36 of 273
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz
RSER1*
DS26524 Quad T1/E1/J1 Transceiver
DS26524 #1
Port # 1
Backplane
Interface
DS26524 #1
Port # 2
Backplane
Interface
DS26524 #1
Port # 3
Backplane
Interface
DS26524 #1
Port # 4
Backplane
Interface
DS26524 #2
Port # 1
Backplane
Interface
DS26524 #2
Port # 2
Backplane
Interface
DS26524 #2
Port # 3
Backplane
Interface
DS26524 #2
Port # 4
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSSYNC
TSYSCLK
TSER
TSIG
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSIG1**
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
RSER1*
RSIG1**
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
37 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 8-5. RSER Output Pin Definitions
PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
RSER1
Receive Serial Data
for Port 1
Combined Receive
Serial Data for
Ports 1 and 2
Combined Receive
Serial Data for
Ports 1–4
Receive Serial Data
for Ports 1–4
RSER2
RSER3
RSER4
Receive Serial Data
for Port 2
Receive Serial Data
for Port 3
Receive Serial Data
for Port 4
Reserved Unused Unused
Combined Receive
Serial Data for Ports 3
and 4
Unused Unused Unused
Unused Unused
Table 8-6. RSIG Output Pin Definitions
PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
RSIG1
RSIG2
RSIG3
RSIG4
Receive Signaling
Data for Port 1
Receive Signaling
Data for Port 2
Receive Signaling
Data for Port 3
Receive Signaling
Data for Port 4
Combined Receive
Signaling Data for
Ports 1 and 2
Unused Unused Unused
Combined Receive
Signaling Data for
Ports 3 and 4
Unused Unused Unused
Combined Receive
Signaling Data for
Ports 1–4
Unused Unused
Receive Signaling
Data for Ports 1–4
38 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 8-7. TSER Input Pin Definitions
PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
TSER1
Transmit Serial Data
for Port 1
Combined Transmit
Serial Data for
Ports 1 and 2
Combined Transmit
Serial Data for Ports
1–4
Transmit Serial Data
for Ports 1–4
TSER2
TSER3
TSER4
Transmit Serial Data
for Port 2
Transmit Serial Data
for Port 3
Transmit Serial Data
for Port 4
Unused Unused Unused
Combined Transmit
Serial Data for
Ports 3 and 4
Unused Unused Unused
Unused Unused
Table 8-8. TSIG Input Pin Definitions
PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
TSIG1
TSIG2
TSIG3
TSIG4
Transmit Signaling
Data for Port 1
Transmit Signaling
Data for Port 2
Transmit Signaling
Data for Port 3
Transmit Signaling
Data for Port 4
Combined Transmit
Signaling Data for
Ports 1 and 2
Unused Unused Unused
Combined Transmit
Signaling Data for
Ports 3 and 4
Unused Unused Unused
Combined Transmit
Signaling Data for
Ports 1–4
Unused Unused
Transmit Signaling
Data for Ports 1–4
Table 8-9. RSYNC Input Pin Definitions
PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.384MHz IBO
RSYNC1
RSYNC2
RSYNC3
RSYNC4
Receive Frame Pulse
for Port 1
Receive Frame Pulse
for Port 2
Receive Frame Pulse
for Port 3
Receive Frame Pulse
for Port 4
Receive Frame Pulse
for Ports 1 and 2
Unused Unused Unused
Receive Frame Pulse
for Ports 3 and 4
Unused Unused Unused
39 of 273
Receive Frame Pulse
for Ports 1–4
Unused Unused
Receive Frame Pulse
for Ports 1–4
DS26524 Quad T1/E1/J1 Transceiver
1
2
K
3
yp)
8.8.3 H.100 (CT Bus) Compatibility
The registers used for controlling the H.100 backplane are RIOCR and TIOCR.
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(RIOCR
.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26524 to accept a CT bus-
compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.
The following rules apply to the H100EN control bit.
1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode)
only. The RSYNC output and other sync signals are not affected.
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz
IBO mode or 2.048MHz backplane operation.
4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for
the TSSYNCIO).
5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR
) and TSSYNCINV (TIOCR) must
be set high to invert the inbound sync signals.
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode
RSYNC
RSYNC
RSYSCL
RSER
NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.
NOTE 2: RSYNC INPUT MODE, H100EN = 1 AND RSYNCINV = 1.
NOTE 3: t
BC
BIT 8 BIT 1 BIT 2
t
BC
(BIT CELL TIME) = 122ns (t
. tBC = 244ns or 488ns ALSO ACCEPTABLE.
40 of 273
DS26524 Quad T1/E1/J1 Transceiver
2
3
yp)
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode
TSSYNCIO1
TSSYNCIO
TSYSCLK
TSER
BIT 8 BIT 1 BIT 2
t
BC
NOTE 1: TSSYNCIO IN NORMAL OPERATION.
NOTE 2: TSSYNCIO WITH H100EN = 1 and TSSYNCINV = 1.
NOTE 3: tBC (BIT CELL TIME) = 122ns (t
. tBC = 244ns OR 488ns ALSO ACCEPTABLE.
8.8.4 Receive and Transmit Channel Blocking Registers
The Receive Channel Blocking registers (RCBR1:RCBR4) and the Transmit Channel Blocking registers
(TCBR1
:TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-
programmable outputs that can be forced either high or low during individual channels. These outputs can be used
to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to 1,
the RCHBLK and TCHBLK pins are held high during the entire corresponding channel time. When used with a T1
(1.544MHz) backplane, only TCBR1
:TCBR2:TCBR3 are used. TCBR4 is included to support an E1 (2.048MHz)
backplane when the elastic store is configured for T1-to-E1 rate conversion. See Section 8.8.1.
8.8.5 Transmit Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled
via the Transmit Gapped-Clock Channel Select registers (TGCCS1
gapped clock mode with the TGCLKEN bit (TESCR
determined by TESCR
.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
.6). Both 56kbps and 64kbps channel formats are supported as
:TGCCS4). The transmit path is enabled for
channel is omitted (only the seven most significant bits of the channel have clocks).
8.8.6 Receive Fractional Support (Gapped Clock Mode)
The DS26524 can be programmed to output gapped clocks for selected channels in the receive and transmit paths
to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. When the
gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled
via the Receive Gapped-Clock Channel Select registers (RGCCS1
gapped clock mode with the RGCLKEN bit (RESCR
determined by RESCR
.7. When 56kbps mode is selected, the clock corresponding to the data/control bit in the
.6). Both 56kbps and 64kbps channel formats are supported as
channel is omitted (only the seven most significant bits of the channel have clocks).
:RGCCS4). The receive path is enabled for
41 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.9 Framers
The DS26524 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and
multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, T1 FDL data, and E1 Si- and Sa-bit information. The receive-side framer decodes AMI, B8ZS line coding,
synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides
clock/data and frame-sync signals to the backplane interface section. Diagnostic capabilities include loopbacks,
and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access
and control of the device.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface
section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and
inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding.
Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via
the framer block. The HDLC controller can be assigned to any time slot, portion of a time slot, or to FDL (T1). The
HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to
manage the flow of data.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic
stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz,
4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions
(asynchronous interface). An IBO is provided to allow multiple framers in the DS26524 to share a high-speed
backplane.
8.9.1 T1 Framing
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit
contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at
the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and
24 for ESF.
The D4 and ESF framing modes are outlined in Table 8-10
12 is ignored if Japanese Yellow is selected.
and Table 8-11. In the D4 mode, framing bit for frame
Table 8-10. D4 Framing Mode
FRAME
NUMBER
1 1
2 0
3 0
4 0
5 1
6 1 A
7 0
8 1
9 1
10 1
11 0
12 0 B
Ft Fs SIGNALING
42 of 273
Table 8-11. ESF Framing Mode
FRAME
NUMBER
1
2 CRC-1
3
4 0
5
6 CRC-2
7
8 0
9
10 CRC-3
11
12
13
14 CRC-4
15
16 0
17
18 CRC-5
19
20 1
21
22 CRC-6
23
24 1
FRAMING FDL CRC SIGNALING
√
√
√
√
√
√
√
√
√
√
√
√
DS26524 Quad T1/E1/J1 Transceiver
√
√
√
√
Table 8-12. SLC-96 Framing
FRAME NUMBER Ft Fs SIGNALING
1 1
2 0
3 0
4 0
5 1
6 1 A
7 0
8 1
9 1
10 1
11 0
12 0 B
13 1
14 0
15 0
16 0
17 1
18 1 C
19 0
20 1
21 1
22 1
23 0
43 of 273
DS26524 Quad T1/E1/J1 Transceiver
FRAME NUMBER Ft Fs SIGNALING
24 C1 (Concentrator Bit) D
25 1
26 C2 (Concentrator Bit)
27 0
28 C3 (Concentrator Bit)
29 1
30 C4 (Concentrator Bit) A
31 0
32 C5 (Concentrator Bit)
33 1
34 C6 (Concentrator Bit)
35 0
36 C7 (Concentrator Bit) B
37 1
38 C8 (Concentrator Bit)
39 0
40 C9 (Concentrator Bit)
41 1
42 C10 (Concentrator Bit) C
43 0
44 C11 (Concentrator Bit)
45 1
46 0 (Spoiler Bit)
47 0 D
48 1 (Spoiler Bit)
49 1
50 0 (Spoiler Bit)
51 0
52 M1 (Maintenance Bit)
53 1
54 M2 (Maintenance Bit) A
55 0
56 M3 (Maintenance Bit)
57 1
58 A1 (Alarm Bit)
59 0
60 A2 (Alarm Bit) B
61 1
62 S1 (Switch Bit)
63 0
64 S2 (Switch Bit)
65 1 C
66 S3 (Switch Bit)
67 0
68 S4 (Switch Bit)
69 1
70 1 (Spoiler Bit)
71 0
72 0 D
44 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.9.2 E1 Framing
The E1 framing consists of FAS, NFAS detection as shown in Table 8-13.
Table 8-13. E1 FAS/NFAS Framing
CRC-4
FRAME
#
0 FAS C1 0 0 1 1 0 1 1
1 NFAS 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
2 FAS C2 0 0 1 1 0 1 1
3 NFAS 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
4 FAS C3 0 0 1 1 0 1 1
5 NFAS 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
6 FAS C4 0 0 1 1 0 1 1
7 NFAS 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
8 FAS C1 0 0 1 1 0 1 1
9 NFAS 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
10 FAS C2 0 0 1 1 0 1 1
11 NFAS 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
12 FAS C3 0 0 1 1 0 1 1
13 NFAS E1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
14 FAS C4 0 0 1 1 0 1 1
15 NFAS E2 1 A Sa4 Sa5 Sa6 Sa7 Sa8
C = C bits are the CRC-4 remainder, A = alarm bits, Sa = bits for data link.
TYPE 1 2 3 4 5 6 7 8
45 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 8-14
shows registers that are related to setting up the framing.
Table 8-14. Registers Related to Setting Up the Framer
REGISTER
FRAMER
ADDRESSES
Transmit Master Mode Register (TMMR) 180h T1/E1 mode.
Transmit Control Register 1 (TCR1) 181h Source of the F-bit.
Transmit Control Register 2 (TCR2) 182h F-bit corruption, selection of SLC-96.
Transmit Control Register 3 (TCR3) 183h ESF or D4 mode selection.
Receive Master Mode Register (RMMR) 080h T1/E1 selection for receiver.
Receive Control Register 1 (RCR1) 081h Resynchronization criteria for the framer.
Receive Control Register 2 (T1RCR2) 014h T1 remote alarm and OOF criteria.
Receive Control Register 2 (E1RCR2) 082h E1 receive loss of signal criteria selection.
Receive Latched Status Register 1 (RLS1) 090h Receive latched status 1.
FUNCTION
Receive Interrupt Mask Register 1 (RIM1) 0A0h Receive interrupt mask 1.
Receive Latched Status Register 2 (RLS2) 091h Receive latched status 2.
Receive Interrupt Mask Register 2 (RIM2) 0A1h Receive interrupt mask 2.
Receive Latched Status Register 4 (RLS4) 093h Receive latched status 4.
Receive Interrupt Mask Register 4 (RIM4) 0A3h Receive interrupt mask 4.
Frames Out of Sync Count Register 1
(FOSCR1
)
Frames Out of Sync Count Register 2
(FOSCR2
)
054h Framer out of sync register 1.
055h Framer out of sync register 2.
E1 Receive Align Frame Register (E1RAF) 064h RAF byte.
E1 Receive Non-Align Frame Register
(E1RNAF
)
Transmit SLC-96 Data Link Register 1
(T1TSLC1
)
Transmit SLC-96 Data Link Register 2
(T1TSLC2)
Transmit SLC-96 Data Link Register 3
(T1TSLC3
)
Receive SLC-96 Data Link Register 1
(T1RSLC1
)
Receive SLC-96 Data Link Register 2
(T1RSLC2)
Receive SLC-96 Data Link Register 3
(T1RSLC3
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
)
065h RNAF byte.
164h Transmit SLC-96 bits.
165h Transmit SLC-96 bits.
166h Transmit SLC-96 bits.
064h Receive SLC-96 bits.
065h Receive SLC-96 bits.
066h Receive SLC-96 bits.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.3 T1 Transmit Synchronizer
The DS26524 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries
within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit
synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are
located in the TSYNCC
register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a loss-of-frame
synchronization has occurred. The real-time bit (LOF) is also provided to indicate when the synchronizer is
searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB.
Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the
recovered frame-sync pulse will be output on this signal. The recovered CRC-4 multiframe sync pulse is output if
enabled with TIOCR
.0 (TSM = 1).
Other key points concerning the E1 transmit synchronizer:
1) The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes.
2) The Tx synchronizer does not perform CRC-6 alignment verification (ESF mode) and does not verify
CRC-4 codewords.
The Tx synchronizer cannot search for the CAS multiframe. Table 8-15
shows the registers related to the transmit
synchronizer.
Table 8-15. Registers Related to the Transmit Synchronizer
REGISTER
Transmit Synchronizer Control Register
(TSYNCC
)
FRAMER
ADDRESSES
18Eh
FUNCTION
Resynchronization control for the transmit
synchronizer.
Transmit Control Register 3 (TCR3) 183h
Transmit Latched Status Register 3
(TLS3)
Transmit Interrupt Mask Register 3
(TIM3)
Transmit I/O Configuration Register
(TIOCR)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
192h
1A2h Provides mask bits for the TLS3 status.
184h TSYNC should be set as an output.
TFM bit selects between D4 and ESF for the
transmit synchronizer.
Provides latched status for the transmit
synchronizer.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4 Signaling
The DS26524 supports both software- and hardware-based signaling. Interrupts can be generated on changes of
signaling data. The DS26524 is also equipped with receive-signaling freeze on loss of synchronization (OOF),
carrier loss, or change of frame alignment. The DS26524 also has hardware pins to indicate signaling freeze.
• Flexible signaling support
o Software or hardware based
o Interrupt generated on change of signaling data
o Receive-signaling freeze on loss of frame, loss of signal, or change of frame alignment
• Hardware pins for carrier loss and signaling freeze indication
Table 8-16. Registers Related to Signaling
REGISTER FRAMER ADDRESSES FUNCTION
Transmit-Signaling Registers 1 to 16
(TS1
to TS16)
Software-Signaling Insertion Enable
Registers 1 to 4 (SSIE1
to SSIE4)
Transmit Hardware-Signaling Channel
Select Registers 1 to 4
(THSCS1
to THSCS4)
Receive-Signaling Control Register
(RSIGC)
Receive-Signaling All-Ones Insertion
Registers 1 to 3
(T1RSAOI1
to T1RSAOI3)
Receive-Signaling Registers 1 to 16
(RS1 to RS16)
Receive-Signaling Status Registers 1
to 4 (RSS1 to RSS4)
Receive-Signaling Change of State
Enable Registers 1 to 4 (RSCSE1 to
RSCSE4)
Receive Latched Status Register 4
(RLS4)
Receive Interrupt Mask Register 4
(RIM4
)
140h to 14Bh (T1/J1)
140h to 14Fh (E1 CAS)
118h, 119h, 11Ah, 11Bh
1C8h, 1C9h, 1CAh, 1CBh
013h Freeze control for receive signaling.
038h, 039h, 03Ah
040h to 04Bh (T1/J1)
040h to 04Fh (E1)
098h to 09Ah (T1/J1)
98h to 9Fh (E1)
0A8h, 0A9h, 0AAh, 0ABh
093h Receive-signaling change of state bit.
0A3h
Transmit ABCD signaling.
When enabled, signaling is inserted for
the channel.
Bits determine which channels will have
signaling inserted in hardware-signaling
mode.
Registers for all-ones insertion (T1 mode
only).
Receive-signaling bytes.
Receive-signaling change of status bits.
Receive-signaling change of state
interrupt enable.
Receive-signaling change of state
interrupt mask bit.
Receive-Signaling Reinsertion Enable
Registers 1 to 4 (RSI1 to RSI4)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
0C8h, 0C9h, 0CAh, 0CBh Registers for signaling reinsertion.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.1 Transmit-Signaling Operation
There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or
hardware based. Processor based refers to access through the transmit-signaling registers, TS1
:TS16, while
hardware based refers to using the TSIG pins. Both methods can be used simultaneously.
8.9.4.1.1 Processor-Based Signaling
In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1:TS16) via the host
interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in
the appropriate bit position in the outgoing data stream. The user can use the transmit multiframe interrupt in
Latched Status Register 1 (TLS1
.2) to know when to update the signaling bits. The user need not update any
transmit-signaling register for which there is no change of state for that register.
Each transmit-signaling register contains the robbed-bit signaling (TCR1
(TCR1
.6 in E1 mode) for one time slot that will be inserted into the outgoing stream. Signaling data can be sourced
.4 in T1 mode) or TS16 CAS signaling
from the TS registers on a per-channel basis by using the software-signaling insertion enable registers,
SSIE1
:SSIE4.
In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1:TS12 contain a full
multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1
D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become
“don’t care” in D4 mode.
In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common-channel
signaling) or CAS (channel-associated signaling) format. The 32 time slots are referenced by two different channel
number schemes in E1. In channel numbering, TS0 to TS31 are labeled channel 1 to channel 32. In phone channel
numbering, TS1 to TS15 are labeled channel 1 to channel 15, and TS17 to TS31 are labeled channel 15 to
channel 30.
8.9.4.2 Time Slot Numbering Schemes
TS
Channel
Phone
Channel
8.9.4.2.1 Hardware-Based Signaling
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and
inserted to the data stream being input at the TSER pin.
Signaling data can be input via the transmit hardware-signaling channel select (THSCS1
) function. The framer can
be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data
stream that is being input at the TSER pin. The user can control which channels are to have signaling data from the
TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available
whether the transmit-side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock
(TSYSCLK) can be either 1.544MHz or 2.048MHz.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.3 Receive-Signaling Operation
There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e.,
software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling
registers, RS1
8.9.4.3.1 Processor-Based Signaling
:RS16. Hardware based refers to the RSIG pin. Both methods can be used simultaneously.
Signaling information is sampled from the receive data stream and copied into the receive-signaling registers,
RS1:RS16. The signaling information in these registers is always updated on multiframe boundaries. This function
is always enabled.
8.9.4.3.2 Change of State
To avoid constant monitoring of the receive-signaling registers, the DS26524 can be programmed to alert the host
when any specific channel or channels undergo a change of their signaling state. RSCSE1
:RSCSE4 are used to
select which channels can cause a change-of-state indication. The change of state is indicated in Latched Status
Register 4 (RLS4
.3). If signaling integration is enabled, the new signaling state must be constant for three
multiframes before a change-of-state indication is indicated. The user can enable the INTB pin to toggle low upon
detection of a change in signaling by setting the interrupt mask bit RIM4
.3. The signaling integration mode is global
and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the receive-signaling
status (RSS1
:RSS4) registers. The information from these registers tells the user which RSx register to read for the
new signaling data. All changes are indicated in the RSS1:RSS4 registers regardless of the RSCSE1:RSCSE4
registers.
8.9.4.3.3 Hardware-Based Receive Signaling
In hardware-based signaling, the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a
signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The T1 robbed bit or E1
TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data
to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment
that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be
enabled or disabled. If the receive elastic store is enabled, the backplane clock (RSYSCLK) can be either
1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble
of each channel. The RSIG data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS)
unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the
lower nibble of each channel. Thus, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each
channel.
8.9.4.3.4 Receive-Signaling Reinsertion at RSER
In this mode, the user provides a multiframe sync at the RSYNC pin and the signaling data will be reinserted based
on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original
signaling data is based on the Fs/ESF frame positions, and the realigned data is based on the user-supplied
multiframe sync applied at RSYNC. In voice channels, this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled; for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling
information cannot be reinserted into a 1.544MHz backplane.
Signaling-reinsertion mode is enabled on a per-channel basis by setting the receive-signaling reinsertion channel
select bit high in the Receive-Signaling Reinsertion Enable register (RSI1
signaling reinserted are selected by writing to the RSI1
:RSI4 registers. In E1 mode, the user generally selects all
:RSI4). The channels that are to have
channels or none for reinsertion.
8.9.4.3.5 Force Receive-Signaling All Ones
In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling bit positions to 1. This is done by
using the T1-mode Receive-Signaling All-Ones Insertion registers (T1RSAOI1
channel select bit in the T1RSAOI1
:T1RSAOI3 registers to select the channels that are to have the signaling forced
:T1RSAOI3). The user sets the
to one.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.3.6 Receive-Signaling Freeze
The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the
requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE
control bit (RSIGC
.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2)
high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer
provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receivesignaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data is held in the last known
good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is
held in the old state for at least an additional 9ms (4.5ms in D4 framing mode, 6ms for E1 mode) before being
allowed to be updated with new signaling data.
The receive-signaling registers are frozen and not updated during a loss-of-sync condition. They will contain the
most recent signaling information before the LOF occurred.
8.9.4.4 Transmit SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008. Registers related to the transmit FDL are shown
in Table 8-17
.
Table 8-17. Registers Related to SLC-96
REGISTER
Transmit FDL Register (T1TFDL) 162h
Transmit SLC-96 Data Link Registers 1
to 3 (T1TSLC1:T1TSLC3)
Transmit Control Register 2 TCR2) 182h
Transmit Latched Status Register 1
(TLS1)
Receive SLC-96 Data Link Registers 1
to 3 (T1RSLC1
:T1RSLC3)
Receive Latched Status Register 7
(RLS7
)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
The T1TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the
T1TFDL
register, the user should configure the DS26524 as shown:
• TCR2
• TCR2
• TCR3
• TCR1
.6 (TSLC96) = 1 Enable transmit SLC-96.
.7 (TFDLS) = 0 Source FS bits via TFDL or SLC-96 formatter.
.2 (TFM) = 1 D4 framing mode.
.6 (TFPT) = 0 Do not “pass through” TSER F-bits.
The DS26524 automatically inserts the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame. Data
from T1TSLC1
TSLC96 located at TLS1
:T1TSLC3 is inserted into the remaining Fs-bit locations of the SLC-96 multiframe. The status bit
.4 is set to indicate that the SLC-96 data link buffer has been transmitted and that the user
should write new message data into T1TSLC1:T1TSLC3. The host has 9ms after the assertion of TLS1.4 to write
the registers T1TSLC1
:T1TSLC3. If no new data is provided in these registers, the previous values are
retransmitted.
FRAMER
ADDRESSES
FUNCTION
For sending messages in transmit SLC-96 Ft/Fs
bits.
164h, 165h, 166h
Registers that control the SLC-96 overhead
values.
Transmit control for data selection source for the
Ft/Fs bits.
190h
Status bit for indicating transmission of data link
buffer.
064h, 065h, 066h —
096h Receive SLC-96 alignment event.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.4.5 Receive SLC-96 Operation (T1 Mode Only)
In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of
message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into
alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96
information can be found in BellCore document TR-TSY-000008.
To enable the DS26524 to synchronize onto a SLC-96 pattern, the following configuration should be used:
• RCR1
• RCR1
• T1RCR2
• RCR1
The SLC-96 message bits can be extracted via the T1RSLC1
at RLS7
.3 is useful for retrieving SLC-96 message data. The RSLC96 bit indicates when the framer has updated
the data link registers T1RSLC1
.5 (RFM) = 1 Set to D4 framing mode.
.3 (SYNCC) = 1 Set to cross-couple Ft and Fs bits.
.4 (RSLC96) = 1 Enable SLC-96 synchronizer.
.7 (SYNCT) = 0 Set to minimum sync time.
:T1RSLC3 registers. The status bit RSLC96 located
:T1RSLC3 with the latest message data from the incoming data stream. Once the
RSLC96 bit is set, the user has 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data
from the T1RSLC1
:T1RSLC3 registers. Note that RSLC96 will not set if the DS26524 is unable to detect the 12-bit
SLC-96 alignment pattern.
8.9.5 T1 Data Link
8.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller
The DS26524 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC
function is available only in T1 mode. Table 8-18
shows the registers related to the transmit bit-oriented code.
Table 8-18. Registers Related to T1 Transmit BOC
REGISTER
FRAMER
ADDRESSES
Transmit BOC Register (T1TBOC) 163h Transmit bit-oriented message code register.
Transmit HDLC Control Register 2 (THC2) 113h Bit to enable sending of transmit BOC.
Transmit Control Register 1(TCR1) 181h Determines the sourcing of the F-bit.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
Bits 0 to 5 in the T1TBOC
register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6)
causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The
transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as
SBOC is set. Note that the TFPT (TCR1
.6) control bit must be set to 0 for the BOC message to overwrite F-bit
information being sampled on TSER.
8.9.5.1.1 To Transmit a BOC
1) Write 6-bit code into the T1TBOC register.
2) Set SBOC bit in THC2
= 1.
FUNCTION
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DS26524 Quad T1/E1/J1 Transceiver
8.9.5.2 Receive Bit-Oriented Code (BOC) Controller
The DS26524 framers contain a BOC generator on the transmit side and a BOC detector on the receive side. The
BOC function is available only in T1, ESF mode in the data link bits. Table 8-19
shows the registers related to the
receive BOC operation.
Table 8-19. Registers Related to T1 Receive BOC
REGISTER
Receive BOC Control Register
(T1RBOCC)
FRAMER
ADDRESSES
015h Controls the receive BOC function.
Receive BOC Register (T1RBOC) 063h Receive bit-oriented message.
FUNCTION
Receive Latched Status Register 7(RLS7) 096h
Receive Interrupt Mask Register 7 (RIM7) 0A6h
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
Indicates changes to the receive bit-oriented
messages.
Mask bits for RBOC for generation of
interrupts.
In ESF mode, the DS26524 continuously monitors the receive message bits for a valid BOC message. The BOC
detect (BD) status bit at RLS7
.0 is set once a valid message has been detected for a time determined by the
receive BOC filter bits RBF0 and RBF1 in the T1RBOCC register. The 6-bit BOC message is available in the
T1RBOC register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same
BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7
.1 is set when a valid BOC is no
longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the
T1RBOCC
register.
The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated
interrupt mask bits in the RIM7
register.
8.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26524’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 8-21
shows the registers related to control of the transmit FDL.
Table 8-20. Registers Related to T1 Transmit FDL
REGISTER
Transmit FDL Register (T1TFDL) 162h FDL code used to insert transmit FDL.
Transmit Control Register 2 (TCR2) 182h Defines the source of the FDL.
FRAMER
ADDRESSES
FUNCTION
Transmit Latched Status Register 2 (TLS2) 191h Transmit FDL empty bit.
Transmit Interrupt Mask Register 2 (HDLC)
(TIM2
)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
1A1h Mask bit for TFDL empty.
When enabled with TCR2.7, the transmit section shifts out into the T1 data stream either the FDL (in the ESF
framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (T1TFDL
new value is written to the T1TFDL
, it is multiplexed serially (LSB first) into the proper position in the outgoing T1
). When a
data stream. After the full eight bits have been shifted out, the framer signals the host controller that the buffer is
empty and that more data is needed by setting the TLS2
.4. The user has 2ms to update the T1TFDL with a new value. If the T1TFDL is not updated, the old value in
TIM2
the T1TFDL
is transmitted once again. Note that in this mode, no zero stuffing is applied to the FDL data. It is
.4 bit to a 1. The INTB bit also toggles low if enabled via
strongly suggested that the HDLC controller be used for FDL messaging applications.
In the D4 framing mode, the framer uses the T1TFDL
the T1TFDL
register must be programmed to 1Ch and TCR2.7 should be set to 0 (source Fs data from the T1TFDL
register to insert the Fs framing pattern. To accomplish this,
register).
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DS26524 Quad T1/E1/J1 Transceiver
The Transmit FDL register (T1TFDL
) contains the facility data link (FDL) information that is to be inserted on a byte
basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
8.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26524’s built-in BOC or HDLC controllers be used for most applications requiring
access to the FDL. Table 8-21
shows the registers related to the receive FDL.
Table 8-21. Registers Related to T1 Receive FDL
REGISTER
Receive FDL Register (T1RFDL) 062h FDL code used to insert transmit FDL.
Receive Latched Status Register 7(RLS7) 096h Receive FDL full bit is in this register.
Receive Interrupt Mask Register 7(RIM7) 0A6h Mask bit for RFDL full.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register
(T1RFDL
). Since the T1RFDL is 8 bits in length, it fills up every 2ms (8 x 250µs). The framer signals an external
controller that the buffer has filled via the RLS7
that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no
zero destuffing is applied for the data provided through the T1RFDL
facility data link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, T1RFDL updates on
multiframe boundaries and reports only the Fs bits.
FRAMER
ADDRESSES
FUNCTION
.2 bit. If enabled via RIM7.2, the INTB pin toggles low, indicating
register. The T1RFDL reports the incoming
8.9.6 E1 Data Link
Table 8-22 shows the registers related to E1 data link.
Table 8-22. Registers Related to E1 Data Link
REGISTER
FRAMER
ADDRESSES
E1 Receive Align Frame Register (E1RAF) 064h Receive frame alignment register.
E1 Receive Non-Align Frame Register
Register (E1RNAF
)
E1 Received Si Bits of the Align Frame
Register (E1RSiAF)
Received Si Bits of the Non-Align Frame
Register E1RSiNAF
)
Received Sa4 to Sa8 Bits Register
(E1RSa4 to E1RSa8)
065h Receive non-frame alignment register.
066h Receive Si bits of the frame alignment frames.
067h
Receive Si bits of the non-frame alignment
frames.
069h, 06Ah,
06Bh, 06Ch,
Receive Sa bits.
06Dh
Transmit Align Frame Register (E1TAF) 164h Transmit align frame register.
Transmit Non-Align Frame Register
(E1TNAF
)
Transmit Si Bits of the Align Frame
Register (E1TSiAF)
Transmit Si Bits of the Non-Align Frame
Register (E1TSiNAF
)
Transmit Sa4 to Sa8 Bits Register
(E1TSa4
to E1TSa8)
E1 Transmit Sa-Bit Control Register
(E1TSACR
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
)
165h Transmit non-align frame register.
166h Transmit Si bits of the frame alignment frames.
167h
Transmit Si bits of the non-frame alignment
frames.
169h, 16Ah,
16Bh, 16Ch,
Transmit Sa4 to Sa8.
16Dh
114h Transmit sources of Sa control.
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FUNCTION
DS26524 Quad T1/E1/J1 Transceiver
8.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode)
The DS26524, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods.
The first involves using the internal E1RAF
/E1RNAF and E1TAF/E1TNAF registers. The second method involves
an expanded version of the first method.
8.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1)
On the receive side, the E1RAF and E1RNAF registers will always report the data as it received in the Sa- and Sibit locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the receive
align frame bit in Receive Latched Status Register 2 (RLS2.0) indicates that the contents of the RAF and RNAF
have been updated. The host can use the RLS2
.0 bit to know when to read the E1RAF and E1RNAF registers. The
host has 250µs to retrieve the data before it is lost.
8.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive Side)
On the receive side there is a set of eight registers (E1RSiAF, E1RSiNAF, E1RRA, E1RSa4:E1RSa8) that report
the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in Receive Latched Status Register 2 (RLS2
.1). The host can use the RLS2.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for
additional information.
8.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit Side)
On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4:E1TSa8) that, via the
Transmit Sa-Bit Control register (E1TSACR), can be programmed to insert both Si and Sa data. Data is sampled
from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1 (TLS1
.3).
The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the
old data will be retransmitted. See the register descriptions for additional information.
8.9.6.2 Sa-Bit Monitoring and Reporting
In addition to the registers outlined above, the DS26524 provides status and interrupt capability in order to detect
changes in the state of selected Sa bits. The E1RSAIMR
register can be used to select which Sa bits are
monitored for a change of state. When a change of state is detected in one of the enabled Sa-bit positions, a status
bit is set in the RLS7
by unmasking RIM7
register via the SaXCD bit (bit 0). This status bit can, in turn, be used to generate an interrupt
.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SaBITS register at
address 06Eh to determine the current value of each Sa bit.
For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE
register reports the received Sa6 codeword. The codeword must be stable for a period of three submultiframes and
be different from the previous stored value in order to be updated in this register. See the Sa6CODE
register
description for further details on the operation of this register and the values reported in it. An additional status bit is
provided in RLS7
status bit in RIM7
(Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this
to allow for interrupt generation when enabled.
8.9.7 Maintenance and Alarms
The DS26524 provides extensive functions for alarm detection and generation. It also provides diagnostic functions
for monitoring of performance and sending of diagnostic information such as the following:
• Real-time and latched status bits, interrupts, and interrupt mask for transmitter and receiver
• LOS detection
• RIA detection and generation
• PDV violation detection
• Error counters
• DS0 monitoring
• Milliwatt generation and detection
• Slip buffer status for transmit and receive
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DS26524 Quad T1/E1/J1 Transceiver
Table 8-23
shows some of the registers related to maintenance and alarms.
Table 8-23. Registers Related to Maintenance and Alarms
REGISTER
FRAMER
ADDRESSES
Receive Real-Time Status Register 1 (RRTS1) 0B0h Real-time receive status 1.
Receive Interrupt Mask Register 1(RIM1) 0A0h Real-time interrupt mask 1.
Receive Latched Status Register 2 (RLS2) 091h Real-time latched status 2.
Receive Real-Time Status Register 3 (RRTS3) 0B2h Real-time receive status 2.
Receive Latched Status Register 3 (RLS3) 092h Real-time latched status 3.
Receive Interrupt Mask Register 3 (RIM3) 0A2h Real-time interrupt mask 3.
Receive Interrupt Mask Register 4 (RIM4) 0A3h Real-time interrupt mask 3.
Receive Latched Status Register 7 (RLS7) 096h Real-time latched status 7.
Receive Interrupt Mask Register 7 (RIM7) 0A6h Real-time interrupt mask 7.
FUNCTION
Transmit Latched Status Register 1 (TLS1) 190h Loss of transmit clock status, TPDV, etc.
Transmit Latched Status Register 3
(Synchronizer) (TLS3)
192h Loss of frame status.
Receive DS0 Monitor Register (RDS0M) 060h Receive DS0 monitor.
Error-Counter Configuration Register (ERCNT) 086h Configuration of the error counters.
Line Code Violation Count Register 1
(LCVCR1)
Line Code Violation Count Register 2
(LCVCR2
)
Path Code Violation Count Register 1
(PCVCR1)
Path Code Violation Count Register 2
(PCVCR2)
Frames Out of Sync Count Register 1
(FOSCR1
)
Frames Out of Sync Count Register 2
(FOSCR2
)
050h Line code violation counter 1.
051h Line code violation counter 2.
052h Receive path code violation counter 1.
053h Receive path code violation counter 2.
054h Receive frame out of sync counter 1
055h Receive frame out of sync counter 2
E-Bit Count Register 1 (E1EBCR1) 056h E-bit count register 1.
E-Bit Count Register 2 (E1EBCR2) 057h E-bit count register 2.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.7.1 Status and Information Bit Operation
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1.
Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a
hardware interrupt via the INTB signal.
8.9.7.1.1 Real-Time Bits
Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm
or a condition. Real-time bits remain stable and valid during the host read operation. The current value of the
internal status signals can be read at any time from the real-time status registers without changing any the latched
status register bits.
8.9.7.1.2 Latched Bits
When an event or an alarm occurs and a latched bit is set to 1, it remains set until cleared by the user. These bits
typically respond on a change-of-state for an alarm, condition, or event, and operate in a read-then-write fashion.
The user should read the value of the desired status bit and then write a 1 to that particular bit location to clear the
latched value (write a 0 to locations not to be cleared). Once the bit is cleared, it is not set again until the event has
occurred again.
8.9.7.1.3 Mask Bits
Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Receive Interrupt
Mask registers (RIM1
:RIM7). When unmasked, the INTB signal is forced low when the enabled event or condition
occurs. The INTB pin is allowed to return high (if no other unmasked interrupts are present) when the user reads
and then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and
the INTB pin clear even if the alarm is still present.
Note that some conditions can have multiple status indications. For example, receive loss of frame (RLOF)
provides the following indications:
RRTS1
.0
(RLOF)
RLS1.0
(RLOFD)
Real-time indication that the receiver is not synchronized with
incoming data stream. Read-only bit that remains high as long as
the condition is present.
Latched indication that the receiver has lost synchronization since
the bit was last cleared. Bit clears when written by the user, even
if the condition is still present (rising edge detect of RRTS1
.0).
Latched indication that the receiver has reacquired
RLS1.4
(RLOFC)
synchronization since the bit was last cleared. Bit clears when
written by the user, even if the condition is still present (falling
edge detect of RRTS1
.0).
57 of 273
Table 8-24. T1 Alarm Criteria
ALARM SET CRITERIA CLEAR CRITERIA
AIS
(Blue Alarm) (See Note 1)
1) D4 Bit 2 Mode
(T1RCR2.0 = 0)
2) D4 12th F-Bit Mode
RAI
(Yellow
Alarm)
(T1RCR2
(Note: This mode is
also referred to as the
“Japanese Yellow
Alarm.”)
3) ESF Mode When 16 consecutive patterns of
.0 = 1)
When over a 3ms window, 4 or
fewer zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences.
When the 12th framing bit is set to
one for two consecutive
occurrences.
00FF appear in the FDL.
DS26524 Quad T1/E1/J1 Transceiver
When over a 3ms window, 5 or
more zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for less than
254 occurrences.
When the 12th framing bit is set to
zero for two consecutive
occurrences.
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in the
FDL.
LOS
(Loss of Signal)
(Note: This alarm is also referred to
When 192 consecutive zeros are
received.
When 14 or more ones out of 112
possible bit positions are received
starting with the first one received.
as receive carrier loss (RCL).)
Note 1: The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate
Note 2: The following terms are equivalent:
properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria
in the DS26524 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit.
RAIS = Blue Alarm
RLOS = RCL
RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices)
RRAI = Yellow Alarm
8.9.8 E1 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (TCR2
are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or
signal). If any one (or more) of these conditions is present, the framer forces an AIS.
When automatic RAI generation is enabled (TCR2
of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, loss of
receive carrier (or signal), or if CRC-4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC-4 is enabled). If any one (or more) of the above conditions is present, the framer transmits
an RAI alarm. RAI generation conforms to ETS 300 011 and ITU-T G.706 specifications.
Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled
at the same time.
.6 = 1), the device monitors the receive-side framer to determine if any of the following conditions
.5 = 1), the framer monitors the receive side to determine if any
8.9.8.1 Receive AIS-CI and RAI-CI Detection
AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all-ones pattern and 0.15
seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in
length in which, if the first bit is numbered bit 0, bits 3088, 3474, and 5790 are logical zeros and all other bits in the
pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The
RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1
.2) is set. RAIS-CI is a latched bit
that should be cleared by the host when read. RAIS-CI continues to set approximately every 1.2 seconds that the
condition is present. The host needs to poll the bit in conjunction with the normal AIS indicators to determine when
the condition has cleared.
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DS26524 Quad T1/E1/J1 Transceiver
RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially
interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI
bit is set when a bit-oriented code of “00111110 11111111” is detected while RRAI (RRTS1
detector uses the receive BOC filter bits (RBF0 and RBF1) located in RBOCC to determine the integration time for
RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read.
RRAI-CI continues to set approximately every 1.1 seconds that the condition is present. The host needs to poll the
bit in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to
enable the 200ms ESF RAI integration time with the RAIIE control bit (T1RCR2
8.9.8.2 T1 Receive-Side Digital Milliwatt Code Generation
Receive-side digital milliwatt code generation involves using the T1 Receive Digital Milliwatt registers
(T1RDMWE1
be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents
a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMWE1
registers represents a particular channel. If a bit is set to 1, the receive data in that channel is replaced with the
digital milliwatt code. If a bit is set to 0, no replacement occurs.
:T1RDMWE3) to determine which of the 24 T1 channels of the T1 line going to the backplane should
.1) in networks that use RAI-CI.
, T1RDMWE2, and T1RDMWE3
.3) is set. The RRAI-CI
8.9.9 Error-Count Registers
The DS26524 contains four counters that are used to accumulate line coding errors, path errors, and
synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62.5ms (E1
mode only), or manually. See the Error-Counter Configuration register (ERCNT
user can use the interrupt from the timer to determine when to read these registers. All four counters saturate at
their respective maximum counts and they will not roll over. (Note: Only the Line Code Violation Count register has
the potential to overflow, but the bit error would have to exceed 10E-2 before this would occur.)
). When updated automatically, the
The DS26524 can share the one-second timer from Port 1 across all ports. All DS26524 error/performance
counters can be configured to update on the shared one-second source, or a separate manual update signal input.
See the Error-Counter Configuration register ERCNT
cores to synchronously latch their counters, the host software can be streamlined to read and process performance
information from multiple spans in a more controlled manner.
8.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of
the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted
as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as
BPVs. If ERCNT
defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be
programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This
counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and
will not rollover. The bit-error rate on an E1 line would have to be greater than 10E-2 before the PCVCR would
saturate. See Table 8-25
.0 is set, then the LCVCR counts code violations as defined in ITU-T O.161. Code violations are
and Table 8-26 for details of exactly what the LCVCRs count.
register for more information. By allowing multiple framer
Table 8-25. T1 Line Code Violation Counting Options
COUNT EXCESSIVE
ZEROS?
(ERCNT
.0)
No No BPVs
Yes No BPVs + 16 consecutive zeros
No Yes BPVs (B8ZS/HDB3 codewords not counted)
Yes Yes BPVs + 8 consecutive zeros
B8ZS ENABLED?
(RCR1
.6)
WHAT IS COUNTED IN
LCVCR1, LCVCR2
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Table 8-26. E1 Line Code Violation Counting Options
DS26524 Quad T1/E1/J1 Transceiver
E1 CODE VIOLATION SELECT
(ERCNT.0)
0 BPVs
1 CVs
8.9.9.2 Path Code Violation Count Register (PCVCR)
In T1 operation, the Path Code Violation Count register (PCVCR) records either Ft, Fs, or CRC-6 errors. When the
receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC-6
codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position.
Via the ERCNT
disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 8-27
exactly what errors the PCVCR counts in T1 operation.
In E1 operation, PCVCR records CRC-4 errors. Since the maximum CRC-4 count in a one-second period is 1000,
this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4 level; it
continues to count if loss of multiframe sync occurs at the CAS level.
The Path Code Violation Count Register 1 (PCVCR1
Register 2 (PCVCR2
.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. PCVCR is
) is the least significant word of a 16-bit counter that records path violations (PVs).
WHAT IS COUNTED IN
LCVCR1, LCVCR2
for a detailed description of
) is the most significant word and Path Code Violation Count
Table 8-27. T1 Path Code Violation Counting Arrangements
FRAMING MODE COUNT Fs ERRORS?
D4 No Errors in the Ft pattern
WHAT IS COUNTED IN
PCVCR1
, PCVCR2
D4 Yes Errors in both the Ft and Fs patterns
ESF Don’t Care Errors in the CRC-6 codewords
8.9.9.3 Frames Out of Sync Count Register (FOSCR)
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is
useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events
as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during
receive loss of synchronization (RLOF = 1) conditions. The FOSCR has an alternate operating mode whereby it will
count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF
mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOF = 1)
conditions. See Table 8-28
In E1 mode, the FOSCR counts word errors in the frame alignment signal in time slot 0. This counter is disabled
when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or
synchronization at either the CAS or CRC-4 multiframe level. Since the maximum FAS word error count in a onesecond period is 4000, this counter cannot saturate.
The Frames Out of Sync Count Register 1 (FOSCR1
Register 2 (FOSCR2
for a detailed description of what the FOSCR is capable of counting.
) is the most significant word and Frames Out of Sync Count
) is the least significant word of a 16-bit counter that records frames out of sync.
Table 8-28. T1 Frames Out of Sync Counting Arrangements
FRAMING MODE
(RCR1.5)
D4 MOS Number of multiframes out of sync
D4 F-Bit Errors in the Ft pattern
ESF MOS Number of multiframes out of sync
ESF F-Bit Errors in the FPS pattern
COUNT MOS OR F-BIT ERRORS
(ERCNT.1)
WHAT IS COUNTED IN
FOSCR1, FOSCR2
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8.9.9.4 E-Bit Counter (EBCR)
DS26524 Quad T1/E1/J1 Transceiver
This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1
) is the most significant word and E-Bit
Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block errors
(FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count
registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second
period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4
level; it continues to count if loss of multiframe sync occurs at the CAS level.
8.9.10 DS0 Monitoring Function
The DS26524 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive
direction at the same time. Table 8-29
shows the registers related to the control of transmit and receive DS0.
Table 8-29. Registers Related to DS0 Monitoring
REGISTER
Transmit DS0 Channel Monitor Select
(TDS0SEL
)
Transmit DS0 Monitor Register
(TDS0M)
Receive Channel Monitor Select Register
(RDS0SEL)
Receive DS0 Monitor Register
(RDS0M
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
)
In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM[4:0] bits
in the TDS0SEL
register. In the receive direction, the RCM[4:0] bits in the RDS0SEL register need to be properly
set. The DS0 channel pointed to by the TCM[4:0] bits appear in the Transmit DS0 Monitor register (TDS0M) and
the DS0 channel pointed to by the RCM[4:0] bits appear in the Receive DS0 Monitor register (RDS0M). The
TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate T1 or E1 channel.
T1 channels 1 to 24 map to register values 0 to 23. E1 channels 1 to 32 map to register values 0 to 31. For
example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be
monitored, then the following values would be programmed into TDS0SEL
TCM4 = 0 RCM4 = 0
TCM3 = 0 RCM3 = 1
TCM2 = 1 RCM2 = 1
TCM1 = 0 RCM1 = 1
TCM0 = 1 RCM0 = 0
FRAMER
ADDRESSES
FUNCTION
189h Transmit channel to be monitored.
1BBh Monitored data.
012h Receive channel to be monitored.
060h Monitored data.
and RDS0SEL:
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DS26524 Quad T1/E1/J1 Transceiver
8.9.11 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions.
The Transmit Idle Code Definition registers (TIDR1
channel. The Transmit Channel Idle Code Enable registers (TCICE1
:TIDR32) are provided to set the 8-bit idle code for each
:TCICE4) are used to enable idle code
replacement on a per-channel basis.
8.9.12 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The
Receive Idle Code Definition registers (RIDR1:RIDR32) are provided to set the 8-bit idle code for each channel.
The Receive Channel Idle Code Enable registers (RCICE1
:RCICE4) are used to enable idle code replacement on
a per-channel basis.
8.9.13 Per-Channel Loopback
The Per-Channel Loopback Enable registers (PCL1:PCL4) determine which channels (if any) from the backplane
should be replaced with the data from the receive side, i.e., off the T1 or E1 line. If this loopback is enabled, the
transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie
RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on
how many channels can be looped back.
Each of the bit positions in the Per-Channel Loopback Enable registers (PCL1
:PCL4) represents a DS0 channel in
the outgoing frame. When these bits are set to 1, data from the corresponding receive channel replaces the data
on TSER
for that channel.
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
The DS26524 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is
enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word,
and CRC-4 checksum in time slot 0. The user can modify the Sa-bit positions and this change in data content will
be used to modify the CRC-4 checksum. This modification, however, does not corrupt any error information the
original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode.
The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input, the user must assert TSYNC
aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align
the data presented to TSER. This mode is enabled with the TCR3
transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4).
.0 control bit (CRC4R). Note that the E1
Figure 8-8. CRC-4 Recalculate Method
TTIP/TRING
INSERT
NEW CRC-4
CODE
EXTRACT
OLD CRC-4
CODE
+
CRC-4
CALCULATOR
62 of 273
XOR
MODIFY
Sa-BIT
POSITIONS
NEW Sa-BIT
DATA
TSER
DS26524 Quad T1/E1/J1 Transceiver
8.9.15 T1 Programmable In-Band Loop Code Generator
The DS26524 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 8-30. Registers Related to T1 In-Band Loop Code Generator
REGISTER
Transmit Code Definition Register 1
(T1TCD1
)
Transmit Code Definition Register 2
(T1TCD2
)
Transmit Control Register 3 (TCR3) 183h
FRAMER
ADDRESSES
1ACh Pattern to be sent for loop code.
1ADh Length of the pattern to be sent.
TLOOP bit for control of number of patterns being
sent.
Transmit Control Register 4 (TCR4) 186h Length of the code being sent.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
To transmit a pattern, the user loads the pattern to be sent into the Transmit Code Definition registers (T1TCD1
and T1TCD2) and selects the proper length of the pattern by setting the TC1 and TC0 bits in Transmit Control
Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern, both T1TCD1 and T1TCD2 must be filled
with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires T1TCD1
accomplished, the pattern is transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless
the transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating pattern
once every 193 bits to allow the F-bit position to be sent.
FUNCTION
to be filled. Once this is
As an example, to transmit the standard loop-up code for Channel Service Units (CSUs), which is a repeating
pattern of ...10000100001..., set TCD1 = 80h, TC0 = 0, TC1 = 0, and TCR3.0 = 1.
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DS26524 Quad T1/E1/J1 Transceiver
8.9.16 T1 Programmable In-Band Loop Code Detection
The DS26524 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 8-31. Registers Related to T1 In-Band Loop Code Detection
REGISTER
Receive In-Band Code Control Register
(T1RIBCC
)
Receive Up Code Definition Register 1
(T1RUPCD1)
Receive Up Code Definition Register 2
(T1RUPCD2
)
Receive Down Code Definition Register 1
(T1RDNCD1
)
Receive Down Code Definition Register 2
(T1RDNCD2)
FRAMER
ADDRESSES
082h
Used for selecting length of receive inband loop code register.
FUNCTION
0ACh Receive up code definition register 1.
0ADh Receive up code definition register 2.
0AEh Receive down code definition register 1.
0AFh Receive up code definition register 2.
Receive Spare Code Register 1 (T1RSCD1) 09Ch Receive spare code register 1.
Receive Spare Code Register 2 (T1RSCD2) 09Dh Receive spare code register 2.
Receive Real-Time Status Register 3 (RRTS3) 0B2h Real-time loop code detect.
Receive Latched Status Register 3 (RLS3) 092h Latched loop code detect bits.
Receive Interrupt Mask Register 3 (RIM3) 0A2h Mask for latched loop code detect bits.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and
“loop-down” code detection. The user programs the codes to be detected in the Receive Up Code Definition
registers (T1RUPCD1
T1RDNCD2
). The length of each pattern is selected via the Receive In-Band Code Control register (T1RIBCC).
There is a third detector (Spare) and it is defined and controlled via the T1RSCD1
and T1RUPCD2) and the Receive Down Code Definition registers (T1RDNCD1 and
/T1RSCD2 and T1RSCC
registers. When detecting a 16-bit pattern, both receive code definition registers are used together to form a 16-bit
register. For 8-bit patterns, both receive code definition registers are filled with the same value. Detection of a 1-,
2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer
detects repeating pattern codes in both framed and unframed circumstances with bit-error rates as high as 10E-2.
The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of the
receive code definition register resets the integration period for that detector. The code detector has a nominal
integration period of 48ms. Thus, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and
LSP) is set to 1. Note that real-time status bits, as well as latched set and clear bits, are available for LUP, LDN,
and LSP (RRTS3
and RLS3). Normally codes are sent for a period of 5 seconds. It is recommended that the
software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously
present.
64 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.9.17 Framer Payload Loopbacks
The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3).
Table 8-32. Registers Related to Framer Payload Loopbacks
RECEIVE CONTROL
REGISTER 3 (RCR3
)
Framer Loopback 083h Transmit data output from the framer is looped back to the receiver.
Payload Loopback 083h The 192-bit payload data is looped back to the transmitter.
Remote Loopback 083h Data recovered by the receiver is looped back to the transmitter.
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
FRAMER
ADDRESSES
FUNCTION
65 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.10 HDLC Controllers
8.10.1 Receive HDLC Controller
The DS26524 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as
specific Sa bits (E1 mode).
The HDLC controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC
controller automatically generates and detects flags, generates and checks the CRC check sum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 8-33
shows the registers related to the HDLC.
Table 8-33. Registers Related to the HDLC
REGISTER
Receive HDLC Control Register (RHC) 010h Mapping of the HDLC to DS0 or FDL.
Receive HDLC Bit Suppress Register
(RHBSE
Receive HDLC FIFO Control Register
(RHFC)
Receive HDLC Packet Bytes Available
Register (RHPBA)
Receive HDLC FIFO Register (RHF) 0B6h The actual FIFDO data.
Receive Real-Time Status Register 5
(RRTS5)
Receive Latched Status Register 5 (RLS5) 094h Latched status.
Receive Interrupt Mask Register 5 (RIM5) 0A4h
Transmit HDLC Control Register 1(THC1) 110h Miscellaneous transmit HDLC control.
Transmit HDLC Bit Suppress Register
(THBSE
Transmit HDLC Control Register 2 (THC2) 113h
Transmit HDLC FIFO Control Register
(THFC
Transmit Real-Time Status Register 2
(TRTS2
Transmit HDLC Latched Status Register 2
(TLS2)
Transmit Interrupt Mask Register 2 (HDLC)
Register (TIM2
Transmit HDLC FIFO Buffer Available
Register (TFBA
Transmit HDLC FIFO Register (THF) 1B4h Transmit HDLC FIFO.
)
)
)
)
)
)
FRAMER
ADDRESSES
011h Receive HDLC bit suppression register.
087h
0B5h
0B4h Indicates the FIFO status.
111h
187h Used to control the transmit HDLC FIFO.
1B1h
191h Indicates the FIFO status.
1A1h Interrupt mask for the latched status.
1B3h
Determines the length of the receive HDLC
FIFO.
Tells the user how many bytes are available in
the teceive HDLC FIFO.
Interrupt mask for interrupt generation for the
latched status.
Transmit HDLC bit suppress for bits not to be
used.
HDLC to DS0 channel selection and other
control.
Indicates the real-time status of the transmit
HDLC FIFO.
Indicates the number of bytes that can be
written into the transmit FIFO.
FUNCTION
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
66 of 273
8.10.1.1 HDLC FIFO Control
DS26524 Quad T1/E1/J1 Transceiver
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC
Transmit HDLC FIFO Control (THFC
When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5
) registers. The FIFO control registers set the watermarks for the FIFO.
.1) is set. RHWM and THRM are
) and
real-time bits and remain set as long as the FIFO’s write pointer is above the watermark. When the transmit FIFO
empties below the low watermark, the TLWM bit in the TRTS2
register is set. TLWM is a real-time bit and remains
set as long as the transmit FIFO’s write pointer is below the watermark. If enabled, this condition can also cause an
interrupt via the INTB pin.
If the receive HDLC FIFO does overrun, the current packet being processed is dropped. The receive FIFO is
emptied. The packet status bit in RRTS5
and RLS5.5 (ROVR) indicate an overrun.
8.10.1.2 Receive HDLC Packet Bytes Available
The lower 7 bits of the Receive HDLC Packet Bytes Available register (RHPBA
) indicates the number of bytes (0 to
64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many
bytes can be read from the receive FIFO without going past the end of a message. This value refers to one of four
possibilities: the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet.
After reading the number of bytes indicated by this register, the host then checks the HDLC status registers for
detailed message status.
If the value in the RHPBA
register refers to the beginning portion of a message or continuation of a message, then
the MSB of the RHPBA register returns a value of 1. This indicates that the host can safely read the number of
bytes returned by the lower 7 bits of the RHPBA register, but there is no need to check the information register
since the packet has not yet terminated (successfully or otherwise).
8.10.1.3 HDLC Status and Information
RRTS5
, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred
(or is occurring), the appropriate bit in one of these registers is set to 1. Some of the bits in these registers are
latched and some are real-time bits that are not latched. This section contains register descriptions that list which
bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to 1, it remains
set until the user reads and clears that bit. The bit is cleared when a 1 is written to the bit, and it will not be set
again until the event has occurred again. The real-time bits report the current instantaneous conditions that are
occurring and the history of these bits is not latched.
Like the other latched status registers, the user follows a read of the status bit with a write. The byte written to the
register informs the device which of the latched bits the user wishes to clear (the real-time bits are not affected by
writing to the status register). The user writes a byte to one of these registers, with a 1 in the bit positions he or she
wishes to clear and a 0 in the bit positions he or she does not wish to clear.
The HDLC status registers RLS5
and TLS2 have the ability to initiate a hardware interrupt via the INTB output
signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC
interrupt mask registers RIM5
and TIM2. Interrupts force the INTB signal low when the event occurs. The INTB pin
is allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
8.10.1.4 HDLC Receive Example
The HDLC status registers in the DS26524 allow for flexible software interface to meet the user’s preferences.
When receiving HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers,
or a combination of polling and interrupt processes can be used. An example routine for using the DS26524 HDLC
receiver is given in Figure 8-9
.
67 of 273
Figure 8-9. Receive HDLC Example
Configure Receive
HDLC Controller
(RHC, RHBSE, RHFC)
Reset Receive
HDLC Controller
(RHC.6)
Start New
Start New
Message Buffer
Message Buffer
Enable Interrupts
RPE and RHWM
Interrupt?
No Action Required
NO
Work Another Process.
DS26524 Quad T1/E1/J1 Transceiver
Start New
Start New
Message Buffer
Message Buffer
NO
(MS = RHPBA[7])
Read N Bytes From
Rx HDLC FIFO (RHF)
N = RHPBA[5..0]
Read RRTS5 for
Packet Status (PS2..0)
Take appropriate action
YES
Read Register
RHPBA
MS = 1?
Rx HDLC FIFO (RHF)
YES
Read N Bytes From
N = RHPBA[5..0]
68 of 273
8.10.2 Transmit HDLC Controller
8.10.2.1 FIFO Information
DS26524 Quad T1/E1/J1 Transceiver
The Transmit HDLC FIFO Buffer Available register (TFBA
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
8.10.2.2 HDLC Transmit Example
The HDLC status registers in the DS26524 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used. An example routine for using the
DS26524 HDLC receiver is given in Figure 8-10
.
) indicates the number of bytes that can be written into
69 of 273
Figure 8-10. HDLC Message Transmit Example
DS26524 Quad T1/E1/J1 Transceiver
Configure Transmit
HDLC Controller
(THC1,THC2,THBSE,THFC)
Reset Transmit
HDLC Controller
(THC.5)
Loop N
Enable TLWM
Interrupt and
Verify TLWM Clear
Read TFBA
N = TFBA[6..0]
Push Message Byte
into Tx HDLC FIFO
(THF)
Last Byte of
Message?
YES
Set TEOM
(THC1.2)
Push Last Byte
into Tx FIFO
Enable TMEND
Interrupt
TMEND
Interrupt?
NO
A
A
No Action Required
Work Another Process
NO
TLWM
Interrupt?
YES
Disable TMEND Interrupt
Prepare New
NO
Message
YES
Read TUDR
A
NO
Status Bit
TUDR = 1
YES
Disable TMEND Interrupt
Resend Message
70 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11 Line Interface Units (LIUs)
The DS26524 has four identical LIU transmit and receive front-ends for the four framers. Each LIU contains three
sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and
data recovery; and the jitter attenuator. The DS26524 LIUs can switch between T1 or E1 networks without
changing any external components on either the transmit or receive side. Figure 8-11
circuit for software-selected termination with protection. In this configuration, the device can connect to 100Ω T1
twisted pair, 110Ω J1 twisted pair, 75Ω or 120Ω E1 twisted pair without additional component changes. The signals
between the framer and LIU are not accessible by the user, thus the framer and LIU cannot be separated. The
transmitters have fast high-impedance capability and can be individually powered down.
The DS26524’s transmit waveforms meet the corresponding G.703 and T1.102 specifications. Internal softwareselectable transmit termination is provided for 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1 twisted pair,
and 75Ω E1 coaxial applications. The receiver can connect to 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1
twisted pair, and 75Ω E1 coaxial. The receive LIU can function with a receive signal attenuation of up to 36dB for
T1 mode and 43dB for E1 mode. The receiver sensitivity is programmable from 12dB to 43dB of cable loss. Also, a
monitor gain setting can be enabled to provide 14dB, 20dB, 26dB, and 32dB of resistive gain.
shows a recommended
71 of 273
DS26524 Quad T1/E1/J1 Transceiver
Figure 8-11. Network Connection for Software-Selected Termination—Longitudinal
Protection
3.3 V
0.01 uF 0.1 uF
3.3 V
0.1 uF
0.1 uF
TX
TIP
TX
RING
RX
TIP
RX
RING
F2
F3
F4
F1
S7
S8
S3
S4
S5
S6
T3
T4
T1
2:1
T2
1:1
S1
560 pF
S2
60 60
TTIP
TRING
RTIP
RRING
Dallas
Single Chip Transceiver
or
Line Interface Unit
DVDD
DVSS
TVDD
TVSS
RVDD
RVSS
68 uF
0.1 uF
NAME DESCRIPTION PART MANUFACTURER NOTES
F1 to F4
1.25A Slow Blow Fuse SMP 1.25 Bel Fuse 5
1.25A Slow Blow Fuse F1250T Teccor Electronics 5
S1, S2 25V (max) Transient Suppressor P0080SA MC Teccor Electronics 1, 5
S3 to S6 180V (max) Transient Suppressor P1800SC MC Teccor Electronics 1, 4, 5
S7, S8 40V (max) Transient Suppressor P0300SC MC Teccor Electronics 1, 5
T1 and T2 Transformer 1:1CT and 1:2CT (3.3V, SMT) PE-68678 Pulse Engineering 2, 3, 5
T3 and T4 Dual Common-Mode Choke (SMT) PE-65857 Pulse Engineering 5
Note 1: Changing S7 and S8 to P1800SC devices provides symmetrical voltage suppresion between tip, ring, and ground.
Note 2: The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated
Note 3: Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers.
Note 4: The ground trace connected to the S3/S4 pair and the S5/S6 pair should be at least 50 mils wide to conduct the extra current
Note 5: Alternative component recommendations and line interface circuits can be found by contacting
Note 6: The 560pF on TTIP/TRING must be tuned to your application.
from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes.
from a longitudinal power-cross event.
telecom.support@dalsemi.com
or in Application Note 324, which is available at www.maxim-ic.com/AN324.
72 of 273
DS26524 Quad T1/E1/J1 Transceiver
Table 8-34. Recommended Supply Decoupling
SUPPLY PINS DECOUPLING CAPACITANCE NOTES
DVDD/DVSS
DVDDIO/DVSSIO
ATVDD/ATVSS
ARVDD/ARVSS
ACVDD/ACVSS
0.01µF + 0.1µF + 1µF + 10µF
0.01µF + 0.1µF + 1µF + 10µF
0.1µF (x8) + 1µF (x4) + 10µF (x2)
0.1µF (x8) + 1µF (x4) + 10µF (x2)
0.1µF + 1µF + 10µF
—
—
It is recommended to use one 0.1µF capacitor for
each ATVDD/ATVSS pair (8 total), one 1µF for
every two ATVDD/ATVSS pairs (4 total), and two
10µF capacitors for the analog transmit supply
pins. These capacitors should be located as close
to the intended power pins as possible.
It is recommended to use one 0.1µF capacitor for
each ARVDD/ARVSS pair (8 total), one 1µF for
every two ARVDD/ARVSS pairs (4 total), and two
10µF capacitors for the analog receive supply pins.
These capacitors should be located as close to the
intended power pins as possible.
—
73 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer
coupled into the RTIP and RRING pins of the DS26524. The user has the option to use internal termination,
software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and
data from the analog signal and passes it through the jitter attenuation mux. The DS26524 contains an active filter
that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive
circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to
-43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km
(E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation mux to the
waveshaping circuitry and line driver. The DS26524 drives the E1 or T1 line from the TTIP and TRING pins via a
coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or
short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in Table 8-35
.
Table 8-35. Registers Related to Control of DS26524 LIU
REGISTER
Global Transceiver Control Register 2
(GTCR2)
Global Transceiver Clock Control Register
(GTCCR
)
Global LIU Software Reset Register
(GLSRR)
Global LIU Interrupt Status Register
(GLISR)
Global LIU Interrupt Mask Register
(GLIMR
)
LIU Transmit Receive Control Register
(LTRCR)
LIU Transmit Impedance and Pulse Shape
Selection Register (LTITSR)
LIU Maintenance Control Register (LMCR) 1002h
FRAMER
ADDRESSES
0F2h Global transceiver control.
0F3h
MPS selections, backplane clock
selections
0F5h Software reset control for the LIU.
0FBh Interrupt status bit for each of the 4 LIUs.
0FEh Interrupt mask register for the LIU.
1000h
1001h
T1/J1/E1 selection, output tri-state, loss
criteria.
Transmit pulse shape and impedance
selection.
Transmit maintenance and jitter
attenuation control register.
LIU Real Status Register (LRSR) 1003h LIU real-time status register.
LIU Status Interrupt Mask Register
(LSIMR)
1004h
LIU Latched Status Register (LLSR) 1005h
LIU mask registers based on latched
status bits.
LIU latched status bits related to loss, open
circuit, etc.
LIU Receive Signal Level Register (LRSL) 1006h LIU receive signal level indicator.
LIU Receive Impedance and Sensitivity
Monitor Register (LRISMR
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
)
1007h
LIU impedance match and sensitivity
monitor.
FUNCTION
74 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.2 Transmitter
NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data
passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to
generate transmit waveforms complaint with T1.102 and G.703 pulse templates.
A line driver is used to drive an internal matched impedance circuit for provision of 75Ω, 100Ω, 110Ω, and 120Ω
terminations. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1
applications) via a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used
must meet the specifications listed in Table 8-37
1.544MHz for T1/J1 operation.
The DS26524 drivers have a short-circuit and open-circuit detection driver-fail monitor. The TXENABLE pin can
high impedance the transmitter outputs for protection switching. The individual transmitters can also be placed in
high impedance through register settings. The DS26524 also has functionality for powering down the transmitters
individually. The relevant telecommunications specification compliance is shown in Table 8-36
. The transmitter requires a transmit clock of 2.048MHz for E1 or
.
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters
TRANSMITTER FUNCTION TELECOMMUNICATIONS COMPLIANCE
T1 Telecom Pulse Template Compliance ANSI T1.403
T1 Telecom Pulse Template Compliance ANSI T1.102
Transmit Electrical Characteristics for E1 Transmission
and Return Loss Compliance
ITU-T G.703
Table 8-37. Transformer Specifications
SPECIFICATION RECOMMENDED VALUE
Turns Ratio 3.3V Applications 1:1 (receive) and 1:2 (transmit) ±2%
Primary Inductance
Leakage Inductance
Intertwining Capacitance 40pF maximum
Transmit Transformer DC
Resistance
Receive Transformer DC
Resistance
Primary (Device Side)
Secondary
Primary (Device Side)
Secondary
600µH minimum
1.0µH maximum
1.0Ω maximum
2.0Ω maximum
1.2Ω maximum
1.2Ω maximum
75 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.2.1 Transmit-Line Pulse Shapes
The DS26524 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The
T1/J1 pulse template is shown in Figure 8-12
. The E1 pulse template is shown in Figure 8-13. The transmit pulse
shape can be configured for each LIU on an individual basis. The LIU transmit impedance selection registers can
be used to select an internal transmit terminating impedance of 100Ω for T1, 110Ω for J1 mode, 75Ω or 120Ω for
E1 mode or no internal termination for E1 or T1 mode. The transmit pulse shape and terminating impedance is
selected by LTITSR
registers. The pulse shapes will be complaint to T1.102 and G.703. Pulse shapes are
measured for compliance at the appropriate network interface (NI). For T1 long haul and E1, the pulse shape is
measured at the far end. For T1 short haul, the pulse shape is measured at the near end.
Figure 8-12. T1/J1 Transmit Pulse Templates
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
- 0.1
- 0.2
NORMALIZED AMPLITUDE
- 0.3
- 0.4
- 0.5
T1.102/87, T1.403,
CB 119 (Oct. 79), &
I.431 Template
- 500
DSX - 1 Template (pe r ANSI T1.102-1993
MAXIMUM CURVE
UI
- 0.77
- 0.39
- 0.27
- 0.27
- 0.12
0.00
0.27
0.35
0.93
1.16
- 400
- 300
Time
- 500
- 255
- 175
- 175
- 75
0
175
225
600
750
Amp.
0.05
0.05
0.80
1.15
1.15
1.05
1.05
- 0.07
0.05
0.05
- 100 0 300 500 700
- 200
MINIMUM CURVE
UI
Tim e Amp.
- 0.77
- 500
-
- 0.23
-
- 0.23
- 0.15
-
0.00
0
0.15
100
0.23
150
0.23
150
0.46
300
0.66
430
0.93
600
1.16
750
150
150
100
TIME (ns)
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.20
-0.05
-0.05
200 400 600
100
DS1 Template (per ANSI T1.403-1995
MAXIMUM CURVE
UI Time Amp.
-0.77
-500
-0.39
-255
-0.27
-175
-0.27
-175
-0.12
-75
0.00
0
0.27
175
0.34
225
0.77
600
1.16
750
0.05
0.05
0.80
1.20
1.20
1.05
1.05
-0.05
0.05
0.05
MINIMUM CURVE
UI Time Amp.
-0.77
-500
-0.23
-150
-0.23
-150
-0.15
-100
0.00
0
0.15
100
0.23
150
0.23
150
0.46
300
0.61
430
0.93
600
1.16
750
-0.05
-0.05
0.50
0.95
0.95
0.90
0.50
-0.45
-0.45
-0.26
-0.05
-0.05
76 of 273
Figure 8-13. E1 Transmit Pulse Templates
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
SCALED AMPLITUDE
0.2
0.1
0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
-0.1
-0.2
194ns
219ns
DS26524 Quad T1/E1/J1 Transceiver
269ns
G.703
Template
0
50 100 150 20 0 250-50-100-150-200-250
TIME (ns)
8.11.2.2 Transmit Power-Down
The individual transmitters can be powered down by setting the TPDE bit in the LIU Maintenance Control register
(LMCR
). Note that powering down the transmit LIU results in a high-impedance state for the corresponding TTIP
and TRING pins.
When tansmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference. Data
input from the framer is ignored. AIS can be sent by setting a bit in the LMCR
the corresponding receiver goes into LOS state and the ATAIS bit is set in the LMCR
. Transmit all ones will also be sent if
.
8.11.2.3 Transmit Short-Circuit Detector/Limiter
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is
approximately 25Ω or less. SCS (LRSR
The LIU Latched Status register (LLSR
.2) provides a real-time indication of when the current limiter is activated.
) provides latched versions of the information, which can be used to activate
an interrupt when enabled via the LSIMR register.
8.11.2.4 Transmit Open-Circuit Detector
The DS26524 can also detect when the TTIP or TRING outputs are open circuited. OCS (LRSR
.1) provides a realtime indication of when an open circuit is detected. Register LLSR provides latched versions of the information,
which can be used to activate an interrupt when enabled via the LSIMR
not available in T1 CSU operating modes (LBO5, LBO6, and LBO7).
register. The open-circuit detect feature is
77 of 273
DS26524 Quad T1/E1/J1 Transceiver
8.11.3 Receiver
The DS26524 contains four identical receivers. The four receivers are designed to be fully software-selectable for
E1, T1, and J1 without the need to change any external resistors. The device couples to the receive E1 or T1
twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 8-37
details. Receive termination and sensitivity are user configurable. Receive termination is configurable for 75Ω,
100Ω, 110Ω, or 120Ω termination by setting the appropriate RIMPM[1:0] bits (LRISMR
termination feature, the resistors labeled Rr in Figure 8-11
the resistors need to be 37.5Ω, 50Ω, or 60Ω each depending on the line impedance. Receive sensitivity is
configurable by setting the appropriate RSMS[1:0] bits (LRISMR
The DS26524 uses a digital clock recovery system. The resultant E1, T1, or J1 clock derived from MCLK is
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the
clock from the PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This
oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in
Figure 8-15
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. If the jitter attenuator (LTRCR
(as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If
the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter
high cycles of the clock. This is due to the highly oversampled digital clock recovery circuitry. See Table 12-2
more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition occurs and the
RCLK is derived from the JACLK source.
.
should be 60Ω each. If external termination is required,
).
). When using the internal
) is placed in the receive path
for transformer
for
8.11.3.1 Receive Level Indicator
The DS26524 reports the signal strength at RTIP and RRING in approximately 2.5dB increments via RSL[3:0]
located in the LIU Receive Signal Level register (LRSL
performance problems.
8.11.3.2 Receive G.703 Section 10 Synchronization Signal
The DS26524 can receive a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T
G.703. To use this mode, set the receive G.703 clock-enable bit RG703 (LRISMR
Impedance and Sensitivity Monitor register (LRISMR
8.11.3.3 Receiver Monitor Mode
The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation
caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to
32dB, along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Impedance and Sensitivity
Monitor register (LRISMR
).
).
). This feature is helpful when trouble shooting line
.7) found in the LIU Receive
78 of 273
Figure 8-14. Typical Monitor Application
T1/E1 LINE
PRIMARY
T1/E1 TERMINATING
DEVICE
DS26524 Quad T1/E1/J1 Transceiver
Rm
Rm
MONITOR
PORT JACK
X
F
M
R
SECONDARY T1/E1
TERMINATING
DEVICE
Rt
DS26524
8.11.3.4 Loss of Signal (LOS)
The DS26524 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for
T1/J1 and ITU-T G.775, or ETS 300 233 for E1 mode of operation.
Loss of signal (LOS) is detected if the receiver level falls below a threshold analog voltage for certain duration.
Alternatively, this can be termed as having received “0s” for a certain duration. The signal level and timing duration
are defined in accordance with the ANSI T1.231, ITU-T G.775, or ETS 300 233 specifications.
For short-haul mode, the loss-detection thresholds are based on cable loss of 12dB to 18dB for both T1/J1 and E1
modes. The loss thresholds are selectable based on Table 9-19
. For long-haul mode, the LOS detection threshold
is based on cable loss of 30dB to 38dB for T1/J1 and 30dB to 45dB for E1 mode. Note there is no explicit bit called
short-haul mode selection. Loss declaration level is set at 3dB lower that the maximum sensitivity setting
programmed in Table 9-19
.
The loss state is exited when the receiver detects a certain ones density at the maximum sensitivity level or higher,
which is 3dB higher than the loss-detection level. The loss-detection signal level and loss-reset signal level are
defined with hysteresis to prevent the receiver from bouncing between “LOS” and “no LOS” states. Table 8-38
outlines the specifications governing the loss function.
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications
CRITERIA
Loss
Detection
Loss Reset
ANSI T1.231 ITU-T G.775 ETS 300 233
No pulses are detected for 175
±75 bits.
Loss is terminated if a duration
of 12.5% ones are detected
over duration of 175 ±75 bits.
Loss is not terminated if 8
consecutive zeros are found if
B8ZS encoding is used. If
B8ZS is not used, loss is not
terminated if 100 consecutive
pulses are zero.
No pulses are detected for
duration of 10 to 255-bit
periods.
The incoming signal has
transitions for duration of 10 to
255-bit periods.
STANDARD
No pulses are detected for a
duration of 2048-bit periods or
1ms.
Loss reset criteria are not
defined.
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DS26524 Quad T1/E1/J1 Transceiver
8.11.3.5 ANSI T1.231 for T1 and J1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19
) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be
declared at 15dB. LOS is reset if the following criteria are met:
1) 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and
RRING.
2) During the 192 bits, fewer than 100 consecutive zeros are detected.
For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on
Table 9-19
) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level
will be 33dB. LOS is reset if the following criteria are met:
1) 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and
RRING.
2) During the 192 bits, fewer than 100 consecutive zeros are detected.
8.11.3.6 ITU-T G.775 for E1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19
) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be
declared at 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity
level for a duration of 192-bit periods.
For long-haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on
Table 9-19
) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level
will be 33dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for
a duration of 192-bit periods.
8.11.3.7 ETS 200 233 for E1 Modes
For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based
on Table 9-19
) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than
or equal to programmed sensitivity level for a duration of 192-bit periods.
For long-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on
Table 9-19
) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or
equal to the programmed sensitivity level for a duration of 192-bit periods.
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DS26524 Quad T1/E1/J1 Transceiver
8.11.4 Jitter Attenuator
The DS26524 contains a jitter attenuator for each LIU that can be set to a depth of 32 or 128 bits via the JADS
(LTRCR
The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used
in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 8-15
can be placed in either the receive path, the transmit path, or disabled by appropriately setting the JAPS1 and
JAPS0 bits in LTRCR
For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied
at MCLK. See the Global Transceiver Clock Control register (GTCCR
requires an accuracy of ±50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy
of ±32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery block or
the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter
attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed in
the transmit side. If the incoming jitter exceeds either 120UI
32 bits), the DS26524 sets the jitter attenuator limit trip set (JALTS) bit in the LIU Latched Status register (LLSR
In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz and in E1 mode it is 0.6Hz.
.4) bit in the LIU Transmit Receive Control register (LTRCR).
.
(buffer depth is 128 bits) or 28UI
P-P
. The jitter attenuator
) for MCLK options. ITU-T specification G.703
(buffer depth is
P-P
.3).
The DS26524 jitter attenuator is complaint with the following specifications shown in Table 8-39
Table 8-39. Jitter Attenuator Standards Compliance
STANDARD
ITU-T I.431, G.703, G.736, G.823
ETS 300 011, TBR 12/13
AT&T TR62411, TR43802
TR-TSY-009, TR-TSY-253, TR-TSY-499
Figure 8-15. Jitter Attenuation
0dB
ITU G.7XX
Prohibited Area
TR 62411 (Dec. 90)
Prohibited Area
-20dB
-40dB
JITTER ATTENUATION (dB)
Prohibited
C
u
r
v
e
B
TBR12
Area
T1E1
C
u
r
v
e
A
.
-60dB
1 10 100 1K 10K
FREQUENCY (Hz)
100K
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DS26524 Quad T1/E1/J1 Transceiver
8.11.5 LIU Loopbacks
The DS26524 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote
loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are
inputs/outputs from the framer. Note that the framer input/output can be in IBO mode where a single TSER/RSER
can be shared by up to eight framers.
8.11.5.1 Analog Loopback
The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at
RTIP and RRING is ignored in analog loopback. This is shown in Figure 8-16
.
Figure 8-16. Analog Loopback
TCLK
TSER
TRANSMIT
FRAMER
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
TRANSMIT
ANALOG
LINE
DRIVER
RCLK
RSER
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
RECEIVE
DIGITAL
RECEIVE
ANALOG
RTIP
RRING
8.11.5.2 Local Loopback
The transmit system data (the internal signals TPOS, TNEG, and TCLK) is looped back to receive-side inputs to
the receive jitter attenuator. The data is also output on TTIP and TRING. Signals at RTIP and RRING are ignored.
This loopback is conceptually shown in Figure 8-17
.
Figure 8-17. Local Loopback
TCLK
TSER
RCLK
RSER
TRANSMIT
FRAMER
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
RECEIVE
DIGITAL
TRANSMIT
ANALOG
RECEIVE
ANALOG
LINE
DRIVER
TTIP
TRING
RTIP
RRING
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DS26524 Quad T1/E1/J1 Transceiver
8.11.5.3 Remote Loopback
The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer
are ignored during a remote loopback. This loopback is conceptually shown in Figure 8-18
.
Figure 8-18. Remote Loopback
TCLK
TCLK
TSER
TSER
RCLK
RCLK
RSER
RSER
TRANSMIT
TRANSMIT
FRAMER
FRAMER
RECEIVE
RECEIVE
FRAMER
FRAMER
OPTIONAL JITTER
OPTIONAL
ATTENUATOR
JITTER
ATTENUATOR
OPTIONAL
JITTER
OPTIONAL JITTER
ATTENUATOR
ATTENUATOR
8.11.5.4 Dual Loopback
TRANSMIT
TRANSMIT
DIGITAL
DIGITAL
RECEIVE
DIGITAL
RECEIVE
DIGITAL
TRANSMIT
TRANSMIT
ANALOG
ANALOG
RECEIVE
ANALOG
RECEIVE
ANALOG
LINE
LINE
DRIVER
DRIVER
TTIP
TTIP
TRING
TRING
RTIP
RTIP
RRING
RRING
The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer
are looped back to the receiver with the optional jitter attenuator. This loopback is invoked if RLB and LLB are both
set in the LIU Maintenance Control register (LMCR
). This loopback is conceptually shown in Figure 8-19.
Figure 8-19. Dual Loopback
TCLK
TSER
RCLK
RSER
TRANSMIT
FRAMER
RECEIVE
FRAMER
OPTIONAL
JITTER
ATTENUATOR
OPTIONAL
JITTER
ATTENUATOR
TRANSMIT
DIGITAL
RECEIVE
DIGITAL
TRANSMIT
ANALOG
RECEIVE
ANALOG
LINE
DRIVER
TTIP
TRING
RTIP
RRING
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DS26524 Quad T1/E1/J1 Transceiver
8.12 Bit-Error-Rate Test (BERT) Function
The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns. It is
used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers.
Table 8-40
shows the registers related to the configure, control, and status of the BERT.
Table 8-40. Registers Related to BERT Configure, Control, and Status
REGISTER
Global BERT Interrupt Status Register
(GBISR
)
Global BERT Interrupt Mask Register
(GBIMR
)
Receive Expansion Port Control Register
(RXPC)
Receive BERT Port Bit Suppress Register
(RBPBS
)
Receive BERT Port Channel Select
Registers 1 to 4 (RBPCS1
:RBPCS4)
Transmit Expansion Port Control Register
(TXPC)
Transmit BERT Port Bit Suppress
Register (TBPBS)
Transmit BERT Port Channel Select
Registers 1 to 4 (TBPCS1:TBPCS4)
BERT Alternating Word Count Rate
Register (BAWC
)
BERT Repetitive Pattern Set Register 1
(BRP1)
BERT Repetitive Pattern Set Register 2
(BRP2)
BERT Repetitive Pattern Set Register 3
(BRP3
)
BERT Repetitive Pattern Set Register 4
(BRP4)
FRAMER
ADDRESSES
0FAh
0FDh
When any of the four BERTs issue an
interrupt, a bit is set.
When any of the four BERTs issue an
interrupt, a bit is set.
FUNCTION
08Ah Enable for the receiver BERT.
08Bh Bit suppression for the receive BERT.
0D4h, 0D5h, 0D6h,
0D7h
Channels to be enabled for the framer to
accept data from the BERT pattern generator.
18Ah Enable for the transmitter BERT
18Bh Bit suppression for the transmit BERT
1D4h, 1D5h, 1D6h,
1D7h
Channels to be enabled for the framer to
accept data from the transmit BERT pattern
generator.
1100h BERT alternating pattern count register.
1101h BERT repetitive pattern set register 1.
1102h BERT repetitive pattern set register 2.
1103h BERT repetitive pattern set register 3.
1104h BERT repetitive pattern set register 4.
BERT Control Register 1 (BC1) 1105h Pattern selection and miscellaneous control.
BERT Control Register 2 (BC2) 1106h BERT bit pattern length control.
BERT Bit Count Register 1 (BBC1) 1107h
BERT bit counter—increments for BERT bit
clocks.
BERT Bit Count Register 2 (BBC2) 1108h BERT bit counter.
BERT Bit Count Register 3 (BBC3) 1109h BERT bit counter.
BERT Bit Count Register 4 (BBC4) 110Ah BERT bit counter.
BERT Error Count Register 1 (BEC1) 110Bh BERT error counter.
BERT Error Count Register 2 (BEC2) 110Ch BERT error counter.
BERT Error Count Register 3 (BEC3) 110Dh BERT error counter.
BERT Latched Status Register (BLSR) 110Eh
BERT Status Interrupt Mask Register
(BSIM
)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 4 can be calculated using the following framer: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 4 for Framers 2 to 4.
110Fh BERT Interrupt mask.
BERT status registers—denotes
synchronization loss and other status.
84 of 273
DS26524 Quad T1/E1/J1 Transceiver
The BERT block can generate and detect the following patterns:
• The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS
• A repetitive pattern from 1 to 32 bits in length
• Alternating (16-bit) words that flip every 1 to 256 words
• Daly pattern
The BERT function must be enabled and configured in the TXPC
then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel
function in the TBPCS1
suppressed with the TBPBS
be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive
bandwidth assignments are independent of each other.
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver can generate interrupts
on: a change in receive-synchronizer status, receive all zeros, receive all ones, error counter overflow, bit counter
overflow, and bit error detection. Interrupts from each of these events can be masked within the BERT function via
the BERT Status Interrupt Mask register (BSIM
the software must read the BERT Latched Status register (BLSR) to determine which event(s) has occurred.
:TBPCS4 and RBCS1:RBCS4 registers. Individual bit positions within the channels can be
and RBPBS registers. Using combinations of these functions, the BERT pattern can
). If the software detects that the BERT has reported an event, then
and RXPC registers for each port. The BERT can
8.12.1 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a
pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32
bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern
was the repeating 5-bit pattern …01101… (where the rightmost bit is the one sent first and received first), then
BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a
pseudorandom pattern, all four registers should be loaded with all ones (i.e., FFh). For an alternating word pattern,
one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For
example, if the DDS stress pattern “7E” is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in
BRP3, and 7Eh in BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h
followed by 100 bytes of 7Eh to be sent and received.
8.12.2 BERT Error Counter
Once the BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error.
Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO
status bit in the BLSR
register.
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DS26524 Quad T1/E1/J1 Transceiver
9. DEVICE REGISTERS
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor octal framer product, DS26528 and DS26401.
The registers control functions of the framers, LIU, and BERT within the DS26524. The map is divided into four
framers, followed by four LIUs and four BERTs. Global registers (applicable to all four transceivers and BERTs) are
located within the address space of Framer 1.
The bulk write mode is a special mode to write all four transceivers with one write command (see the GTCR1
register). Figure 9-1 shows the register map.
The register details are provided in the following tables. The framer registers bits are provided for Framer 0, and
address bits A[11:8] determine the framer addressed.
9.1 Register Listings
Table 9-1. Register Address Ranges (in Hex)
CHANNEL
— 00F0–00FF — — — —
CH1 — 0000–00EF 0100–01EF 1000–101F 1100–110F
CH2 — 0200–02EF 0300–03EF 1020–103F 1110–111F
CH3 — 0400–04EF 0500–05EF 1040–105F 1120–112F
CH4 — 0600–06EF 0700–07EF 1060–107F 1130–113F
GLOBAL
REGISTERS
RECEIVE
FRAMER
TRANSMIT
FRAMER
LIU BERT
86 of 273
Figure 9-1. Register Memory Map for the DS26524
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
drs = 0000 0000 0000
drs = 0000 1111 0000
drs = 0001 0000 0000
drs = 0001 1111 0000
drs = 0010 0000 0000
Framer 1 Rx Regs
Global Registers
Framer 1 Tx Regs
Reserved
Framer 2 Regs
DS26524 Quad T1/E1/J1 Transceiver
000
240 Regs
240 Regs
0EF
0F0
0FF
100
1EF
1F0
1FF
200
drs = 0100 0000 0000
drs = 0101 1111 1111
drs = 0110 0000 0000
drs = 0111 1111 1111
drs = 1000 0000 0000
drs = 01111 1111 1111
drs = 10000 0000 0000
drs = 10000 1111 1111
drs = 10001 0000 0000
drs = 10001 0111 1111
3FF
400
Framer 3 Regs
5FF
600
Framer 4 Regs
7FF
800
Reserved
FFF
1000
LIU Regs
10FF
1100
BERT
117F
Reserved
drs = 11111 1111 1111
1FFF
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DS26524 Quad T1/E1/J1 Transceiver
9.1.1 Global Register List
Table 9-2. Global Register List
GLOBAL REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
0F0h GTCR1 Global Transceiver Control Register 1 R/W
0F1h GFCR Global Framer Control Register R/W
0F2h GTCR2 Global Transceiver Control Register 2 R/W
0F3h GTCCR Global Transceiver Clock Control Register R/W
0F4h — Reserved —
0F5h GLSRR Global LIU Software Reset Register R/W
0F6h GFSRR Global Framer and BERT Software Reset Register R/W
0F7h — Reserved —
0F8h IDR Device Identification Register R
0F9h GFISR Global Framer Interrupt Status Register R
0FAh GBISR Global BERT Interrupt Status Register R
0FBh GLISR Global LIU Interrupt Status Register R
0FCh GFIMR Global Framer Interrupt Mask Register R/W
0FDh GBIMR Global BERT Interrupt Mask Register R/W
0FEh GLIMR Global LIU Interrupt Mask Register R/W
01Fh — Reserved —
Note 1: Reserved registers should only be written with all zeros.
Note 2: The global registers are located in the framer address space. The corresponding address space for the other framers is
“Reserved,” and should be initialized with all zeros for proper operation.
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DS26524 Quad T1/E1/J1 Transceiver
9.1.2 Framer Register List
Table 9-3. Framer Register List
Note: Only the Framer 1 address is presented here.The same set of register definitions applies for transceiver 2 to 4 in accordance with the
DS26524 map offsets. Transceiver offset is (n - 1) x 200 hex, where n designates the transceiver in question.
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
000h–00Fh — Reserved —
010h RHC Receive HDLC Control Register R/W
011h RHBSE Receive HDLC Bit Suppress Register R/W
012h RDS0SEL Receive Channel Monitor Select Register R/W
013h RSIGC Receive-Signaling Control Register R/W
014h
015h T1RBOCC Receive BOC Control Register (T1 Mode Only) R/W
016h–01Fh — Reserved —
020h RIDR1 Receive Idle Code Definition Register 1 R/W
021h RIDR2 Receive Idle Code Definition Register 2 R/W
022h RIDR3 Receive Idle Code Definition Register 3 R/W
023h RIDR4 Receive Idle Code Definition Register 4 R/W
024h RIDR5 Receive Idle Code Definition Register 5 R/W
025h RIDR6 Receive Idle Code Definition Register 6 R/W
026h RIDR7 Receive Idle Code Definition Register 7 R/W
027h RIDR8 Receive Idle Code Definition Register 8 R/W
028h RIDR9 Receive Idle Code Definition Register 9 R/W
029h RIDR10 Receive Idle Code Definition Register 10 R/W
02Ah RIDR11 Receive Idle Code Definition Register 11 R/W
02Bh RIDR12 Receive Idle Code Definition Register 12 R/W
02Ch RIDR13 Receive Idle Code Definition Register 13 R/W
02Dh RIDR14 Receive Idle Code Definition Register 14 R/W
02Eh RIDR15 Receive Idle Code Definition Register 15 R/W
02Fh RIDR16 Receive Idle Code Definition Register 16 R/W
030h RIDR17 Receive Idle Code Definition Register 17 R/W
031h RIDR18 Receive Idle Code Definition Register 18 R/W
032h RIDR19 Receive Idle Code Definition Register 19 R/W
033h RIDR20 Receive Idle Code Definition Register 20 R/W
034h RIDR21 Receive Idle Code Definition Register 21 R/W
035h RIDR22 Receive Idle Code Definition Register 22 R/W
036h RIDR23 Receive Idle Code Definition Register 23 R/W
037h RIDR24 Receive Idle Code Definition Register 24 R/W
038h
039h
03Ah
03B RIDR28 Receive Idle Code Definition Register 28 (E1 Mode) —
03C
03Dh
03Eh
T1RCR2 Receive Control Register 2 (T1 Mode)
E1RSAIMR
Receive Sa-Bit Interrupt Mask Register (E1 Mode)
T1RSAOI1 Receive-Signaling All-Ones Insertion Register 1 (T1 Mode Only)
RIDR25 Receive Idle Code Definition Register 25 (E1 Mode)
T1RSAOI2 Receive-Signaling All-Ones Insertion Register 2 (T1 Mode Only)
RIDR26 Receive Idle Code Definition Register 26 (E1 Mode)
T1RSAOI3 Receive-Signaling All-Ones Insertion Register 3 (T1 Mode Only)
RIDR27 Receive Idle Code Definition Register 27 (E1 Mode)
T1RDMWE1 T1 Receive Digital Milliwatt Enable Register 1 (T1 Mode Only)
RIDR29 Receive Idle Code Definition Register 29 (E1 Mode)
T1RDMWE2 T1 Receive Digital Milliwatt Enable Register 2 (T1 Mode Only)
RIDR30 Receive Idle Code Definition Register 30 (E1 Mode)
T1RDMWE3 T1 Receive Digital Milliwatt Enable Register 3 (T1 Mode Only)
RIDR31 Receive Idle Code Definition Register 31 (E1 Mode)
89 of 273
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
03Fh RIDR32 Receive Idle Code Definition Register 32 (E1 Mode) —
040h RS1 Receive-Signaling Register 1 R
041h RS2 Receive-Signaling Register 2 R
042h RS3 Receive-Signaling Register 3 R
043h RS4 Receive-Signaling Register 4 R
044h RS5 Receive-Signaling Register 5 R
045h RS6 Receive-Signaling Register 6 R
046h RS7 Receive-Signaling Register 7 R
047h RS8 Receive-Signaling Register 8 R
048h RS9 Receive-Signaling Register 9 R
049h RS10 Receive-Signaling Register 10 R
04Ah RS11 Receive-Signaling Register 11 R
04Bh RS12 Receive-Signaling Register 12 R
04Ch RS13 Receive-Signaling Register 13 (E1 Mode only) —
04Dh RS14 Receive-Signaling Register 14 (E1 Mode only) —
04Eh RS15 Receive-Signaling Register 15 (E1 Mode only) —
04Fh RS16 Receive-Signaling Register 16 (E1 Mode only) —
050h LCVCR1 Line Code Violation Count Register 1 R
051h LCVCR2 Line Code Violation Count Register 2 R
052h PCVCR1 Path Code Violation Count Register 1 R
053h PCVCR2 Path Code Violation Count Register 2 R
054h FOSCR1 Frames Out of Sync Count Register 1 R
055h FOSCR2 Frames Out of Sync Count Register 2 R
056h E1EBCR1 E-Bit Counter 1 (E1 Mode Only) R
057h E1EBCR2 E-Bit Counter 2 (E1 Mode Only) R
058h–05Fh — Reserved —
060 RDS0M Receive DS0 Monitor Register R
061 — Reserved —
062h
T1RFDL Receive FDL Register (T1 Mode)
E1RRTS7
Receive Real-Time Status Register 7 (E1 Mode)
R
063h T1RBOC Receive BOC Register (T1 Mode) R
064h
065h
066h
T1RSLC1 Receive SLC-96 Data Link Register 1 (T1 Mode)
E1RAF
E1 Receive Align Frame Register (E1 Mode)
T1RSLC2 Receive SLC-96 Data Link Register 2 (T1 Mode)
E1RNAF
E1 Receive Non-Align Frame Register (E1 Mode)
T1RSLC3 Receive SLC-96 Data Link Register 3 (T1 Mode)
E1RSiAF
E1 Received Si Bits of the Align Frame Register (E1 Mode)
R
R
R
067h E1RSiNAF Received Si Bits of the Non-Align Frame Register (E1 Mode) R
068h E1RRA Received Remote Alarm Register (E1 Mode) R
069h E1RSa4 E1 Receive Sa4 Bits Register (E1 Mode Only) R
06Ah E1RSa5 E1 Receive Sa5 Bits Register (E1 Mode Only) R
06Bh E1RSa6 E1 Receive Sa6 Bits Register (E1 Mode Only) R
06Ch E1RSa7 E1 Receive Sa7 Bits Register (E1 Mode Only) R
06Dh E1RSa8 Receive Sa8 Bits Register (E1 Mode Only) R
06Eh SaBITS E1 Receive SaX Bits Register R
06Fh Sa6CODE Received Sa6 Codeword Register R
070h–07Fh — Reserved —
080h RMMR Receive Master Mode Register R/W
081h
082h
RCR1 Receive Control Register 1 (T1 Mode)
Receive Control Register 1 (E1 Mode)
RCR1
T1RIBCC Receive In-Band Code Control Register (T1 Mode)
E1RCR2
Receive Control Register 2 (E1 Mode)
R/W
R/W
90 of 273
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
083h RCR3 Receive Control Register 3 R/W
084h RIOCR Receive I/O Configuration Register R/W
085h RESCR Receive Elastic Store Control Register R/W
086h ERCNT Error-Counter Configuration Register R/W
087h RHFC Receive HDLC FIFO Control Register R/W
088h RIBOC Receive Interleave Bus Operation Control Register R/W
089h T1RSCC In-Band Receive Spare Control Register (T1 Mode Only) R/W
08Ah RXPC Receive Expansion Port Control Register R/W
08B RBPBS Receive BERT Port Bit Suppress Register R/W
08Ch–08Fh — Reserved —
090h RLS1 Receive Latched Status Register 1 R/W
091h RLS2 Receive Latched Status Register 2 R/W
092h RLS3 Receive Latched Status Register 3 R/W
093 RLS4 Receive Latched Status Register 4 R/W
094h RLS5 Receive Latched Status Register 5 (HDLC) R/W
095h — Reserved —
096h
RLS7 Receive Latched Status Register 7 (T1 Mode)
Receive Latched Status Register 7 (E1 Mode)
RLS7
R/W
097h — Reserved —
098h RSS1 Receive-Signaling Status Register 1 R/W
099h RSS2 Receive-Signaling Status Register 2 R/W
09Ah RSS3 Receive-Signaling Status Register 3 R/W
09Bh RSS4 Receive-Signaling Status Register 4 (E1 Mode Only) R/W
09Ch T1RSCD1 Receive Spare Code Definition Register 1 (T1 Mode Only) R/W
09Dh T1RSCD2 Receive Spare Code Definition Register 2 (T1 Mode Only) R/W
09Eh — Reserved —
09Fh RIIR Receive Interrupt Information Register R/W
0A0h RIM1 Receive Interrupt Mask Register 1 R/W
0A1h RIM2 Receive Interrupt Mask Register 2 (E1 Mode Only) R/W
0A2h
RIM3 Receive Interrupt Mask Register 3 (T1 Mode)
Receive Interrupt Mask Register 3 (E1 Mode)
RIM3
R/W
0A3h RIM4 Receive Interrupt Mask Register 4 R/W
0A4h RIM5 Receive Interrupt Mask Register 5 (HDLC) R/W
0A5h — Reserved —
0A6h RIM7 Receive Interrupt Mask Register 7 (T1 Mode) R/W
0A7h — Reserved —
0A8h RSCSE1 Receive-Signaling Change of State Enable Register 1 R/W
0A9h RSCSE2 Receive-Signaling Change of State Enable Register 2 R/W
0AAh RSCSE3 Receive-Signaling Change of State Enable Register 3 R/W
0ABh RSCSE4 Receive-Signaling Change of State Enable Register 4 (E1 Mode Only) —
0ACh T1RUPCD1 Receive Up Code Definition Register 1 (T1 Mode Only) R/W
0ADh T1RUPCD2 Receive Up Code Definition Register 2 (T1 Mode Only) R/W
0AEh T1RDNCD1 Receive Down Code Definition Register 1 (T1 Mode Only) R/W
0AFh T1RDNCD2 Receive Down Code Definition Register 2 (T1 Mode Only) R/W
0B0h RRTS1 Receive Real-Time Status Register 1 R
0B1h — Reserved —
0B2h
RRTS3 Receive Real-Time Status Register 3 (T1 Mode)
RRTS3
Receive Real-Time Status Register 3 (E1 Mode)
R
0B3h — Reserved —
0B4h RRTS5 Receive Real-Time Status Register 5 (HDLC) R
0B5h RHPBA Receive HDLC Packet Bytes Available Register R
0B6h RHF Receive HDLC FIFO Register R
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DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
0B7h–0BFh — Reserved —
0C0h RBCS1 Receive Blank Channel Select Register 1 R/W
0C1h RBCS2 Receive Blank Channel Select Register 2 R/W
0C2h RBCS3 Receive Blank Channel Select Register 3 R/W
0C3h RBCS4 Receive Blank Channel Select Register 4 (E1 Mode Only) R/W
0C4h RCBR1 Receive Channel Blocking Register 1 R/W
0C5h RCBR2 Receive Channel Blocking Register 2 R/W
0C6h RCBR3 Receive Channel Blocking Register 3 R/W
0C7h RCBR4 Receive Channel Blocking Register 4 (E1 Mode Only) R/W
0C8h RSI1 Receive-Signaling Reinsertion Enable Register 1 R/W
0C9h RSI2 Receive-Signaling Reinsertion Enable Register 2 R/W
0CAh RSI3 Receive-Signaling Reinsertion Enable Register 3 R/W
0CBh RSI4 Receive-Signaling Reinsertion Enable Register 4 (E1 Mode Only) R/W
0CCh RGCCS1 Receive Gapped Clock Channel Select Register 1 R/W
0CDh RGCCS2 Receive Gapped Clock Channel Select Register 2 R/W
0CEh RGCCS3 Receive Gapped Clock Channel Select Register 3 R/W
0CFh RGCCS4 Receive Gapped Clock Channel Select Register (E1 Mode Only) R/W
0D0h RCICE1 Receive Channel Idle Code Enable Register 1 R/W
0D1h RCICE2 Receive Channel Idle Code Enable Register 2 R/W
0D2h RCICE3 Receive Channel Idle Code Enable Register 3 R/W
0D3h RCICE4 Receive Channel Idle Code Enable Register 4 (E1 Mode Only) R/W
0D4h RBPCS1 Receive BERT Port Channel Select Register 1 R/W
0D5h RBPCS2 Receive BERT Port Channel Select Register 2 R/W
0D6h RBPCS3 Receive BERT Port Channel Select Register 3 R/W
0D7h RBPCS4 Receive BERT Port Channel Select Register (E1 Mode Only) R/W
0D8h–0EFh — Reserved —
0F0h–0FFh
Global
Registers
(Section 9.3)
See the Global Register list in Table 9-2
“Reserved” in Framers 2 to 4.
. Note that this space is
R/W
100h–10Fh — Reserved —
110h THC1 Transmit HDLC Control Register 1 R/W
111h THBSE Transmit HDLC Bit Suppress Register R/W
112h — Reserved —
113h THC2 Transmit HDLC Control Register 2 R/W
114h E1TSACR E1 Transmit Sa-Bit Control Register (E1 Mode) R/W
115h–117h — Reserved —
118h SSIE1 Software-Signaling Insertion Enable Register 1 R/W
119h SSIE2 Software-Signaling Insertion Enable Register 2 R/W
11Ah SSIE3 Software-Signaling Insertion Enable Register 3 R/W
11Bh SSIE4 Software-Signaling Insertion Enable Register 4 (E1 Mode Only) R/W
11Ch–11Fh — Reserved —
120h TIDR1 Transmit Idle Code Definition Register 1 R/W
121h TIDR2 Transmit Idle Code Definition Register 2 R/W
122h TIDR3 Transmit Idle Code Definition Register 3 R/W
123h TIDR4 Transmit Idle Code Definition Register 4 R/W
124h TIDR5 Transmit Idle Code Definition Register 5 R/W
125h TIDR6 Transmit Idle Code Definition Register 6 R/W
126h TIDR7 Transmit Idle Code Definition Register 7 R/W
127h TIDR8 Transmit Idle Code Definition Register 8 R/W
128h TIDR9 Transmit Idle Code Definition Register 9 R/W
129h TIDR10 Transmit Idle Code Definition Register 10 R/W
12Ah TIDR11 Transmit Idle Code Definition Register 11 R/W
92 of 273
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
12Bh TIDR12 Transmit Idle Code Definition Register 12 R/W
12Ch TIDR13 Transmit Idle Code Definition Register 13 R/W
12Dh TIDR14 Transmit Idle Code Definition Register 14 R/W
12Eh TIDR15 Transmit Idle Code Definition Register 15 R/W
12Fh TIDR16 Transmit Idle Code Definition Register 16 R/W
130h TIDR17 Transmit Idle Code Definition Register 17 R/W
131h TIDR18 Transmit Idle Code Definition Register 18 R/W
132h TIDR19 Transmit Idle Code Definition Register 19 R/W
133h TIDR20 Transmit Idle Code Definition Register 20 R/W
134h TIDR21 Transmit Idle Code Definition Register 21 R/W
135h TIDR22 Transmit Idle Code Definition Register 22 R/W
136h TIDR23 Transmit Idle Code Definition Register 23 R/W
137h TIDR24 Transmit Idle Code Definition Register 24 R/W
138h TIDR25 Transmit Idle Code Definition Register 25 (E1 Mode Only) R/W
139h TIDR26 Transmit Idle Code Definition Register 26 (E1 Mode Only) R/W
13Ah TIDR27 Transmit Idle Code Definition Register 27 (E1 Mode Only) R/W
13Bh TIDR28 Transmit Idle Code Definition Register 28 (E1 Mode Only) R/W
13Ch TIDR29 Transmit Idle Code Definition Register 29 (E1 Mode Only) R/W
13Dh TIDR30 Transmit Idle Code Definition Register 30 (E1 Mode Only) R/W
13Eh TIDR31 Transmit Idle Code Definition Register 31 (E1 Mode Only) R/W
13Fh TIDR32 Transmit Idle Code Definition Register 32 (E1 Mode Only) R/W
140h TS1 Transmit-Signaling Register 1 R/W
141h TS2 Transmit-Signaling Register 2 R/W
142h TS3 Transmit-Signaling Register 3 R/W
143h TS4 Transmit-Signaling Register 4 R/W
144h TS5 Transmit-Signaling Register 5 R/W
145h TS6 Transmit-Signaling Register 6 R/W
146h TS7 Transmit-Signaling Register 7 R/W
147h TS8 Transmit-Signaling Register 8 R/W
148h TS9 Transmit-Signaling Register 9 R/W
149h TS10 Transmit-Signaling Register 10 R/W
14Ah TS11 Transmit-Signaling Register 11 R/W
14Bh TS12 Transmit-Signaling Register 12 R/W
14Ch TS13 Transmit-Signaling Register 13 R/W
14Dh TS14 Transmit-Signaling Register 14 R/W
14Eh TS15 Transmit-Signaling Register 15 R/W
14Fh TS16 Transmit-Signaling Register 16 R/W
150h TCICE1 Transmit Channel Idle Code Enable Register 1 R/W
151h TCICE2 Transmit Channel Idle Code Enable Register 2 R/W
152h TCICE3 Transmit Channel Idle Code Enable Register 3 R/W
153h TCICE4 Transmit Channel Idle Code Enable Register 4 (E1 Mode Only) R/W
154h–161h — Reserved —
162h T1TFDL Transmit FDL Register (T1 Mode Only) R/W
163h T1TBOC Transmit BOC Register (T1 Mode Only) R/W
164h
165h
166h
T1TSLC1 Transmit SLC-96 Data Link Register 1 (T1 Mode)
E1TAF
Transmit Align Frame Register (E1 Mode)
T1TSLC2 Transmit SLC-96 Data Link Register 2 (T1 Mode)
E1TNAF
Transmit Non-Align Frame Register (E1 Mode)
T1TSLC3 Transmit SLC-96 Data Link Register 3 (T1 Mode)
E1TSiAF
Transmit Si Bits of the Align Frame Register (E1 Mode)
R/W
R/W
R/W
167h E1TSiNAF Transmit Si Bits of the Non-Align Frame Register (E1 Mode Only) R/W
168h E1TRA Transmit Remote Alarm Register (E1 Mode) R/W
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DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
169h E1TSa4 Transmit Sa4 Bits Register (E1 Mode Only) R/W
16Ah E1TSa5 Transmit Sa5 Bits Register (E1 Mode Only) R/W
16Bh E1TSa6 Transmit Sa6 Bits Register (E1 Mode Only) R/W
16Ch E1TSa7 Transmit Sa7 Bits Register (E1 Mode Only) R/W
16Dh E1RSa8 Receive Sa8 Bits Register (E1 Mode Only) R/W
16Eh–17Fh — Reserved —
180h TMMR Transmit Master Mode Register R/W
181h
182h
TCR1 Transmit Control Register 1 (T1 Mode)
Transmit Control Register 1 (E1 Mode)
TCR1
TCR2 Transmit Control Register 2 (T1 Mode)
Transmit Control Register 2 (E1 Mode)
TCR2
R/W
R/W
183h TCR3 Transmit Control Register 3 R/W
184h TIOCR Transmit I/O Configuration Register R/W
185h TESCR Transmit Elastic Store Control Register R/W
186h TCR4 Transmit Control Register 4 (T1 Mode Only) R/W
187h THFC Transmit HDLC FIFO Control Register R/W
188h TIBOC Transmit Interleave Bus Operation Control Register R/W
189h TDS0SEL Transmit DS0 Channel Monitor Select Register R/W
18Ah TXPC Transmit Expansion Port Control Register R/W
18Bh TBPBS Transmit BERT Port Bit Suppress Register R/W
18Ch–18Dh — Reserved —
18Eh TSYNCC Transmit Synchronizer Control Register R/W
18F — Reserved —
190h TLS1 Transmit Latched Status Register 1 R/W
191h TLS2 Transmit Latched Status Register 2 (HDLC) R/W
192h TLS3 Transmit Latched Status Register 3 (Synchronizer) R/W
193h–19Eh — Reserved —
19Fh TIIR Transmit Interrupt Information Register R/W
1A0h TIM1 Transmit Interrupt Mask Register 1 R/W
1A1h TIM2 Transmit Interrupt Mask Register 2 (HDLC) R/W
1A2h TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) R/W
1A3h–1ABh — Reserved —
1ACh T1TCD1 Transmit Code Definition Register 1 (T1 Mode Only) R/W
1ADh T1TCD2 Transmit Code Definition Register 2 (T1 Mode Only) R/W
1AEh–1B0h — Reserved —
1B1h TRTS2 Transmit Real-Time Status Register 2 (HDLC) R
1B2h — Reserved —
1B3h TFBA Transmit HDLC FIFO Buffer Available R
1B4h THF Transmit HDLC FIFO Register W
1B5h–1BhA — Reserved —
1BBh TDS0M Transmit DS0 Monitor Register R
1BCh–1BFh — Reserved —
1C0h TBCS1 Transmit Blank Channel Select Register 1 R/W
1C1h TBCS2 Transmit Blank Channel Select Register 2 R/W
1C2h TBCS3 Transmit Blank Channel Select Register 3 R/W
1C3h TBCS4 Transmit Blank Channel Select Register 4 (E1 Mode Only) R/W
1C4h TCBR1 Transmit Channel Blocking Register 1 R/W
1C5h TCBR2 Transmit Channel Blocking Register 2 R/W
1C6h TCBR3 Transmit Channel Blocking Register 3 R/W
1C7h TCBR4 Transmit Channel Blocking Register 4 (E1 Mode Only) R/W
1C8h THSCS1 Transmit Hardware-Signaling Channel Select Register 1 R/W
1C9h THSCS2 Transmit Hardware-Signaling Channel Select Register 2 R/W
94 of 273
DS26524 Quad T1/E1/J1 Transceiver
FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
1CAh THSCS3 Transmit Hardware-Signaling Channel Select Register 3 R/W
1CBh THSCS4
Transmit Hardware-Signaling Channel Select Register 4 (E1 Mode
Only)
R/W
1CCh TGCCS1 Transmit Gapped-Clock Channel Select Register 1 R/W
1CDh TGCCS2 Transmit Gapped-Clock Channel Select Register 2 R/W
1CEh TGCCS3 Transmit Gapped-Clock Channel Select Register 3 R/W
1CFh TGCCS4 Transmit Gapped-Clock Channel Select Register 4 (E1 Mode Only) R/W
1D0h PCL1 Per-Channel Loopback Enable Register 1 R/W
1D1h PCL2 Per-Channel Loopback Enable Register 2 R/W
1D2h PCL3 Per-Channel Loopback Enable Register 3 R/W
1D3h PCL4 Per-Channel Loopback Enable Register 4 (E1 Mode Only) R/W
1D4h TBPCS1 Transmit BERT Port Channel Select Register 1 R/W
1D5h TBPCS2 Transmit BERT Port Channel Select Register 2 R/W
1D6h TBPCS3 Transmit BERT Port Channel Select Register 3 R/W
1D7h TBPCS4 Transmit BERT Port Channel Select Register 4 (E1 Mode Only) R/W
1D8h–1FFh — Reserved —
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DS26524 Quad T1/E1/J1 Transceiver
9.1.3 LIU and BERT Register List
Table 9-4. LIU Register List
LIU REGISTER LIST
ADDRESS NAME DESCRIPTION
1000h LTRCR LIU Transmit Receive Control Register
1001h LTITSR LIU Transmit Impedance and Pulse Shape Selection Register
1002h LMCR
1003h LRSR LIU Real Status Register
1004h LSIMR LIU Status Interrupt Mask Register
1005h LLSR LIU Latched Status Register
1006h LRSL LIU Receive Signal Level Register
1007 LRISMR LIU Receive Impedance and Sensitivity Monitor Register
1008h–101Fh — Reserved
LIU Maintenance Control Register
Table 9-5. BERT Register List
BERT REGISTER LIST
ADDRESS NAME DESCRIPTION
1100h BAWC BERT Alternating Word Count Rate Register
1101h BRP1 BERT Repetitive Pattern Set Register 1
1102h BRP2 BERT Repetitive Pattern Set Register 2
1103h BRP3 BERT Repetitive Pattern Set Register 3
1104h BRP4 BERT Repetitive Pattern Set Register 4
1105h BC1 BERT Control Register 1
1106h BC2 BERT Control Register 2
1107h BBC1 BERT Bit Count Register 1
1108h BBC2 BERT Bit Count Register 2
1109h BBC3 BERT Bit Count Register 3
110Ah BBC4 BERT Bit Count Register 4
110Bh BEC1 BERT Error Count Register 1
110Ch BEC2 BERT Error Count Register 2
110Dh BEC3 BERT Error Count Register 3
110Eh BLSR BERT Latched Status Register
110Fh BSIM BERT Status Interrupt Mask Register
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DS26524 Quad T1/E1/J1 Transceiver
9.2 Register Bit Maps
9.2.1 Global Register Bit Map
Table 9-6. Global Register Bit Map
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0F0h GTCR1 — — RLOFLTS GIBO — BWE GCLE GIPI
0F1h GFCR IBOMS1 IBOMS0 BPCLK1 BPCLK0 RFLOSSFS RFMSS TCBCS RCBCS
0F2h GTCR2 — — — — — LOSS
0F3h GTCCR
0F4h — — — — — — — — —
0F5h GLSRR
0F6h GFSRR
0F7h — — — — — — — — —
0F8h IDR ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0F9h GFISR — — — —
0Fah GBISR — — — —
0FBh GLISR — — — —
0FCh GFIMR — — — —
0FDh GBIMR — — — —
0FEh GLIMR — — — —
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0
— — — LSRST4 LSRST3 LSRST2
—
— — — FSRST4 FSRST3 FSRST2
—
BFREQSEL FREQSEL MPS1 MPS0
FIS4 FIS3 FIS2
BIS4 BIS3 BIS2
LIS4 LIS3 LIS2
FIM4 FIM3 FIM2
BIM4 BIM3 BIM2
LIM4 LIM3 LIM2
TSSYNCIOSEL
—
LSRST1
FSRST1
FIS1
BIS1
LIS1
FIM1
BIM1
LIM1
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DS26524 Quad T1/E1/J1 Transceiver
9.2.2 Framer Register Bit Map
Table 9-7 contains the framer registers of the DS26524. Some registers have dual functionality based on the
selection of T1/J1 or E1 operating mode in the RMMR
and TMMR registers. These dual-function registers are
shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is
the bit functionality in E1 mode, in italics. Bits that are not used for an operating mode are noted with a dash “—“.
When there is only one set of bit definitions listed for a register, the bit functionality does not change with respect to
the selection of T1/J1 or E1 mode. All registers not listed are reserved and should be initialized with a value of 00h
for proper operation. The addresses shown are for Framer 1. Addresses for Framer 2 to 4 can be calculated using
the following formula: Address for Framer N = (Framer 1 address + (N - 1) x 200h).
Table 9-7. Framer Register Bit Map
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
010h RHC RCRCD RHR RHMS RHCS4 RHCS3 RHCS2 RHCS1 RHCS0
011h RHBSE BSE8 BSE7 BSE6 BSE5 BSE4 BSE3 BSE2 BSE1
012h RDS0SEL — — — RCM4 RCM3 RCM2 RCM1 RCM0
013h RSIGC
014h
015h T1RBOCC RBR — RBD1 RBD0 — RBF1 RBF0 —
020h RIDR1 C7 C6 C5 C4 C3 C2 C1 C0
021h RIDR2 C7 C6 C5 C4 C3 C2 C1 C0
022h RIDR3 C7 C6 C5 C4 C3 C2 C1 C0
023h RIDR4 C7 C6 C5 C4 C3 C2 C1 C0
024h RIDR5 C7 C6 C5 C4 C3 C2 C1 C0
025h RIDR6 C7 C6 C5 C4 C3 C2 C1 C0
026h RIDR7 C7 C6 C5 C4 C3 C2 C1 C0
027h RIDR8 C7 C6 C5 C4 C3 C2 C1 C0
028h RIDR9 C7 C6 C5 C4 C3 C2 C1 C0
029h RIDR10 C7 C6 C5 C4 C3 C2 C1 C0
02Ah RIDR11 C7 C6 C5 C4 C3 C2 C1 C0
02Bh RIDR12 C7 C6 C5 C4 C3 C2 C1 C0
02Ch RIDR13 C7 C6 C5 C4 C3 C2 C1 C0
02Dh RIDR14 C7 C6 C5 C4 C3 C2 C1 C0
02Eh RIDR15 C7 C6 C5 C4 C3 C2 C1 C0
02Fh RIDR16 C7 C6 C5 C4 C3 C2 C1 C0
030h RIDR17 C7 C6 C5 C4 C3 C2 C1 C0
031h RIDR18 C7 C6 C5 C4 C3 C2 C1 C0
032h RIDR19 C7 C6 C5 C4 C3 C2 C1 C0
033h RIDR20 C7 C6 C5 C4 C3 C2 C1 C0
034h RIDR21 C7 C6 C5 C4 C3 C2 C1 C0
035h RIDR22 C7 C6 C5 C4 C3 C2 C1 C0
036h RIDR23 C7 C6 C5 C4 C3 C2 C1 C0
037h RIDR24 C7 C6 C5 C4 C3 C2 C1 C0
038h
039h
03Ah
T1RCR2 — — — RSLC96 OOF2 OOF1 RAIIE RD4RM
E1RSAIMR
T1RSAOI1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RIDR25 C7 C6 C5 C4 C3 C2 C1 C0
T1RSAOI2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RIDR26 C7 C6 C5 C4 C3 C2 C1 C0
T1RSAOI3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RIDR27 C7 C6 C5 C4 C3 C2 C1 C0
— — — RFSA1 — RSFF RSFE RSIE
— — — CASMS — RSFF RSFE RSEI
— — — RSa4IM RSa5IM RSa6IM RSa7IM RSa8IM
98 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
03Bh
03Ch
03Dh
03Eh
03Fh
040h RS1
041h RS2
042h RS3
043h RS4
044h RS5
045h RS6
046h RS7
047h RS8
048h RS9
049h RS10
04Ah RS11
04Bh RS12
04Ch
04Dh
04Eh
04Fh
050h LCVCR1 LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCCV8
051h LCVCR2 LCVC7 LCVC6 LCVC5 LCVC4 LCVC3 LCVC2 LCVC1 LCVC0
052h PCVCR1 PCVC15 PCVC14 PCVC13 PCVC12 PCVC11 PCVC10 PCVC9 PCVC8
053h PCVCR2 PCVC7 PCVC6 PCVC5 PCVC4 PCVC3 PCVC2 PCVC1 PCVC0
054h FOSCR1 FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8
055h FOSCR2 FOS7 FOS6 FOS5 FOS4 FOS3 FOS2 FOS1 FOS0
RIDR28
T1RDMWE1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
RIDR29 C7 C6 C5 C4 C3 C2 C1 C0
T1RDMWE2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
RIDR30 C7 C6 C5 C4 C3 C2 C1 C0
T1RDMWE3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
RIDR31 C7 C6 C5 C4 C3 C2 C1 C0
RIDR32
RS13
RS14
RS15
RS16
—
C7 C6 C5 C4 C3 C2 C1 C0
—
C7 C6 C5 C4 C3 C2 C1 C0
CH1-A CH1-B CH1-C CH1-D CH13-A CH13-B CH13-C CH13-D
0 0 0 0 X Y X X
CH2-A CH2-B CH2-C CH2-D CH14-A CH14-B CH14-C CH14-D
CH1-A CH1-B CH1-C CH1-D CH16-A CH16-B CH16-C CH16-D
CH3-A CH3-B CH3-C CH3-D CH15-A CH15-B CH15-C CH15-D
CH2-A CH2-B CH2-C CH2-D CH17-A CH17-B CH17-C CH17-D
CH4-A CH4-B CH4-C CH4-D CH16-A CH16-B CH16-C CH16-D
CH3-A CH3-B CH3-C CH3-D CH18-A CH18-B CH18-C CH18-D
CH5-A CH5-B CH5-C CH5-D CH17-A CH17-B CH17-C CH17-D
CH4-A CH4-B CH4-C CH4-D CH19-A CH19-B CH19-C CH19-D
CH6-A CH6-B CH6-C CH6-D CH18-A CH18-B CH18-C CH18-D
CH5-A CH5-B CH5-C CH5-D CH20-A CH20-B CH20-C CH20-D
CH7-A CH7-B CH7-C CH7-D CH19-A CH19-B CH19-C CH19-D
CH6-A CH6-B CH6-C CH6-D CH21-A CH21-B CH21-C CH21-D
CH8-A CH8-B CH8-C CH8-D CH20-A CH20-B CH20-C CH20-D
CH7-A CH7-B CH7-C CH7-D CH22-A CH22-B CH22-C CH22-D
CH9-A CH9-B CH9-C CH9-D CH21-A CH21-B CH21-C CH21-D
CH8-A CH8-B CH8-C CH8-D CH23-A CH23-B CH23-C CH23-D
CH10-A CH10-B CH10-C CH10-D CH22-A CH22-B CH22-C CH22-D
CH9-A CH9-B CH9-C CH9-D CH24-A CH24-B CH24-C CH24-D
CH11-A CH11-B CH11-C CH11-D CH23-A CH23-B CH23-C CH23-D
CH10-A CH10-B CH10-C CH10-D CH25-A CH25-B CH25-C CH25-D
CH12-A CH12-B CH12-C CH12-D CH24-A CH24-B CH24-C CH24-D
CH11-A CH11-B CH11-C CH11-D CH26-A CH26-B CH26-C CH26-D
— — — — — — — —
CH12-A CH12-B CH12-C CH12-D CH27-A CH27-B CH27-C CH27-D
— — — — — — — —
CH13-A CH13-B CH13-C CH13-D CH28-A CH28-B CH28-C CH28-D
— — — — — — — —
CH14-A CH14-B CH14-C CH14-D CH29-A CH29-B CH29-C CH29-D
— — — — — — — —
CH15-A CH15-B CH15-C CH15-D CH30-A CH30-B CH30-C CH30-D
— — — — — —
—
— — — — — —
—
99 of 273
DS26524 Quad T1/E1/J1 Transceiver
ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
056h
057h
060h RDS0M B1 B2 B3 B4 B5 B6 B7 B8
061h — — — — — — — — —
062h
063h T1RBOC — — RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0
064h
065h
066h
067h
068h
069h
06Ah
06Bh
06Ch
06Dh
06Eh SaBITS
06Fh Sa6CODE — — — — Sa6n Sa6n Sa6n Sa6n
080h RMMR FRM_EN
081h
082h
083h RCR3 IDF — RSERC — — — PLB FLB
084h RIOCR
085h RESCR RDATFMT RGCLKEN — RSZS RESALGN RESR RESMDM RESE
086h ERCNT
087h RHFC — — — — — — RFHWM1 RFHWM0
088h RIBOC — IBS1 IBS0 IBOSEL IBOEN DA2 DA1 DA0
089h T1RSCC — — — — — RSC2 RSC1 RSC0
08Ah RXPC
08Bh RBPBS BPBSE8 BPBSE7 BPBSE6 BPBSE5 BPBSE4 BPBSE3 BPBSE2 BPBSE1
090h RLS1 RRAIC RAISC RLOSC RLOFC RRAID RAISD RLOSD RLOFD
091h
092h
093h RLS4 RESF RESEM RSLIP — RSCOS 1SEC TIMER RMF
094h RLS5 — — ROVR RHOBT RPE RPS RHWMS RNES
096h
E1EBCR1
E1EBCR2
T1RFDL RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
E1RRTS7
T1RSLC1 C8 C7 C6 C5 C4 C3 C2 C1
E1RAF
T1RSLC2 M2 M1 S=0 S=1 S=0 C11 C10 C9
E1RNAF
T1RSLC3 S=1 S4 S3 S2 S1 A2 A1 M3
E1RSiAF SiF14 SiF12 SiF10 SiF8 SiF6 SiF4 SiF2 SiF0
E1RSiNAF
E1RRA
E1RSa4
E1RSa5
E1RSa6
E1RSa7
E1RSa8
RCR1 (T1) SYNCT RB8ZS RFM ARC SYNCC RJC SYNCE RESYNC
RCR1
T1RIBCC — — RUP2 RUP1 RUP0 RDN2 RDN1 RDN0
E1RCR2
RLS2 (T1) RPDV — COFA 8ZD 16ZD SEFE B8ZS FBE
RLS2
RLS3 (T1) LORCC LSPC LDNC LUPC LORCD LSPD LDND LUPD
RLS3
RLS7 (T1) — — RRAI-CI RAIS-CI RSLC96 RFDLF BC BD
RLS7
EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
CSC5 CSC4 CSC3 CSC2 CSC0 CRC4SA CASSA FASSA
Si 0 0 1 1 0 1 1
Si 1 A Sa4
SiF15 SiF13 SiF11 SiF9 SiF7 SiF5 SiF3 SiF1
RRAF15 RRAF13 RRAF11 RRAF9 RRAF7 RRAF5 RRAF3 RRAF1
RSa4F15 RSa4F13 RSa4F11 RSa4F9 RSa4F7 RSa4F5 RSa4F3 RSa4F1
RSa5F15 RSa5F13 RSa5F11 RSa5F9 RSa5F7 RSa5F5 RSa5F3 RSa5F1
RSa6F15 RSa6F13 RSa6F11 RSa6F9 RSa6F7 RSa6F5 RSa6F3 RSa6F1
RSa7F15 RSa7F13 RSa7F11 RSa7F9 RSa7F7 RSa7F5 RSa7F3 RSa7F1
RSa8F15 RSa8F13 RSa8F11 RSa8F9 RSa8F7 RSa8F5 RSa8F3 RSa8F1
— — —
INIT_DONE
(E1)
RSa8S RSa7S RSa6S RSa5S RSa4S
(E1) — CRCRC CASRC FASRC RSA1 RSA0 RCMF RAF
(E1) LORCC
(E1) — — — — — — Sa6CD SaXCD
—
RCLKINV
RCLKINV
1SECS MCUS MECU ECUS EAMS FSBE MOSCRF LCVCRF
1SECS MCUS MECU ECUS EAMS
— — — —
— — — — —
RHDB3 RSIGM RG802 RCRC4 FRC SYNCE RESYNC
RSYNCINV
RSYNCINV
—
— — — — SFTRST T1/E1
H100EN RSCLKM RSMS RSIO RSMS2 RSMS1
H100EN RSCLKM
V52LNKC RDMAC LORCD
Sa4 Sa5 Sa6 Sa7 Sa8
Sa5
—
— RBPDIR RBPFUS RBPEN
Sa6 Sa7 Sa8
— —
RSIO RSMS2 RSMS1
— —
RBPDIR
—
—
V52LNKD RDMAD
RLOSA
LCVCRF
RBPEN
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