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DS26401
User Manual
309 pgs1.61 Mb0
Table of contents
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MAXIM DS26401 User Manual

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www.maxim-ic.com
GENERAL DESCRIPTION
APPLICATIONS
Line Cards Routers
Add-Drop Multiplexers IMA
DSLAMs ATM
Timing Systems WAN Interface
PBXs
Switches
Central Office Equipment
Go to www.maxim-ic.com/telecom for a complete list of Telecommunications data sheets, evaluation kits, application notes, and software downloads.
Customer-Premise Equipment
DS26401
Octal T1/E1/J1 Frame
FEATURES
§ 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters
§ Independent Transmit and Receive Paths
§ Flexible Signaling Extraction and Insertion
§ Alarm Detection and Insertion
§ Transmit Synchronizer
§ AMI, B8ZS, HDB3, NRZ Line Coding
§ Performance Monitor Counters
§ BOC Message Controller (T1)
§ Two-Frame Elastic Store Buffers for Each
Transmitter and Receiver
§ One HDLC Controller per Framer
§ RAI-CI and AIS-CI Support
§ Full-Feature BERT can be Mapped to Any Port
§ Flexible TDM Backplane Supports Bus Rates
from 1.544MHz to 16.384MHz
§ Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
§ JTAG Test Port
§ Single 3.3V Supply with 5V Tolerant Inputs
§ 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS26401 DS26401N -40°C to +85°C 256 BGA
0°C to +70°C 256 BGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1
REV: 072403
.
DS26401 Octal T1/E1/J1 Framer
TABLE OF CONTENTS
1. APPLICABLE STANDARDS ........................................................................................................7
2. FEATURES ..................................................................................................................................8
2.1 FRAMER/FORMATTER .....................................................................................................................................8
2.2 SYSTEM INTERFACE........................................................................................................................................8
2.3 HDLC CONTROLLERS ....................................................................................................................................9
2.4 TEST AND DIAGNOSTICS .................................................................................................................................9
2.5 CONTROL PORT..............................................................................................................................................9
3. BLOCK DIAGRAMS...................................................................................................................10
4. SIGNAL LIST (SORTED BY SIGNAL NAME)............................................................................13
5. SIGNAL DESCRIPTIONS...........................................................................................................17
5.1 RECEIVE FRAMER SIGNALS...........................................................................................................................17
5.2 TRANSMIT FRAMER SIGNALS.........................................................................................................................19
5.3 PARALLEL CONTROL PORT............................................................................................................................20
5.4 SYSTEM INTERFACE......................................................................................................................................21
5.5 TEST............................................................................................................................................................22
6. REGISTER MAP.........................................................................................................................23
7. GLOBAL FUNCTIONS...............................................................................................................24
7.1 GLOBAL REGISTERS .....................................................................................................................................24
7.2 GLOBAL REGISTER DESCRIPTION AND OPERATION ........................................................................................25
7.3 IBO MULTIPLEXER........................................................................................................................................27
7.4 INTERRUPT TREE ..........................................................................................................................................37
8. T1 RECEIVER ............................................................................................................................38
8.1 T1 RECEIVER REGISTER MAP.......................................................................................................................38
8.2 T1 RECEIVE FRAMER DESCRIPTION AND OPERATION.....................................................................................43
8.3 RECEIVE MASTER-MODE REGISTER..............................................................................................................44
8.4 INTERRUPT INFORMATION REGISTER .............................................................................................................44
8.5 T1 RECEIVE CONTROL REGISTERS ...............................................................................................................45
8.6 H.100 (CT BUS) COMPATIBILITY...................................................................................................................50
8.7 T1 RECEIVE STATUS AND INFORMATION ........................................................................................................52
8.8 T1 RECEIVE-SIDE DIGITAL MILLIWATT CODE GENERATION ............................................................................63
8.9 T1 ERROR COUNT REGISTERS......................................................................................................................64
8.10 DS0 MONITORING FUNCTION ....................................................................................................................69
8.11 T1 RECEIVE SIGNALING OPERATION..........................................................................................................70
8.12 T1 RECEIVE PER-CHANNEL IDLE CODE INSERTION ....................................................................................76
8.13 RECEIVE-CHANNEL BLOCKING OPERATION ................................................................................................77
8.14 RECEIVE ELASTIC STORES OPERATION .....................................................................................................78
8.15 FRACTIONAL T1 SUPPORT (GAPPED-CLOCK MODE)...................................................................................82
8.16 T1 BIT-ORIENTED CODE (BOC) CONTROLLER...........................................................................................83
8.17 RECEIVE SLC-96 OPERATION...................................................................................................................85
8.18 RECEIVE FDL...........................................................................................................................................86
8.19 PROGRAMMABLE IN-BAND LOOP-CODE DETECTION ...................................................................................87
8.20 RECEIVE HDLC CONTROLLER...................................................................................................................92
8.21 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................100
8.22 INTERFACING THE T1 RX FRAMER TO THE BERT .....................................................................................102
9. T1 TRANSMIT..........................................................................................................................104
9.1 T1 TRANSMIT REGISTER MAP .....................................................................................................................104
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DS26401 Octal T1/E1/J1 Framer
T1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION...........................................................................108
9.2
9.3 TRANSMIT-MASTER MODE REGISTER ..........................................................................................................109
9.4 INTERRUPT INFORMATION REGISTERS .........................................................................................................109
9.5 T1 TRANSMIT CONTROL REGISTERS ...........................................................................................................110
9.6 T1 TRANSMIT STATUS AND INFORMATION ....................................................................................................115
9.7 T1 PER-CHANNEL LOOPBACK .....................................................................................................................118
9.8 T1 TRANSMIT DS0 MONITORING FUNCTION ................................................................................................119
9.9 T1 TRANSMIT SIGNALING OPERATION .........................................................................................................120
9.10 T1 TRANSMIT PER-CHANNEL IDLE CODE INSERTION ................................................................................123
9.11 T1 TRANSMIT CHANNEL BLOCKING REGISTERS........................................................................................124
9.12 T1 TRANSMIT ELASTIC STORES OPERATION ............................................................................................125
ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................126
9.13 FRACTIONAL T1 SUPPORT (GAPPED CLOCK MODE) .................................................................................129
9.14 T1 TRANSMIT BIT ORIENTED CODE (BOC) CONTROLLER .........................................................................130
9.15 T1 TRANSMIT FDL..................................................................................................................................131
9.16 TRANSMIT SLC–96 OPERATION ..............................................................................................................132
9.17 TRANSMIT HDLC CONTROLLER...............................................................................................................133
9.18 HDLC TRANSMIT EXAMPLE .....................................................................................................................141
9.19 PROGRAMMABLE IN-BAND LOOP-CODE GENERATOR................................................................................142
9.20 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................144
9.21 INTERFACING THE T1 TX FORMATTER TO THE BERT ................................................................................146
9.22 T1 TRANSMIT SYNCHRONIZER .................................................................................................................148
10. E1 RECEIVER..........................................................................................................................150
10.1 E1 RECEIVER REGISTER MAP .................................................................................................................150
10.2 E1 RECEIVE FRAMER DESCRIPTION AND OPERATION...............................................................................155
10.3 RECEIVE MASTER MODE REGISTER.........................................................................................................156
10.4 INTERRUPT INFORMATION REGISTERS......................................................................................................157
10.5 E1 RECEIVE CONTROL REGISTERS .........................................................................................................158
10.6 H.100 (CT BUS) COMPATIBILITY.............................................................................................................162
10.7 E1 RECEIVE STATUS AND INFORMATION ..................................................................................................164
10.8 E1 ERROR COUNT REGISTERS................................................................................................................175
10.9 DS0 MONITORING FUNCTION ..................................................................................................................181
10.10 E1 RECEIVE SIGNALING OPERATION........................................................................................................182
10.11 E1 RECEIVE PER-CHANNEL IDLE CODE INSERTION ..................................................................................187
10.12 RECEIVE CHANNEL BLOCKING OPERATION...............................................................................................188
10.13 RECEIVE ELASTIC STORES OPERATION ...................................................................................................189
ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................192
10.14 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE).................................................................................193
10.15 ADDITIONAL SA-BIT AND SI-BIT RECEIVE OPERATION (E1 MODE).............................................................194
10.16 RECEIVE HDLC CONTROLLER.................................................................................................................200
HDLC RECEIVE EXAMPLE .....................................................................................................................................207
10.17 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................208
10.18 INTERFACING THE E1 RX FRAMER TO THE BERT .....................................................................................210
11. E1 TRANSMIT..........................................................................................................................212
11.1 E1 TRANSMIT REGISTER MAP .................................................................................................................212
11.2 E1 TRANSMIT FORMATTER DESCRIPTION AND OPERATION .......................................................................216
11.3 TRANSMIT MASTER MODE REGISTER.......................................................................................................217
11.4 INTERRUPT INFORMATION REGISTERS......................................................................................................218
11.5 E1 TRANSMIT CONTROL REGISTERS .......................................................................................................219
11.6 AUTOMATIC ALARM GENERATION ............................................................................................................221
11.7 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)......................................................................223
11.8 E1 TRANSMIT STATUS AND INFORMATION ................................................................................................225
11.9 PER-CHANNEL LOOPBACK.......................................................................................................................228
11.10 E1 TRANSMIT DS0 MONITORING FUNCTION.............................................................................................229
11.11 E1 TRANSMIT SIGNALING OPERATION......................................................................................................230
11.12 E1 TRANSMIT PER-CHANNEL IDLE CODE INSERTION ................................................................................233
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DS26401 Octal T1/E1/J1 Framer
E1 TRANSMIT CHANNEL BLOCKING REGISTERS .......................................................................................234
11.13
11.14 E1 TRANSMIT ELASTIC STORES OPERATION ............................................................................................235
ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................236
11.15 FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE).................................................................................239
11.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 MODE) ....................................................240
11.17 TRANSMIT HDLC CONTROLLER...............................................................................................................247
11.18 HDLC TRANSMIT EXAMPLE .....................................................................................................................255
11.19 INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................256
11.20 INTERFACING THE E1 TRANSMITTER TO THE BERT ..................................................................................258
11.21 E1 TRANSMIT SYNCHRONIZER .................................................................................................................260
12. BERT........................................................................................................................................262
12.1 BERT REGISTERS ..................................................................................................................................262
12.2 BERT DESCRIPTION AND OPERATION .....................................................................................................263
12.3 PATTERN GENERATION ...........................................................................................................................264
12.4 PATTERN SYNCHRONIZATION...................................................................................................................265
12.5 BER CALCULATION.................................................................................................................................265
12.6 ERROR GENERATION ..............................................................................................................................265
12.7 BERT CONTROL REGISTERS ..................................................................................................................267
12.8 BERT STATUS REGISTER .......................................................................................................................271
12.9 PSEUDORANDOM PATTERN REGISTERS ...................................................................................................272
12.10 COUNT REGISTERS .................................................................................................................................274
12.11 RAM ACCESS.........................................................................................................................................275
13. FUNCTIONAL TIMING ............................................................................................................. 276
13.1 DELAYS ..................................................................................................................................................276
13.2 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................................277
13.3 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................282
13.4 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS.........................................................................................286
13.5 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................288
14. OPERATING PARAMETERS...................................................................................................291
15. TIMING.....................................................................................................................................292
15.1 MICROPROCESSOR BUS AC CHARACTERISTICS .......................................................................................292
15.2 RECEIVER AC CHARACTERISTICS............................................................................................................295
15.3 TRANSMIT AC CHARACTERISTICS ............................................................................................................298
15.4 JTAG INTERFACE TIMING .......................................................................................................................301
15.5 SYSTEM CLOCK AC CHARACTERISTICS ...................................................................................................301
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................302
16.1 TAP CONTROLLER STATE MACHINE ........................................................................................................303
16.2 INSTRUCTION REGISTER..........................................................................................................................306
16.3 TEST REGISTERS....................................................................................................................................307
17. PACKAGE INFORMATION ...................................................................................................... 308
18. THERMAL INFORMATION ...................................................................................................... 309
19. REVISION HISTORY................................................................................................................309
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DS26401 Octal T1/E1/J1 Framer
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................10
Figure 3-2. Typical PLL Connection..........................................................................................................................11
Figure 3-3. Typical Bipolar Network-Side Interface to Framers ................................................................................11
Figure 3-4. Typical NRZ Network-Side Interface to Framers....................................................................................12
Figure 7-1. Internal IBO Multiplexer Equivalent Circuit—4.096MHz .........................................................................28
Figure 7-2. Internal IBO Multiplexer Equivalent Circuit—8.192MHz .........................................................................29
Figure 7-3. Internal IBO Multiplexer Equivalent Circuit—16.394MHz ......................................................................30
Figure 8-1. RSYNC Input in H.100 (CT Bus) Mode ..................................................................................................50
Figure 8-2. TSSYNC Input in H.100 (CT Bus) Mode ................................................................................................51
Figure 8-3. Receive HDLC Example........................................................................................................................99
Figure 9-1. HDLC Message Transmit Example .....................................................................................................141
Figure 10-1. RSYNC Input in H.100 (CT Bus) Mode ..............................................................................................162
Figure 10-2. TSSYNC Input in H.100 (CT Bus) Mode ............................................................................................163
Figure 10-3. Receive HDLC Example....................................................................................................................207
Figure 11-1. HDLC Message Transmit Example ....................................................................................................255
Figure 12-1. Shared BERT Block Diagram .............................................................................................................266
Figure 13-1. T1 Receive-Side D4 Timing ...............................................................................................................277
Figure 13-2. T1 Receive-Side ESF Timing .............................................................................................................277
Figure 13-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) .............................................................278
Figure 13-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................278
Figure 13-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................279
Figure 13-6. T1 Receive-Side Interleave Bus Operation, BYTE Mode...................................................................280
Figure 13-7. T1 Receive-Side Interleave Bus Operation, FRAME Mode................................................................281
Figure 13-8. T1 Transmit-Side D4 Timing ..............................................................................................................282
Figure 13-9. T1 Transmit-Side ESF Timing ............................................................................................................282
Figure 13-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) ...........................................................283
Figure 13-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ..........................................283
Figure 13-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................284
Figure 13-13. T1 Transmit-Side Interleave Bus Operation, BYTE Mode................................................................284
Figure 13-14. T1 Transmit Interleave Bus Operation, FRAME Mode.....................................................................285
Figure 13-15. E1 Receive-Side Timing ...................................................................................................................286
Figure 13-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................286
Figure 13-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ...........................................287
Figure 13-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ...........................................287
Figure 13-19. E1 Transmit-Side Timing..................................................................................................................288
Figure 13-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ...........................................................288
Figure 13-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) .........................................289
Figure 13-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ..........................................289
Figure 13-23. E1 G.802 Timing...............................................................................................................................290
Figure 15-1. Intel Bus Read Timing (BTS = 0).......................................................................................................293
Figure 15-2. Intel Bus Write Timing (BTS = 0).......................................................................................................293
Figure 15-3. Motorola Bus Read Timing (BTS = 1) ...............................................................................................294
Figure 15-4. Motorola Bus Write Timing (BTS = 1) ...............................................................................................294
Figure 15-5. Receive Framer Timing—Backplane (T1 Mode) ...............................................................................295
Figure 15-6. Receive-Side Timing—Elastic Store Enabled (T1 Mode)..................................................................296
Figure 15-7. Receive Framer Timing—Line Side ..................................................................................................297
Figure 15-8. Transmit Formatter Timing—Backplane ...........................................................................................299
Figure 15-9. Transmit Formatter Timing, Elastic Store Enabled ...........................................................................300
Figure 15-10. Transmit Formatter Timing—Line Side ...........................................................................................300
Figure 15-11. JTAG Interface Timing Diagram.......................................................................................................301
Figure 16-1. JTAG Functional Block Diagram ........................................................................................................302
Figure 16-2. Tap Controller State Diagram............................................................................................................303
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DS26401 Octal T1/E1/J1 Framer
LIST OF TABLES
Table 7-1. Pin Functions with IBO Mux Enabled ......................................................................................................31
Table 8-1. T1 Alarm Criteria .....................................................................................................................................53
Table 8-2. T1 Line-Code Violation Counting Options ...............................................................................................66
Table 8-3. T1 Path-Code Violation Counting Arrangements ....................................................................................67
Table 8-4. T1 Frames Out-of-Sync Counting Arrangements ....................................................................................68
Table 10-1. E1 Sync/Resync Criteria......................................................................................................................159
Table 10-2. E1 Alarm Criteria .................................................................................................................................165
Table 10-3. E1 Line Code Violation Counting Options ...........................................................................................177
Table 12-1. Pseudo-Random Pattern Generation ..................................................................................................273
Table 13-1. Throughput Delays ..............................................................................................................................276
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture ..................................................................................306
Table 16-2. ID Code Structure ................................................................................................................................307
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DS26401 Octal T1/E1/J1 Framer
1. APPLICABLE STANDARDS
The DS26401 conforms to the applicable parts of the following standards.
SPECIFICATION TITLE
ANSI
T1.102-1993 Digital Hierarchy—Electrical Interfaces T1.107-1995 Digital Hierarchy—Formats Specification T1.231-1997 Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance Monitoring T1.403-1999 Network and Customer Installation Interfaces—DS1 Electrical Interface
AT&T
TR54016
TR62411 High Capacity Digital Service Channel Interface Specification
ITU
G.704, 1995
G.706, 1991
G.732, 1993 Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s G.736, 1993 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s G.775, 1994 Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria
G.823, 1993
I.431, 1993 Primary Rate User-Network Interface—Layer 1 Specification O.151, 1992 Error Performance Measuring Equipment Operating at the Primary Rate and Above O.161, 1988 In-service code violation monitors for digital systems
ETSI
ETS 300 011, 1998
ETS 300 166, 1993
ETS 300 233, 1994 Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate
CTR 4, 1995
I.432, 1993 B-ISDN User-Network Interface—Physical Layer Specification–ITU-T
CTR 12, 1993
CTR 13, 1996
TTC
JT-G.704, 1995 Frame Structures on Primary and Secondary Hierarchical Digital Interfaces
JTI.431, 1995 ISDN Primary Rate User-Network Interface Layer 1 Specification
Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Superframe Format
Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736 kbit/s Hierarchical Levels Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704
The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048kbps Hierarchy
Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1: Layer 1 specification Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048 kbit/s-based plesiochronous or synchronous digital hierarchies
Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access
Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 kbit/s digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface Business Telecommunications (BTC); 2048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface
7
DS26401 Octal T1/E1/J1 Framer
2. FEATURES
2.1 Framer/Formatter
§ Fully Independent Transmit and Receive Functionality
§ Full Receive and Transmit Path Transparency
§ T1 Framing Formats D4 and ESF per T1.403, and Expanded SLC-96 Support (TR-TSY-008)
§ E1 FAS Framing and CRC-4 Multiframe per G.704/G.706 and G.732 CAS Multiframe
§ Detailed Alarm and Status Reporting with Optional Interrupt Support
§ Large Path and Line Error Counters for
T1: BPV, CV, CRC6, and Framing Bit Errors E1: BPV, CV, CRC4, E-Bit, and Frame Alignment Errors Timed or Manual Update Modes
§ DS1 Idle Code Generation on a Per-Channel Basis in Both Transmit and Receive Paths User-Defined Digital Milliwatt
§ ANSI T1.403-1998 Support
§ G.965 V5.2 Link Detect
§ Ability to Monitor One DS0 Channel in Both the Transmit and Receive Paths
§ In-Band Repeating Pattern Generators and Detectors
Three Independent Detectors Patterns from 1 to 8 bits or 16 bits in Length
§ Bit Oriented Code (BOC) Support
§ Flexible Signaling Support
Software- or Hardware-Based Interrupt Generated on Change of Signaling Data Signaling Debounce Optional Receive Signaling Freeze on Loss of Frame (LOF), Loss of Signal (LOS), or Change-of-Frame Alignment
§ Hardware Pins Provided to Indicate Loss of Frame, Loss of Signal, Loss-of-Transmit Clock (LOTC), or
Signaling Freeze Condition
§ Automatic RAI Generation to ETS 300 011 Specifications
§ RAI-CI and AIS-CI Support
§ Expanded Access to Sa and Si Bits
§ Option to Extend Carrier Loss Criteria to a 1ms Period as per ETS 300 233
§ Japanese J1 Support
Ability to Calculate and Check CRC6 According to the Japanese Standard Ability to Generate Yellow Alarm According to the Japanese Standard
2.2 System Interface
§ Independent Two-Frame Receive and Transmit Elastic Stores Independent Control and Clocking Controlled Slip Capability with Status Minimum Delay Mode Supported
§ Maximum Backplane Rate of 16.384MHz in IBO Mode
§ Supports T1 to E1 Conversion
§ Programmable Output Clocks for Fractional T1, E1, H0, and H12 Applications
§ Interleaving PCM Bus Operation (IBO)
§ Hardware Signaling Capability
Receive Signaling Reinsertion to a Backplane Multiframe Sync Availability of Signaling in a Separate PCM Data Stream Signaling Freezing
§ Ability to Pass the T1 F-Bit Position Through the Elastic Stores in the 2.048MHz Backplane Mode
§ User-Selectable Synthesized Clock Output
8
2.3 HDLC Controllers
§ HDLC Engine (One per Framer):
§ Independent 64-byte Rx and Tx Buffers with Interrupt Support
§ Access FDL, Sa, or Single DS0 Channel
§ Compatible with Polled or Interrupt Driven Environments
2.4 Test and Diagnostics
§ Global, Full-Feature BERT
Any Pseudo-Random Pattern Up to 2 Up to 32 Taps can be Used Simultaneously User-Defined Repetitive Patterns Up to 512 Bytes in Length Large, 48-Bit Error and Bit Counters Map to Any Framer/DS0/FDL (T1) or Sa Bits (E1)
§ Programmable Error Insertion
§ BPV Insertion
§ F-Bit Corruption for Line Testing
§ Loopbacks
Remote Local Per-Channel
§ IEEE 1149.1 Support
32
- 1
DS26401 Octal T1/E1/J1 Framer
2.5 Control Port
§ 8-Bit Parallel Control Port
§ Intel or Motorola Nonmultiplexed Support
§ Flexible Status Registers Support Polled, Interrupt, or Hybrid Program Environments
§ Software Reset Supported
§ Hardware Reset Pin
9
3. BLOCK DIAGRAMS
Figure 3-1. Block Diagram
DS26401 Octal T1/E1/J1 Framer
DS26401
RPOS RNEG RCLK
TPOS TNEG
TCLKO
FRAMER #7
FRAMER #6
FRAMER #5
FRAMER #4
FRAMER
T1/E1
T1/E1
FRAMER #3
FRAMER
FRAMER
T1/E1
T1/E1
FRAMER #2
FRAMER
FRAMER
T1/E1
T1/E1
FRAMER
FRAMER
T1/E1
T1/E1
FRAMER
FRAMER
T1/E1
FRAMER
FRAMER
T1/E1
FRAMER
FRAMER
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
HDLCs
MICRO PROCESSOR
INTERFACE
FRAMER #8
T1/E1
T1/E1
T1/E1
HDLCs
BERT
BACKPLANE
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
BACKPLANE
INTERFACE
INTERFACE
ELASTIC
ELASTIC
STORES
STORES
JTAG PORT
THE BERT FUNCTION MAY BE ASSIGNED TO ANY PORT
BACKPLANE
BACKPLANE
BACKPLANE
INTERFACE
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
INTERFACE
INTERFACE
ELASTIC
ELASTIC
ELASTIC
ELASTIC
STORES
STORES
STORES
STORES
ELASTIC
ELASTIC
ELASTIC
STORES
ELASTIC
ELASTIC
STORES
STORES
ELASTIC
ELASTIC
STORES
STORES
STORES
STORES
PLL
IBO
THE IBO FUNCTION ALLOWS ACCESS TO ALL 8 PORTS INDIVIDUALLY OR AS 4 GROUPS OF 2, 2 GROUPS OF 4, OR 1 GROUP OF 8 PORTS.
RECEIVE AND
TRANSMIT
BACKPLANE
SIGNALS
10
CONTROLLER
PORT
TEST
PORT
CLOCKS
Figure 3-2. Typical PLL Connection
2.048MHz or
1.544MHz
GCLK_IN GCLK_OUT
REF_CLK
DS26401
PLL
BPCLK 2.048MHz, 4.096MHz
8.192MHz or 16.384MHz
Figure 3-3. Typical Bipolar Network-Side Interface to Framers
DS26401 Octal T1/E1/J1 Framer
DS26401
RPOSx
T1/E1 LIU
OR OTHER SOURCE OF BIPOLAR DATA
RNEGx
RCLKx
TPOSx
TNEGx
TCLKx
1 OF 8 FRAMERS
2.048MHz or
1.544MHz
11
Figure 3-4. Typical NRZ Network-Side Interface to Framers
DS26401 Octal T1/E1/J1 Framer
RPOSx
RNEGx
DS26401
T1/E1 LIU
RCLKx
OR OTHER SOURCE OF NRZ DATA
NOTE: SET TCR3.7 = 1 TO SELECT NRZ MODE FOR TPOSx. SET RCR3.6 = 1 TO SELECT NRZ MODE FOR RPOSx.
TPOSx
TNEGx
TCLKx
1 OF 8 FRAMERS
2.048MHz or
1.544MHz
12
4. SIGNAL LIST (SORTED BY SIGNAL NAME)
PIN NAME TYPE FUNCTION
B5 A5 C6 E8 A6 B6 D7 C7 A7 D8 C8 A8
F16 BPCLK O Programmable Backplane Clock
B2 BTS I Motorola or Intel Bus Type Select B4 A1 C4 A2 B3 D5 A3 D6
A4 G16 GCLK_IN I Global Clock Input G13 GCLK_OUT O Global Clock Output R12 HIZE I High-Z Enable
E9
N10 JTCLK I JTAG Clock T11 JTDI I JTAG Data Input P11 JTDO O JTAG Data Output T10 JTMS I JTAG Test Mode Select R11 JTRST I JTAG Reset
B7, B13, D2, D15, E6,
E14, F2, G14, J16, M9,
N15, P2, P8, R5
B1 RCHBLK/CLK1 O Rx Channel Block/Clock for Framer 1
H1 RCHBLK/CLK2 O Rx Channel Block/Clock for Framer 2
L5 RCHBLK/CLK3 O Rx Channel Block/Clock for Framer 3
P6 RCHBLK/CLK4 O Rx Channel Block/Clock for Framer 4 N11 RCHBLK/CLK5 O Rx Channel Block/Clock for Framer 5
M15 RCHBLK/CLK6 O Rx Channel Block/Clock for Framer 6
E15 RCHBLK/CLK7 O Rx Channel Block/Clock for Framer 7 A13 RCHBLK/CLK8 O Rx Channel Block/Clock for Framer 8
C2 RCLK1 I Rx Clock for Framer 1
H4 RCLK2 I Rx Clock for Framer 2
L4 RCLK3 I Rx Clock for Framer 3
N6 RCLK4 I Rx Clock for Framer 4
M11 RCLK5 I Rx Clock for Framer 5
L14 RCLK6 I Rx Clock for Framer 6 E16 RCLK7 I Rx Clock for Framer 7
C12 RCLK8 I Rx Clock for Framer 8
E7 F15 REF_CLK I Reference Clock (1.544MHz/2.048MHz) T12
E5 RF/RMSYNC1 O Rx Frame/MF Sync for Framer 1
H3 RF/RMSYNC2 O Rx Frame/MF Sync for Framer 2
N1 RF/RMSYNC3 O Rx Frame/MF Sync for Framer 3
T5 RF/RMSYNC4 O Rx Frame/MF Sync for Framer 4 T13 RF/RMSYNC5 O Rx Frame/MF Sync for Framer 5
13
ADDR0 I ADDR1 I ADDR2 I ADDR3 I ADDR4 I ADDR5 I ADDR6 I ADDR7 I ADDR8 I
ADDR9 I ADDR10 I ADDR11 I
CS
DATA0 I/O
DATA1 I/O
DATA2 I/O
DATA3 I/O
DATA4 I/O
DATA5 I/O
DATA6 I/O
DATA7 I/O
INT
N.C. No Connect
RD (DS)
RESET
mP Address Bus Bit 0 mP Address Bus Bit 1 mP Address Bus Bit 2 mP Address Bus Bit 3 mP Address Bus Bit 4 mP Address Bus Bit 5 mP Address Bus Bit 6 mP Address Bus Bit 7 mP Address Bus Bit 8 mP Address Bus Bit 9 mP Address Bus Bit 10 mP Address Bus Bit 11
I Chip Select (Active Low)
mP Data Bus Bit 0 mP Data Bus Bit 1 mP Data Bus Bit 2 mP Data Bus Bit 3 mP Data Bus Bit 4 mP Data Bus Bit 5 mP Data Bus Bit 6 mP Data Bus Bit 7
O Interrupt (Active Low)
I Read Strobe (Active Low)
I Global Reset (Active Low)
DS26401 Octal T1/E1/J1 Framer
14
DS26401 Octal T1/E1/J1 Framer
PIN NAME TYPE FUNCTION
M16 RF/RMSYNC6 O Rx Frame/MF Sync for Framer 6
F14 RF/RMSYNC7 O Rx Frame/MF Sync for Framer 7
C13 RF/RMSYNC8 O Rx Frame/MF Sync for Framer 8
D1 RLOF/LOTC1 O RLOF or LOTC for Framer 1 K2 RLOF/LOTC2 O RLOF or LOTC for Framer 2 T1 RLOF/LOTC3 O RLOF or LOTC for Framer 3
P7 RLOF/LOTC4 O RLOF or LOTC for Framer 4 P13 RLOF/LOTC5 O RLOF or LOTC for Framer 5 K14 RLOF/LOTC6 O RLOF or LOTC for Framer 6
C15 RLOF/LOTC7 O RLOF or LOTC for Framer 7 D11 RLOF/LOTC8 O RLOF or LOTC for Framer 8
F5 RLOS/RSIGF1 O RLOS for Framer 1
J4 RLOS/RSIGF2 O RLOS for Framer 2
R2 RLOS/RSIGF3 O RLOS for Framer 3
T7 RLOS/RSIGF4 O RLOS for Framer 4 T16 RLOS/RSIGF5 O RLOS for Framer 5 K13 RLOS/RSIGF6 O RLOS for Framer 6
C16 RLOS/RSIGF7 O RLOS for Framer 7
A11 RLOS/RSIGF8 O RLOS for Framer 8
C1 RNEG1 I Rx Negative Data for Framer 1
H5 RNEG2 I Rx Negative Data for Framer 2
M4 RNEG3 I Rx Negative Data for Framer 3 R6 RNEG4 I Rx Negative Data for Framer 4
N12 RNEG5 I Rx Negative Data for Framer 5
L16 RNEG6 I Rx Negative Data for Framer 6
D16 RNEG7 I Rx Negative Data for Framer 7
B12 RNEG8 I Rx Negative Data for Framer 8
D4 RPOS1 I Rx Positive Data for Framer 1
J2 RPOS2 I Rx Positive Data for Framer 2
P1 RPOS3 I Rx Positive Data for Framer 3
T6 RPOS4 I Rx Positive Data for Framer 4 T14 RPOS5 I Rx Positive Data for Framer 5 L13 RPOS6 I Rx Positive Data for Framer 6
G12 RPOS7 I Rx Positive Data for Framer 7
E11 RPOS8 I Rx Positive Data for Framer 8
E4 RSER1 O Receive Serial Data for Framer 1
J1 RSER2 O Receive Serial Data for Framer 2
R1 RSER3 O Receive Serial Data for Framer 3 M7 RSER4 O Receive Serial Data for Framer 4
R14 RSER5 O Receive Serial Data for Framer 5
L15 RSER6 O Receive Serial Data for Framer 6 F12 RSER7 O Receive Serial Data for Framer 7 A12 RSER8 O Receive Serial Data for Framer 8
D3 RSIG1 O Receive Signaling Data for Framer 1
J3 RSIG2 O Receive Signaling Data for Framer 2
N3 RSIG3 O Receive Signaling Data for Framer 3
N7 RSIG4 O Receive Signaling Data for Framer 4 T15 RSIG5 O Receive Signaling Data for Framer 5 K12 RSIG6 O Receive Signaling Data for Framer 6 F13 RSIG7 O Receive Signaling Data for Framer 7
C11 RSIG8 O Receive Signaling Data for Framer 8
E3 RSYNC1 I/O Rx Frame/MF Sync for Framer 1
K1 RSYNC2 I/O Rx Frame/MF Sync for Framer 2 M5 RSYNC3 I/O Rx Frame/MF Sync for Framer 3 R7 RSYNC4 I/O Rx Frame/MF Sync for Framer 4
R15 RSYNC5 I/O Rx Frame/MF Sync for Framer 5
K16 RSYNC6 I/O Rx Frame/MF Sync for Framer 6 E13 RSYNC7 I/O Rx Frame/MF Sync for Framer 7 B11 RSYNC8 I/O Rx Frame/MF Sync for Framer 8
C3 RSYSCLK1 I Receive System Clock for Framer 1 H2 RSYSCLK2 I Receive System Clock for Framer 2 N2 RSYSCLK3 I Receive System Clock for Framer 3 M6 RSYSCLK4 I Receive System Clock for Framer 4
R13 RSYSCLK5 I Receive System Clock for Framer 5
15
DS26401 Octal T1/E1/J1 Framer
PIN NAME TYPE FUNCTION
L12 RSYSCLK6 I Receive System Clock for Framer 6 H12 RSYSCLK7 I Receive System Clock for Framer 7 D12 RSYSCLK8 I Receive System Clock for Framer 8
F3 TCHBLK/CLK1 O Tx Channel Block/Clock for Framer 1
L2 TCHBLK/CLK2 O Tx Channel Block/Clock for Framer 2 R3 TCHBLK/CLK3 O Tx Channel Block/Clock for Framer 3 N8 TCHBLK/CLK4 O Tx Channel Block/Clock for Framer 4
P14 TCHBLK/CLK5 O Tx Channel Block/Clock for Framer 5
J15 TCHBLK/CLK6 O Tx Channel Block/Clock for Framer 6
A16 TCHBLK/CLK7 O Tx Channel Block/Clock for Framer 7
C10 TCHBLK/CLK8 O Tx Channel Block/Clock for Framer 8
F4 TCLK1 I Tx Clock for Framer 1
L1 TCLK2 I Tx Clock for Framer 2
T3 TCLK3 I Tx Clock for Framer 3 R9 TCLK4 I Tx Clock for Framer 4
P15 TCLK5 I Tx Clock for Framer 5
J13 TCLK6 I Tx Clock for Framer 6 B15 TCLK7 I Tx Clock for Framer 7 B10 TCLK8 I Tx Clock for Framer 8
G1 TCLKO1 O Tx Clock Output for Framer 1 M3 TCLKO2 O Tx Clock Output for Framer 2
P5 TCLKO3 O Tx Clock Output for Framer 3
P10 TCLKO4 O Tx Clock Output for Framer 4
M14 TCLKO5 O Tx Clock Output for Framer 5 H13 TCLKO6 O Tx Clock Output for Framer 6 D13 TCLKO7 O Tx Clock Output for Framer 7
B8 TCLKO8 O Tx Clock Output for Framer 8
P12 TESTPIN1 I Used for factory tests (Note 1)
M10 TESTPIN2 I Used for factory tests (Note 1)
G5 TNEG1 O Tx Negative Data for Framer 1
L3 TNEG2 O Tx Negative Data for Framer 2 P4 TNEG3 O Tx Negative Data for Framer 3 T9 TNEG4 O Tx Negative Data for Framer 4
P16 TNEG5 O Tx Negative Data for Framer 5
H15 TNEG6 O Tx Negative Data for Framer 6
A15 TNEG7 O Tx Negative Data for Framer 7
B9 TNEG8 O Tx Negative Data for Framer 8 F1 TPOS1 O Tx Positive Data for Framer 1
J5 TPOS2 O Tx Positive Data for Framer 2 N4 TPOS3 O Tx Positive Data for Framer 3 M8 TPOS4 O Tx Positive Data for Framer 4
N13 TPOS5 O Tx Positive Data for Framer 5
J12 TPOS6 O Tx Positive Data for Framer 6 E12 TPOS7 O Tx Positive Data for Framer 7 A10 TPOS8 O Tx Positive Data for Framer 8
G4 TSER1 I Transmit Serial Data for Framer 1 M1 TSER2 I Transmit Serial Data for Framer 2 N5 TSER3 I Transmit Serial Data for Framer 3
P9 TSER4 I Transmit Serial Data for Framer 4 N14 TSER5 I Transmit Serial Data for Framer 5 H16 TSER6 I Transmit Serial Data for Framer 6
B14 TSER7 I Transmit Serial Data for Framer 7
C9 TSER8 I Transmit Serial Data for Framer 8 G3 TSIG1 I Transmit Signaling Data for Framer 1 M2 TSIG2 I Transmit Signaling Data for Framer 2
T4 TSIG3 I Transmit Signaling Data for Framer 3 R10 TSIG4 I Transmit Signaling Data for Framer 4 M13 TSIG5 I Transmit Signaling Data for Framer 5 H14 TSIG6 I Transmit Signaling Data for Framer 6 C14 TSIG7 I Transmit Signaling Data for Framer 7
A9 TSIG8 I Transmit Signaling Data for Framer 8
E1 TSSYNC1 I Transmit System Sync for Framer 1
K4 TSSYNC2 I Transmit System Sync for Framer 2
T2 TSSYNC3 I Transmit System Sync for Framer 3
PIN NAME TYPE FUNCTION
T8 TSSYNC4 I Transmit System Sync for Framer 4 R16 TSSYNC5 I Transmit System Sync for Framer 5
J14 TSSYNC6 I Transmit System Sync for Framer 6 D14 TSSYNC7 I Transmit System Sync for Framer 7 D10 TSSYNC8 I Transmit System Sync for Framer 8
G2 TSYNC1 I/O Tx Frame/MF Sync for Framer 1
K5 TSYNC2 I/O Tx Frame/MF Sync for Framer 2 R4 TSYNC3 I/O Tx Frame/MF Sync for Framer 3 N9 TSYNC4 I/O Tx Frame/MF Sync for Framer 4
N16 TSYNC5 I/O Tx Frame/MF Sync for Framer 5 G15 TSYNC6 I/O Tx Frame/MF Sync for Framer 6
A14 TSYNC7 I/O Tx Frame/MF Sync for Framer 7
D9 TSYNC8 I/O Tx Frame/MF Sync for Framer 8
E2 TSYSCLK1 I Transmit System Clock for Framer 1
K3 TSYSCLK2 I Transmit System Clock for Framer 2
P3 TSYSCLK3 I Transmit System Clock for Framer 3 R8 TSYSCLK4 I Transmit System Clock for Framer 4
M12 TSYSCLK5 I Transmit System Clock for Framer 5
K15 TSYSCLK6 I Transmit System Clock for Framer 6 B16 TSYSCLK7 I Transmit System Clock for Framer 7 E10 TSYSCLK8 I Transmit System Clock for Framer 8
F8, F9, G8, G9, H6, H7
H10, H11, J6, J7, J10,
J11, K8, K9, L8, L9
F6, F7, F10, F11, G6,
G7, G10, G11, H8, H9,
J8, J9, K6, K7, K10,
K11, L6, L7, L10, L11
C5
V
—
DD
V
— Signal
SS
WR (R/W)
I W rite Strobe (Active Low)
DS26401 Octal T1/E1/J1 Framer
Note 1: Connect to VSS.
16
DS26401 Octal T1/E1/J1 Framer
5. SIGNAL DESCRIPTIONS
5.1 Receive Framer Signals
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. RPOS can be used for unipolar (NRZ) data if enabled by the Input Data Format bit (IDF) at RCR3.7.
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of RCLK for bipolar data to be clocked through the receive side framer. Data on RPOS and RNEG will typically be AMI, B8ZS, or HDB3 format bipolar data. The RNEG input should be grounded when the DS26401 is set to receive unipolar (NRZ) data, enabled by the Input Data Format bit (IDF) at RCR3.7.
Signal Name: Signal Description: Signal Type: A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive side framer.
Signal Name: Signal Description: Signal Type: Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name: Signal Description: Signal Type: Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name: Signal Description: Signal Type: An extracted pulse, one RCLK wide that identifies either frame or multiframe boundaries. If set to output frame boundaries then RSYNC can be programmed to output doublewide pulses on signaling frames in T1 mode.
Signal Name: Signal Description: Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz, or 16.384MHz receive backplane clock. Only used when the receive-side elastic store function is enabled. Should be tied low in applications that do not use the receive-side elastic store.
RPOS (1–8) Receive Positive Data Input Input
RNEG (1–8) Receive Negative Data Input Input
RCLK (1–8) Receive Clock Input
RSER (1–8) Receive Serial Data Output
RSIG (1–8) Receive Signaling Output Output
RSYNC (1–8) Receive Sync Input/Output
RSYSCLK (1–8) Receive System Clock Input
17
DS26401 Octal T1/E1/J1 Framer
Signal Name: Signal Description: Signal Type:
RCHBLK/CLK (1–8) Receive Channel Block/Clock Output
Pin can be configured to output either RCHBLK or RCHCLK. RCHBLK is a user programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps, service, 768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning.
RCHCLK is a 192 kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated bit clock useful for fractional services. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
Signal Name: Signal Description: Signal Type:
RLOF/LOTC (1–8) Receive Loss of Frame/Loss of Transmit Clock Output
A dual function output that is controlled by the GCR1.5 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for approximately three clock periods.
Signal Name: Signal Description: Signal Type:
RLOS/RSIGF (1–8) Receive Loss of Signal/Receive Signaling Freeze Output
A dual function output that is controlled by the GCR2.3 control bit. This pin can be programmed to toggle high when the framer detects a loss of signal condition, or when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition.
Signal Name: Signal Description: Signal Type:
RF/RMSYNC (1–8) Receive Frame Sync/Receive Multiframe Sync Output
A dual function output controlled by the GCR2.2 control bit. RFSYNC is an extracted 8kHz pulse, one RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), which identifies multiframe boundaries. When the receive elastic store is enabled, the RMSYNC signal indicates the multiframe sync on the system (backplane) side of the e-store. In E1 mode, will indicate either the CRC4 or CAS multiframe as determined by the RSMS2 control bit at RIOCR.1
18
DS26401 Octal T1/E1/J1 Framer
5.2 Transmit Framer Signals
Signal Name: Signal Description: Signal Type: Update on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be programmed to source NRZ data via the output data format (TCR3.7) control bit.
Signal Name: Signal Description: Signal Type: Update on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
Signal Name: Signal Description: Signal Type: A 1.544MHz or a 2.048MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name: Signal Description: Signal Type: This clock is provided to simplify interface to a line interface unit (LIU). This signal is used to register the TPOS and TNEG outputs and is typically synchronous with the TCLK input. However, in framer and payload loopback applications this signal becomes synchronous with RCLK.
Signal Name: Signal Description: Signal Type: Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name: Signal Description: Signal Type: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name: Signal Description: Signal Type: A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This signal can also be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set to output doublewide pulses at signaling frames in T1 mode.
Signal Name: Signal Description: Signal Type: Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.
TPOS (1–8) Transmit Positive Data Output Output
TNEG (1–8) Transmit Negative Data Output Output
TCLK (1–8) Transmit Clock Input
TCLKO (1–8) Transmit Clock Output Output
TSER (1–8) Transmit Serial Data Input
TSIG (1–8) Transmit Signaling Input Input
TSYNC (1–8) Transmit Sync Input / Output
TSSYNC (1–8) Transmit System Sync Input
19
DS26401 Octal T1/E1/J1 Framer
Signal Name: Signal Description: Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store.
Signal Name: Signal Description: Signal Type: A dual function pin. TCHBLK is a user programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384kbps (H0), 768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning.
TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated bit clock useful for fractional services. Synchronous with TCLK when the transmit­side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
TSYSCLK (1–8) Transmit System Clock Input
TCHBLK/CLK (1–8) Transmit Channel Block Output
5.3 Parallel Control Port
Signal Name: Signal Description: Signal Type: This bus selects a specific register in the DS26401 during read/write access. ADDR11 is the MSB and ADDR0 is the LSB.
Signal Name: Signal Description: Signal Type: This 8-bit, bidirectional data bus is used for read/write access of the DS26401 information and control registers. DATA7 is the MSB and DATA0 is the LSB.
Signal Name: Signal Description:
Signal Type: This active-low signal is used to qualify register read/write accesses. The RD and WR signals are qualified with CS.
Signal Name: Signal Description: Signal Type: This active-low signal along with CS qualifies read access to one of the DS26401 registers. The DS26401 drives the DATA bus with the contents of the addressed register while
Signal Name: Signal Description: Signal Type: This active-low signal along with CS qualifies write access to one of the DS26401 registers. Data at DATA[7:0] is written into the addressed register at the rising edge of
Signal Name: Signal Description:
Signal Type: This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INT is deasserted when all interrupts have been acknowledged and serviced.
20
ADDR[11:0] Microprocessor Address Bus Input
DATA[7:0] Microprocessor Data Bus Input/Output
CS
Chip Select Input
RD (DS)
Read Enable Input
RD and CS are both low.
WR (R/W)
Write Enable Input
WR while CS is low.
INT
Interrupt Output
DS26401 Octal T1/E1/J1 Framer
Signal Name: Signal Description: Signal Type: Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RD (DS), and
WR (R/W) pins. If BTS = 1, these pins assume the function listed in parentheses ().
BTS Bus Type Select Input
5.4 System Interface
Signal Name: Signal Description: Signal Type: A continuous T1 (1.544MHz) or E1 (2.048MHz) clock used to create GCLK_OUT and BPCLK.
Signal Name: Signal Description: Signal Type: This output clock is generated from the REF_CLK input and is a 45MHz clock. This pin is usually connected to GCLK_IN.
Signal Name: Signal Description: Signal Type: Primary clock for internal state machines. Can be connected to GCLK_OUT, or provided by the user. The GCLK_IN frequency must be between 43MHz and 49MHz for proper operation.
Signal Name: Signal Description: Signal Type: Programmable clock output created from REFCLK. Can be set to 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz.
Signal Name: Signal Description: Signal Type: Active-low reset. Forcing this input low sets all internal registers to their default value.
Signal Name: Signal Description: Signal Type: Active high. Forcing this input high when the RESET and JTRST pins are low will hold all outputs in high-impedance mode.
REF_CLK Reference Clock Input
GCLK_OUT Global Clock Output Output
GCLK_IN Global Clock Input Input
BPCLK Backplane Clock Output
RESET
System Reset Input
HIZE High-Z Enable Input
21
DS26401 Octal T1/E1/J1 Framer
5.5 Test
Signal Name: Signal Description: Signal Type: JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally through a 10k this pin should be held low.
Signal Name: Signal Description: Signal Type: This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k
Signal Name: Signal Description: Signal Type: This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name: Signal Description: Signal Type: Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor.
Signal Name: Signal Description: Signal Type: Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.
JTRST IEEE 1149.1 Test Reset Input
W resistor operation. If boundary scan is not used,
JTMS IEEE 1149.1 Test Mode Select Input
W pullup resistor.
JTCLK IEEE 1149.1 Test Clock Signal Input
JTDI IEEE 1149.1 Test Data Input Input
JTDO IEEE 1149.1 Test Data Output Output
22
DS26401 Octal T1/E1/J1 Framer
6. REGISTER MAP
The DS26401 has an 8-bit mP control bus with 12 address bits. The address bits are structured as follows:
MSB LSB
XXXXXXXXXXXX
Per Port Registers (See below for exceptions)
Rx/Tx Select: 0 ³ Receive 1
Port Select: 000 ³ Port 1 111
³ Transmit
³ Port 8
23
DS26401 Octal T1/E1/J1 Framer
7. GLOBAL FUNCTIONS
7.1 Global Registers
ADDRESS NAME TYPE FUNCTION PAGE
0F0 GCR1 R/W Global Control Register 1 25 0F1 GCR2 R/W Global Control Register 2 26 0F2 — — Unused, must be set = 0 for proper operation — 0F3 — — Unused, must be set = 0 for proper operation — 0F4 — — Unused, must be set = 0 for proper operation — 0F5 — — Unused, must be set = 0 for proper operation — 0F6 — — Unused, must be set = 0 for proper operation — 0F7 — — Unused, must be set = 0 for proper operation — 0F8 IDR R Device ID Register 35 0F9 GSR1 R Global Status Register 1 36
0FA GSR2 R Global Status Register 2 37 0FB — — Unused, must be set = 0 for proper operation — 0FC — — Unused, must be set = 0 for proper operation — 0FD — — Unused, must be set = 0 for proper operation — 0FE — — Unused, must be set = 0 for proper operation —
0FF — — Unused, must be set = 0 for proper operation —
24
DS26401 Octal T1/E1/J1 Framer
7.2 Global Register Description and Operation
Register Name: Register Description: Register Address:
Bit # 7 6 5 4 3 2 1 0 Name BBEDIM BLOSIM RLOFLTS GIBO REFCLKS BWE GCLE GIPI Default 0 0 0 0 0 0 0 0
Bit 0 / Global Interrupt Pin Inhibit (GIPI)
0 = Normal operation (interrupt pin (INT) toggles low on an unmasked interrupt condition) 1 = Interrupt inhibit (interrupt pin (
Bit 1 / Global Counter Latch Enable (GCLE). A low-to-high transition on this bit, when enabled, latches the framer
performance-monitor counters and the internal BERT counters. Each framer can be independently enabled to accept this input, as well as the BERT. This bit must be cleared and set again to perform another counter latch.
Bit 2 / Bulk Write Enable (BWE). When this bit is set, a port write to one of the octal ports is mapped into all 8
ports. This bit is useful for device initialization. It must be cleared before performing a read operation. 0 = Normal operation 1 = Bulk write is enabled
Bit 3 / Reference Clock-Frequency Select (REFCLKS).
generator depending on the frequency of the reference clock input. 0 = REF_CLK is 1.544MHz 1 = REF_CLK is 2.048MHz
Bit 4 / Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or externally
wire-OR operation. Normally this bit should be set = 0 and the internal mux is used.
0 = Use internal IBO mux
1 = Externally wire-OR TSERs and RSERs for IBO operation
Bit 5 / Receive Loss-of-Frame/Loss-of-Transmit Clock-Indication Select (RLOFLTS) 0 = RLOF/LOTCx pins indicate receive loss-of-frame
1 = RLOF/LOTCx pins indicate loss-of-transmit clock
Bit 6 / BERT Loss-of-Sync Interrupt Mask (BLOSIM) 0 = DS26401 does not generate an interrupt on INT for a BERT LOS
1 = DS26401 generates an interrupt on
Bit 7 / BERT Bit-Error-Detect Interrupt Mask (BBEDIM)
0 = DS26401 does not generate an interrupt on 1 = DS26401 generates an interrupt on
GCR1 Global Control Register 1 0F0h
INT) is forced high (inactive) when this bit is set)
This bit sets the divider ratio of the internal clock
INT for a BERT LOS
INT for a BERT bit-error detect
INT for a BERT bit-error detect
25
DS26401 Octal T1/E1/J1 Framer
Register Name: Register Description: Register Address:
GCR2 Global Control Register 2 0F1h
Bit # 7 6 5 4 3 2 1 0 Name IBOMS1 IBOMS0 BPCLK1 BPCLK0 RLOSSFS RFMSS TCBCS RCBCS Default 0 0 0 0 0 0 0 0
Bit 0 / Receive-Channel Block/Clock Select (RCBCS). This bit controls the function of all eight RCHBLK/CLK
pins.
0 = RCHBLK/CLK pins output RCHBLK (1–8) (receive-channel block)
1 = RCHBLK/CLK pins output RCHCLK (1–8) (receive-channel clock)
Bit 1 / Transmit-Channel Block/Clock Select (TCBCS). This bit controls the function of all eight TCHBLK/CLK
pins. 0 = TCHBLK/CLK pins output TCHBLK (1–8) (transmit-channel block) 1 = TCHBLK/CLK pins output TCHCLK (1–8) (transmit-channel block)
Bit 2 / Receive-Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all eight RF/RMSYNC
pins. 0 = RF/RMSYNC pins output RFSYNC (1–8) (receive-frame sync) 1 = RF/RMSYNC pins output RMSYNC (1–8) (receive-multiframe sync)
Bit 3 / Receive Loss-of-Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of all eight
RLOS/RSIGF pins. 0 = RLOS/RSIGF pins output RLOS (1–8) (receive loss-of-signal) 1 = RLOS/RSIGF pins output RSIGF (1–8) (receive-signaling freeze)
Bits 4, 5 / Backplane Clock Select 0–1 (BPCLK0/1).
BPCLK pin.
BPCLK1 BPCLK0 BPCLK Frequency (MHz)
0 0 2.048 0 1 4.096 1 0 8.192 1 1 16.384
Bits 6, 7 / Interleave Bus Operation Mode Select 0–1 (IBOMS0/1). These bits determine the configuration of the
IBO (interleaved bus) multiplexer. These bits should be used with the Rx and Tx IBO control registers within each of the framer units. Additional information concerning the IBO mux is given in Section 7.3
IBOMS1 IBOMS0 IBO Mode
0 0 IBO Mux Disabled 0 1 4.096MHz (2 per) 1 0 8.192MHz (4 per) 1 1 16.384MHz (8 per)
These bits determine the clock frequency output on the
.
26
DS26401 Octal T1/E1/J1 Framer
7.3 IBO Multiplexer
The IBO multiplexer is used with the IBO function located within each framer/formatter block (controlled by the RIBOC and TIBOC registers). When enabled, the IBO multiplexer simplifies user interface by connecting TDM bus signals internally. The IBO multiplexer eliminates the need for ganged external wiring and tri-state output drivers on the RSER and RSIG pins.
The DS26401 also supports the traditional mode of IBO operation by allowing complete access to individual framers and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This operation mode is enabled per framer in the associated RIBOC and TIBOC registers, while leaving the IBO multiplexer disabled (IBOMS0 = 0 and IBOMS1 = 0).
Figure 7-1
the pin function changes for each mode of the IBO multiplexer.
The transmit and receive IBO functions are described in Sections 8.21 and 11.19
, Figure 7-2, and Figure 7-3 show the equivalent internal circuit for each IBO mode. Table 7-1 describes
(E1 REC).
(T1 XMIT), 9.20 (T1 REC), 10.17 (E1 XMIT),
27
DS26401 Octal T1/E1/J1 Framer
Figure 7-1. Internal IBO Multiplexer Equivalent Circuit—4.096MHz
RSER1
RSIG1
RSYNC1 RSYSCLK1
TSER1 TSIG1 TSSYNC1 TSYSCLK1
RSER3
RSIG3
RSYNC3 RSYSCLK3
TSER3 TSIG3 TSSYNC3 TSYSCLK3
RSER5
RSIG5
RSYNC5 RSYSCLK5
TSER5 TSIG5 TSSYNC5 TSYSCLK5
RSER7
RSIG7
RSYNC7 RSYSCLK7
TSER7 TSIG7 TSSYNC7 TSYSCLK7
Port # 1
Backplane
Interface
Port # 2
Backplane
Interface
Port # 3
Backplane
Interface
Port # 4
Backplane
Interface
Port # 5
Backplane
Interface
Port # 6
Backplane
Interface
Port # 7
Backplane
Interface
Port # 8
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
28
DS26401 Octal T1/E1/J1 Framer
Figure 7-2. Internal IBO Multiplexer Equivalent Circuit—8.192MHz
RSER1
Port # 1
Backplane
Interface
Port # 2
Backplane
Interface
Port # 3
Backplane
Interface
Port # 4
Backplane
Interface
Port # 5
Backplane
Interface
Port # 6
Backplane
Interface
Port # 7
Backplane
Interface
Port # 8
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSSYNC
TSYSCLK
TSER
TSIG
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSIG1
RSYNC1 RSYSCLK1
TSER1 TSIG1 TSSYNC1 TSYSCLK1
RSER5
RSIG5
RSYNC5 RSYSCLK5
TSER5 TSIG5 TSSYNC5 TSYSCLK5
29
DS26401 Octal T1/E1/J1 Framer
Figure 7-3. Internal IBO Multiplexer Equivalent Circuit—16.394MHz
RSER(1) RSER(2) RSER(3)
Port # 1
Backplane
Interface
Port # 2
Backplane
Interface
Port # 3
Backplane
Interface
Port # 4
Backplane
Interface
Port # 5
Backplane
Interface
Port # 6
Backplane
Interface
Port # 7
Backplane
Interface
Port # 8
Backplane
Interface
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER
RSIG
RIBO_OEB
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER(4) RSER(5) RSER(6) RSER(7) RSER(8)
RIBO_OEB(1-8)
To Mux
RSIG(1) RSIG(2) RSIG(3) RSIG(4) RSIG(5) RSIG(6) RSIG(7) RSIG(8)
RIBO_OEB(1-8)
To MuxTo Mux
To MuxTo Mux
To MuxTo Mux
To MuxTo Mux
To MuxTo Mux
To MuxTo Mux
To MuxTo Mux
RSER1
RSIG1
RSYNC1 RSYSCLK1
TSER1 TSIG1 TSSYNC1 TSYSCLK1
30
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