MAXIM DS26303 User Manual

www.maxim-ic.com

DS26303

3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit

GENERAL DESCRIPTION

The DS26303 is an 8-channel short-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of applications are supported through internal termination or external termination. A single bill of material can support E1/T1/J1 with minimum external components. Redundancy is supported through nonintrusive monitoring, optimal high-impedance modes, and configurable 1:1 or 1+1 backup enhancements. An on-chip synthesizer generates the E1/T1/J1 clock rates by a single master clock input of various frequencies. Two clock output references are also offered.

APPLICATIONS

T1 Digital Cross-Connects ATM and Frame Relay Equipment Wireless Base Stations ISDN Primary Rate Interface E1/T1/J1 Multiplexer and Channel Banks E1/T1/J1 LAN/WAN Routers

FUNCTIONAL DIAGRAM

Jtag

RTIP RRING

TTTIP TRING

Software Control, Hardware Control

and JTAG

Receiver

Transmitter

MODESEL

RLOS

RPOS RNEG RCLK

TPOS TNEG TCLK

FEATURES

 8 Complete E1, T1, or J1 Short-Haul Line

Interface Units

 Independent E1, T1, or J1 Selections  Internal Software-Selectable Transmit and

Receive-Side Termination

 Crystal-Less Jitter Attenuator  Selectable Single-Rail and Dual-Rail Mode

and AMI or HDB3/B8ZS Line Encoding and Decoding

 Detection and Generation of AIS  Digital/Analog Loss-of-Signal Detection as

per T1.231, G.775, and ETS 300 233

 External Master Clock can be Multiple of

2.048MHz or 1.544MHz for T1/J1 or E1 Operation; This Clock will be Internally Adapted for T1 or E1 Use

 Built-In BERT Tester for Diagnostics  8-Bit Parallel Interface Support for Intel or

Motorola Mode or a 4-Wire Serial Interface

 Hardware Mode Interface Support  Transmit Short-Circuit Protection  G.772 Nonintrusive Monitoring  Specification Compliance to the Latest T1

and E1 Standards—ANSI T1.102, AT&T Pub 62411, T1.231, T1.403, ITU-T G.703, G.742, G.775, G.823, ETS 300 166, and ETS 300 233

 Single 3.3V Supply with 5V Tolerant I/O  JTAG Boundary Scan as per IEEE 1149.1  144-Pin eLQFP Package

DS26303

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

ORDERING INFORMATION

PART

DS26303L-XXX 0°C to +70°C 144 eLQFP DS26303L-XXX+ 0°C to +70°C 144 eLQFP DS26303LN-XXX -40°C to +85°C 144 eLQFP DS26303LN-XXX+ -40°C to +85°C 144 eLQFP

Note: When XXX is 075, the part defaults to 75Ω impedance in E1 mode; when XXX is 120, the part defaults to 120

+ Denotes a lead-free/RoHS-compliant package. e = Exposed Pad.

TEMP RANGE PIN-PACKAGE

impedance.

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

1 DETAILED DESCRIPTION...............................................................................................................6

2 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7

3 BLOCK DIAGRAMS.........................................................................................................................9

4 PIN DESCRIPTION.........................................................................................................................11

4.1 HARDWARE AND HOST PORT OPERATION ......................................................................................20

4.1.1 Hardware Mode................................................................................................................................... 20

4.1.2 Serial Port Operation .......................................................................................................................... 21

4.1.3 Parallel Port Operation........................................................................................................................ 22

4.1.4 Interrupt Handling ............................................................................................................................... 22

5 REGISTERS....................................................................................................................................24

5.1 REGISTER DESCRIPTION ...............................................................................................................29

5.1.1 Primary Registers................................................................................................................................ 29

5.1.2 Secondary Registers........................................................................................................................... 38

5.1.3 Individual LIU Registers...................................................................................................................... 40

5.1.4 BERT Registers ..................................................................................................................................47

6 FUNCTIONAL DESCRIPTION........................................................................................................54

6.1 POWER-UP AND RESET ................................................................................................................. 54

6.2 MASTER CLOCK ............................................................................................................................54

6.3 TRANSMITTER ...............................................................................................................................55

6.3.1 Transmit Line Templates .................................................................................................................... 56

6.3.2 LIU Transmit Front-End ...................................................................................................................... 58

6.3.3 Dual-Rail Mode ................................................................................................................................... 59

6.3.4 Single-Rail Mode................................................................................................................................. 59

6.3.5 Zero Suppression—B8ZS or HDB3 .................................................................................................... 59

6.3.6 Transmit Power-Down ........................................................................................................................ 59

6.3.7 Transmit All Ones................................................................................................................................ 59

6.3.8 Driver Fail Monitor............................................................................................................................... 59

6.4 RECEIVER .....................................................................................................................................59

6.4.1 Peak Detector and Slicer ....................................................................................................................59

6.4.2 Clock and Data Recovery ...................................................................................................................59

6.4.3 Loss of Signal...................................................................................................................................... 60

6.4.4 AIS ...................................................................................................................................................... 60

6.4.5 Bipolar Violation and Excessive Zero Detector................................................................................... 62

6.4.6 LIU Receiver Front-End ......................................................................................................................62

6.5 HITLESS-PROTECTION SWITCHING (HPS) ......................................................................................62

6.6 JITTER ATTENUATOR .....................................................................................................................64

6.7 G.772 MONITOR ...........................................................................................................................65

6.8 LOOPBACKS ..................................................................................................................................65

6.8.1 Analog Loopback ................................................................................................................................65

6.8.2 Digital Loopback.................................................................................................................................. 65

6.8.3 Remote Loopback............................................................................................................................... 66

6.8.4 Dual Loopback .................................................................................................................................... 67

6.9 BERT...........................................................................................................................................68

6.9.1 Configuration and Monitoring.............................................................................................................. 68

6.9.2 BERT Interrupt Handling..................................................................................................................... 69

6.9.3 Receive Pattern Detection ..................................................................................................................69

6.9.4 Transmit Pattern Generation............................................................................................................... 71

7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................................72

7.1 TAP CONTROLLER STATE MACHINE ..............................................................................................73

7.1.1 Test-Logic-Reset................................................................................................................................. 73

7.1.2 Run-Test-Idle ...................................................................................................................................... 73

7.1.3 Select-DR-Scan .................................................................................................................................. 73

7.1.4 Capture-DR......................................................................................................................................... 73

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

7.1.5 Shift-DR...............................................................................................................................................73

7.1.6 Exit1-DR.............................................................................................................................................. 73

7.1.7 Pause-DR............................................................................................................................................ 73

7.1.8 Exit2-DR.............................................................................................................................................. 73

7.1.9 Update-DR ..........................................................................................................................................73

7.1.10 Select-IR-Scan.................................................................................................................................... 74

7.1.11 Capture-IR........................................................................................................................................... 74

7.1.12 Shift-IR................................................................................................................................................ 74

7.1.13 Exit1-IR ...............................................................................................................................................74

7.1.14 Pause-IR............................................................................................................................................. 74

7.1.15 Exit2-IR ...............................................................................................................................................74

7.1.16 Update-IR............................................................................................................................................ 74

7.2 INSTRUCTION REGISTER................................................................................................................76

7.2.1 EXTEST ..............................................................................................................................................76

7.2.2 HIGHZ................................................................................................................................................. 76

7.2.3 CLAMP................................................................................................................................................ 76

7.2.4 SAMPLE/PRELOAD ...........................................................................................................................76

7.2.5 IDCODE ..............................................................................................................................................76

7.2.6 BYPASS.............................................................................................................................................. 76

7.3 TEST REGISTERS ..........................................................................................................................77

7.3.1 Boundary Scan Register..................................................................................................................... 77

7.3.2 Bypass Register.................................................................................................................................. 77

7.3.3 Identification Register ......................................................................................................................... 77

8 OPERATING PARAMETERS.........................................................................................................78

9 THERMAL CHARACTERISTICS....................................................................................................79

10 AC CHARACTERISTICS................................................................................................................80

10.1 LINE INTERFACE CHARACTERISTICS ...............................................................................................80

10.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS .................................................................81

10.3 SERIAL PORT ................................................................................................................................93

10.4 SYSTEM TIMING ............................................................................................................................94

10.5 JTAG TIMING................................................................................................................................96

11 PIN CONFIGURATION ...................................................................................................................97

11.1 144-PIN LQFP WITH EXPOSED PAD ..............................................................................................97

12 PACKAGE INFORMATION ............................................................................................................98

12.1 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (56-G6037-002) (SHEET 1 OF 2) .............. 98

12.2 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (SHEET 2 OF 2)......................................... 99

13 DOCUMENT REVISION HISTORY...............................................................................................100

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

LIST OF FIGURES

Figure 3-1. Block Diagram ........................................................................................................................................... 9

Figure 3-2. Receive Logic Detail................................................................................................................................ 10

Figure 3-3. Transmit Logic Detail............................................................................................................................... 10

Figure 4-1. 144-Pin eLQFP Pin Assignment ............................................................................................................. 19

Figure 4-2. Serial Port Operation for Write Access ................................................................................................... 21

Figure 4-3. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 21

Figure 4-4. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 22

Figure 4-5. Interrupt Handling Flow Diagram ............................................................................................................ 23

Figure 6-1. Prescaler PLL and Clock Generator ....................................................................................................... 54

Figure 6-2. T1 Transmit Pulse Templates ................................................................................................................. 56

Figure 6-3. E1 Transmit Pulse Templates ................................................................................................................. 57

Figure 6-4. LIU Front-End.......................................................................................................................................... 58

Figure 6-5. HPS Logic ............................................................................................................................................... 63

Figure 6-6. HPS Block Diagram................................................................................................................................. 63

Figure 6-7. Jitter Attenuation ..................................................................................................................................... 64

Figure 6-8. Analog Loopback..................................................................................................................................... 65

Figure 6-9. Digital Loopback...................................................................................................................................... 66

Figure 6-10. Remote Loopback ................................................................................................................................. 66

Figure 6-11. Dual Loopback ...................................................................................................................................... 67

Figure 6-12. PRBS Synchronization State Diagram.................................................................................................. 70

Figure 6-13. Repetitive Pattern Synchronization State Diagram............................................................................... 71

Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 72

Figure 7-2. TAP Controller State Diagram................................................................................................................. 75

Figure 10-1. Intel Nonmuxed Read Cycle ................................................................................................................. 82

Figure 10-2. Intel Mux Read Cycle ............................................................................................................................ 83

Figure 10-3. Intel Nonmux Write Cycle...................................................................................................................... 85

Figure 10-4. Intel Mux Write Cycle ............................................................................................................................ 86

Figure 10-5. Motorola Nonmux Read Cycle .............................................................................................................. 88

Figure 10-6. Motorola Mux Read Cycle..................................................................................................................... 89

Figure 10-7. Motorola Nonmux Write Cycle .............................................................................................................. 91

Figure 10-8. Motorola Mux Write Cycle ..................................................................................................................... 92

Figure 10-9. Serial Bus Timing Write Operation........................................................................................................ 93

Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 93

Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 93

Figure 10-12. Transmitter Systems Timing ............................................................................................................... 94

Figure 10-13. Receiver Systems Timing ................................................................................................................... 95

Figure 10-14. JTAG Timing ....................................................................................................................................... 96

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

LIST OF TABLES

Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7

Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8

Table 4-1. Pin Descriptions........................................................................................................................................ 11

Table 4-2. Hardware Mode Configuration Examples................................................................................................. 20

Table 4-3. Parallel Port Mode Selection and Pin Functions ...................................................................................... 22

Table 5-1. Primary Register Set ................................................................................................................................ 24

Table 5-2. Secondary Register Set............................................................................................................................ 25

Table 5-3. Individual LIU Register Set....................................................................................................................... 25

Table 5-4. BERT Register Set ................................................................................................................................... 26

Table 5-5. Primary Register Set Bit Map ................................................................................................................... 27

Table 5-6. Secondary Register Set Bit Map .............................................................................................................. 27

Table 5-7. Individual LIU Register Set Bit Map.......................................................................................................... 28

Table 5-8. BERT Register Bit Map ............................................................................................................................ 28

Table 5-9. G.772 Monitoring Control ......................................................................................................................... 32

Table 5-10. TST Template Select Transceiver Register ........................................................................................... 35

Table 5-11. Template Selection................................................................................................................................. 35

Table 5-12. Address Pointer for Bank Selection........................................................................................................ 37

Table 5-13. MCLK Selections .................................................................................................................................... 42

Table 5-14. Jitter Attenuator Bandwidth Selections................................................................................................... 43

Table 5-15. PLL Clock Select .................................................................................................................................... 45

Table 5-16. Clock A Select ........................................................................................................................................ 45

Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters ............................................ 55

Table 6-2. Registers Related to Control of DS26303 Transmitters ........................................................................... 55

Table 6-3. DS26303 Template Selections................................................................................................................. 56

Table 6-4. LIU Front-End Values............................................................................................................................... 58

Table 6-5. Loss Criteria T1.231, G.775, and ETS 300 233 Specifications................................................................ 60

Table 6-6. AIS Criteria T1.231, G.775, and ETS 300 233 Specifications.................................................................. 61

Table 6-7. AIS Detection and Reset Criteria ............................................................................................................. 61

Table 6-8. Registers Related to AIS Detection.......................................................................................................... 61

Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting ..................................................................... 62

Table 6-10. Pseudorandom Pattern Generation........................................................................................................ 68

Table 6-11. Repetitive Pattern Generation ................................................................................................................ 68

Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 76

Table 7-2. ID Code Structure..................................................................................................................................... 77

Table 7-3 Device ID Codes........................................................................................................................................ 77

Table 8-1. Recommended DC Operating Conditions................................................................................................ 78

Table 8-2. Capacitance.............................................................................................................................................. 78

Table 8-3. DC Characteristics.................................................................................................................................... 78

Table 9-1. Thermal Characteristics............................................................................................................................ 79

Table 10-1. Transmitter Characteristics..................................................................................................................... 80

Table 10-2. Receiver Characteristics......................................................................................................................... 80

Table 10-3. Intel Read Mode Characteristics ............................................................................................................ 81

Table 10-4. Intel Write Cycle Characteristics ............................................................................................................ 84

Table 10-5. Motorola Read Cycle Characteristics ..................................................................................................... 87

Table 10-6. Motorola Write Cycle Characteristics ..................................................................................................... 90

Table 10-7. Serial Port Timing Characteristics .......................................................................................................... 93

Table 10-8. Transmitter System Timing .................................................................................................................... 94

Table 10-9. Receiver System Timing......................................................................................................................... 95

Table 10-10. JTAG Timing Characteristics................................................................................................................ 96

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

1 DETAILED DESCRIPTION

The DS26303 is a single-chip, 8-channel, short-haul line interface unit (LIU) for T1 (1.544Mbps) and E1 (2.048Mbps) applications. Eight independent receivers and transmitters are provided in an eLQFP package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single reference clock called MCLK. MCLK can be either 1.544MHz or 2.048MHz or a multiple thereof, and either frequency can be internally adapted for T1, J1, or E1 mode. Internal impedance match provided for both transmit and receive paths reduces external component count. The transmit waveforms are compliant to G.703 and T1.102 specifications. The DS26303 provides software-selectable internal transmit termination for 100Ω T1 twisted pair, 110Ω J1 twisted pair, 120Ω E1 twisted pair, and 75Ω E1 coaxial applications. The transmitters have fast high-impedance capability and can be individually powered down.

The receivers can function with up to 15dB of receive signal attenuation for T1 mode and E1 mode. The DS26303

can be configured as a 7-channel LIU with channel 1 used for nonintrusive monitoring in accordance with G.772. The receivers and transmitters can be programmed into single-rail or dual-rail mode. AMI or HDB/B8ZS encoding and decoding is selectable in single-rail mode. A 128-bit crystal-less on-board jitter attenuator for each LIU can be placed in the receive or transmit directions. The jitter attenuator meets the ETS CTR12/13 ITU-T G.736, G.742, G.823, and AT&T Pub 62411 specifications.

The DS26303 detects and generates AIS in accordance with T1.231, G.775, and ETS 300 233. Loss of signal is detected in accordance with T1.231, G.775, and ETS 300 233. The DS26303 can perform digital, analog, remote, and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.

The DS26303 can be configured using an 8-bit multiplexed or nonmultiplexed Intel or Motorola port, a 4-pin serial port, or in limited modes of operation using hardware mode.

The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled into the RTIP and RRING pins of the DS26303. The user has the option to select internal termination of 75Ω, 100Ω, 110Ω, or 120Ω applications. The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator, outputting the received line clock at RCLK and data at RPOS and RNEG.

The DS26303 receivers can recover data and clock for up to 15dB of attenuation of the transmitted signals in T1

and E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8.

The DS26303 contains eight identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to TCLK. The data at these pins can be single-rail or dual-rail. This data is processed by waveshaping circuitry and line drivers to output a pulse at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.

The DS26303 drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The DS26303 requires a 1:2 transformer for the transmit path and a 2:1 transformer for the receive path.

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

2 TELECOM SPECIFICATIONS COMPLIANCE

The DS26303 LIU meets all the relevant latest telecommunications specifications. Table 2-1 provides the T1 specifications and

Table 2-1. T1-Related Telecommunications Specifications

ANSI T1.102–Digital Hierarchy Electrical Interface

AMI Coding

B8ZS Substitution Definition

DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6 V peak; Power level between

12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is greater than 26dB. The DSX-1 cable is restricted up to 655 feet.

This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cable of 1000 feet.

ANSI T1.231–Digital Hierarchy–Layer 1 in Service Performance Monitoring

BPV Error Definition, Excessive Zero Definition, LOS description, AIS definition

ANSI T1.403–Network and Customer Installation Interface–DS1 Electrical Interface

Description of the Measurement of the T1 Characteristics—100Ω, pulse shape and template according to T1.102; power level 12.4dBm to 19.7dBm when all ones are transmitted.

LBO for the Customer Interface (CI) is specified as 0dB, 7.5dB, and 15dB. Line rate is ±32ppm. Pulse Amplitude is 2.4V to 3.6V.

AIS generation as unframed all ones is defined.

The total cable attenuation is defined as 22dB. The DS26303 functions up to 36dB cable loss.

Note that the pulse mask defined by T1.403 and T1.102 are different—specifically at Times 0.61, -0.27, -34, and 0.77. The DS26303 is compliant to both templates.

Pub 62411

This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer

characteristics are tighter than G.736 and jitter tolerance is tighter the G.823.

Table 2-2 provides the E1 specifications for the relevant sections applicable to the DS26303.

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Table 2-2. E1-Related Telecommunications Specifications

ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces

Defines the 2048kbps bit rate: 2048 ±50ppm. The transmission media are 75Ω coax or 120Ω twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns.

Return loss: 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB

Nominal peak voltage is 2.37V for coax and 3V for twisted pair.

The pulse mask for E1 is defined in G.703.

Defines the 2048 kHz synchronization interface (Chapter 13). Contact factory for usage details.

ITU-T G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps

The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.

Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.

ITU-T G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps

The DS26303 jitter attenuator is compliant with jitter transfer curve for sinusoidal jitter input.

ITU-T G.772

This specification provides the method for using receiver for transceiver 0 as a monitor for the rest of the seven transmitter/receiver combinations.

ITU-T G.775

An LOS detection criterion is defined.

ITU-T G.823–The control of jitter and wander within digital networks that are based on 2.048kbps Hierarchy

G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and 100kHz.

ETS 300 166

This specification provides transmit return loss of 6dB for a range of 0.25fb to 0.05fb, and 8dB for a range of 0.05fb to 1.5fb where fb equals 2.048kHz for 2.048kbps interface.

ETS 300 233

This specification provides LOS and AIS signal criteria for E1 mode.

Pub 62411

This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer

characteristics are tighter than G.736 and jitter tolerance is tighter than G.823.

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3 BLOCK DIAGRAMS

Figure 3-1. Block Diagram

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

RRING

RTIP

TRING

TTIP

TYPICAL OF ALL 8 CHANNELS

Optional

Termination

Analog Loopback

Filter

Line Drivers

Peak Detector

Unframed All

Ones Insertion

VCO/PLL

Clock/Data

Wave Shaping

Recovery

Jitter Attenuator

Remote Loopback (Dual Mode)

MUX

Local Loopback

Jitter Attenuator

T1CLK E1CLK

MUX

2.048MHz to

1.544MHz PLL

Remote Loopback

Receive Logic

DS26303

Transmit Logic

RLOS

RPOS/RDAT

RCLK

RNEG/CV

TPOS/TDAT

TCLK

TNEG

Reset

Port Interface

MUX

CLKE

WRB/DSB/SDI

RDB/RWB

MOTEL

RDY/ACKB/SDO

ASB/ALE/SCLK

BSWB

D7/AD7/

A0 to A4

D0 to D6/

AD0 to AD6

Control

Interrupt

CSB

and

INTB

MODESEL

JTAG PORT

JTMS

JTRSTB

JTCLK

JTDI

JTDO

T1CLK E1CLK

Master Clock

Adapter

MCLK

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Figure 3-2. Receive Logic Detail

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

RCLK

POS

NEG

EZDE

Excessive

Zero Detect T1.231

Decoder (G.703, T1.102)

BPVs, Code Violatiions

B8ZS/HDB3/AMI

(T1.231, O.161)

ENCODE

LCS

CODE

Figure 3-3. Transmit Logic Detail

LOS

RCLK

IAISEL

AISEL

Insert

(AIS)

RPOS

RNEG/CV

MCLK

NRZ Data

BPV/CV/EXZ

ENCV

CVDEB

ENCODE

AIS

Detector

G.775, ETSI 300233,

T1.231

LASCS

MUX

All Ones

SRMS

To Remote

Loopback

BEIR

BPV Insert

SRMS

MUX

LCS

CODE

ENCODE

B8ZS/HDB3/AMI

Coder (G.703,

T1.102)

TPOS/

TDATA

TNEG/

BPV

TCLK

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

4 PIN DESCRIPTION

Table 4-1. Pin Descriptions

NAME PIN TYPE FUNCTION

ANALOG TRANSMIT AND RECEIVE

TTIP1 45 TTIP2 52 TTIP3 57 TTIP4 64 TTIP5 117 TTIP6 124 TTIP7 129

TTIP8 136 TRING1 46 TRING2 51 TRING3 58 TRING4 63 TRING5 118 TRING6 123 TRING7 130 TRING8 135

RTIP1 48 RTIP2 55 RTIP3 60 RTIP4 67 RTIP5 120 RTIP6 127 RTIP7 132

RTIP8 139 RRING1 49 RRING2 54 RRING3 61 RRING4 66 RRING5 121 RRING6 126 RRING7 133 RRING8 138

Analog Output

Analog

Input

Analog

Input

Transmit Bipolar Tip for Channel 1 to 8. These pins are

differential line-driver tip outputs. These pins will be high impedance if pin OE is low or the corresponding

high. If the corresponding clock TCLKn is low for 64 MCLKs, the

corresponding transmitter is put in power-down mode. The

differential outputs of TTIPn and TRINGn can provide internal

matched impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

Transmit Bipolar Ring for Channel 1 to 8. These pins are

differential line-driver ring outputs. These pins will be high impedance if pin OE is low or the corresponding

high. If the corresponding clock TCLKn is low for 64 MCLKs, the

corresponding transmitter is put in power-down mode. The

differential outputs of TTIPn and TRINGn can provide internal

matched impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

Receive Bipolar Tip for Channel 1 to 8. Receive analog input for

differential receiver. Data and clock are recovered and output at

RPOSn/RNEGn and RCLKn pins, respectively. The differential inputs of RTIPn and RRINGn can provide internal matched

impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

Receive Bipolar Ring for Channel 1 to 8. Receive analog input

for differential receiver. Data and clock are recovered and output

at RPOSn/RNEGn and RCLKn pins, respectively. The differential inputs of RTIPn and RRINGn can provide internal matched

impedance for E1 75Ω, E1 120Ω, T1 100Ω, or J1 110Ω.

OEB.OEBn bit is

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

DIGITAL Tx/Rx

TPOS1/TDATA1 37

TPOS2/TDATA2 30

TPOS3/TDATA3 80

TPOS4/TDATA4 73

TPOS5/TDATA5 108

TPOS6/TDATA6 101

TPOS7/TDATA7 8

TPOS8/TDATA8 1

Transmit Positive-Data Input for Channel 1 to 8/Transmit Data Input for Channel 1 to 8

TPOS[1:8]: When the DS26303 is configured in dual-rail mode, the data input to TPOSn is output as a positive pulse on the line (TTIPn and TRINGn) as follows:

TPOSn TNEGn Output Pulse

0 0 Space 0 1 Negative Pulse 1 0 Positive Pulse 1 1 Space

TDATA[1:8]: When the device is configured in single-rail mode, NRZ data is input to TDATAn. The data is HDB3, B8ZS or AMI

encoded before being output to the line.

TNEG1 38

TNEG2 31

Transmit Negative Data for Channel 1 to 8. When the DS26303 is configured in dual-rail mode, the data input to TNEGn is output

TNEG3 79

TNEG4 72

TNEG5 109

TNEG6 102

as a negative pulse on the line (TTIPn and TRINGn) as follows:

TPOSn TNEGn Output Pulse

0 0 Space 0 1 Negative Pulse 1 0 Positive Pulse

TNEG7 7

1 1 Space

TNEG8 144

TCLK1 36

TCLK2 29

Transmit Clock for Channel 1 to 8. The transmit clock must be

1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock used to sample the data on TPOSn/TNEGn or TDATn on the falling edge. TCLKn can be inverted.

TCLK3 81

If TCLKn is high for 16 or more MCLKs, then an all-ones signal is

TCLK4 74

TCLK5 107

TCLK6 100

TCLK7 9

TCLK8 2

RPOS1/RDATA1 40 RPOS2/RDATA2 33

RPOS3/RDATA3 77

RPOS4/RDATA4 70

RPOS5/RDATA5 111 RPOS6/RDATA6 104

RPOS7/RDATA7 5

RPOS8/RDATA8 142

tri-state

transmitted on the corresponding line (TTIPn and TRINGn). When TCLKn starts clocking again, normal operation will resume on the

corresponding line.

If TCLKn is low for 64 or more MCLKs, the corresponding

transmitter channel will power down and the line will be put into

high impedance. When TCLKn starts clocking again the

corresponding transmitter will power up, resume normal operation, and the line will come out of high impedance.

Receive Positive-Data Output for Channel 1 to 8/Receive Data Output for Channel 1 to 8

RPOS[1:8]: In dual-rail mode, this output indicates a positive pulse on RTIPn/RRINGn. If a given receiver is in power-down mode, the corresponding RPOSn pin is high impedance.

RDATA[1:8]: In single-rail mode, NRZ data is output to this pin.

Note: During an RLOS condition, the RPOSn/RDATAn output remainactive.

12 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

RNEG1/CV1 41

Receive Negative-Data Output for Channel 1 to 8/Code Violation for Channel 1 to 8

RNEG2/CV2 34

RNEG[1:8]: In dual-rail mode, this output indicates a negative

RNEG3/CV3 76

RNEG4/CV4 69

RNEG5/CV5 112

tri-state

RNEG6/CV6 105

pulse on RTIPn/RRINGn. If a given receiver is in power-down mode, the corresponding RNEGn pin is high impedance.

CV[1:8]: In single-rail mode, bipolar violation, code violation, and excessive zeros are reported by driving CVn high for one clock

cycle. If HDB3 or B8ZS encoding is not selected, this pin indicates only BPVs.

RNEG7/CV7 4

Note: During an RLOS condition, the RNEGn/CVn output remains

RNEG8/CV8 141

active.

RCLK1 39 RCLK2 32 RCLK3 78 RCLK4 71 RCLK5 110

tri-state

RCLK6 103

Receive Clock for Channel 1 to 8. The receive data RPOSn/RNEGn or RDATn is clocked out on the rising edge of RCLKn. RCLKn can be inverted. If a given receiver is in powerdown mode, RCLKn is high impedance.

RCLK7 6 RCLK8 143

Master Clock. This is an independent free-running clock that can

be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode. The clock selection is available by

MCLK 10 I

MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be internally adapted to 1.544MHz and a multiple of 1.544MHz can be internally adapted to 2.048MHz. In hardware mode, internal adaptation is not available so the user must provide 2.048MHz ±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.

Loss-of-Signal Output/T1-E1 Clock

MC bits

RLOS1: This output goes high when there are no transitions on

the receiveline over a specified interval. The output goes low when there is sufficient ones density on the receiveline. The RLOS

assertion and desertion criteria are described in the Functional

RLOS1/TECLK 42 O

Description section. The RLOS outputs can be configured to

comply with T1.231, ITU-T G.775, or ETS 300 233. In hardware mode, ETS 300 233 “RLOS Criteria” is not available.

TECLK: When enabled (

a T1- or E1-programmable clock output. For T1 or E1 frequency selection, see the hardware mode.

RLOS2 35

RLOS3 75

RLOS4 68

RLOS5 113

Loss-of-Signal Output

RLOS[2:8]: RLOS2: This output goes high when there are no

transitions on the receiveline over a specified interval. The output goes low when there is sufficient ones density on the receiveline. The RLOS assertion and desertion criteria are described in the

RLOS6 106

Functional Description (Section

configured to comply with T1.231, ITU-T G.775, or ETS 300 233.

RLOS7 3

In hardware mode, ETS 300 233 “RLOS Criteria” is not available.

RLOS8 140

MC.TECLKE is set), this output becomes

CCR register. This option is not available in

6). The RLOS outputs can be

13 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

Clock A. This output becomes a programmable clock output when

CLKA 93

tri-state

enabled ( register. This option is not available in hardware mode. If this

MC.CLKAE is set). For frequency options, see the CCR

option is not used, the pin should be left unconnected.

N.C. 94

(pulled

to V

No Connection. Pin should be left unconnected or grounded.

)

HARDWARE AND PORT OPERATION

Mode Selection. This pin is used to select the control mode of the

DS26303.

MODESEL 11

MUX/

TIMPRM

MOTEL/

CODE

43 I

88 I

(pulled

DDIO

Low → Hardware Mode

/2 → Serial Host Mode

DDIO

High → Parallel Host Mode

/2)

Note: When left unconnected, do not route signals with fast transitions near MODESEL. This practice minimizes capacitive coupling.

Multiplexed/Nonmultiplexed Select Pin/ Transmit Impedance/Receive Impedance Match

MUX: In host mode with a parallel port, this pin is used to select

multiplexed address and data operation or separate address and data. When mux is a high, multiplexed address and data is used.

TIMPRM: In hardware mode, this pin selects the internal transmit

termination impedance and receive impedance match for E1 mode and T1/J1 mode.

0 → 75Ω for E1 mode or 100Ω for T1 mode 1 → 120Ω for E1 mode or 110Ω for J1 mode

Note: If the part number ends with 120, the default is 120 low and 75

Motorola Intel Select/Code

when high for El mode only.

MOTEL: When in parallel host mode, this pin selects Motorola

mode when low and Intel mode when high.

CODE: In hardware mode, AMI encoding/decoding for all the LIUs

is selected when the pin is high. When the pin is low, B8ZS is selected for T1 mode and HDB3 for E1 mode for all the LIUs.

Chip Select Bar/Jitter Attenuator Select

when

CSB/

JAS

(In HW

mode, pulled

/2)

DDIO

CSB: This signal must be low during all accesses to the registers. JAS: In hardware mode, this pin is used as a jitter attenuator

select.

Low → Jitter attenuator is in the transmit path.

/2 → Jitter attenuator is not used.

DDIO

High → Jitter attenuator is in the receive path.

Note: When left unconnected in hardware mode, do not route signals with fast transitions near JAS, in order to minimize capacitive coupling.

14 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

Serial Clock/Address Latch Enable/Address Strobe Bar/Template Selection 2

SCLK: In the serial host mode, this pin is the serial clock. Data on

SDI is clocked on the rising edge of SCLK. The data is clocked on SDO on the rising edge of SCLK if CLKE is high. If CLKE is low the data on SDO is clocked on the falling edge of SCLK.

SCLK/ALE/

ASB/TS2

86 I

ALE: In parallel Intel multiplexed mode, the address lines are

latched on the falling edge of ALE. Tie ALE pin high if using nonmultiplexed mode.

ASB: In parallel Motorola multiplexed mode, the address is

sampled on the falling edge of ASB. Tie ASB pin high if using nonmultiplexed mode.

TS2: In hardware mode, this pin signal is one of the template

selection bits. See

Read Bar/Read Write Bar/Template Selection 1

RDB: In Intel host mode, this pin must be low for read operation.

RDB/RWB/TS1 85 I

RWB: In Motorola mode, this pin is low for write operation and

high for read operation.

TS1: In hardware mode, this pin signal is one of the template

selection bits. See

Serial Data Input/Write Bar/Data Strobe Bar/Template Selection 0

SDI: In the serial host mode, this pin is the serial input SDI. It is

sampled on the rising edge of SCLK. Data is input LSB first.

WRB: In Intel host mode, this pin is active low during write

operation. The data is sampled on the rising edge of WRB.

SDI/WRB/DSB/TS0 84 I

DSB: In the parallel Motorola mode, this pin is active low. During a

write operation the data is sampled on the rising edge of DSB. During a read operation the data (D[7:0] or AD[7:0]) is driven on the falling edge of DSB. In the nonmultiplexed Motorola mode, the address bus (A[5:0]) is latched on the falling edge of DSB.

Table 5-11.

TS0: In hardware mode, this pin signal is one of the template

select bits. See

Table 5-11.

15 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

Serial Data Out/Ready Output/Acknowledge Bar/Receive Impedance Off

SDO: In serial host mode, the SDO data is output on this pin. If a

serial write is in progress this pin is in high impedance. During a read SDO is high impedance when SDI is in command/ address mode. If CLKE is low, SDO is output on the rising edge of SCLK, if CLKE is high, SDO is output on the falling edge. Data is

SDO/RDY/ACKB/

RIMPOFF

83 I/O

output LSB first.

RDY: A low on this pin reports to the host that the cycle is not

complete and wait states must be inserted. A high means the cycle is complete.

ACKB: In Motorola parallel mode, a low on this pin indicates that

the read data is available for the host or that the written data cycle is complete.

RIMPOFF: In hardware mode when this input pin is high, all the

RTIP and RING pins have internal impedance switched off.

Active-Low Interrupt Bar. This interrupt signal is driven low when

an event is detected on any of the enabled interrupt sources in any of the register banks. When there are no active and enabled interrupt sources, the pin can be programmed to either drive high or not drive high (see Section

4.1.4). The reset default is to not

drive high when there are no active enabled interrupt sources. All

INTB

O, open drain

interrupt sources are disabled after a software reset and they must be programmed to be enabled.

D7/AD7/LP8 28

D6/AD6/LP7 27

D5/AD5/LP6 26

I/O (In

D4/AD4/LP5 25

mode, pulled

D3/AD3/LP4 24

DDIO

D2/AD2/LP3 23

D1/AD1/LP2 22

D0/AD0/LP1 21

Data Bus 7–0/Address/Data Bus 7–0/Loopback Select 8–1

D[7:0]: In nonmultiplexed host mode, these pins are the

bidirectional data bus.

AD[7:0]: In multiplexed host mode, these pins are the bidirectional

address/data bus. Note that AD7 and AD6 do not carry address information, and in serial host mode AD6–AD0 should be grounded.

In serial host mode, this pin should be tied low.

LP[8:1] In hardware mode, these pins set the loopback modes for

the corresponding LIU as follows:

/2)

Low → Remote Loopback

/2 → No Loopback

DDIO

High → Analog Loopback

Note: When left unconnected in hardware mode, do not route signals with fast transitions near LP1–LP8. This practice minimizes capacitive coupling.

16 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

Address Bus 4–0/G.772 Monitoring Control/Rx Impedance

A4/RIMPMSB 12

Mode Select

A[4:0]: These five pins are address pins in parallel host mode. In

A3/GMC3 13

serial host mode and multiplexed host mode, these pins should be grounded.

RIMPMSB: In hardware mode when this pin is low, the internal

A2/GMC2 14

impedance mode is selected, so all RTIP and RING pins require no external resistance component. When high, external impedance mode is selected so all RTIP and RING pins require

A1/GMC1 15

external resistance. GMC[3:0]: In hardware mode, these signal pins are used to select

a transmit line (TTIPn/TRINGn) or receive line (RTIPn/RRINGn)

A0/GMC0 16

for nonintrusive monitoring. Receiver 1 is used to monitor channels 2 to 8 See

Table 5-9.

Output Enable. If this pin is pulled low, all the transmitter outputs

OE 114 I

(TTIPn and TRINGn) are high impedance. Additionally, the user

may use this same pin to turn off all the impedance matching for the receivers at the same time if register bit

GMR.RHPMC is set.

Clock Edge. When CLKE is high, SDO is valid on the falling edge

of SCLK. When CLKE is low SDO is valid on the rising edge of

SCLK. When CLKE is high, the RCLKn for all the channels is

CLKE 115 I

inverted. This aligns RPOSn/RNEGn on the falling edge of RCLKn

and overrides the settings in register

RCLKI. When low,

RPOSn/RNEGn is aligned according to the settings in register

RCLKI.

JTAG

JTRSTB 95 I, pullup

JTAG Test Port Reset. This pin if low resets the JTAG port. If not

used it can be left floating.

JTAG Test Mode Select. This pin is clocked on the rising edge of

JTMS 96 I, pullup

JTCLK and is used to control the JTAG selection between scan and test machine control.

JTAG Test Clock. The data JTDI and JTMS are clocked on rising

JTCLK 97 I

edge of JTCLK and JTDO is clocked out on the falling edge of JTCLK.

JTDO 98

high-Z

JTAG Test Data Out. This is the serial output of the JTAG port.

The data is clocked out on the falling edge of JTCLK.

Test Data Input. This pin input is the serial data of the JTAG test.

JTDI 99 I, pullup

The data on JTDI is clocked on the rising edge of JTCLK. This pin can be left unconnected.

17 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

NAME PIN TYPE FUNCTION

POWER SUPPLIES

DVDD 19 —

DVSS 20 —

VDDIO 17, 92 —

VSSIO 18, 91 —

3.3V Digital Power Supply Digital Ground

3.3V I/O Power Supply I/O Ground

TVDD1 44

TVDD2 53

TVDD3 56

TVDD4 65

—

3.3V Power Supply for the Transmitter

TVDD5 116

TVDD6 125

TVDD7 128

TVDD8 137

TVSS1 47

TVSS2 50

TVSS3 59

TVSS4 62

TVSS5 119

TVSS6 122

TVSS7 131

TVSS8 134

AVDD 90 —

AVSS 89 —

—

Analog Ground for Transmitters

3.3V Analog Core Power Supply Analog Core Ground

18 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Figure 4-1. 144-Pin eLQFP Pin Assignment

NAME PIN NAME PIN NAME PIN NAME PIN

TPOS8/TDATA8 1 TPOS1/TDATA1 37 TPOS4/TDATA4 73 TNEG5 109

TCLK8 2 TNEG1 38 TCLK4 74 RCLK5 110 RLOS7 3 RCLK1 39 RLOS3 75 RPOS5/RDATA5 111

RNEG7/CV7 4 RPOS1/RDATA1 40 RNEG3/CV3 76 RNEG5/CV5 112

RPOS7/RDATA7 5 RNEG1/CV1 41 RPOS3/RDATA3 77 RLOS5 113

RCLK7 6 RLOS1/TECLK 42 RCLK3 78 OE 114

TNEG7 7 MUX/TIMPRM 43 TNEG3 79 CLKE 115

TPOS7/TDATA7 8 TVDD1 44 TPOS3/TDATA3 80 TVDD5 116

TCLK7 9 TTIP1 45 TCLK3 81 TTIP5 117

MCLK 10 TRING1 46 INTB 82 TRING5 118

MODESEL 11 TVSS1 47

A4/RIMPMSB 12 RTIP1 48 SDI/WRB/DSB/TS0 84 RTIP5 120

A3/GMC3 13 RRING1 49 RDB/RWB/TS1 85 RRING5 121 A2/GMC2 14 TVSS2 50 SCLK/ALE/ASB/TS2 86 TVSS6 122 A1/GMC1 15 TRING2 51 CSB/JAS 87 TRING6 123

A0/GMC0 16 TTIP2 52 MOTEL/CODE 88 TTIP6 124

VDDIO 17 TVDD2 53 AVSS 89 TVDD6 125 VSSIO 18 RRING2 54 AVDD 90 RRING6 126

DVDD 19 RTIP2 55 VSSIO 91 RTIP6 127

DVSS 20 TVDD3 56 VDDIO 92 TVDD7 128 D0/AD0/LP1 21 TTIP3 57 CLKA 93 TTIP7 129

D1/AD1/LP2 22 TRING3 58 N.C. 94 TRING7 130 D2/AD2/LP3 23 TVSS3 59 JTRSTB 95 TVSS7 131 D3/AD3/LP4 24 RTIP3 60 JTMS 96 RTIP7 132

D4/AD4/LP5 25 RRING3 61 JTCLK 97 RRING7 133 D5/AD5/LP6 26 TVSS4 62 JTDO 98 TVSS8 134 D6/AD6/LP7 27 TRING4 63 JTDI 99 TRING8 135

D7/AD7/LP8 28 TTIP4 64 TCLK6 100 TTIP8 136

TCLK2 29 TVDD4 65 TPOS6/TDATA6 101 TVDD8 137

TPOS2/TDATA2 30 RRING4 66 TNEG6 102 RRING8 138

TNEG2 31 RTIP4 67 RCLK6 103 RTIP8 139 RCLK2 32 RLOS4 68 RPOS6/RDATA6 104 RLOS8 140

RPOS2/RDATA2 33 RNEG4/CV4 69 RNEG6/CV6 105 RNEG8/CV8 141

RNEG2/CV2 34 RPOS4/RDATA4 70 RLOS6 106 RPOS8/RDATA8 142

RLOS2 35 RCLK4 71 TCLK5 107 RCLK8 143

TCLK1 36 TNEG4 72 TPOS5/TDATA5 108 TNEG8 144

SDO/RDY/ACKB/

RIMPOFF

83 TVSS5 119

19 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

4.1 Hardware and Host Port Operation

4.1.1 Hardware Mode

The DS26303 supports a hardware configuration mode that allows the user to configure the device through setting levels on the device’s pins. This mode allows the configuration of the DS26303 without the use of a microprocessor. Not all of the device features are supported in the hardware mode. To see all available options for this hardware mode, see the pin descriptions in

Table 4-2 provides two basic examples of configurations available in hardware mode by setting pins.

Table 4-1.

Table 4-2. Hardware Mode Configuration Examples

PIN NAME,

HARDWARE

MODE

STANDARD MODE CONFIGURATION

T1 E1

NOTES

TTIP[8:1] Output Output —

TRING[8:1] Output Output —

RTIP[8:1] Input Input —

RRING[8:1] Input Input —

TPOS[8:1] Input Input — TNEG[8:1] Input Input —

TCLK[8:1] Input: 1.544MHz Input: 2.048MHz —

RPOS[8:1] Output Output —

RNEG[8:1] Output Output —

RCLK[8:1] Output: 1.544MHz Output: 2.048MHz —

MCLK Input: 1.544MHz Input: 2.048MHz Used as recovery clock.

RLOS[8:1] Output Output Meets T1.231 and ITU-T G.775.

MODESEL 0 0 Low for hardware mode.

TIMPRM 0

(Part number ends in -75)

100Ω for T1 mode/75Ω E1 mode.

CODE 1 1 AMI encoding/decoding.

JAS N.C.: Pulled to V

TS[2:0] 111 000

RIMPOFF 0 0

INTB

N.C. N.C. Not used in hardware mode.

LP[8:1] N.C.: Pulled to V

/2 N.C.: Pulled to V

DDIO

/2 N.C.: Pulled to V

DDIO

/2 Jitter attenuator is not used.

DDIO

Set template T1 (655ft)-100Ω/E1-75Ω. Receive impedance should default to on.

/2 Internally pulled to V

DDIO

/2.

RIMPMS 0 0 Internal impedance mode selected.

GMC[3:0] 0000 0000 No monitoring enabled.

OE 1 1

CLKE 0 0

All TTIPn and TRINGn outputs are

enabled.

RPOSn/RNEGn are clocked on rising

edge.

JTRSTB Input, Pulled Up Input, Pulled Up JTAG.

JTMS Input Input —

JTCLK Input Input —

JTDO Output, High-Z Output, High-Z —

JTDI Input, Pulled Up Input, Pulled Up — RSTB Input, Pullup Input, Pullup Reset. CLKA N.C. N.C. Not available in hardware node.

PIN 94 N.C. N.C. —

20 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

4.1.2 Serial Port Operation

Setting MODESEL = VDDIO/2 enables the serial bus interface on the DS26303. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section the AC timing of the serial port. All serial port accesses are LSB first. See

Figure 4-2 to Figure 4-4.

10.3 for

This port is compatible with the SPI interface defined for Motorola processors. An example of this is Motorola’s MMC2107.

Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write (0). The next 5 bits identify the register address (A1 to A5; A6 and A7 are ignored).

All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.

Figure 4-2. Serial Port Operation for Write Access

12345678910111213141516SCLK

CSB

SDI

DO D6

A1 A2 A3 A4 A5 A6 X

(lsb)

WRITE ACCESS ENABLED

SDO

(msb)

D1 D2 D3 D4 D5 D7

(lsb) (msb)

Figure 4-3. Serial Port Operation for Read Access with CLKE = 0

1234 56789 10111213141516

SCLK

CSB

SDI

(msb)

D1 D2 D3 D4 D5 D6

(lsb)

SDO

Read Access Enabled

A1 A2 A3 A4 A5

(lsb)

(msb)

21 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Figure 4-4. Serial Port Operation for Read Access with CLKE = 1

SCLK

123456 78910111213141516

CSB

SDI

A1 A2 A3 A4 A5

(lsb)

SDO

4.1.3 Parallel Port Operation

When using the parallel interface on the DS26303 the user has the option for either multiplexed bus operation or non-multiplexed bus operation. The ALE pin is pulled high in non-multiplexed bus operation. The DS26303 can operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects the Intel mode. The parallel port is only operational if the MODESEL pin is pulled high. The following table lists all the pins and their functions in the parallel port mode. See the timing diagrams in Section

(msb)

(lsb)

D3 D4 D5

(msb)

10 for more details.

Table 4-3. Parallel Port Mode Selection and Pin Functions

MODESEL, MOTEL,

MUX

100 Non-multiplexed Motorola 110 Non-multiplexed Intel 101 Multiplexed Motorola 111 Multiplexed Intel

4.1.4 Interrupt Handling

INTB must be pulled high externally with a 10kΩ resistor for wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when not active by setting register

There are three events that can potentially trigger an interrupt: a loss of signal (LOS), driver fault monitor (DFM), or an alarm indication signal (AIS). The interrupt functions as follows:

• When a status bit ( corresponding interrupt status bit ( low if the event is enabled through the corresponding interrupt-enable bit (

LOSIE:LOSIEn).

• When an interrupt occurs, the host processor must read the three interrupt status registers (

LOSIS) to determine the source of the interrupt. If the interrupt status registers are set for clear-on-read

GISC.CWE reset), the read also clears the interrupt status register, which clears the output INTB pin. If the

( interrupt status registers are set for clear-on-write (

AISIS:AISIn, DFMIS:DFMISn, or LOSIS:LOSISn) in order to clear it, which clears the output INTB pin.

bit (

• Subsequently, the host processor can read the corresponding status register ( the real-time status of the event.

Note: The BERT can also generate an interrupt. The BERT interrupt handling is described in Section

PARALLEL HOST

INTERFACE

ADDRESS, DATA, AND CONTROL

CSB, ACKB, DSB, RWB, ASB, A[4:0], D[7:0], INTB CSB, RDY, WRB, RDB, ALE, A[4:0], D[7:0], INTB CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB CSB, RDY, WRB, RDB, ALE, AD[7:0], INTB

GISC.INTM.

AIS:AISn, DFMS:DFMSn, or LOSS:LOSn) changes on an interruptible event, the

AISIS:AISIn, DFMIS:DFMISn, or LOSIS:LOSISn) is set. The INTB pin will go

AISIE:AISIEn, DFMIE:DFMIEn, or

AISIS, DFMIS, and

GISC.CWE set), a 1 must be written to the interrupt status

AIS, DFMS, or LOSS) to check

6.9.2.

22 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Figure 4-5. Interrupt Handling Flow Diagram

Interrupt Allowed

Interrupt Conditon

Read Interrupt Status

Read Corresponding Status

Service the Interrupt

Exist?

Yes

23 of 101

DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

5 REGISTERS

Five address bits are used to control the settings of the registers. AD[4:0] are used in both the parallel nonmultiplexed mode and in multiplexed mode. In serial mode, the address is input serially on SDI. The register space contains control for channels 1 to 8 from address 00 hex to 1F hex. The pointer to access the different banks of registers. This register must be set to AA hex for access of the secondary bank of registers, 01 hex for access to the individual LIU bank of registers, and 02 hex for access of the BERT bank of registers. The primary bank of registers is accessed upon reset of this register to 00 hex.

Table 5-1. Primary Register Set

ADDRESS

Identification ID 00 xxx00000 xx00000 R Analog Loopback Configuration ALBC 01 xxx00001 xx00001 RW Remote Loopback Configuration RLBC 02 xxx00010 xx00010 RW Transmit All-Ones Enable TAOE 03 xxx00011 xx00011 RW Loss-of-Signal Status LOSS 04 xxx00100 xx00100 RW Driver Fault Monitor Status DFMS 05 xxx00101 xx00101 RW Loss-of-Signal Interrupt Enable LOSIE 06 xxx00110 xx00110 RW Driver Fault Monitor Interrupt Enable DFMIE 07 xxx00111 xx00111 RW Loss-of-Signal Interrupt Status LOSIS 08 xxx01000 xx01000 R Driver Fault Monitor Interrupt Status DFMIS 09 xxx01001 xx01001 R Software Reset SWR 0A xxx01010 xx01010 W G.772 Monitor Control GMC 0B xxx01011 xx01011 RW Digital Loopback Configuration DLBC 0C xxx01100 xx01100 RW LOS/AIS Criteria Selection LASCS 0D xxx01101 xx01101 RW Automatic Transmit All-Ones Select ATAOS 0E xxx01110 xx01110 RW Global Configuration GC 0F xxx01111 xx01111 RW Template Select Transceiver TST 10 xxx10000 xx10000 RW Template Select TS 11 xxx10001 xx10001 RW Output-Enable Bar OEB 12 xxx10010 xx10010 RW Alarm Indication Signal Status AIS 13 xxx10011 xx10011 R AIS Interrupt Enable AISIE 14 xxx10100 xx10100 RW AIS Interrupt Status AISIS 15 xxx10101 xx10101 R

Reserved — 16–1E

Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW

HEX

PARALLEL

INTERFACE

A[7:0] (HEX)

xxx10110–

xxx11110

ADDP (1F) register is used as a

SERIAL

INTERFACE

A[7:1] (HEX)

xx10110–

xx11110

—

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Table 5-2. Secondary Register Set

ADDRESS

Single-Rail Mode Select SRMS 00 xxx00000 xx00000 RW Line Code Selection LCS 01 xxx00001 xx00001 RW Reserved — 02 xxx00010 xx00010 — Receive Power-Down Enable RPDE 03 xxx00011 xx00011 RW Transmit Power-Down Enable TPDE 04 xxx00100 xx00100 RW Excessive Zero Detect Enable EZDE 05 xxx00101 xx00101 RW Code Violation Detect Enable Bar CVDEB 06 xxx00110 xx00110 RW

Reserved — 07–1E

Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW

HEX

PARALLEL INTERFACE A[7:0] (HEX)

xxx00111–

xxx11110

SERIAL INTERFACE A[7:1] (HEX)

xx00111–

xx11110

—

Table 5-3. Individual LIU Register Set

ADDRESS

Individual Jitter Attenuator Enable IJAE 00 xxx00000 xx00000 RW Individual Jitter Attenuator Position Select IJAPS 01 xxx00001 xx00001 RW Individual Jitter Attenuator FIFO Depth Select IJAFDS 02 xxx00010 xx00010 RW Individual Jitter Attenuator FIFO Limit Trip IJAFLT 03 xxx00011 xx00011 R Individual Short Circuit Protection Disabled ISCPD 04 xxx00100 xx00100 RW Individual AIS Select IAISEL 05 xxx00101 xx00101 RW Master Clock Select MC 06 xxx00110 xx00110 RW Global Management Register GMR 07 xxx00111 xx00111 RW

Reserved — 08–0B

Reserved — 0C–0F

Bit Error Rate Tester Control BTCR 10 xxx10000 xx10000 RW BPV Error Insertion BEIR 11 Xxx10001 xxx10001 RW Line Violation Detect Status LVDS 12 xxx10010 xx10010 R Receive Clock Invert RCLKI 13 xxx10011 xx10011 RW Transmit Clock Invert TCLKI 14 xxx10100 xx10100 RW Clock Control CCR 15 xxx10101 xx10101 RW RCLK Disable Upon LOS RDULR 16 xxx10110 xx10110 RW Global Interrupt Status Control GISC 1E xxx11110 xx11110 RW Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW

HEX

PARALLEL INTERFACE A[7:0] (HEX)

xxx01000–

xxx01011

xxx01100–

xxx01111

SERIAL INTERFACE A[7:1] (HEX)

xx01000–

xx01011

xx01100–

xx01111

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Table 5-4. BERT Register Set

ADDRESS

BERT Control BCR 00 xxx00000 xx00000 RW Reserved — 01 xxx00001 xx00001

BERT Pattern Configuration 1 BPCR1 02 xxx00010 xx00010 RW BERT Pattern Configuration 2 BPCR2 03 xxx00011 xx00011 RW BERT Seed/Pattern 1 BSPR1 04 xxx00100 xx00100 RW BERT Seed/Pattern 2 BSPR2 05 xxx00101 xx00101 RW BERT Seed/Pattern 3 BSPR3 06 xxx00110 xx00110 RW BERT Seed/Pattern 4 BSPR4 07 xxx00111 xx00111 RW Transmit Error-Insertion Control TEICR 08 xxx01000 xx01000 RW

Reserved — 09–0B

BERT Status BSR 0C xxx01100 xx01100 R Reserved — 0D xxx01101 xx01101 — BERT Status Register Latched BSRL 0E xxx01110 xx01110 RW Reserved — 0F xxx01111 xx01111 — BERT Status Register Interrupt Enable BSRIE 10 xxx10000 xx10000 RW

Reserved — 11–13

Receive Bit-Error Count Register 1 RBECR1 14 xxx10100 xx10100 R Receive Bit-Error Count Register 2 RBECR2 15 xxx10101 xx10101 R Receive Bit-Error Count Register 3 RBECR3 16 xxx10110 xx10110 R Reserved — 17 xxx10111 xx10111 — Receive Bit Count Register 1 RBCR1 18 xxx11000 xx11000 R Receive Bit Count Register 2 RBCR2 19 xxx11001 xx11001 R Receive Bit Count Register 3 RBCR3 1A xxx11010 xx11010 R Receive Bit Count Register 4 RBCR4 1B xxx11011 xx11011 R

Reserved — 1C–1E

Address Pointer for Bank Selection ADDP 1F xxx11111 xx11111 RW

HEX

PARALLEL

INTERFACE

A7–A0 (HEX)

xxx01001–

xxx01010

xxx10001–

xxx10011

xxx11100–

xxx11110

SERIAL

INTERFACE

A7–A1 (HEX)

xx01001–

xx01010—

xx10001–

xx10011

xx11100–

xx11110

—

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Table 5-5. Primary Register Set Bit Map

ID 00 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

ALBC 01 RW ALBC8 ALBC7 ALBC6 ALBC5 ALBC4 ALBC3 ALBC2 ALBC1 RLBC 02 RW RLBC8 RLBC7 RLBC6 RLBC5 RLBC4 RLBC3 RLBC2 RLBC1 TAOE 03 RW TAOE8 TAOE7 TAOE6 TAOE5 TAOE4 TAOE3 TAOE2 TAOE1 LOSS 04 RW LOSS8 LOSS7 LOSS6 LOSS5 LOSS4 LOSS3 LOSS2 LOSS1 DFMS 05 RW DFMS8 DFMS7 DFMS6 DFMS5 DFMS4 DFMS3 DFMS2 DFMS1

LOSIE 06 RW LOSIE8 LOSIE7 LOSIE6 LOSIE5 LOSIE4 LOSIE3 LOSIE2 LOSIE1 DFMIE 07 RW DFMIE8 DFMIE7 DFMIE6 DFMIE5 DFMIE4 DFMIE3 DFMIE2 DFMIE1 LOSIS 08 R LOSIS8 LOSIS7 LOSIS6 LOSIS5 LOSIS4 LOSIS3 LOSIS2 LOSIS1 DFMIS 09 R DFMIS8 DFMIS7 DFMIS6 DFMIS5 DFMIS4 DFMIS3 DFMIS2 DFMIS1

SWR 0A W SWR8 SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1

GMC 0B RW BERTDIR BMCKS BTCKS — GMC3 GMC2 GMC1 GMC0 DLBC 0C RW DLBC8 DLBC7 DLBC6 DLBC5 DLBC4 DLBC3 DLBC2 DLBC1

LASCS 0D RW LASCS8 LASCS7 LASCS6 LASCS5 LASCS4 LASCS3 LASCS2 LASCS1 ATAOS 0E RW ATAOS8 ATAOS7 ATAOS6 ATAOS5 ATAOS4 ATAOS3 ATAOS2 ATAOS1

GC 0F RW RIMPMS AISEL SCPD CODE JADS — JAPS JAE

TST 10 RW — — — — — TST2 TST1 TST0

TS 11 RW RIMPOFF TIMPOFF — — TIMPRM TS2 TS1 TS0

OEB 12 RW OEB8 OEB7 OEB6 OEB5 OEB4 OEB3 OEB2 OEB1

AIS 13 R AIS8 AIS7 AIS6 AIS5 AIS4 AIS3 AIS2 AIS1 AISIE 14 RW AISIE8 AISIE7 AISIE6 AISIE5 AISIE4 AISIE3 AISIE2 AISIE1 AISIS 15 R AISI8 AISI7 AISI6 AISI5 AISI4 AISI3 AISI2 AISI1

Reserved 16-1E — — — — — — — — —

ADDP 1F RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

Note: Underlined bits are read-only.

Table 5-6. Secondary Register Set Bit Map

SRMS 00 RW SRMS8 SRMS7 SRMS6 SRMS5 SRMS4 SRMS3 SRMS2 SRMS1

LCS 01 RW LCS8 LCS7 LCS6 LCS5 LSC4 LCS3 LSC2 LSC1

Reserved 02 RW — — — — — — — —

RPDE 03 RW RPDE8 RPDE7 RPDE6 RPDE5 RPDE4 RPDE3 RPDE2 RPDE1 TPDE 04 RW TPDE8 TDPE7 TPDE6 TPDE5 TPDE4 TPDE3 TPDE2 TPDE1 EZDE 05 RW EZDE8 EZDE7 EZDE6 EZDE5 EZDE4 EZDE3 EZDE2 EZDE1

CVDEB 06 RW CVDEB8 CVDEB7 CVDEB6 CVDEB5 CVDEB4 CVDEB3 CVDEB2 CVDEB1

Reserved 07-1E — — — — — — — — —

ADDP 1F RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

Table 5-7. Individual LIU Register Set Bit Map

IJAE 00 RW IJAE8 IJAE7 IJAE6 IJAE5 IJAE4 IJAE3 IJAE2 IJAE1

IJAPS 01 RW IJAPS8 IJAPS7 IJAPS6 IJAPS5 IJAPS4 IJAPS3 IJAPS2 IJAPS1 IJAFDS 02 RW IJAFDS8 IJAFDS7 IJAFDS6 IJAFDS5 IJAFDS4 IJAFDS3 IJAFDS2 IJAFDS1 IJAFLT 03 R IJAFLT8 IJAFLT7 IJAFLT6 IJAFLT5 IJAFLT4 IJAFLT3 IJAFLT2 IJAFLT1

ISCPD 04 RW ISCPD8 ISCPD7 ISCPD6 ISCPD5 ISCPD4 ISCPD3 ISCPD2 ISCPD1

IAISEL 05 RW IAISEL8 IAISEL7 IAISEL6 IAISEL5 IAISEL4 IAISEL3 IAISEL2 IAISEL1

MC 06 RW — PCLKI TECLKE CLKAE MPS1 MPS0 FREQS PLLE

GMR 07 RW — — — — — JABWS1 JABWS0 RHPMC

Reserved 08 RW — — — — — — — — Reserved 09 RW — — — — — — — — Reserved 0A RW — — — — — — — — Reserved 0B RW — — — — — — — — Reserved 0C R — — — — — — — — Reserved 0D R — — — — — — — — Reserved 0E R — — — — — — — — Reserved 0F R — — — — — — — —

BTCR 10 RW BTS2 BTS1 BTS0 — — — — BERTE

BEIR 11 RW BEIR8 BEIR7 BEIR6 BEIR5 BEIR4 BEIR3 BEIR2 BEIR1

LVDS 12 R LVDS8 LVDS7 LVDS6 LVDS5 LVDS4 LVDS3 LVDS2 LVDS1

RCLKI 13 RW RCLKI8 RCLKI7 RCLKI6 RCLKI5 RCLKI4 RCLKI3 RCLKI2 RCLKI1

TCLKI 14 RW TCLKI8 TCLKI7 TCLKI6 TCLKI5 TCLKI4 TCLKI3 TCLKI2 TCLKI1

CCR 15 RW PCLKS2 PCLKS1 PCLKS0 TECLKS CLKA3 CLKA2 CLKA1 CLKA0

RDULR 16 RW RDULR8 RDULR7 RDULR6 RDULR5 RDULR4 RDULR3 RDULR2 RDULR1

GISC 1E RW — — — — — — INTM CWE

ADDP 1F RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

Note: Underlined bits are read-only.

Table 5-8. BERT Register Bit Map

BCR 00 RW PMUM LPMU RNPL RPIC MPR APRD TNPL TPIC

Reserved 01 — — — — — — — — —

BPCR1 02 RW — QRSS PTS PLF4 PLF3 PLF2 PLF1 PLF0 BPCR2 03 RW — — — PTF4 PTF3 PTF2 PTF1 PTF0

BSPR1 04 RW BSP7 BSP6 BSP5 BSP4 BSP3 BSP2 BSP1 BSP0

BSPR2 05 RW BSP15 BSP14 BSP13 BSP12 BSP11 BSP10 BSP9 BSP8

BSPR3 06 RW BSP23 BSP22 BSP21 BSP20 BSP19 BSP18 BSP17 BSP16

BSPR4 07 RW BSP31 BSP30 BSP29 BSP28 BSP27 BSP26 BSP25 BSP24

TEICR 08 RW — — TEIR2 TEIR1 TEIR0 BEI TSEI MEIMS

Reserved 09–0B — — — — — — — — —

BSR 0C R — — — — PMS — BEC OOS

Reserved 0D — — — — — — — — —

BSRL 0E R — — — — PMSL BEL BECL OOSL

Reserved 0F — — — — — — — — —

BSRIE 10 RW — — — — PMSIE BEIE BECIE OOSIE

Reserved 11–13 — — — — — — — — —

RBECR1 14 R BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0

RBECR2 15 R BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8

RBECR3 16 R BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16

Reserved 17 — — — — — — — — —

RBCR1 18 R BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

RBCR2 19 R BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8

RBCR3 1A R BC23 BC22 BC21 BC20 BC19 BC18 BC17 BC16

RBCR4 1B R BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24

Reserved 1C–1E — — — — — — — — —

ADDP 1F RW ADDP7 ADDP6 ADDP5 ADDP4 ADDP3 ADDP2 ADDP1 ADDP0

Note: Underlined bits are read-only.

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

5.1 Register Description

This section details the register description of each bit. Whenever the variable “n” in italics is used in any of the

5.1.1 Primary Registers

Bit # 7 6 5 4 3 2 1 0 Name ID7

Bit 7: Device CODE ID Bit 7 (ID7). This bit is zero for the 75Ω impedance part number and one for the 120Ω

impedance part number.

Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device

contains.

Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID2 to ID0). These bits tell the user the revision of the part. Contact the

factory for details.

ID6 ID5 ID4 ID3 ID2 ID1 ID0

ID Identification Register 00h

Bit # 7 6 5 4 3 2 1 0 Name ALBC8 ALBC7 ALBC6 ALBC5 ALBC4 ALBC3 ALBC2 ALBC1 Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Analog Loopback Configuration Bits Channel n (ALBCn). When this bit is set, LIUn is placed in analog loopback. TTIPn and TRINGn are looped back to RTIPn and RRINGn. The data at RTIPn and RRINGn is

ignored. The LOS detector is still in operation. The jitter attenuator is in use if enabled for the transmitter or receiver.

Bit # 7 6 5 4 3 2 1 0 Name RLBC8 RLBC7 RLBC6 RLBC5 RLBC4 RLBC3 RLBC2 RLBC1 Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Remote Loopback Configuration Bits Channel n (RLBCn). When this bit is set, remote loopback is enabled on LIUn. The analog-received signal goes through the receiver and is looped back to the transmitter. The data at TPOSn and TNEGn is ignored. The jitter attenuator is in use if enabled. Note: LIUn is placed in dual

loopback if

DLBC:DLBCn is also set.

ALBC Analog Loopback Configuration Register 01h

RLBC Remote Loopback Configuration Register 02h

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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit

TAOE Transmit All-Ones Enable Register 03h

Bit # 7 6 5 4 3 2 1 0 Name TAOE8 TAOE7 TAOE6 TAOE5 TAOE4 TAOE3 TAOE2 TAOE1 Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Transmit All-Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of all ones is sent on channel n (TTIPn and TRINGn). MCLK is used as a reference clock for the transmit all-ones signal. The data arriving at TPOSn and TNEGn is ignored.

LOSS Loss-of-Signal Status Register 04h

Bit # 7 6 5 4 3 2 1 0 Name LOSS8

LOSS7 LOSS6 LOSS5 LOSS4 LOSS3 LOSS2 LOSS1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Loss-of-Signal Status Channel n (LOSSn). When this bit is set, an LOS condition has been detected on LIUn. The criteria and conditions of LOS are described in Section

6.4.3: Loss of Signal.

DFMS Driver Fault Monitor Status Register 05h

Bit # 7 6 5 4 3 2 1 0 Name DFMS8

DFMS7 DFMS6 DFMS5 DFMS4 DFMS3 DFMS2 DFMS1

Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short or open circuit at the transmit driver for LIUn.

LOSIE Loss-of-Signal Interrupt Enable Register 06h

Bit # 7 6 5 4 3 2 1 0 Name LOSIE8 LOSIE7 LOSIE6 LOSIE5 LOSIE4 LOSIE3 LOSIE2 LOSIE1 Default 0 0 0 0 0 0 0 0

Bits 7 to 0: Loss-of-Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in the LOS status for LIUn can generate an interrupt.

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+ 71 hidden pages

MAXIM DS26303 User Manual

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1 DETAILED DESCRIPTION

2 TELECOM SPECIFICATIONS COMPLIANCE

3 BLOCK DIAGRAMS

4 PIN DESCRIPTION

4.1 Hardware and Host Port Operation

4.1.1 Hardware Mode

4.1.2 Serial Port Operation

4.1.3 Parallel Port Operation

5 REGISTERS

5.1 Register Description