MAXIM DS2482-800 User Manual

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DS2482-800

www.maxim-ic.com

Eight-Channel 1-Wire Maste

GENERAL DESCRIPTION

The DS2482-800 is an I²C* to 1-Wireâ bridge device
that interfaces directly to standard (100kHz max) or
fast (400kHz max) I²C masters to perform bi­directional protocol conversion between the I²C
master and any downstream 1-Wire slave devices.
Relative to any attached 1-Wire slave device, the
DS2482-800 is a 1-Wire master. Internal factory­trimmed timers relieve the system host processor
from generating time-critical 1-Wire waveforms,
supporting both standard and Overdrive 1-Wire
communication speeds. To optimize 1-Wire
waveform generation, the DS2482-800 performs
slew-rate control on rising and falling 1-Wire edges
and has a programmable feature to mask the fast
presence pulse edge that some 1-Wire slave devices
can generate. Programmable strong pullup features
support 1-Wire power delivery to 1-Wire devices such
as EEPROMs and sensors. The DS2482-800
combines these features with eight independent 1­Wire I/O channels. The I²C slave address assignment
is controlled by three binary address inputs, resolving
potential conflicts with other I²C slave devices in the
system.

APPLICATIONS

§ Wireless Base Stations

§ Central Office Switches

§ PBXs

§ Rack-Based Servers

§ Medical Clinical Diagnostic Equipment

TYPICAL OPERATING CIRCUIT

V

CC

R

P

SDA

(I²C port)

µC

Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under
the Philips I
defined by Philips.
1-Wire is a registered trademark of Dallas Semiconductor.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

2

C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as

SCL

AD0
AD1
AD2

DS2482 800

IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7

1-Wire lines

R

t

1 of 22

1-Wire
Device #1

1-Wire
Device #2

FEATURES

§ I²C Host Interface, Supports 100kHz and 400kHz
I²C Communication Speeds

§ 1-Wire Master I/O with Selectable Active or
Passive 1-Wire Pullup

§ Provides Reset/Presence, 8-Bit, Single-Bit, and
Three-Bit 1-Wire I/O Sequences

§ Eight Channels of Independently Operated
1-Wire I/O

§ Standard and Overdrive 1-Wire Communication
Speeds

§ Slew Controlled 1-Wire Edges

§ Selectable 1-Wire Slave Presence Pulse Falling

Edge Masking to Control Fast Edges on the
1-Wire Line

§ Supports Low-Impedance 1-Wire Strong Pullup
for EEPROMs, Temp Sensors, or Other 1-Wire
Slaves That Have Momentary High Current
Modes

§ Three Address Inputs for I²C Address
Assignment

§ Wide Operating Range: 2.9V to 5.5V, -40°C to
+85°C

§ 16-Pin SO Package (150 mil)

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2482S-800
DS2482S-800/T&R

-40 to +85°C

-40 to +85°C

16 SO (150 mil )
16 SO (150 mil )

PIN CONFIGURATION

IO3

SCL

SDA

VDD

NC

AD2

AD1

AD0

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

IO2

IO1

IO0

GND

IO4

IO5

IO6

9

IO7

.

REV: 110204

DS2482-800: Eight-Channel 1-Wire Master

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current Into Any Pin
Operating Temperature Range
Junction Temperature

+150°C

Storage Temperature Range
Soldering Temperature

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

±20mA

-40°C to +85°C

-55°C to +125°C

See IPC/JEDEC J-STD-020A

ELECTRICAL CHARACTERISTICS

(VCC = 2.9V to 5.5V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC

Operating Current ICC (Note 1) 0.75 mA

1-Wire Input High V

1-Wire Input Low V

1-Wire Weak Pullup Resistor R

1-Wire Output Low V

Active Pullup On Time t

Strong Pullup Voltage Drop DV

3.3V Pulldown Slew Rate
(Note 6)

5V Pulldown Slew Rate
(Note 6)

3.3V Pullup Slew Rate (Note 6) PU

5V Pullup Slew Rate (Note 6) PU

Power-On Reset Trip Point V

WPU

APUOT

STRPU

PD

PD

POR

IH1

IL1

OL1

SRC

SRC

SRC

SRC

1-Wire TIMING (Note 16) See Figures 3, 5, 6, and 7

Write 1/Read Low Time t

Read Sample Time t

1-Wire Time Slot t

W1L

MSR

slot

Fall Time High-to-Low at
Standard Speed (Note 6)

t

Fall Time High-to-Low at

F1

Overdrive Speed (Note 6)

3.3V 2.9 3.3 3.7
5V 4.5 5.0 5.5

3.3V (Notes 2, 3) 1.9
5V (Notes 2, 3) 3.4

3.3V (Notes 2, 3) 0.75
5V (Notes 2, 3) 1.0

(Note 4) 800 1675

V

V

V

W

At 4mA load 0.4 V

Standard (Notes 4, 16) 2.3 2.5 2.7
Overdrive (Notes 4, 16) 0.4 0.5 0.6

VCC ³ 3.2V, 1.5mA load

VCC ³ 5.2 V, 3mA load

Standard (3.3V ±10%)
Overdrive (3.3V ±10%)
Standard (5.0V ±10%)

Overdrive (5.0V ±10%)
Standard (3.3V ±10%)
Overdrive (3.3V ±10%)

Standard (5.0V ±10%)
Overdrive (5.0V ±10%)

0.3

0.5

1 4.2
5 22.1
2 6.5

10 40

0.8 4

2.7 20

1.3 6

3.4 31

µs

V

V/µs

V/µs

V/µs

V/µs

2.2 V

Standard 7.6 8 8.4
Overdrive 0.9 1 1.1

Standard 13.3 14 15

Overdrive 1.4 1.5 1.8

Standard 65.8 69.3 72.8

µs

µs

µs

Overdrive 9.9 10.5 11.0

3.3V to 0V (Note 5) 0.54 3.0

5.0V to 0V (Note 5) 0.55 2.2

3.3V to 0V (Note 5) 0.10 0.59

µs

5.0V to 0V (Note 5) 0.09 0.44

2 of 22

DS2482-800: Eight-Channel 1-Wire Master

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Write 0 Low Time t

Write 0 Recovery Time t

Reset Low Time t

Presence-Detect Sample Time t

Sampling for Short and
Interrupt

Reset High Time t

Presence Pulse Mask Start t
Presence Pulse Mask Stop t

W0L

REC0

RSTL

MSP

t

SI

RSTH

ppm1

ppm2

Standard 60 64 68

µs

Overdrive 7.1 7.5 7.9

Standard 5.0 5.3 5.6

Overdrive 2.8 3.0 3.2

Standard 570 600 630

Overdrive 68.4 72 75.6

Standard 66.5 70 73.5

Overdrive 7.1 7.5 7.9

Standard 7.6 8 8.4

Overdrive 0.7 0.75 0.8

Standard 554.8 584 613.2

Overdrive 70.3 74 77.7

µs

µs

µs

µs

µs

(Note 7) 9.5 10 10.5 µs
(Note 7) 57 60 63 µs

I²C-Pins (Note 8) See Figure 10

VCC = 2.9V to 3.7V

LOW Level Input Voltage VIL

= 4.5V to 5.5V

V

CC

HIGH Level Input Voltage VIH

Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage at
3mA Sink Current
Output Fall Time from V
V

with a Bus Capacitance

ILmax

Ihmin

to

V

hys

V

0.4 V

OL

tof 60 250 ns

-0.5

0.7 ×
V

CC

0.05 ×
V

CC

V

0.25 ×
V

CC

0.22 ×
V

CC

V

+

CC

0.5V

V

V

from 10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter

t

SDA and SCL pins only 50 ns

SP

Input Current Each I/O Pin with
an Input Voltage Between

0.1V

CCmax

and 0.9V

CCmax

(Notes 9, 10) -10 10 µA

I

i

Input Capacitance Ci (Note 9) 10 pF
SCL Clock Frequency f

0 400 kHz

SCL

Hold Time (Repeated) START
Condition. After this Period, the

t

0.6 µs

HD:STA

First Clock Pulse is Generated.
LOW Period of the SCL Clock t
HIGH Period of the SCL Clock t
Setup Time for a Repeated
START Condition
Data Hold Time t
Data Setup Time t
Setup Time for STOP Condition t
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line

Oscillator Warm-Up Time

1.3 µs

LOW

0.6 µs

HIGH

t

0.6 µs

SU:STA

(Notes 11, 12) 0.9 µs

HD:DAT

(Note 13) 250 ns

SU:DAT

0.6 µs

SU:STO

t

1.3 µs

BUF

C

(Note 14) 400 pF

b

t

(Note 15) 100 µs

OSCWUP

3 of 22

Note 1:

Operating current with 1-Wire write byte sequence followed by continuous Read of Status Register at
400KHz in Overdrive.

Note 2:

With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the
passive pullup on threshold V
capacitive load on the 1-Wire bus must not exceed 300pF.

Note 3:
Note 4:
Note 5:
Note 6:

Active pullup guaranteed to turn on between V
Active or resistive pullup choice is configurable.
Fall time high to low (t
These values apply at full load, i. e., 1nF at standard speed and 0.3nF at Overdrive speed. For
reduced load, the pulldown slew rate is slightly faster.

Note 7:
Note 8:
Note 9:
Note 10:
Note 11:

Presence pulse masking only applies to standard speed.
All I²C timing values are referred to V
Applies to SDA, SCL, and AD0, AD1, AD2.
I/O pins of the DS2482 do not obstruct the SDA and SCL lines if V
The DS2482 provides a hold time of at least 300ns for the SDA signal (referred to the V
signal) to bridge the undefined region of the falling edge of SCL.

Note 12:

The maximum t
SCL signal.

Note 13:

A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t

³250ns must then be met. This is automatically the case if the device does not stretch the LOW

SU:DAT

period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
standard-mode I²C-bus specification) before the SCL line is released.

Note 14:

C

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according

B

to I²C-Bus Specification v2.1 are allowed.

Note 15:
Note 16:

I²C communication should not take place for the max t
Except for t

F1

Therefore, if one of these parameters is found to be off the typical value, it is safe to assume that all of
these parameters deviate from their typical value in the same direction and by the same degree.

PIN DESCRIPTION

may not be reached in the available time. With Overdrive speed the

IL1

IL1MAX

) is derived from PD

F1

IHmin

has only to be met if the device does not stretch the LOW period (t

HD:DAT

referenced from 0.9 × VCC to 0.1 × VCC.

SRC,

and V

ILmax

, all 1-Wire timing specifications and t

DS2482-800: Eight-Channel 1-Wire Master

and V

IH1MIN

.

levels.

is switched off.

CC

= 1000 + 250 = 1250ns (according to the

SU:DAT

time following a power-on reset.

OSCWUP

are derived from the same timing circuit.

APUOT

of the SCL

IHmin

) of the

LOW

PIN NAME FUNCTION

1 IO3 IO Driver for 1-Wire Line #3
2 SCL I²C Serial Clock Input; must be tied to VCC through a pullup resistor.
3 SDA I²C Serial Data Input/Output; must be tied to VCC through a pullup resistor.
4 VCC Power Supply Input
5 NC Not Connected
6 AD2
7 AD1
8 AD0

I²C Address Inputs; must be tied to VCC or GND. These inputs determine the I²C slave
address of the device, see Figure 9.

9 IO7 IO Driver for 1-Wire Line #7
10 IO6 IO Driver for 1-Wire Line #6
11 IO5 IO Driver for 1-Wire Line #5
12 IO4 IO Driver for 1-Wire Line #4
13 GND Ground Reference
14 IO0 IO Driver for 1-Wire Line #0
15 IO1 IO Driver for 1-Wire Line #1
16 IO2 IO Driver for 1-Wire Line #2

4 of 22

Figure 1. Block Diagram

AD0AD1A

DS2482-800: Eight-Channel 1-Wire Master

SDA

SCL

D2

T-Time OSC

Config

Register

I²C

Interface

Controller

I/O

Controller

Status

Register

Read Data

Register

Channel

Select

Line

XCVR

Line

XCVR

Line

XCVR

Line

XCVR

Line

XCVR

Line

XCVR

Line

XCVR

Line

XCVR

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

DETAILED DESCRIPTION

The DS2482-800 is a self-timed 8-channel 1-Wire master, which supports advanced 1-Wire waveform features
including standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence pulse
masking. Once supplied with command and data, the I/O controller of the DS2482 performs time-critical 1-Wire
communication functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for
ROM Search, without requiring interaction with the host processor. The host obtains feedback (completion of a 1­Wire function, presence pulse, 1-Wire short, search direction taken) through the Status Register and data through
the Read Data register. The DS2482 communicates with a host processor through its I²C bus interface in standard­mode or in fast-mode. The logic state of three address pins (2 address pins with the 1-channel version) determines
the I²C slave address of the DS2482, allowing up to 8 devices operating on the same bus segment without
requiring a hub.

DEVICE REGISTERS

The DS2482 has four registers that the I²C host can read: Channel Selection, Configuration, Status, and Read
Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the
host will read in a subsequent read access, is defined by the instruction that the has DS2482 executed last. The
host has read and write access to the Channel Selection and Configuration Registers to select one of several 1­Wire channels and to enable certain 1-Wire features.

5 of 22

DS2482-800: Eight-Channel 1-Wire Master

g

A

A

Channel Selection Register

The content of the Channel Selection Register specifies which of the channels is selected and will be the target of
subsequent 1-Wire communication commands. The DS2482-800 supports eight 1-Wire communication channels
IO0 to IO7. Only one of these channels can be active/selected at any time. Once selected, a 1-Wire channel
remains selected until a different channel is selected through the Channel Select command or by initiating a
device reset. After a device reset (power-up cycle or initiated by the Device Reset command) the IO0 channel is
selected.

Configuration Register

The DS2482 supports allows four 1-Wire features that are enabled or selected through the Configuration Register.
These features are:

§ Active Pullup (APU)

§ Presence Pulse Masking (PPM)

§ Strong Pullup (SPU)

§ 1-Wire Speed (1WS)

These features can be selected in any combination. They apply equally to all 1-Wire channels. While APU, PPM
and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended.

Configuration Register Bit Assignment

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1WS SPU PPM APU 1WS SPU PPM APU

After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration Register reads
00h. When writing to the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.

Active Pullup (APU)

The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (R

resistor)

WPU

will be used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active
Pullup should be selected if the 1-Wire line has a substantial length (30 meters or more) or if there is a large
number (~20 or more) of devices connected to a 1-Wire line. The active pullup does not apply to the rising
edge of a presence pulse or a recovery after a short on the 1-Wire line.

The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482 or 1-Wire
slave) ends. From this point on the 1-Wire bus is pulled high through R

internal to the DS2482. VCC and the

WPU

capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive
pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has
reached a level between V
slew rate, as represented by the dashed line. The active pullup continues until t

IL1max

and V

, the DS2482 actively pulls the 1-Wire line high applying a controlled

IH1min

is expired at t3. From that time

APUOT

on the resistive pullup will continue.

Figure 2. Rising Edge Pullup

V

CC

V

IH1MIN

V

IL1MAX

0V

1-Wire bus is
dischar

ed

PU = 1

t

1

t

APUOT

t

2

t

3

PU = 0

6 of 22

DS2482-800: Eight-Channel 1-Wire Master

Presence Pulse Masking (PPM)

The PPM bit controls whether the DS2482 will mask the leading edge (falling) of presence pulses. When PPM = 0,
masking is disabled. Presence pulse masking applies only to standard 1-Wire speed (1WS = 0); this bit has no
function if 1WS = 1 (Overdrive speed). Presence pulse masking can improve the performance of large 1-Wire
networks since it prevents the fast falling edge of a presence pulse generated by a 1-Wire slave device from
propagating through the network and getting reflected. Reflections can cause glitches in the network that in turn
may cause slave devices to lose synchronization with the 1-Wire master.

Figure 3 shows the timing references for the PPM. If enabled (PPM = 1), the DS2482 begins pulling the 1-Wire line
low at t

after the reset low time t

PPM1

is expired. The pulldown ends at t

RSTL

, at which a 1-Wire slave, if present,

PPM2

will be pulling the 1-Wire line low. The falling edge of the presence pulse mask is slew rate controlled.

Figure 3. Presence Pulse Masking

V

CC

0V

RESET PULSE PRESENCE PULSE

APU con-

t

RSTL

trolled edge

t

PPM1

t

PPM2

t

RSTH

Resistive
pull-up

Pull-up DS2482 Pull-down 1-W Slave Pull-down

DS2482 pull-down with PPM = 1; Standard speed only

Strong Pullup (SPU)

The SPU bit controls whether the DS2482 applies a low-impedance pullup to V

on the 1-Wire line after the last

CC

bit of either a 1-Wire Write Byte command or after a 1-Wire Single Bit command has completed. The strong
pullup feature is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory
or when performing a SHA-1 computation, and with parasitically powered temperature sensors or A-to-D
converters. The respective device data sheets specify the location in the communications protocol after which the
strong pullup should be applied. The SPU bit in the configuration register of the DS2482 must be set immediately
prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power.

If SPU is 1, the DS2482 applies active pullup to the rising edge of the time slot in which the strong pullup starts,
regardless of the APU bit setting. However, in contrast to setting APU = 1 for active pullup, the low-impedance
pullup will not end after t

is expired. Instead, as shown in Figure 4, the low-impedance pullup remains active

APUOT

until: a) the next 1-Wire communication command (the typical case), b) by writing to the Configuration Register with
the SPU bit being 0 (alternative), or c) by issuing the Device Reset command. Additionally, when the pullup ends,
the SPU bit is automatically reset to 0. Using the strong pullup does not change the state of the APU bit in the
Configuration Register.

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