MAXIM DS2482-100 User Manual

www.maxim-ic.com

GENERAL DESCRIPTION

The DS2482-100 is an I2C to 1-Wire® bridge device that interfaces directly to standard (100kHz max) or fast (400kHz max) I bidirectional protocol conversion between the I

C masters to perform

C master and any downstream 1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2482-100 is a 1-Wire master. Internal factory trimmed timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and Overdrive 1-Wire communication speeds. To optimize 1-Wire waveform generation, the DS2482-100 performs slew rate control on rising and falling 1-Wire edges and provides additional programmable features to match drive characteristics to the 1-Wire slave environment. Programmable strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs and sensors. The DS2482-100 combines these features with an output to control an external MOSFET for enhanced strong pullup application. The I²C slave address assignment is controlled by two binary address inputs, resolving potential conflicts with other I

C slave devices in the system.

APPLICATIONS

Printers Medical Instruments Industrial Sensors Cell Phones, PDAs

TYPICAL OPERATING CIRCUIT

(I²C port)

µC

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

*RP

SDA SCL

DS2482-100

AD0 AD1

PCTLZ

Current Limiting Resistor

Optional circuitry

1-Wire line

*Rt

1-Wire Device

DS2482-100

Single-Channel 1-Wire Maste

FEATURES

 I2C Host Interface, Supports 100kHz and 400kHz

C Communication Speeds

 1-Wire Master IO with Selectable Active or

Passive 1-Wire Pullup

 Provides Reset/Presence, 8-Bit, Single-Bit, and

Three-Bit 1-Wire IO Sequences

 Standard and Overdrive 1-Wire Communication

Speeds

 Slew Controlled 1-Wire Edges  Selectable 1-Wire Slave Presence-Pulse Falling

Edge Masking to Control Fast Edges on the 1-Wire Line

 Strong 1-Wire Pullup Provided by an Internal

Low-Impedance Signal Path

 PCTLZ Output to Optionally Control an External

MOSFET for Stronger Pullup Requirements

 Two Address Inputs for I  Operating Range: 2.9V to 5.5V, -40°C to +85°C  8-Pin, 150-mil SO Package and 9 WLP Package

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2482S-100+ DS2482S-100+T&R DS2482X-100+T

+Denotes a lead-free/RoHS-compliant package. T/T&R = Tape and reel.

PIN CONFIGURATIONS

VCC

GND

SCL

WLP, Top View with Laser Mark, Contacts Not Visible.

See 21-0067 for WLP package outline drawing.

1 Mark

4821

yywwrr

##xx

1 2 3

C Address Assignment

-40°C to +85°C

PCTLZ

SDA

1 = PCTLZ 2 = AD1

3 = AD0 B1 = SCL B2 = SDA B3 = VCC C2 = GND C3 = IO

yywwrr = Date/Revision ###xx = Lot Number

8 SO (150 mils) 8 SO (150 mils) 9 WLP (2.5k pcs)

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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REV: 061208

DS2482-100: Single-Channel 1-Wire Master

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground -0.5V, +6V Maximum Current into Any Pin Operating Temperature Range Junction Temperature

+150°C

Storage Temperature Range Soldering Temperature

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.

Refer to the IPC/JEDEC J-STD-020 Specification.

±20mA

-40°C to +85°C

-55°C to +125°C

ELECTRICAL CHARACTERISTICS

(VCC = 2.9V to 5.5V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage VCC

Operating Current ICC (Note 1) 0.75 mA

1-Wire Input High V

1-Wire Input Low V

1-Wire Weak Pullup Resistor R

1-Wire Output Low V

Active Pullup On Time t

Strong Pullup Voltage Drop ΔV

Pulldown Slew Rate (Note 6)

Pullup Slew Rate (Note 6)

Power-On Reset Trip Point V

WPU

APUOT

STRPU

POR

IH1

IL1

OL1

SRC

1-Wire TIMING (Note 5) (See Figures 3, 5, 6, and 7)

Write 1/Read Low Time t

Read Sample Time t

1-Wire Time Slot t

Fall Time High-to-Low (Notes 6, 7)

W1L

MSR

SLOT

3.3V 2.9 3.3 3.7 5V 4.5 5.0 5.5

3.3V (Notes 2, 3) 1.9 5V (Notes 2, 3) 3.4

3.3V (Notes 2, 3) 0.9 5V (Notes 2, 3) 1.2

(Note 4) 1000 1675 Ω

At 4mA load 0.4 V

Standard (Notes 4, 5) 2.3 2.5 2.7 Overdrive (Notes 4, 5) 0.4 0.5 0.6

VCC ≥ 3.2V, 1.5mA load

VCC ≥ 5.2V, 3mA load

Standard (3.3V ±10%) Overdrive (3.3V ±10%) Standard (5.0V ±10%)

Overdrive (5.0V ±10%) Standard (3.3V ±10%)

Overdrive (3.3V ±10%) Standard (5.0V ±10%) Overdrive (5.0V ±10%)

0.3

0.5

1 4.2 5 22.1 2 6.5

10 40

0.8 4

2.7 20

1.3 6

3.4 31

µs

V/µs

2.2 V

Standard 7.6 8 8.4 Overdrive 0.9 1 1.1

Standard 13.3 14 15

Overdrive 1.4 1.5 1.8

Standard 65.8 69.3 72.8

Overdrive 9.9 10.5 11.0

µs

Standard (3.3V to 0V) 0.54 3.0

Overdrive (3.3V to 0V) 0.10 0.59

Standard (5.0V to 0V) 0.55 2.2

µs

Overdrive (5.0V to 0V) 0.09 0.44

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DS2482-100: Single-Channel 1-Wire Master

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Write-0 Low Time t

Write-0 Recovery Time t

Reset Low Time t

Presence Detect Sample Time t

Sampling for Short and Interrupt

Reset High Time t

Presence-Pulse Mask START t Presence-Pulse Mask STOP t

W0L

REC0

RSTL

MSP

RSTH

PPM1

PPM2

Standard 60 64 68

Overdrive 7.1 7.5 7.9

Standard 5.0 5.3 5.6

Overdrive 2.8 3.0 3.2

Standard 570 600 630

Overdrive 68.4 72 75.6

Standard 66.5 70 73.5

Overdrive 7.1 7.5 7.9

Standard 7.6 8 8.4

Overdrive 0.7 0.75 0.8

Standard 554.8 584 613.2

Overdrive 70.3 74 77.7

µs

(Note 8) 9.5 10 10.5 µs (Note 8) 57 60 63 µs

CONTROL PIN (PCTLZ)

= 2.9V, 1.2mA load

Output-Low Voltage V

Output-High Voltage V

OLP

0.4mA load current

OHP

current

0.4 V

–

0.5V

I²C PINS (Note 9) (See Figure 10)

VCC = 2.9V to 3.7V

LOW Level Input Voltage VIL

= 4.5V to 5.5V

HIGH Level Input Voltage VIH

Hysteresis of Schmitt Trigger Inputs LOW Level Output Voltage at 3mA Sink Current Output Fall Time from V

with a Bus Capacitance

ILmax

Ihmin

HYS

0.4 V

60 250 ns

-0.5

0.7 × V

0.05 × V

0.25 × V

0.22 × V

0.5V

from 10pF to 400pF Pulse Width of Spikes that are Suppressed by the Input Filter

SDA and SCL pins only 50 ns

Input Current Each I/O Pin with

an Input Voltage Between

CCMAX

and 0.9V

CCMAX

0.1V

(Notes 10, 11) -10 10 µA

Input Capacitance CI (Note 10) 10 pF SCL Clock Frequency f

0 400 kHz

SCL

Hold Time (Repeated) START Condition. After this Period, the

0.6 µs

HD:STA

First Clock Pulse is Generated LOW Period of the SCL Clock t HIGH Period of the SCL Clock t Setup Time for a Repeated START Condition

1.3 µs

LOW

0.6 µs

HIGH

0.6 µs

SU:STA

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DS2482-100: Single-Channel 1-Wire Master

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Data Hold Time t Data Setup Time t Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Capacitive Load for Each Bus Line Oscillator Warm-Up Time t

Note 1: Operating current with 1-Wire write byte sequence followed by continuous Read of Status register at 400kHz in Overdrive. Note 2: With standard speed the total capacitive load of the 1-Wire bus should not exceed 1nF, otherwise the passive pullup on

Note 3: Active pullup guaranteed to turn on between V Note 4: Active or resistive pullup choice is configurable. Note 5: Except for t

Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at Overdrive speed. For reduced load, the pulldown slew Note 7: Fall time high-to-low (t

Note 8: Presence-pulse masking only applies to standard speed. Note 9: All I²C timing values are referred to V Note 10: Applies to SDA, SCL, and AD0, AD1. Note 11: The I/O pins of the DS2482-100 do not obstruct the SDA and SCL lines if V Note 12: The DS2482-100 provides a hold time of at least 300ns for the SDA signal (referred to the V

Note 13: The maximum t Note 14:

Note 15: C Note 16: I²C communication should not take place for the max t

threshold V exceed 300pF.

parameters is found to be off the typical value, it is safe to assume that all of these parameters deviate from their typical value in the same direction and by the same degree.

rate is slightly faster.

undefined region of the falling edge of SCL.

A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + t (according to the standard-mode I²C-bus specification) before the SCL line is released.

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall times according to I²C-bus Specification

v2.1 are allowed.

may not be reached in the available time. With Overdrive speed the capacitive load on the 1-Wire bus must not

IL1

, all 1-Wire timing specifications and t

) is derived from PD

has only to be met if the device does not stretch the LOW period (t

HD:DAT

(Notes 12, 13) 0.9 µs

HD:DAT

(Note 14) 250 ns

SU:DAT

0.6 µs

SU:STO

1.3 µs

BUF

(Note 15) 400 pF

(Note 16) 100 µs

OSCWUP

IHmin

and V

IL1MAX

APUOT

, referenced from 0.9 × VCC to 0.1 × VCC.

SRC

and V

ILmax

levels.

OSCWUP

IH1MIN

are derived from the same timing circuit. Therefore, if one of these

is switched off.

time following a power-on reset.

of the SCL signal) to bridge the

IHmin

) of the SCL signal.

LOW

SU:DAT

≥250ns must then be

SU:DAT

= 1000 + 250 = 1250ns

PIN DESCRIPTION

PIN NAME FUNCTION

1 VCC Power Supply Input 2 IO IO Driver for 1-Wire Line 3 GND Ground Reference 4 SCL I²C Serial Clock Input. Must be tied to VCC through a pullup resistor. 5 SDA I²C Serial Data Input/Output. Must be tied to VCC through a pullup resistor.

Active-low control output for an external P-channel MOSFET to provide extra power to

6 PCTLZ

7 AD1

AD0

the 1-Wire line, e.g., for use with 1-Wire devices that require a higher current temporarily to operate. I²C Address Inputs. Must be tied to V

or GND. These inputs determine the I²C slave

address of the device (see Figure 9).

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Figure 1. Block Diagram

DS2482-100

Config

DS2482-100: Single-Channel 1-Wire Master

T-Time OSC

SDA

SCL

D0 D1

I²C

Interface

Controller

I/O

Controller

Status

Read Data

Line

XCVR

PCTLZ

DETAILED DESCRIPTION

The DS2482-100 is a self-timed 1-Wire master, which supports advanced 1-Wire waveform features including standard and Overdrive speeds, active pullup, strong pullup for power delivery, and presence-pulse masking. The active pullup affects rising edges on the 1-Wire side. The strong pullup function uses the same pullup transistor as the active pullup but with a different control algorithm. In addition, the strong pullup activates the PCTLZ pin, controlling optional external circuitry to deliver additional power beyond the capabilities of the on-chip pullup transistor. Once supplied with command and data, the I/O controller of the DS2482-100 performs time-critical 1-Wire communication functions such as reset/presence detect cycle, read-byte, write-byte, single-bit R/W and triplet for ROM Search, without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse, 1-Wire short, search direction taken) through the Status register and data through the Read Data register. The DS2482-100 communicates with a host processor through its I bus interface in standard mode or in fast mode. The logic state of two address pins determines the I

C slave

address of the DS2482-100, allowing up to four devices operating on the same bus segment without requiring a hub.

DEVICE REGISTERS

The DS2482-100 has three registers that the I²C host can read: Configuration, Status, and Read Data. These registers are addressed by a read pointer. The position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruction that the DS2482-100 executed last. The host has read and write access to the Configuration register to enable certain 1-Wire features.

Configuration Register

The DS2482-100 supports four 1-Wire features that are enabled or selected through the Configuration register. These features are:

 Active Pullup (APU)  Presence Pulse Masking (PPM)  Strong Pullup (SPU)  1-Wire Speed (1WS)

These features can be selected in any combination. While APU, PPM, and 1WS maintain their state, SPU returns to its inactive state as soon as the strong pullup has ended.

Configuration Register Bit Assignment

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

1WS SPU PPM APU 1WS SPU PPM APU

After a device reset (power-up cycle or initiated by the Device Reset command) the Configuration register reads 00h. When writing to the Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one's complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.

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DS2482-100: Single-Channel 1-Wire Master

Active Pullup (APU)

The APU bit controls whether an active pullup (controlled slew-rate transistor) or a passive pullup (R used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Active Pullup should be selected if the 1-Wire line has a substantial length (several 10m) or if there is a large number (~20 or

more) of devices connected to a 1-Wire line. The active pullup does not apply to the rising edge of a presence pulse or a recovery after a short on the 1-Wire line.

The circuit that controls rising edges (Figure 2) operates as follows: At t1 the pulldown (from DS2482-100 or 1-Wire slave) ends. From this point on the 1-Wire bus is pulled high through R

internal to the DS2482-100. VCC and the

WPU

capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues, as represented by the solid line. With active pullup enabled (APU = 1), when at t2 the voltage has reached a level between V

IL1max

and V

controlled slew rate, as represented by the dashed line. The active pullup continues until t

, the DS2482-100 actively pulls the 1-Wire line high applying a

IH1min

APUOT

From that time on the resistive pullup continues. See the Strong Pullup (SPU) section for a way to keep the pullup

transistor conducting beyond t3.

resistor) is

WPU

is expired at t3.

Figure 2. Rising Edge Pullup

PU = 1

APUOT

IH1MIN

IL1MAX

1-Wire bus is dischar

PU = 0

Presence-Pulse Masking (PPM)

The PPM bit controls whether the DS2482-100 masks the leading edge (falling) of presence pulses. When PPM = 0, masking is disabled. Presence pulse masking applies only to standard 1-Wire speed (1WS = 0); this bit has no function if 1WS = 1 (Overdrive speed). Presence-Pulse Masking can improve the performance of large 1-Wire networks since it prevents the fast falling edge of a presence pulse generated by a 1-Wire slave device from propagating through the network and getting reflected. Reflections can cause glitches in the network that in turn can cause slave devices to lose synchronization with the 1-Wire master.

Figure 3 shows the timing references for the Presence-Pulse Masking. If enabled (PPM = 1), the DS2482-100 begins pulling the 1-Wire line low at t

after the reset low time t

PPM1

is expired. The pulldown ends at t

RSTL

PPM2

, at which a 1-Wire slave, if present, is pulling the 1-Wire line low. The falling edge of the presence-pulse mask is slewrate controlled.

Figure 3. Presence-Pulse Masking

RESET PULSE PRESENCE PULSE

PU con-

trolled edge

PPM1

RSTL

Pull-up DS2482 Pull-down 1-W Slave Pull-down

DS2482 pull-down with PPM = 1; Standard speed only

PPM2

Resistive pull-up

RSTH

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DS2482-100: Single-Channel 1-Wire Master

Strong Pullup (SPU)

The SPU bit is used to activate the strong pullup function prior to a 1-Wire Write Byte or 1-Wire Single Bit command. Strong pullup is commonly used with 1-Wire EEPROM devices when copying scratchpad data to the main memory or when performing an SHA-1 computation, and with parasitically powered temperature sensors or A/D converters. The respective device data sheets specify the location in the communications protocol after which the strong pullup should be applied. The SPU bit must be set immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power. The strong pullup uses the same internal pullup transistor as the active pullup feature. For cases where the internal strong pullup has insufficient strength, the PCTLZ pin can be used to control an external p-channel MOSFET to supply additional power beyond the drive capability of the DS2482-100 to the 1-Wire line. See the ΔV

parameter in the Electrical Characteristics to

STRPU

determine if the internal strong pullup is sufficient given the current load on the device.

If SPU is 1, the DS2482-100 treats the rising edge of the time slot in which the strong pullup starts as if the active pullup was activated. However, in contrast to the active pullup, the strong pullup, i.e., the internal pullup transistor, remains conducting, as shown in Figure 4, until one of three events occurs: the DS2482-100 receives a command that generates 1-Wire communication (the typical case); the SPU bit in the Configuration register is written to 0; or the DS2482-100 receives the Device Reset command. As long as the strong pullup is active, the PCTLZ output is low. When the strong pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup feature does not change the state of the APU bit in the Configuration register.

Figure 4. Low-Impedance Pullup Timing

Last bit of 1-Wire Write Byte or 1-Wire Single Bit Function

Write 1 case

Write 0 case

Next Time Slot or 1-Wire Reset

SLOT

PCTLZ

DS2482 resistive Pullup DS2482 Pulldown

DS2482 strong Pullup

1-Wire Speed (1WS)

The 1WS bit determines the timing of any 1-Wire communication generated by the DS2482-100. All 1-Wire slave devices support standard speed (1WS = 0), where the transfer of a single bit (t 65µs. Many 1-Wire device can also communicate at a higher data rate, called Overdrive speed. To change from standard to Overdrive speed, a 1-Wire device needs to receive an Overdrive Skip ROM or Overdrive Match ROM command, as explained in the device data sheets. The change in speed occurs immediately after the 1-Wire device has received the speed-changing command code. The DS2482-100 must take part in this speed change to stay

synchronized. This is accomplished by writing to the Configuration register with the 1WS bit being 1 immediately after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Configuration register

with the 1WS bit being 0 followed by a 1-Wire Reset command changes the DS2482-100 and any 1-Wire devices on the active 1-Wire line back to standard speed.

in Figure 4) is completed within

SLOT

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