MAXIM DS2430A User Manual

www.maxim-ic.com

DS2430A

256-Bit 1-Wire EEPROM

FEATURES

 256-bit Electrically Erasable Programmable

Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike

 Built-in multidrop controller ensures

compatibility with other MicroLAN products

 EEPROM organized as one page of 32 bytes

for random access

 Reduces control, address, data, and power to a

single data pin

 Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3kbits per second

 8-bit family code specifies DS2430A

communication requirements to reader

 Presence detector acknowledges when reader

first applies voltage

 Low cost TO-92 or 6-pin TSOC and Flip Chip

surface mount package

 Reads and writes over a wide voltage range of

2.8V to 6.0V from -40°C to +85°C

ORDERING INFORMATION

DS2430A TO-92 Package
DS2430AP 6-pin TSOC Package
DS2430A/T&R TO-92 Package, Tape & Reel
DS2430AP/T&R TSOC Package, Tape & Reel
DS2430A+ TO-92 Package
DS2430AP+ 6-pin TSOC Package
DS2430A+T&R TO-92 Package, Tape & Reel
DS2430AP+T&R TSOC Package, Tape & Reel
DS2430AX Flip Chip, 10k Tape & Reel
DS2430AX-S Flip Chip, 2.5k Tape & Reel
+ Indicates lead-free compliance.

PIN ASSIGNMENT

TO-92

DALLAS

DS2430A

1 2 3

2 3

BOTTOM VIEW

See Mech.

Drawings Section

TSOC PACKAGE

1

6

2

5

3

4

TOP VIEW

3.7mm x 4.0mm x 1.5mm

SIDE VIEW

See Mech.

Drawing Section

4 3

2430A
rrd#xx

1 2

Flip Chip, Top View
with Laser Mark,
Contacts Not Visible.
“rrd” = Revision/Date
#xx = Lot Number

See 56-G7016-001 for
package outline.

PIN DESCRIPTION

TO-92 TSOC Flip Chip

Pin 1 Ground Ground Ground
Pin 2 Data Data Data
Pin 3 NC NC NC
Pin 4 –––– NC NC
Pin 5 –––– NC ––––
Pin 6 –––– NC ––––

1 of 16 011607

DS2430A

DESCRIPTION

The DS2430A 256-bit 1-Wire EEPROM identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2430A consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus
256 bits of user-programmable EEPROM and a 64-bit one-time programmable application register. The
power to read and write the DS2430A is derived entirely from the 1-Wire® communication line. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.
The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity
that allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that
allows standard assembly equipment to handle the device easily for attachment to printed circuit boards
or wiring. Typical applications include storage of calibration constants, board identification, and product
revision status.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2430A. The DS2430A has four main data components: 1) 64-bit lasered ROM, 2) 256-bit
EEPROM data memory with scratchpad, 3) 64-bit one-time programmable application register with
scratchpad and 4) 8-bit status memory. The hierarchical structure of the 1-Wire protocol is shown in
Figure 2. The bus master must first provide one of the four ROM Function Commands: 1) Read ROM, 2)
Match ROM, 3) Search ROM, 4) Skip ROM. The protocol required for these ROM Function Commands
is described in Figure 8. After a ROM Function Command is successfully executed, the memory
functions become accessible and the master can provide any one of the four memory function commands.
The protocol for these memory function commands is described in Figure 6. All data is read and written
least significant bit first.

64-BIT LASERED ROM

Each DS2430A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code
(14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure

3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR
gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas

1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are

initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted
in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th
bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits
of CRC should return the shift register to all 0s.

1-Wire and iButton are registered trademarks of Dallas Semiconductor.

2 of 16

DS2430A BLOCK DIAGRAM Figure 1

DS2430A

3 of 16

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2

DS2430A

64-BIT LASERED ROM Figure 3

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (14H)

MSB LSB MSB LSB MSB LSB

1-WIRE CRC GENERATOR Figure 4

Polynomial = X8 + X5 + X4 + 1

4 of 16

DS2430A

MEMORY

The memory of the DS2430A consists of three separate sections, called data memory, application
register, and status register (Figure 5). The data memory and the application register each have its own
intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data
memory can be read and written as often as desired. The application register, however, is one-time
programmable only. Once the application register is programmed, it is automatically write protected. The
status register will indicate if the application register is already locked or if it is still available for storing
data. As long as the application register is unprogrammed, the status register will read FFh. Copying data
from the register scratchpad to the application register will clear the 2 least significant bits of the status
register, yielding an FCh the next time one reads the status register.

DS2430A MEMORY MAP Figure 5

MEMORY FUNCTION COMMANDS

The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the different
memory sections of the DS2430A. An example is shown later in this document.

WRITE SCRATCHPAD [0Fh]

After issuing the Write Scratchpad command, the master must first provide a 1-byte address, followed by
the data to be written to the scratchpad for the data memory. The DS2430A will automatically increment
the address after every byte it received. After having received a data byte for address 1Fh, the address
counter will wrap around to 00h for the next byte and writing continues until the master sends a Reset
Pulse.

READ SCRATCHPAD [AAh]

This command is used to verify data previously written to the scratchpad before it is copied into the final
storage EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1­byte starting address from where data is to be read. The DS2430A will automatically increment the
address after every byte read by the master. After the data of address 1Fh has been read, the address
counter will wrap around to 00h for the next byte and reading continues until the master sends a Reset
Pulse.

5 of 16