MAXIM DS2413 User Manual

19-5316; 7/10

www.maxim-ic.com

GENERAL DESCRIPTION

The DS2413 is a dual-channel programmable I/O

1-Wire

chip. The PIO outputs are configured as open-drain and provide up to 20mA continuous sink capability and off-state operating voltage up to 28V. Control and sensing of the PIO pins is performed with a dedicated device-level command protocol. To provide a high level of fault tolerance in the end application, the 1-Wire IO and PIO pins are all capable of withstanding continuous application of voltages up to 28V max. Communication and operation of the DS2413 is performed with the single contact Maxim/Dallas 1-Wire serial interface.

APPLICATIONS

 LED Control  Accessory Identification and Control  General Purpose Input/Output  Key-Pick Systems  Industrial Controllers  System Monitoring

TYPICAL OPERATING CIRCUIT

PUP

PX.Y

µC

mands, Registers, and Modes are capitalized for

Com clarity.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

DS2413

GND

PIOA

PIOB

LED

Switch

Local Power

DS2413

1-Wire Dual Channel

Addressable Switch

FEATURES

 Open-Drain Programmable I/O Pins  PIO Pins Support 20mA max Continuous Current

Sink

 Supports 28V (max) PIO Pin Operating Voltage  On-Resistance of PIO Pulldown Transistor 20

max; OFF Resistance 1M min

 Parasitic Power Supply Through 1-Wire  Communicates to Host with a Single Digital

Signal at 14.9kb or 100kbps Using 1-Wire Protocol

 Unique 64-bit ROM Serial Number Factory

Lasered Into Each Device

 Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

 1-Wire IO Pin Supports 28V Absolute Maximum

DC Level for Fault Conditions

 Operates Over a Wide 1-Wire Voltage Range of

2.8V to 5.25V from 0°C to +70°C

 High ESD Immunity of 1-Wire IO Pin: 8kV HBM

Typical

 TSOC and TDFN Packages Available

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS2413P+ 0°C to +70°C TSOC DS2413P+T&R 0°C to +70°C TSOC DS2413Q+T&R 0°C to +70°C TDFN

+ Denotes a lead(Pb)-free package/RoHS-compliant package. T&R = Tape and reel.

PIN CONFIGURATION

TSOC TDFN

ywwrr

Exposed Paddle

413

mrrF

Top View with Marking. TDFN Contacts

2413

Not Visible in this View.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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DS2413: 1-Wire Dual Channel Addressable Switch

ABSOLUTE MAXIMUM RATINGS

Voltage on Any Pin to GND -0.5V, +30V Maximum Current into IO Pin Maximum Current into PIO Pin Maximum Current Through GND Pins (Both Pins Tied Together) Operating Temperature Range 0°C to +70°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Lead Temperature (soldering, 10s) Soldering Temperature (reflow)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS T

= 0°C to +70°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN GENERAL DATA

1-Wire Pullup Voltage (Note 1)

1-Wire Pullup Resistance

Input Load Current I

PUP

Standard speed 2.8 5.25 Overdrive speed 2.9 5.25 DC only; no 1-Wire communication 28 (Notes 1, 2)

 5.25V

PUP

 3.30V

PUP

1.5 2.2

3.5 70

3.5 15

V(IO) = 28V (Note 3) 400 950 Input Capacitance CIO At 25°C (Notes 4, 5) 800 pF Input Low Voltage V High-to-Low Switching Threshold Low-to-High Switching Threshold Switching Hysteresis V Output Low Voltage V

Recovery Time (Notes 1, 12)

(Notes 5, 13)

Time slot Duration (Note 1, 5)

REC

REH

SLOT

(Notes 1, 6) 0.4 V

(Notes 5, 7, 8) 0.4 3.2 V

(Notes 5, 7, 9) 0.7 3.6 V

(Notes 5, 10) 0.2 V

At 4mA Current Load (Note 11)

Standard speed, R

Overdrive speed, R

PUP

= 2.2k

= 2.2k Overdrive speed, directly prior to reset pulse; R

PUP

= 2.2k

0.4 V 5 2

Standard speed 0.5 5.0 Rising-Edge Hold-off Time Overdrive speed Not applicable (0) Standard speed, V

PUP

 4.5V

65 Standard speed (Note 14) 67 Overdrive speed, V (Note 14)

PUP

 4.5V

Overdrive speed (Note 14) 10

IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE

480 960

48 80

63 80

7.0

8.2

0 0.7

Reset Low Time (Note 1) t

Presence Detect High Time (Notes 14, 15)

Presence Detect Fall Time (Notes 5, 16)

RSTL

PDH

FPD

Standard speed, V Standard speed (Note 14) 600 960 Overdrive speed, V

PUP

 4.5V

 4.5V Overdrive speed (Note 14) Standard speed, V Standard speed 15 68 Overdrive speed, V

PUP

 4.5V

 4.5V Overdrive speed 2 Standard speed, V Standard speed 0.24 1.6 Overdrive speed, V

> 4.5V 0.24 1.4

PUP

 4.5V

PUP

Overdrive speed 0 0.9

Presence Detect Low Time (Note 15)

PDL

Standard speed, V Standard speed (Note 14) 60 260 Overdrive speed, V (Note 14) Overdrive speed (Note 14) 8

> 4.5V 60 240

PUP

 4.5V

PUP

25mA 30mA 60mA

+300°C +260°C

k

µA

µs

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DS2413: 1-Wire Dual Channel Addressable Switch

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Presence Detect Sample Time (Notes 1, 20)

MSP

Standard speed, V Standard speed 69.6 75 Overdrive speed, V

> 4.5V 67.4 75

PUP

 4.5V

7.7 10

µs

Overdrive speed 9.1 10

IO PIN, 1-Wire WRITE

Write-0 Low Time (Notes 1, 17)

W0L

Standard speed, V Standard speed (Note 14) 62 120 Overdrive speed, V (Note 14)

> 4.5V 60 120

PUP

 4.5V

PUP

7 16

µs

Overdrive speed (Note 14) 8 16

(Notes 1, 17)

W1L

Standard speed 5 15 Write-1 Low Time Overdrive speed 1 2

µs

IO PIN, 1-Wire READ Read Low Time

(Notes 1, 18) Read Sample Time

(Notes 1, 18)

MSR

Standard speed 5 Overdrive speed 1 Standard speed Overdrive speed

+ 

15 2

15 - 

2 - 

µs

PIO Pins

Leakage Current ILP Pin at 28V (Note 19) 8.5 24 µA Input Capacitance CP (Note 5) 100 pF Output low voltage V Input Low Voltage V Input High Voltage (Note 21)

OLP

ILP

IHP

20mA load current 0.4 V (Note 1) 0.8 V

–

(Note 1)

PUP

0.3V

28 V

Note 1: System requirement. Note 2: Full R

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 or DS2480B may be required. The DS2482-x00 may not always detect the DS2413 presence pulse. For proper operation it may be necessary to disregard (force to 1) the PPD bit in the DS2482-x00 status register.

Note 3: The I-V characteristic is linear for voltages greater than 10V. Note 4:

Capacitance on the data pin could be 800pF when V after V

Note 5: Guaranteed by design and simulation. Not production tested. Note 6: The voltage on IO needs to be less than or equal to V Note 7: V

Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After V Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single DS2413 attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at t Note 14: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 15: t

pulse. t

Note 16: Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is

80% of V

Note 17:

 in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V duration for the master to pull the line low is t

Note 18:

 in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from V of the bus master. The actual maximum duration for the master to pull the line low is t

Note 19: The I-V characteristic is linear for voltages greater than 7V. Note 20: t

Note 21: Production tested for V

range guaranteed by design and simulation. not production tested. Production testing performed at a fixed R

PUP

is first applied. If a 2.2k resistor is used to pull up the data line, 2.5µs

has been applied the parasite capacitance will not affect normal communications.

PUP

and VTH are functions of the internal supply voltage, which is a function of V

maximum specifications are valid at V

is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.

is deemed to have ended when the voltage on IO drops below 80% of V

PDH

MSP

PDH

is deemed to have begun when the voltage on IO drops below 20% of V

PDL

and the time at which the voltage is 20% of V

PUP

is a system required sample point and not directly production tested. Production testing is performed on related parameters and t

. Parameter t

PDL

is guaranteed by design and simulation, not production tested.

FPD

. V

IHP(min)

IHP(max)

PUPmax

is guaranteed by design and simulation, not production tested.

PUP

whenever the master drives the line low.

ILMAX

(5.25V). In any case, VTL < VTH < V

after VTH has been previously reached.

REH

PUP

W1Lmax

+ tF -  and t

+ tF -  respectively.

W0Lmax

and the 1-Wire Recovery Times. The VTH and

PUP

on the leading edge of the presence-detect low

PUP

on the leading edge of the pulse.

PUP

to VTH. The actual maximum

to the input high threshold

RLmax

+ tF.

PUP

value.

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DS2413: 1-Wire Dual Channel Addressable Switch

LEGACY VALUES DS2413 VALUES

PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED

MIN MAX MIN MAX MIN MAX MIN MAX

SLOT

RSTL

PDH

PDL

W0L

(incl. t

REC)

61µs (undef.) 7µs (undef.) 67µs (undef.) 10µs (undef.)

480µs (undef.) 48µs 80µs 600µs 960µs 63µs 80µs

15µs 60µs 2µs 6µs 15µs 68µs 2µs 8.2µs 60µs 240µs 8µs 24µs 60µs 260µs 8µs 32µs 60µs 120µs 6µs 16µs 62µs 120µs 8µs 16µs

PIN DESCRIPTION

NAME TSOC PIN # TDFN PIN # FUNCTION

IO 2 2 1-Wire bus interface. Open-drain, requires external pullup resistor.

PIOA 6 4 Programmable I/O pin, open-drain with weak pulldown, power-on

default is off (PIOA = 1).

PIOB 4 6 Programmable I/O pin, open-drain with weak pulldown, power-on

default is off (PIOB = 1). GND1 1 3 Ground reference 1 GND2 5 5 Ground reference 2; both GND pins must be connected in the

application.

NC 3 1 Not connected

Exposed Paddle (TDFN only). Solder evenly to the board’s ground

GND — EP

plane for proper operation. See Application Note 3273 for additional

information.

DESCRIPTION

The DS2413 combines two PIO pins and a fully featured 1-Wire interface in a single chip. PIO outputs are opendrain, operate at up to 28V and provide an on resistance of 20 max. A robust communication protocol ensures that PIO output changes occur error-free. Each DS2413 has a Registration Number that is 64 bits long. The Registration Number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. Device power is supplied parasitically from the 1-Wire bus. The DS2413’s applications of include accessory identification and control, system monitoring, and general-purpose input/output.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major sections of the DS2413. The DS2413 has two main components: 64-bit Registration Number, and PIO Control. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) OverdriveMatch ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the PIO functions become accessible and the master may provide one of the two PIO Function commands. The protocol for these commands is described in Figure 6. All data is read and written least significant bit first.

Figure 1. Block Diagram

Internal V

1-Wire

Interface

PIO

Control

64-Bit Registration

Number

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PIOB

PIOA

DS2413: 1-Wire Dual Channel Addressable Switch

64-BIT LASERED ROM

Each DS2413 has a unique ROM Registration Number that is 64 bits long, as shown in Figure 3. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X

+ X5 + X4 + 1. Additional information about the Dallas 1-Wire CRC is available in Application Note 27. The shift register bits are initialized to zero. Then starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros.

Figure 2. Hierarchical Structure for 1-Wire Protocol

DS2413

Command Level:

1-Wire ROM Function

Commands (see Figure 10)

DS2413-specific

PIO Function Commands

(see Figure 6)

Figure 3. 64-Bit LASERED ROM

MSB LSB

8-Bit CRC Code 48-Bit Serial Number

MSB LSB MSB LSB MSB LSB

Figure 4. 1-Wire CRC Generator

Available Commands:

Read ROM Match ROM Search ROM Skip ROM Resume Overdrive Skip Overdrive Match

PIO Access Read PIO Access Write

Command Codes:

33h 55h F0h CCh

3Ch 69h

F5h 5Ah

Data Field Affected:

64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag RC-Flag RC-Flag RC-Flag, OD-Flag 64-bit Reg. #, RC-Flag,

PIO Pins PIO Pins

8-Bit Family Code (3Ah)

OD-Flag

Polynomial = X8 + X5 + X4 + 1

STAGE

INPUT DATA

STAGE

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DS2413: 1-Wire Dual Channel Addressable Switch

PIO STUCTURE

Each PIO consists of an open-drain pulldown transistor with 28V capability. The transistor is controlled by the PIO Output Latch, as shown in Figure 5. The PIO Control unit connects the PIOs to the 1-Wire interface.

Figure 5. PIO Simplified Logic Diagram

PIO Pin

State

PIO Output

Latch State.

PIO Pin

PIO Data

PIO Clock

CLOCK

PIO Out-

ut Latch

PIO FUNCTION COMMANDS

The PIO Function Flow Chart (Figure 6) describes the protocols necessary to access the PIO pins of the DS2413. Examples on how to use these functions are included at the end of this document. The communication between master and DS2413 takes place either at standard speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode, the DS2413 powers up in standard speed.

PIO ACCESS READ [F5h]

This command reads the PIO logical status and reports it together with the state of the PIO Output Latch in an endless loop. A PIO Access Read can be terminated at any time with a 1-Wire Reset.

PIO Status Bit Assignment

b7 b6 b5 b4 b3 b2 b1 b0

Complement of b3 to b0

The state of both PIO channels is sampled at the same time. The first sampling occurs during the last (most significant) bit of the command code F5h. The PIO status is then reported to the bus master. While the master receives the last (most significant) bit of the PIO status byte, the next sampling occurs and so on until the master generates a 1-Wire Reset. The sampling occurs with a delay of t previous byte, as shown in Figure 7. The value of "x" is approximately 0.2µs.

PIOB Output

Latch State

Figure 7. PIO Access Read Timing Diagram

MS 2 bits of previous byte

PIOB Pin

State

PIOA Output

Latch State

+x from the rising edge of the MS bit of the

REH

LS 2 bits of PIO Status byte

PIOA Pin

State

REH

Sampling Point

Notes:

1 2 The sample point timing also applies to the PIO Access Write command, with the "previous byte" being the

The "previous byte" could be the command code or the data byte resulting from the previous PIO sample.

write confirmation byte (AAh).

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