MAXIM DS2408 Technical data

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PART

TEMP RANGE

PIN-PACKAGE

DS2408S+

-40°C to +85°C

16 SO

DS2408S+T&R

-40°C to +85°C

16 SO

19-5702; 12/10

www.maxim-ic.com

FEATURES

 Eight Channels of Programmable I/O with

Open-Drain Outputs

 On-Resistance of PIO Pulldown Transistor

100Ω (max); Off-Resistance 10MΩ (typ)

 Individual Activity Latches Capture

Asynchronous State Changes at PIO Inputs for Interrogation by the Bus Master

 Data-Strobe Output to Synchronize PIO Logic

States to External Read/Write Circuitry

 Built-in Multidrop Controller Ensures

Compatibility with Other Dallas Semiconductor

1-Wire

Net Products

 Supports 1-Wire Conditional Search Command

with Response Controlled by Programmable PIO Conditions

 Unique Factory-Lasered 64-Bit Registration

Number Ensures Error-Free Device Selection and Absolute Part Identity

 Communicates to Host with a Single Digital

Signal at 15.3kbps or 100kbps using 1-Wire Protocol

 Operating Range: 2.8V to 5.25V, -40°C to

+85°C

DS2408

1-Wire 8-Channel Addressable Switch

PIN CONFIGURATION

150-mil SO

ORDERING INFORMATION

+Denotes a lead(Pb) -free package. T&R = Tape and reel.

DESCRIPTION

The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain and provide an on resistance of 100Ω max. A robust PIO channel-access communication protocol ensures that PIO output-sett ing c hang es occu r err or-free. A data-vali d st robe ou tput can be used to latch PIO logic state s into external circuitry such as a D/A converter (DAC) or microcontroller data bus.

DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit ROM registration number that is factory lasered into the chip. The registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408 devices can reside on a comm on 1-Wire bus and can operate independently of each other. The DS2408 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity; the conditions to cause participation in the conditional search are programmable. The DS2408 has an optional V supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire bus. When an externa l supply is prese nt, PIO states are maintained in the abse nce of the 1-Wire bus power source. The RSTZ signal is configurable to serve as either a hard-wired reset for the PIO output or as a strobe for external circuitry to indicate that a PIO write or PIO read has completed.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

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DS2408

P0 to P7, RSTZ, I/O Voltage to GND

-0.5V, +6V

P0 to P7, RSTZ, I/O combined sink current

20mA

Operating Temperat ur e Range

-40°C to +85°C

Junction Temperature

+150°C

Storage Temperatu r e Range

-55°C to +125°C

Lead temperatur e (so lder ing 10s)

+300°C

Soldering Temperature (reflow)

+260°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

1-Wire Pullup Standard speed

2.8

5.25

Overdrive speed

3.3

5.25

Standby Supply Current

VCC at V I/O pin at 0.3V

I/O Pin General Data

1-Wire Pullup Input Capacitance

CIO

(No tes 3, 4)

1200

I/O pin at V VCC at 0V

High-to-Low Switching Threshold

Input-Low Voltag e

(No tes 1, 7)

0.30

Low-to-High Switching Threshold

Switching Hyster es is

(No tes 9, 4)

0.16

0.73

Output-Low Voltage at 4mA

Standard speed, R

2.2kΩ

Overdrive speed, R

2.2kΩ

Overdrive speed, D irectly Rising-Edge Hold-off Standard speed

0.5 5

Overdrive speed

0.5 2

Timeslot Dur ation Standard speed

Overdrive speed

ABSOLUTE MAXIMUM RATINGS*

* This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

ELECTRICAL CHARACTE RISTICS

= 0V or ≥ V

, TA = -40°C or +85°C.)

PUP

Voltage

Resistance

Input L oad C urr ent I

Recovery Time (Note 1)

PUP

CCS

PUP

REC

PUP,

(No tes 1, 2)

PUP,

(No tes 4, 5, 6) 0.5

(No tes 4, 5, 8) 0.8

(Note 10)

PUP

1 µA

2.2

kΩ

1 µA

3.2 V

3.4 V

0.4 V

µs

Time (Notes 11, 4)

(No tes 1, 12)

2 of 39

REH

SLOT

prior to reset pulse; R = 2.2kΩ

PUP

µs

DS2408

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

I/O Pin, 1-Wire Reset, Presence-Detect Cycle

Standard speed, V

4.5V

Standard speed

660

720

Overdrive speed

53 80

Presence-Detect High Time (No te 12 )

Standard speed

15 60

Overdrive speed

2 7

Standard speed, V

Standard speed

1 8

Overdrive speed

Standard speed, V

4.5V

Standard speed

280

Overdrive speed

7 27

Standard speed, V

4.5V

Standard speed

68 75

Overdrive speed

8 9

I/O Pin, 1-Wire Write

Write-0 Lo w Time (Notes 1, 12, 14)

Standard speed

120

Overdrive speed

8 13

Write-1 Lo w Time Standard speed

5 15

Overdrive speed

1 1.8

Writ e Sample Time

Standard speed

15 60

I/O Pin, 1-Wire Read

Read-Low Time Standard speed

15 - δ

Overdrive speed

Read-0 Low Time

Standard speed

15 60

Read-Sa mple Time Standard speed

Overdrive speed

tRL + δ

1.8

P0 to P7, RSTZ Pin

Input-Low Voltag e

(No tes 1, 7)

0.30

VX = max (V

)

Output-Low Voltage Leakage Current

5.25V at the pin

µA

Output Fall Time

FPIO

(No tes 4, 16)

100

Minimum-Sensed PIO Pulse

Reset-Low Time (No tes 1, 12)

Presence-Detect Fa ll Time (No te 13 )

Presence-Detect Low Time (No te 12 )

Presence-Detect Sa mp le Time (Note 1)

RSTL

PDH

FPD

PDL

MSP

W0L

4.5V

PUP

480

720

µs

240

µs

(No tes 1, 12, 14)

(Slave Sampling)

(Note 12)

(Notes 1, 15)

(Data From Slave)

(Note 12)

(No tes 1, 12, 15)

Input-High Volt ag e V

at 4mA

W1L

SLS

SPD

MSR

Overdrive speed 1.8

tRL + δ

PUP,VCC

(Note 1)

VX - 0.8

(Note 10)

1.8 - δ

5.25 V

0.4 V

µs

PWMIN

3 of 39

(No tes 4, 17)

5 µs

DS2408

Note 1:

System Requirement

Note 2:

Max imum a llowable pullup re sistanc e is a function of the number o f 1-Wire devices in the

Note 3:

If a 2.2kΩ resistor is used to pull up the data line to V

, 5µs after po wer has been applied,

the parasite capac itance does not affect normal communications.

Note 4:

Guaranteed by design—not pro duction tested.

Note 5:

VTL and VTH are functions of the internal supply v oltage, which in parasitic po w er mode, is a

are valid at V

PUP

= 5.25V. In any case, VTL < VTH < V

PUP

Note 6:

Voltage below which, during a falling edge on I/O, a logic '0' is detected.

Note 7:

The voltage on I/O needs to be less or equal to V

whenever t he master d r ives t he line

low.

Note 8:

Voltage above which, dur ing a r ising edge on I/ O, a logic '1' is detected.

Note 9:

After VTH is crossed during a rising edge on I/O, the voltage on I/O has to dr op by VHY to be detected as logic '0'.

Note 10:

The I-V characterist ic is linear for vo ltages less than 1V.

Note 11:

The earliest reco gnition of a negative edge is possible at t

after VTH has been reached

Note 12:

Highlighted numbers are NOT in compliance with the published 1-Wire standards. S ee comparis on t able below.

Note 13:

Interval during the negative edge on I/O at the beginning of a presence detect pu lse bet ween

Note 14:

ε in Figure 14 represents the time required for the pu llup circuitry to pull the voltage on I/O

W1LMAX

W0LMAX

Note 15:

the master to pull the lin e low is t

RLMAX

+ tF.

Note 16:

Interval during the device-generated negative edge on any PIO p in or the RSTZ pin between

PUP

. PIO pullup resistor = 2.2kΩ.

Note 17:

Width of the narrowest pu lse which tr ips the activity latch (for any PIO pin) or causes a reset

Note 18:

Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined. No requir eme nt fo r curre nt balance among different pins.

syste m and 1-Wire r ecovery times. The specified value here applies to syste ms with only one devic e and wit h the minimum 1-Wire recovery times. For more heavily loaded s yst ems, an active pullup such as that found in the DS2480B may be required.

PUP

function of V

and the 1-Wire recovery times. The VTH and VTL max imum speci fi cations

PUP

ILMAX

REH

before.

the time at which the voltage is 90% of V

PUP

and the time at which the voltage is 10% of

PUP

up from VIL to VTH. The actual maximum durat ion for t he master to pu ll the line low is t

+ tF - ε and t

+ tF - ε respectively.

δ in Figure 14 represents the time required for the pu llup circu itry to pull the voltage on I/O up from VIL to the input high thr eshold of the bus master . The actual maximum duration for

the time at which the voltage is 90% of V

(for the RSTZ pin). For a pulse duration tPW: If tPW < t t

PWMIN(min)

< tPW < t

PWMIN(max)

, the pulse may or may not be reject ed. If tPW > t

and the time at which the voltage is 10% of

PUP

PWMIN(min)

, the pulse will be reject ed. If

pulse will be recognized and latched.

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PWMIN(max)

the

STANDARD VALUES

DS2408 VALUES

STANDARD

SPEED

OVERDRIVE

SPEED

STANDARD

SPEED

OVERDRIVE

SPEED

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

SLOT

(incl. t

REC)

61µs

(undef.)

7µs

(undef.)

65µs 1)

(undef.)

10µs

(undef.)

RSTL

480µs

(undef.)

48µs

80µs

660µs

720µs

53µs

80µs

PDH

15µs

60µs

2µs

6µs

15µs

60µs

2µs

7µs

PDL

60µs

240µs

8µs

24µs

60µs

280µs

7µs

27µs

W0L

60µs

120µs

6µs

16µs

60µs

120µs

8µs

13µs

SLS

, t

SPD

15µs

60µs

2µs

6µs

15µs

60µs

1.8µs

8µs

NAME

DESCRIPTION

N.C.

Not Connected

supervisor IC to the RSTZ pin.

Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND if not used.

I/O

1-Wire Interface. Open-dra in, requires external pullup resistor.

GND

Ground

N.C.

Not Connected

I/O Pin of Channel 7. Same charact er ist ics as P0.

I/O Pin of Channel 6. Same charact er ist ics as P0.

I/O Pin of Channe l 5. S ame chara cteristics as P0.

RST

STRB

RST

STRB

RST

I/O pin of channel 4; same charact er ist ics as P0

I/O pin of channel 3; same charact er ist ics as P0

I/O pin of channel 2; same charact er ist ics as P0

I/O pin of channel 1; same charact er ist ics as P0

N.C.

Not connected

N.C.

Not connected

PARAMETER

NAME

Intentional ch ange , lo nger recovery-t ime require ment due to mod ified 1 -Wire front end.

PIN DESCRIPTION

I/O Pin of Channel 0. Logic input/open-drain output wit h 100Ω maximum on-resistance; 0V to 5.25V operating range. Power-on default is

2 P0

indeterminate. If it is a pplication-critical for the o utp uts to powe r up in the "off" state, the user should attach an appropriate pow er -on-reset circuit or

DS2408

3 VCC

10 RSTZ

SW configurable PIO reset input ( (

). When configured as

) or open-drain strobe output

, a LOW input sets all PIO outputs to the "off" state by setting all bits in the PIO Output Latch State Register. When configured as

, an output strobe will occur after a P I O write (see Channel-Access Write command) or after a PIO Read (see Channe lAccess Read command). The power-on default function of this pin is

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DS2408

64-BIT

LASERED ROM

CRC16

GENERATOR

PAGE

CONTROL

1-WIRE

FUNCTION

CONTROL

PORT

FUNCTION

CONTROL

I/O

GND

PARASITE POWER

INTERNAL V

PORT

INTER-

FACE

RSTZ

P0 P1 P2 P3 P4 P5 P6 P7

APPLICATION

The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers, remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network interface o f a microco ntroller. Typical applicat ion circuits and co mmunicat ion examples are found later in this data sheet (Figures 17 to 22).

OVERVIEW

Figure 1 shows the relationships between the major function blocks of the DS2408. The device has two main d at a co mponent s: 1) 64-bit lasered ROM, and 2) 64-bit register page o f contro l and st atu s register s. Figure 2 shows t he hierar chical structure of the 1-Wire protocol. The bus master must first p r ovide one of the eight ROM funct ion co mmands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM, 7) Overdrive-Match ROM, or 8) Resume. Upon completion of an Overdrive ROM command byte executed at standard speed, the device will enter overdrive mode, where a ll subseque nt co mmunicat ion occurs at a higher speed. T he proto col require d for these ROM function co mmands is described in Figure 12. After a ROM funct ion command is successfully executed, the control functions become acc essible and t he master may provide any o ne o f the fiv e available commands. The protocol for t hese control commands is described in Figure 8. All data is read and written least significant bit first.

Figure 1. DS2408 BLOCK DIAGRAM

6 of 39

Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL

1-Wire Net

Other

Devices

Bus

Master

Command Level:

1-Wire ROM Function

Commands

DS2408-Specific

Control Function

Commands

DS2408

Available Commands:

Read ROM Match ROM Search ROM Skip ROM Conditional Search

ROM Overdrive Match Overdrive Skip Resume

Read PIO Registers Channel Access Read Channel Access Write Write Conditional

Search Register

Reset Activity Latches

Data Field Affected:

64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG RC-FLAG 64-BIT ROM, RC-FLAG, Port Status,

Cond. Search Settings, 64-BIT ROM, RC-FLAG, OD-Flag RC-FLAG, OD-Flag RC-FLAG

PIO Registers Port Input Latches Port Output Latches Conditional Search Register

Activity Latches

Cmd

Codes:

33h 55h

F0h CCh ECh

69h

3Ch A5h

F0h

F5h

5Ah

CCh

C3h

MSB

LSB

MSB LSB

DS2408

PARASITE POWER

The DS2408 can der ive its power ent irely from the 1-Wire bu s b y st or ing e n er g y o n a n int e r nal ca p a c it o r during periods of time whe n the signa l line is high. During low times the devic e continues to oper at e from this “parasite” po wer sour ce until the 1-Wire bus retu rns high to replenish t he parasite (capac ito r) supp ly. If power is available, the VCC pin sho uld be connec ted t o the e xternal voltage sup ply.

Figure 3. 64-BIT LASERED ROM

8-BIT

CRC CODE

48-BIT SERIAL NUMBER

64-BIT LASERED ROM

Each DS2408 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a uniqu e serial number. The last eight bits are a CRC of the first 56 bits. See F ig u r e 3 for details. The 1-Wire CRC is ge nerated using a polynom ial generator consist ing of a shift register and XOR g at es as s how n in F igure 4. T he po lyno mia l is X Dallas 1-Wire Cyc lic Re dund ancy Che c k is ava ilab le in Application Note 27.

7 of 39

8-BIT FAMILY

CODE (29h)

+ X

+ 1 . A dd it io na l in for mat io n a bo ut t he

DS2408

X0X1X2X3X4X5X6X7X

POLYNOMIAL =

X8 + X5 + X4 + 1

STAGE

INPUT DATA

The shift regist er bits are initialized to 0. Then, start ing with the least significant bit of the family co de, one bit at a t ime is shifted in. After the eighth bit of the family code has been ent ered, the se ria l number is entered. After the ser ial number has been entered, the shift reg ister contains the CRC value. Shift ing in the eight bits of CRC returns the shift register to all 0s.

Figure 4. 1 -Wire CRC GENERATOR

The registers needed t o operate the DS2408 are organized as a Reg ister Page, as shown in Figure 5. All registers are volatile, i. e., they lose their state when the device is powered down. PIO, Conditional Search, and Contro l/Statu s registers are read /written using t he device level Read PIO Registers and Write Conditional Search Register commands described in subsequent sections and Figure 8 of this document.

Figure 5. DS2408 REGISTER ADDRESS MAP

ADDRESS RANGE ACCESS TYPE DESCRIPTION

0000h to 0087h R Undefined Data 0088h R PIO Logic State 0089h R PIO Output Latch State Register 008Ah R PIO Activity Lat c h State Register 008Bh R/W Conditional S ear c h Channel S election Mask 008Ch R/W Conditional Search Channel Polarity S elec tion 008Dh R/W Control/Status Register 008Eh to 008Fh R These Bytes Always Read FFh

8 of 39

DS2408

STRB

008Ah

AL7

AL6

AL5

AL4

AL3

AL2

AL1

AL0

RST

PIO Logic-State Regis ter

The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers command. Reading t his register does not generate a signal at t he RSTZ pin, even if it is configured as

. See the Channel-Access commands desc ription for deta ils on

PIO Logic State Register Bitmap

ADDR b7 b6 b5 b4 b3 b2 b1 b0 0088h P7 P6 P5 P4 P3 P2 P1 P0

This register is read-only. Each bit is as sociated with the p in of the respect ive PIO c han nel a s sho wn in Figure 6. The data in this register is sampled at the last (most significant ) bit of the byte t hat proceeds reading the first (least significant ) bit of this reg ister. See the Read PIO Registers command descript ion for det a ils .

PIO Output Latch State Register

The data in this reg ister represent s the latest data writt en to the PIO thro ugh the Channel-access Write command. This register is read using t he Read PIO Registers co mmand. Reading this register does no t

generate a signa l at the RSTZ p in, even if it is co nfigured as description for det ails on

. This register is not affected if the device reinitializes itself after an ESD

. See the Channel-access commands

hit.

PIO Output Latch State Register Bitmap

ADDR b7 b6 b5 b4 b3 b2 b1 b0 0089h PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0

This register is read-o nly. Each b it is assoc iated with the output latch of the respect ive PIO channel as shown in Figu re 6.

The f lip-flops of t his register will power up in a random stat e. If the chip has to power up w ith all PIO channels off, a LOW pu lse must be generat ed on the RSTZ pin, e.g., by means o f an open-drain CPU supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure t hat RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).

PIO Activity Latch State Register

The data in this regist er repr esent s the curr ent st ate of the PIO activity latches. This reg ister is read using the Read PIO Regist ers co mmand. Read ing th is reg ister does not generate a signa l at the RSTZ p in, eve n if it is configured as

. See the Channel-access commands description for details on

PIO Activity Latch State Register Bitmap

ADDR b7 b6 b5 b4 b3 b2 b1 b0

This register is read-only. Each b it is associated w ith the activit y latch of the respect ive PIO channel as show n in Figu re 6. This reg ister is cleared to 00h by a power-o n reset, by a low pulse on the RST Z pin

(only if RSTZ is configured as

input), or by successful execution of the Reset Activity Latches

command.

9 of 39

Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM

PIO OUTPUT LATCH

PIO ACTI

VITY

LATCH

EDGE

DETECTOR

PORT

FUNCTION

CONTROL

TO ACTIVITY LATCH

STATE REGISTER

TO PIO LOGIC

STATE REGISTER

TO PIO OUTPUT LATCH STATE REG.

"1"

CLR ACT LATCH

ROS

STRB

CHANNEL

I/O PIN

RSTZ

DATA

CLOCK

POWER ON RESET

ADDR

DS2408

Conditional Search Channel Selection Mask Register

The data in this register controls whether a PIO channel qualifies for participation in the conditional search command. To include one or more o f the PIO channels, the bits in this register that correspond to those channe ls n eed to be set t o 1. This reg ist er can o nl y b e writt en t hrough the Write Conditional S ear ch Reg is ters command .

Conditional Search Channel Selection Mask Register Bitmap

008Bh SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

This register is read/write. Each bit is assoc iated with the respect ive PIO channel as s hown in Figure 7. This register is cleared to 00h by a power-on reset

10 of 39

DS2408

AL7

PLS

SP0

SM0

SM7

SP7

AL0

CSR

INPUT FROM

CHANNELS 1 TO 6

(NOT SHOWN)

CHANNEL 0

CHANNEL 7

Conditional Search Channel Polarity Selection Register

The data in t his register speci fies the po larity of each select ed PIO channel for the device to respond to the conditional searc h co mmand. Within a PIO channel, t he data so ur ce may be either the channel's input signal (pin) or t he channel's activity latch, as spec ified by the PLS bit in t he Contr ol/St atus regist er at address 008Dh. This regist er can o nly be wr itten throu gh t he Write Co nd it iona l Searc h Regist er s command.

Conditional Search Channel Polarity Selection Register Bitmap

ADDR b7 b6 b5 b4 b3 b2 b1 b0

008Ch SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

This register is read/write. Each bit is associated with t he respective PIO channel as s hown in Fig ure 7. This register is cleared to 00h by a power-on reset.

Figure 7. Conditional Search Logic

11 of 39

DS2408

BIT DESCRIPTION

BIT(S)

DEFINITION

1: bitwise AND

RST

STRB

RST

STRB

Control/Status Register

The data in this reg ister reports st atus information, d etermines the function o f the RSTZ pin and fur ther configures the de vice for condit ional search. This re gist er c an o nly be wr itt en t hrou gh t he Wr ite C ond itional Search Registers command.

Control/Status Register Bitmap

ADDR b7 b6 b5 b4 b3 b2 b1 b0

008Dh VCCP 0 0 0 PORL ROS CT PLS

This register is read/wr ite. Withou t VCC supp ly, this register reads 08 h after a po wer-o n r eset . The fu nctional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function; they wil l always r ead 0 and cannot be set to 1.

Control/Status Register Details

PLS: Pin or Activity Latch Select

CT: Conditional Search Logical Term

ROS: RSTZ Pin Mode Control

PORL: Power-On Reset Latch

VCCP: VCC Power Status (Read-Only)

b0 Selects either the PIO pins or the PIO activity latches as input for the

conditional search. 0: pin selected (default) 1: activity latch selected

b1 Specifies whether the data of two or more channels needs to be OR’ed

or AND’ed to meet the qualifyi ng c ondition for the device to respond to a conditional search. If only a single channel is selected in the channel selection mask (008B h) this bit is a don't care. 0: bitwise OR (default)

b3 Specifies whether the dev ice has performed a power-on reset. This bi t

b7 For VCC powered operation the VCC pin needs to be tied to a voltage

Configures RSTZ as eit her 0: configured as 1: configured as

can only be cleared to 0 under soft ware cont r ol. As long as this bit is 1 the device will always respond to a conditional search.

source ≥ V 0: V 1: V

PUP

pin is grounded

-powered operation

input or

input (default)

output

The interaction o f the various s ignals that det ermine whether t he device respo nds to a cond itional search is illu st rat ed in Figure 7. T he selection mask SM s elects t he part icipating channe ls. The po larity select ion SP deter mines for each channe l whether the c hannel signa l needs to be 1 or 0 to qualify. T he PLS bit determines whether all channel signals are t aken from the act ivity latches or I/O p ins. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or OR’ed result as the condit ional searc h response signal CSR.

Note on CT bit:

OR The qualifying condition is met if the input (pin state or activity latch) for one o r more se lected

channels matches the corr espond ing polarity.

AND For the qua l ifyin g co ndition to be met, the input (pin sta te or activity latch) for every selected

channel must match the co rresponding pola rity.

12 of 39

Figure 8-1. CONTROL FUNCTIONS FLOW CHART

Bus Master TX

TA1 (T7:T0), TA2 (T15:T8)

F0h

Read PIO Reg.?

Address

< 90h?

To Figure 8

2nd Part

From Figure 8

2nd Part

Bus Master TX Control

Function Command

To ROM Functions

Flow Chart (Figure 12)

From ROM Functions Flow Chart (Figure 12)

DS2408 sets Register

Address = (T15:T0)

Bus Master RX Data Byte

from Register Address

Bus Master RX CRC16 of Command, Address,

Data Bytes

Bus Master

RX “1”s

DS2408 Incre-

ments Address

Counter

Master

TX Reset?

Address

< 90h?

Master

TX Reset?

Master

TX Reset?

Note:

To read the three PIO state and latch register bytes, the target address should be 0088h. Returned data for a target address <0088h is undefined.

Address

= 88h?

DS2408 Samples

PIO Pin Status

Note 1)

See the command description for the exact timing of the PIO pin sampling.

DS2408

13 of 39

Figure 8-2. CONTROL FUNCTIONS FLOW CHART

DS2408

14 of 39

Figure 8-3. CONTROL FUNCTIONS FLOW CHART

DS2408

15 of 39

DS2408

IO (1-Wire)

STRB\

Example - Sampled State = 72h

MS 2 bits of previous byte (8Dh)

LS 2 bits of data byte (72h)

SPD

Sampling Point

STRB

CONTROL FUNCTION COMMANDS

Once a ROM function command is completed, the Control Function Commands can be issued. The Control Functions Flow Chart (Figure 8) describes the protocols necessary for accessing the PIO channels and the spec ial function register s of the DS2408. The commu nicat ion betw een the master and the DS2408 takes p lace either at st andard speed (default, OD = 0 ) or at overdrive speed ( OD = 1). If not explicitly set into the overdrive mode, the device op er ates at standard speed.

Read PIO Registers [F0h]

The Read PIO Registers command is used to read any of the device's registers. After issuing the command, the master must pro vide the 2-byte tar get address. A fter these two b ytes, the mast er read s data beginning from the target address and may continue until address 008Fh. If the master co nt inues reading, it will receive an invert ed 16-bit CRC o f the command, address b ytes, and al l data bytes read from t he initial starting byte through the end o f the register page. This CRC16 is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addr essed location and continuing thro ug h t o the last byte o f the r egister page. After the bus master has received the CRC16, the DS2408 responds to any subsequent read-time slo ts w ith logical 1’s until a 1-Wire Reset command is issued. If this command is issued with target address 0088h (PIO Logic Stat e Regist er ) , t he PIO sampling t ak es place during the transmissio n of the MS bit of TA2. I f the target address is lower t han 0088h, the sampling takes p lace while the master reads the MS bit fro m address 0087h.

Channel-Access Read [F5h]

In contrast to reading the PIO log ical state from address 88h, this co mmand reads t he st atus in an endless loop. After 32 bytes of PIO pin status the DS2408 inserts an inverted CRC16 into the data stream, which allows the master to verify whet her the data was received error -free. A Channel-Access Read can be terminated at any time with a 1-Wire Reset .

Figure 9. CHANNEL-ACCESS READ TIMING

Notes:

1) The "previous byte" cou ld be the co mmand code, the data byte resulting fro m the previous PI O

sample, or the MS byte of a CRC16. The example show s a read -1 time slot.

2) The samp le point timing also app lies t o the Channel-access Write co mmand, with the "previous byte"

bein g the write confirma tion byte (AAh). No Channel-Access Write command.

16 of 39

pulse results when sampling occurs during a

DS2408

STRB

IO (1-Wi re)

PIO

STRB\

39h

72h

SLS

SPDtSPD

Case #1

- MS Bit of new PIO

state is 0

Example - Old State = 39h, New state = 72h

MS 2 bi t s of inverted new-st ate by te (8Dh )

LS 2 bi t s of confirmat i on byt e (AAh)

Case #2 - MS Bit of new PIO

state is 1

Example - Old State = 72h, New state = 93h

MS 2 bi t s of inverted new-st ate by te (6Ch )

LS 2 bi t s of confirmat i on byt e (AAh)

72h

93h

SPD

SPDVTH

STRB

RST

The status of al l eight PIO c hannels is sampled at the same time. Th e first sampling occ u rs du ring the last (most significant ) bit of the command code F5h. While t he master rece ives the MSB of the PIO stat us (i.e., the status of pin P7) the next sampling occurs and so on until the master has received 31 PIO samples. Next, the master rece ives the inverted CRC16 o f the command byte and 32 PIO sa mples (first pass) o r the CRC of 32 PI O samples (subseq u ent passes). Wh i le the last (most signi f icant) b it of the CRC is transmitted the next PIO sampling takes place. The delay between t he beginning of the time slot and the sampling point is independent of the bit value being transmitted and the data direction (see Figure 9). If the RSTZ pin is configured as

, a strobe signa l will be generated d uring the tr ansm issio n o f th e first two (least significa nt) bits of PIO data. The strobe can signal a FIFO or a microco ntroller to apply the next data byte at the PIO for the master to read t hrough the 1-Wire line.

Channel-Access Write [5Ah]

The Channel-Access Write command is the only way to write to the PIO output-latch state register (address 0089h), which controls the open-dra in o u tput tr ans is t o r s o f t he P I O c ha n ne ls. In a n e ndle ss lo o p this command first w rites new data to t he PIO and then reads back t he PIO status. The implic it read-afterwrite can be used by the mast er for statu s verificatio n or for a fast co mmunicat ion with a micro co ntro ller that is connected to the port pins and RSTZ for synchronization. A Channel-Access Write can be ter minated at any time with a 1-Wire Reset.

Figure 10 . CHANNEL-ACCESS WRITE TIMING

Note: Both examples as sume that the RSTZ p in is configured as input (default), the RSTZ pin needs to be tied high (to VCC o r V function properly. Leaving the pin unconnected will forc e the output transistor s of the PI O cha nnels to the "off" state and the PIO out put latches will al l read "1". S ee F igure 6 for a schemat ic of the log ic.

After the command code the master transmits a byte that determines the new state of the PIO output transistors. The first (least significant) bit is associated to P0. To switch the output transistor off (nonconducting) t he c or re spo nd ing bit va lue is 1 . T o sw itch t he tr ans ist o r o n t hat bit need s t o be 0 . T his w a y the data byte t ransmitted as the new PIO out put state arrives in its tr ue form at the PIO pins. To protect the transmission against data errors, the master has to repeat t he new PIO byte in its inverted for m. Only if the transmission was success ful will the PIO st atus change. The actua l transition at the PIO to the new state occurs during the last (most significant) bit of the inverted new PIO data byte and depends on the polarity of that bit, as shown in Figure 10. If this bit is a 1, the transition begins after t case of a 0, the transition begins at the end of the time slot , when the VTH t hresho ld is cr o ssed. To inform the master about the successful change o f the PIO status, the DS2408 transmits a co nfirmat ion byte with

17 of 39

output. If RSTZ is configured as

) for the Cha nnel-Access Wr ite to

PUP

is e xpir ed; in

SLS

DS2408

STRB

the data pattern AAh. If t he RS T Z pin is conf igured as transmission of the first two (least significant) bits of the co nfir mation byte. The st r obe can signal a FIF O or a microcontroller t o read the new data b yte from the PIO. While the last bit o f the confirmat ion byte is transmitted, the DS2408 samples the status of the PIO pins, as shown in Figure 9, and sends it to the master. Dep ending on the data, t he mast er can either cont inue writing more dat a to the PIO o r issue a 1Wire reset to end the command.

, a strobe signal will be g enerated during the

Write Conditional Search Register [CCh]

This command is used to tell the DS2408 the conditions that need to be met for t he device to respo nd to a Conditional Searc h co mmand, to define the function of the RSTZ pin and to clear t he po wer-on reset flag.

After issuing the co mmand the master sends t he 2-byte target address, which must be a value bet ween 008Bh and 008Dh. Next the master sends the byte t o be writt en to the addres sed cell. I f the address wa s valid, the byte is immed iately written to its locat ion in the register page. The master no w can either end the command by issuing a 1-Wire reset or send anot her byte for the next higher address. Once r egister address 008Dh has been wr itten, any su bsequent data bytes w ill be igno red. The mast er has to send a 1Wire reset to end the command. Since the Wr ite Conditional Searc h Register flow does not include an y error-checking for t he new register data, it is important to verify corr ect writing by reading the reg isters using the Read PIO Register s command.

Reset Activi ty Latches [C3h ]

Each PIO channel include s an activity latch that is set whenever t here is a state trans ition at a PI O pin. This change may be caused by an external event/signal or by writing to the PIO. Depending on the application t here may be a need t o reset the act ivity latch after having cap tured and serviced a n exter nal event . Sinc e ther e is onl y read access to the PIO Activity Latch Stat e Register, the DS2408 sup ports a special command to reset the latches. After having received the command code, the device resets all activity latches s imultaneous ly. There are two ways for the master to verify the execut ion of the Reset Activity Latches command. The easiest way is to start reading from the 1-Wire line right after the command code is transmitt ed. In this case the master will read AAh bytes unt il it sends a 1-Wire reset . The other way to verify execution is to read register address 008Ah.

1-WIRE BUS SYSTEM

The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2408 is a slave de vice. The bus master is typically a microco ntroller or PC. For s mall configurations the 1-Wire communicat ion signals ca n be generated under so ftware control using a sing le port pin. For multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip (DS9097U ser ies) are recommended. This simplifies the hardware d esign and frees the micro processor from responding in rea l time.

The discussion of this bus system is broken do wn into three topics: hardware co nfiguration, transactio n sequence, and 1-Wire s igna ling (signal type s and timing). The 1 -Wire pro tocol defines bus t r ansactions in terms of the bus stat e during specific t ime slot s that ar e initiated on t he falling edg e of sync pu lses fro m the bus master.

HARDWARE CONFIGURATION

The 1 -Wire bus has only a single line by definition; it is important that each device o n the bus be able to drive it at the appro priate time. To facilitate t his, each device attached to the 1-Wire bus must have open drain or tri-state outputs. The 1-Wire port of the DS2408 is open-drain with an internal circuit equivalent to that shown in Figure 11.

18 of 39

DS2408

OPEN-DRAIN

PORT PIN

RX = RECEIVE TX = TRANSMIT

100Ω MOSFET

PUP

DATA

SEE TEXT

SIMPLE BUS MASTER

DS2408 1-Wire PORT

PUP

DS2480B

+5V

HOST CPU

VDD POL RXD TXD

VPP

1-W

GND

SERIAL IN

SERIAL OUT

SERIAL

PORT

TO 1-Wire DATA

DS2480B BUS MASTER

Figure 11. HARDWARE CONFIGURATION

A multidrop bus c ons ists of a 1 -Wire bus w it h mu l tiple slaves at tached. At standard spe ed the 1-W ire bus has a maximum data rat e of 15.3kbps. Communication speed for 1-Wire devices can be typical ly boosted to 142kbps by activating the overdrive mode; however, the maximum overdrive data rate for the DS2408 is 100kbps. The value of the pullup resistor primarily depends on the network size and load conditions.

For most applications the optimal value of the pullup resistor will be approximately 2.2kΩ for standard speed and 1.5kΩ for overdrive speed.

The idle stat e for the 1-Wire bu s is high. I f for any reaso n a transaction needs to be suspend ed, the bus MUST be left in the idle stat e if the transact ion is to resume. If this does no t o ccur and the bus is left low for more than 16µs (overdrive speed) or more than 120µs (standard speed), one or more devices o n the bus may be reset. With the DS2408 the bus must be left low for no longer than 13µs a t overdrive s pe ed to ensure that none of the slave devices on the 1-Wire bus performs a reset. The DS2408 communicates properly when used in conjunction with a DS2480B 1-Wire driver and serial port adapt ers that are based on this driver chip. When operating the device in overdrive or below 4.5V, some 1-Wire I/O timing values must be modified (see EC table).

19 of 39

DS2408

TRANSACTION SEQUENCE

The protocol for accessing the DS2408 through the 1-Wir e p ort is as follows:

 Initialization  ROM Function C ommand  Contro l Functio n C ommand  Transaction/Data

Illustrations o f the transaction sequence for the various co nt r ol function commands are found later in this document.

INITIALIZATION

All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset p ulse transmitted by the bus m aster followed by presence pulse(s) t ransmitted b y the slave(s). The presence pulse lets the bus master know that the DS2408 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section.

ROM FUNCTION COMMANDS

Once the bus mast er has det ected a presence, it ca n issue o ne o f the seven ROM funct ion commands . Al l ROM function commands are eight bits long. A list of these commands follows (see the flowchart in Figure 12).

Read ROM [33h]

This command allows the bus master to read the DS2408's 8-bit family code, unique 48-bit serial number, and 8 -bit CRC. This co mmand can only be u sed if there is a s ingle device on t he bus. If more than o ne sla ve is pres ent on the bus, a data co llision will occu r when all slaves try to transmit at the same t ime (open dra in will pro duce a wired-AN D resu lt). The r esult ant fami ly cod e and 48-bit serial nu mber wil l result in a mismatch of the CRC.

Match ROM [55h]

The Match ROM command, followed by a 64-bit ROM seque nce, allows the bus master to addre ss a specific DS2408 on a multidrop bus. Only the DS2408 that exactly matches the 64-bit ROM sequence will respond to the following co ntrol fu nction co mmand. All slaves that d o not match the 64-bit ROM sequence will wait for a r eset p ulse. This command can be used with either single o r mult iple devic es on the bus.

Search ROM [F0h]

When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a proce ss of eli m in ation to ide ntif y t he 64 -bit ROM codes of all sla ve devices on the bus. T he search ROM process is the repet ition of a simple three-step rout ine: read a bit, read the complement of the bit, the n write the desired v alue of that bit. The bus ma ster perfor ms this simple, t hree-step ro utine on each bit o f the ROM. After o ne complete pass, the bus mast er knows the contents o f the ROM in o ne device. The remaining number of devices and their ROM codes may be identified by additional passes. See Application Note 187 for a detailed discussion on the Search ROM command process including a software example.

Conditional Search [ECh]

The Conditional Searc h ROM command operates sim ilarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. The condit ion is specified by the Conditional Search channel and polarity selection (addresses 008Bh, 008Ch), the bit functions CT and

20 of 39

DS2408

PLS of the Control/Stat us Register (address 008Dh), and t he state of the PIO channels. See F igure 7 for a description of the Conditional Search logic. The device also responds to the Conditional Search if the PO RL bit is s et . T he C on dit iona l Sear ch RO M pro vides an eff icie nt mea ns for the bu s mast er t o det ermine devices on a multidrop system t hat have to signal a n important event, such as a state change at a PIO pin caused by an external sig nal. After each pass of the condit ional search t hat successfully determined the 64-bit ROM for a specific device o n the multidrop bus, t hat particular device ca n be individually accessed as if a Match ROM had been issued, since all ot her devices will have dro pped out of the search process and will be wa it ing for a reset pulse.

Skip ROM [CCh]

This command ca n s ave time in a single-drop bus syste m by allow ing the bus master to access the contr ol functions without providing the 64-bit ROM co de. If more t han one slave is present on the bu s and a Read command is issued following the Skip ROM co mmand, data collision will occur on the bus as multip le slave s tr a nsmit simultaneo usly (open-dr ain pulldowns will produce a wired-AND result).

Resume Command [A5h]

In a typical applicat ion the DS2408 ca n be accessed severa l times to complete a co ntrol or adjustment function. In a multidrop environment t his means that the 64-bit ROM sequence of a Mat ch ROM command has to be repeated for ever y access. To maximize the dat a throug hput in a multidro p environment, the Resume C omm and functio n is i mplemented. This function che c ks the status of the RC f lag a nd, i f it i s set, direct ly trans fers cont ro l to t he control functions, similar t o a S kip ROM co mma nd . T he o n ly wa y t o set the RC flag is through successfully executing the Match ROM, Search ROM, Conditional Search ROM, or Overdrive-Match ROM command. Once the RC flag is set, the device can be repeatedly accessed thro ugh the Resu me Co mmand fu nct ion. Access ing anot her devic e on t he bus w ill c lear t he RC flag, preventing two or more devices from simultaneously responding to the Resume Command funct io n.

Skip ROM [3Ch]

On a single-drop bus this command can save time by allowing the bus master to access the control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS2408 in the overdrive mode (OD = 1). All communication following this command has t o occur at overdr ive speed until a reset p ulse of minimum 480µs durat ion resets al l devices on the bus to standard speed (OD = 0). When issued on a multidro p bus t his command will set all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrivesupporting devic e, a reset pu lse at o verdr ive speed ha s to be issued fo llowed by a Match ROM o r S earc h ROM command sequence. This will speed up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdr ive Skip ROM command is followed by a Read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open-drain pulldowns will produce a wired-AND result).

Overdrive Match ROM [69h]

The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at overdrive speed allows the bus mast er to addr ess a specific DS2408 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS2408 t hat exactly matches the 64-bit ROM seque nce will respond to the subsequent co ntrol funct ion command. S laves alread y in overdr ive mode fro m a previous Overdrive Sk ip or Ma tch co mmand w ill re main in o verdr ive mo de. A ll overd rive-capable slaves will ret urn to standard speed at the next Reset P ulse of minimum 480µs durat ion. The Overdrive Match ROM co mmand can be used with eith er s ingle or multiple dev ices o n the bus.

21 of 39

Figure 12 -1. ROM FUNCTIONS FLOW CHART

From Figure 12

2nd Part

To Control Functions Flow Chart (Figure 8)

Master TX Bit 0

Master TX Bit 63

Master TX Bit 1

RC = 1

DS2408 TX

CRC Byte

DS2408 TX

Serial Number

(6 Bytes)

DS2408 TX

Family Code

(1 Byte)

Bit 0

Match?

Bit 1

Match?

Bit 63

Match?

DS2408 TX Bit 0 DS2408 TX Bit 0

Master TX Bit 0

DS2408 TX Bit 1 DS2408 TX Bit 1

Master TX Bit 1

DS2408 TX Bit 63 DS2408 TX Bit 63

Master TX Bit 63

RC = 1

Bit 0

Match?

Bit 1

Match?

Bit 63

Match?

To Figure 12

2nd Part

RC = 0

YYY

F0h

Search ROM

Command?

55h

Match ROM

Command?

ECh

Cond. Search

Command?

33h

Read ROM

Command?

To Figure 12

2nd Part

From Control Functions

Flow Chart (Figure 8)

Bus Master TX ROM

Function Command

DS2408 TX

Presence Pulse

Reset Pulse?

OD = 0

Bus Master TX

Reset Pulse

From Figure 12, 2

Part

Condition Met?

DS2408 TX Bit 0 DS2408 TX Bit 0

Master TX Bit 0

DS2408 TX Bit 1 DS2408 TX Bit 1

Master TX Bit 1

DS2408 TX Bit 63 DS2408 TX Bit 63

Master TX Bit 63

RC = 1

Bit 0

Match?

Bit 1

Match?

Bit 63

Match?

DS2408

22 of 39

Figure 12 -2. ROM FUNCTIONS FLOW CHART

From Fi gure 12

1st Part

From Fi gure 12

1st Part

To Fi gure 12, 1st Part

RC = 1 ?

RC = 0 ; OD = 1

Mas ter TX Bit 0

Mas ter TX Bit 63

Mas ter TX Bit 1

RC = 1

Bit 0

Match?

Bit 1

Match?

Bi t 63

Match?

69h

O verdrive Match

ROM?

RC = 0 ; OD = 1

Master

TX R eset ?

Master

TX R eset ?

3Ch

Overdrive

Ski p ROM?

A5h

Resume

Command?

RC = 0

CCh

Ski p ROM

Command?

To Fi gure 12

1st Part

DS2408

23 of 39

DS2408

1-WIRE SIGNALING

The DS2408 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on o ne line: Reset S equence with Re set Pu lse and Presence Pu lse, Write-Z e ro, W r it e -One, and Read-Data. Except for the presence pulse, the bus master initiates all these signals. The DS2408 can communicate at two different speeds, st andard speed, and o verdrive speed. If not explicitly set into the overdrive mode, the DS2408 will communicate at standard speed. While in overdrive mode, the fast tim ing ap plie s to a ll wavefor ms .

To get from idle to act ive, t he vo ltage on the 1-Wire line needs to fall from V To get from active to idle, the voltage needs to rise from V

past the VTH thr eshold. The V

ILMAX

below the VTL threshold.

PUP

ILMAX

vo ltage is relev ant for the DS2408 whe n determ ining a logical leve l, not tr iggering any events.

Figure 13 shows the init ia lization sequence requ ired to begin any co mmu nication with the DS240 8. A Reset Pulse followed by a Prese nce Pu lse indicates t he DS2408 is read y to receive dat a, given the corr ect ROM a nd control function command. I f the bus mast er uses s lew-rate control on the falling edg e, it must pu ll do w n t he l in e fo r t the overdrive mode returning the device to st andard speed. If the DS2408 is in over drive mode and t

+ tF to compensate for the edge. A t

RSTL

duration o f 480µs or longer will exit

RSTL

is no longer than 80µs the device w ill remain in overdrive mode.

Figure 13. INITIALIZA TI ON PROCEDURE “RESET AND PRESENCE PULSES”

After the bus mast er has released t he line it go es into receive mode (RX). The 1-Wir e bus is t he n p ulled to V threshold is crossed, the DS2408 waits for t l ow for t

via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the VTH

PUP

and then transmits a Presence Pulse by pulling the line

PDH

. To detect a presence pulse, the master must test the logical state of the 1-Wire line at t

PDL

MSP

The t expired, the DS2408 is ready for data communication. In a mixed population network, t

window must be at least the sum o f t

RSTH

PDHMAX

, t

PDLMAX

, and t

RECMIN

. I mmediat ely a fter t

should be

RSTH

extended to a minimum of 480µs at standard spee d and 48µs at overdrive speed to accommodate other 1Wire devices.

24 of 39

DS2408

PUP

IHMASTER

ILMAX

DS2408

Sampling

Window

SLSMIN

SLOT

W1LtSLSMAX

REC

PUP

IHMASTER

VTH

VTL

ILMAX

DS2408

Sampling

Window

SLSMIN

SLOT

SLSMAX

W0L

Read/Write Time Slots

Data communicat ion with the DS240 8 t akes place in t ime slots, whic h carry a sing le bit e ach. Wr ite t ime slots transport data from bus master to slave. Read time slots transfer data from slave to master. The definitions of the wr ite and read time slot s are illu s trated in Figure 14.

All co mmunica tion be gins wit h the mast er pu lling the dat a line lo w. As the vo ltage on t he 1-Wir e line fal ls below the thr esho ld VTL, the DS2408 st art s it s int ernal time base. The to lera nce o f t he slave time base creat es a slave-sampling window, which st retches from t

SLSMIN

to t

SLSMAX

. The vo ltage on the data

line at the sampling point deter mines whether the DS2408 decodes the time slot as 1 or 0.

Master-to-Slave

For a write-o ne time slot, t he voltage on the data line must have crossed t he V write-one lo w t ime t below the V

THMIN

W1LMAX

threshold until the write-zero low time t communication, the voltage on the data line should not exceed V After the V

threshold has been crossed, the DS2408 needs a recovery time t

THMAX

has e xpired. For a w rite-zero time slot , the voltage on t he data line must st a y

W0LMIN

has expired. For most reliable

dur ing the entire t

ILMAX

the next time slot.

thr es hold aft er t he

THMAX

W0L

before it is ready for

REC

window.

Figure 14. READ/WRITE TIMING DIAGRAM

Write-One Time Slot

Write-Zero Time Slot

25 of 39

DS2408

Read-Data Time Slot

Slave-to-Master

A re ad-dat a time slot beg ins like a wr ite-one time slot. The voltage on t he data line must remain be low V

u ntil t he rea d low t ime tRL has expired. Dur ing t he tRL w indow , when res pond ing wit h a 0, t he

TLMIN

DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown end s and the voltage st ar ts rising again. When responding with a 1, the DS2408 does not ho ld the dat a line low at all, and the voltage starts rising as soon as tRL is over .

Th e s um o f tRL + δ (rise time) on o ne side and the internal timing generato r of the DS2408 on the other side define the master sampling window (t

MSRMIN

to t

MSRMAX

) in which t he master must per fo rm a read from the data line. For most reliable c ommunic a tion, tRL shou ld be as short as per missible and t he mast er should r ead clo s e to but no later than t t

is exp ir ed. This guara ntees sufficient reco very time t

SLOT

MSRMAX

. After reading from the data line, the master must wa it until

fo r t he DS2408 to get ready fo r the next

REC

time slot.

Improved Network Behavior

In a 1 -Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networ ks therefore are su scept ible to noise of various or igins. Depending on the phys ical size a nd to polog y of the netwo rk, reflect ions fro m end po ints and bra nch po ints can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communicat io n line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitc h during the rising edge of a t ime slot can cause a slave device to lose sync hronizatio n with the master and, as a consequence, result in a Search ROM co mmand coming to a dead end or cause a device level command t o abort. For better per formance in network applications, t he DS2408 uses a new 1-Wire front e nd, wh ich makes it less se nsitive t o noise a nd also reduces t he magnitude of noise in ject ed by the slave device itself.

The 1 -Wire front end of the DS2408 d iffers from traditional slave devices in four charact eristics.

1) The falling edge o f the prese nce pulse has a co ntro lled slew rate. This prov ides a better match to the

line impedance than a digitally switched transistor, converting the high-frequency ringing known from t ra d itio n a l de v ic es int o a s mo o th er lo w-bandw idth transition. The slew rat e control is specifie d by the parameter t

2) There is additional lowpass filtering in the circuit t hat detects the fa lling edge at the beginning of a

time slot. This reduces the sensitivity to high-frequency noise. This addit iona l f iltering does not apply at overdrive speed.

, which has different va l ues fo r standard a nd overd rive s pee d.

FPD

26 of 39

3) The input buffer was designed with hysteres is. If a negat ive glitch cro sses VTH but do es n’t go belo w

PUP

REH

Case A

Case C

Case B

VTH - VHY, it will not be recognized ( Fig ure 15, Case A). The hysteresis is effective at a ny 1-Wire speed.

4) There is a t ime window spec ified by the r ising edg e hold-o ff t ime t

igno red, even if t hey extend be lo w the VTH - VHY threshold (Figure 15, Case B, tGL < t

dur ing which glitc hes w ill b e

REH

). Deep

REH

voltage droops or glitches that appear late after crossing the VTH thr e shold a nd ext e nd be yond t he t window cannot be f iltered o ut and wi ll be t aken as the beginning o f a new time slot (Figure 15, Case

C, tGL ≥ t

REH

Figure 15. NOISE SUPPR ESSION SCHEME

CRC GENERATION

The D S2 408 has t wo d iffer e nt t ype s o f cyc l ic r edu nda ncy c he ck s (C RC s). One CR C is a n 8 -b it t ype an d is stored in the most significant byte of the 64-bit ROM. T he bus mast er can co mpute a C RC va lue from the first 56 bits of the 64-bit ROM and compare it to the value st ored within the DS2408 to determine if the ROM data has been rece ived er ro r free. T he equiva le nt polynomial f u nctio n of t h is C R C is X

+ 1. This 8-bit CRC is received in the true (noninverted) for m. It is computed at the factory and lasered

into the ROM.

The ot her CRC is a 16-bit t ype, generat ed acco rd ing to t he standard ized CRC16-p olynomial fu nc tio n X

+ X

+ X2 + 1. T his C RC is used for error d etection when reading dat a through the end of the re gister

page using the Read PIO Regist ers command, for fast ver ification of the dat a transfer when writ ing to or reading from t he scratchpad, and w hen reading fr om the PIO using t he Channel-access Read co mmand. In cont rast to t he 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRCgenerator inside the DS2408 chip (Figure 16) calculates a new 16-bit CRC as shown in the co mmand flow chart of Figure 8. The bus master compares the CRC value read from the device to the one it calculates fro m the dat a and decides w hether t o continue with a n operat ion or to rer ead the port ion of the data with the CRC error.

Wit h t he Read PIO Regist ers flow c hart , t he 16-bit CRC value is the result o f shifting the command byte into the cleared CR C g enerator, fo llowed b y t he 2 ad dr ess b yte s a nd the data bytes beginning at the target address and ending with t he last byte of the register page, address 008Fh.

With the initial pass through the Channel-access Read command flow, the CRC is generated by first clearing the CRC generat or and t hen shifting in the command co de followed by 32 bytes of PIO pin data. Subsequent pa s ses thr ough the command flow wi ll ge nerate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in 32 bytes read from the PIO pins. For more informat ion on generating CRC values see A pplication Note 27.

+ X5 +

DS2408

REH

27 of 39

Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL

POLYNOMIAL = X16 + X15 + X2 + 1

0X1

X2X3X

5X6

X7X

X9X10X

11X12

X13X

14X15

STAGE

INPUT DATA

CRC OUTPUT

VCC

DS80C520

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

P3.7/RD

P3.6/

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TXD0

P3.0/RXD0

XTAL2

XTAL124RTCX2

RTCX1

P2.6/AD14

P2.5/AD13

P2.4/AD12

P2.3/AD11

P2.2/AD10

P2.7/AD15

P2.1/AD9

P2.0/AD8

PSEN

ALE

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

47U

DS2408

GND5VCC

PULLUP PROVIDED BY CPU

8051 Equiv CPU

GND

VCC

RSTZ

Figure 17. DS2408 AS SLAVE INTERFACE FOR MICROCONTROLLER

DS2408

The data direction (upload/download) is determined by application-specific data protocol.

28 of 39

Figure 18. DS2408 AS SLA VE INTERFACE FOR INTELLIGENT DISPLAY

DS9503

47U

VCC

LEDK

LEDA

STB

R/W

D/C

CONTRAST

VCC

GND

VCC

10K

VCC

DS2408

GND

VCC

3IO4

Local iButton Probe

LCD Display

Down

Select

5VDC

GND

RSTZ

ACM1601B 16X1 Display

with Back Light

VCC

DS2408

VCC

GND

7P68

11P312

13P114

2.2K

VCC

PIC12C508

OSC2/P4

OSC1/P5

2P07

P2/CK

CLR/P3

GND

VCC

MICROCONTROLLER

WITH FEW I/O PINS

RSTZ

24 I/O LINES OR 3 BYTE-WIDE BUSES FROM A SINGLE PIN

VCC

GND

P77P6

P59P411P3

VCC

RSTZ

DS2408

VCC

GND

P68P5

11P312

13P114P02

VCC

RSTZ

DS2408

Figure 19. DS2408 AS MICROCONTROLLER PORT EXPANDER

29 of 39

Figure 20. DS2 408 AS µC-OPERATED KEYBOARD SCANNER

VCC

10kΩ

1098765432

10U

DS2408

GND

VCC

POR Circuit

To More Switch Rows

(Up to 4 x 4, 3 x 5 or 2 x 6)

GND

VCC

RST

GND

DS1811

VCC

RSTZ

The DS1811 has an internal pull-up resistor of 5.5 k

Ω

BAT54

0.1U

100k

123456789

DS2408

GND

VCC

3IO4

SWITCHES OR PUSH-BUTTONS

Parasite

Power

VCC

GND

RSTZ

DS2408

Figure 21. DS2408 AS PARASITE-POWERED PUSH-BUTTON SENSOR

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Figure 22. DS2408 AS MULTIPURPOSE SENSOR/ACTUATOR

10kΩ

VCC

BSS-84

1N4004

47U

VCC

OPTOISO

1kΩ

470Ω

VCC

LED

DS2408

GND

VCC

4mA

8mA

VCC

GND

RSTZ

SWITCHES OR PUSHBUTTONS

ISOLATED OUTPUT

DRY CONTACT

LED INDICATOR

VCC

DS2408

31 of 39

Command-Speci fic 1-Wire Communication Protocol—Legend

SYMBOL DESCRIPTION

RST 1-Wire Reset Pulse generated by m aster .

PD 1-Wire Presence Pulse generat ed by sl ave.

Select Command and data to sati sfy the ROM function protocol.

RPR Command "Read PIO Register s".

CAR Command "Channel -Access Read". CAW Command "Channel-Access Write". WCS Command "Write Conditional Search Register".

RAL Command "Reset Activity Latches".

TA Target Address TA1, TA2.

<data> Transfer of an undetermined amount of data.

CRC16\ Transfer of an inverted CRC16.

FF loop Indef inite loop where the master reads FF bytes. AA loop Indefinit e loop where the m aster r eads AA by tes.

<32 samples>,

CRC16\ loop

<new state>, <new

state\>

AAh, <read back>

<new state>,

Indefinit e loop where the m aster r eads 32 PI O sam ples followed by an inverted CRC16. Transfer of 2 bytes, where the second byte is the bit-inverse o f the first byte . Th e first

byte will be taken as the new PIO state. Transfer of 2 bytes, where the first byte is a constant (AAh) and the second byt e is the

current PIO stat e. Transfer of 2 bytes, where the second byte is NOT the bit-inverse of the first by te.

DS2408

Command-Speci fic 1-Wire Communication Protocol—Color Codes

Master to slave Slave to master

Read PIO Registers (Success)

RST PD Select RPR TA <data> CRC16\ FF loop

Read PIO Registers (Fail Address)

RST PD Select RPR TA FF loop

Channel-Access Read (Cannot Fail)

RST PD Select CAR <32 samples>, CRC16\ loop

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Channel-Access Write (Success)

STRB

Step 1 TX

(Reset)

Reset pulse

Loop

RST PD Select CAW <new state>, <new state\> AAh, <read back>

Channel-Access Write (Fail New State)

RST PD Select CAW <new state>, <invalid> FF loop

Write Conditional Search Register (Success)

RST PD Select WCS TA <data> FF l oop

Write Conditional Search Register (Fail Address)

RST PD Select WCS TA FF l oop

Reset Activity Latches (Cannot Fail)

DS2408

RST PD Select RAL AA loop

COMMUNICATION EXAMPLES

The examples in this sect ion demonst rat e the use of ROM and contr o l functions in t ypical situat ions. T he first two examples are related to Figure 17. They show how to write to the PIO with readback for verification or for receiving an immediate response (example 1) and how to read from the PIO in an endless loop (example 2). The third example assumes a net work of multiple DS2408s where each of the devices is connected to 8 pushbuttons, as in Figure 21.

Example 1

Task: Write to t he PIO with readback for verification or for rece iving an immediate response. This task is broken into the following steps:

1) Configure RSTZ as

2) Verify configurat ion setting.

3) Write to the PIO and read back the respo nse.

Wit h only a sin gle DS2408 connected to the bus master, the co mmunication is as follows:

output.

33 of 39

MASTER MODE DATA (LSB FIR ST) COMMENTS

RX (Presence) Presence pulse

TX CCh Issue Skip ROM command TX CCh Issue Write Conditional Search Register

command TX 8Dh TA1, target address = 8Dh TX 00h TA2, target address = 008Dh TX 04h Write byte to Control/ S tatus Register

MASTER MODE

DATA (LSB FIR ST)

COMMENTS

TX (Reset) Reset pulse

(Presence)

Presence pulse

Step 2 TX

CCh

Issue Skip ROM command

8Dh

TA1, target address = 8Dh

00h

TA2, target address = 008Dh

(Reset)

Reset pulse

(Presence)

Presence pulse

5Ah

Issue Channel-access Write command

Write byte to PIO

(Reset)

Reset pulse

(Presence)

Presence pulse

STRB

TX F0h Issue Read PIO Register s command

RX 84h Read Control/Stat us Regi ster and verify

Step 3 TX CCh Issue Skip ROM command

TX <inverted PIO output byte> Write inverted byte to PIO

(—) (—) DS2408 updates PIO status if t r ansmission

was OK

RX AAh Read for verific ation (AAh = success)

(—) (—) DS2408 samples PIO pin status

RX <PIO pin status byte> Read PIO pin status

TX <PIO output byt e> Write byte to PIO (next byte) TX <inverted PIO output byte> Write inverted byte to PIO (next byte)

RX AAh Read for verific ation (AAh = success) RX <PIO pin status byte> Read PIO pin status

(—) (—)

Repeat the previ ous 4 steps with more PIO

output data as needed in t he application.

DS2408

When using this communication example to send data to a remote microcontroller, as in Figure 17, sync hronization between t he master and the remote microcontroller can be maintained by transmitting data packets that begin with a length byte and end with a CRC16. See Application Note 114, section "UNIVERSAL DATA PACKET" for details.

Example 2

Task: Read from the PIO in an endless loop. This task is broken into the following steps:

1) Configure RSTZ as

2) Verify configurat ion setting.

3) Read from the PIO.

With only a single DS2408 co nnected to the bus master, the communicat ion is as follows:

MASTER MODE DATA (LSB FIRS T) COMMENTS

Step 1 TX (Reset) Reset pulse

RX (Presence) Presence pulse

TX CCh Issue Skip ROM command TX CCh TX 8Dh TA1, target address = 8Dh

TX 00h TA2, target address = 008Dh

34 of 39

output.

Issue Write Conditional Search Register

command

MASTER MODE

DATA (LSB FIRS T)

COMMENTS

TX 04h Write byte to Control/ S tatus Register

(Reset)

Reset pulse

(Presence)

Presence pulse

F0h

Issue Read PIO Registers command

8Dh

TA1, target address = 8Dh

84h

Read Control/Status Register and verify

(Reset)

Reset pulse

Step 3 TX

CCh

Issue Skip ROM command

F5h

Issue Channel-access Read command

(—)

DS2408 samples PIO pi n status

status

<2 bytes CRC16>

Read CRC16

Step 2 TX CCh Issue Skip ROM command

TX 00h TA2, target address = 008Dh

RX (Presence) Presence pulse

RX <PIO pin status byte> Read PIO pin status

Repeat the previ ous 2 steps unti l the master

(—) (—)

has received a total of 32 bytes of PIO pin

DS2408

(—) (—)

TX (Reset) Reset pulse

RX (Presence) Presence pulse

PIO pin status and CRC loop can be

continued as long as the application requires.

When using this communication example to read data from a remote microcontroller, as in Figure 17, synchronization between the remote microcontroller and the master can be maintained by transmitting data packets that begin with a length byte and end with a CRC16. See Application Note 114, sectio n "UNIVERSAL DATA PACKET" for details.

Example 3

Task: Detect the specific DS24 08 w here the button was pressed and identify the pin to which the pushbutton is connected. This task is bro ken into the following steps:

1) Configu re the conditional s earch a nd verify c onfig uration s etting.

2) Sw itch off al l channe l output tra nsisto rs.

3) Clear the activity latches.

4) Search until a pushbutt on is pressed.

5) Identify device and pushbutton; reset activity latches.

The device has to respond to t he co nditional search if the activity latch of at least one o f the 8 channels is set. This requires the following setup data for the condit ional searc h reg ist er s:

Channel Selection Mask, select all channels ⇒ FFh Channel Polarity Selectio n , select logic 1 for all channels ⇒ FFh

35 of 39

Control/Status register,

MASTER MODE

DATA (LSB FIR ST)

COMMENTS

(Presence)

Presence pulse

55h

Issue Match ROM command

transistors if transmission was OK

FFh

Read PIO pin status and verif y ; FFh = OK

(Reset)

Reset pulse

Step 3 TX

A5h

Issue Resume command

Issue Reset Activity Latch command

(Presence)

Presence pulse

Source is Activity Latch ⇒ PLS = 1 Term is OR ⇒ C T = 0 RST Z = inactive (input) ⇒ ROS = 0 Clear Power-On Reset Latch ⇒ PORL = 0 The resulting setup data for the Control/Status Register is 01h.

For each DS2408 in the applicat ion, perform the following initialization:

Step 1 TX (Reset) Reset pulse

TX <8 byte ROM ID> Send ROM ID of the device to be accessed TX CCh TX 8Bh T A 1, target address = 8Bh

TX 00h TA2, target address = 008Bh TX FFh Write Channel Sel ection Mask TX FFh Write Channel Pol ari ty S elec tion TX 01h Write Control/Status Register TX (Reset) Reset pulse

RX (Presence) Presence pulse

TX A5h I ssue Resum e c om m and TX F0h Issue Read PIO Register s command TX 8Bh T A 1, target address = 8Bh TX 00h TA2, target address = 008Bh

RX <FFh, FFh, 81h> Read Registers and v erify

TX (Reset) Reset pulse

RX (Presence) Presence pulse

Step 2 TX A5h Issue Resume com m and

TX 5Ah I ssue Channel-access Write command TX FFh Write byte to PIO TX 00h Write inverted byte to PIO

(—) (—)

Issue Write Conditional Search Register

command

DS2408 switches off all channel output

DS2408

RX AAh Read for verific ation (AAh = success)

RX (Presence) Presence pulse

RX AAh Read for verific ation (AAh = success)

TX (Reset) Reset pulse

36 of 39

After all DS2408s are init ialized, p er form the search process below as an endless loo p:

MASTER MODE

DATA (LSB FIR ST)

COMMENTS

Step 4 TX (Reset) Reset pulse

RX (Presence) Presence pulse

TX ECh I ssue Conditional Searc h ROM command

Read 2 bits; if both bits are 1, no push button

has been pressed; in this case retur n to Step

RX <2 bits>

Step 5 TX <1 bits>

RX <2 bits>

TX <1 bits>

(—) (—)

TX F0h Issue Read PIO Register s command TX 88h TA1, target address = 88h TX 00h TA2, target address = 0000h

RX <8 data bytes>

RX <2 bytes CRC16>

TX (Reset) Reset pulse

RX (Presence) Presence pulse

TX A5h I ssue Resum e c om m and TX C3 Issue Reset Activ ity Latch command

RX AAh Read for verific ation (AAh = success)

(—) (—)

4. If the bit patter n is 01 or 10 or 00, a push

button has been pressed; in this case

continue with Step 5.

Identify and selec t t he LS bit of t he ROM ID

of the DS2408 that has responded to the

Conditional S ear c h.

Read 2 bits; this rel ates to t he next bit of the

ROM ID of the participating devic e( s).

Identify and selec t t he nex t bit of t he ROM ID

of the DS2408 that has responded to the

Conditional S ear c h.

Repeat the previ ous 2 steps unti l one dev ice

has been identified and ac c essed. (see Note

Read register page; t he data in the Activity

Latch State Register tells which button has

been pressed.

Read CRC16 and verify correct data

transmission.

Now, as the device and push button ar e

identified and the Activity Latch is cleared,

continue at Step 4.

Note 1: For a full descript ion of the Search Algorithm see Application Note 187.

DS2408

37 of 39

DS2408

STRB

APPLICATIONS INF OR MATION

Power-up timing

The DS2408 is sensitive to the power-on slew rate and can inadvertently power up with a test mode feature enabled. When t his o ccur s, t he P0 port do es not respond to the Channel Access Write command.

For most reliable operation, it is recommended to disable the test mode after every power-on reset using the Disable Test Mode sequence shown below. The 64-bit ROM code must be tr ansmitted in the same bit sequence as with the Match ROM command, i.e., least significant bit first. This precaution is recommended in paras ite power mode (VCC pin connected to GND) as well as with VCC power.

Disable Test Mode

RST PD 96h <64-bit DS2408 ROM Code> 3Ch RST PD

Power-up St at e of P0 to P7

When the DS2408 powers up, the state of the I/O pins P0 to P7 is indeter minate. This behavior may not be acceptable for some applications. To e nsure that P0 t o P7 power up in the "off" state, it is ne ces sary to have a suitable power-on-reset circuit, such as the DS1811 , or a super visor I C connected to the RSTZ pin.

RS TZ Pin

When not configured as

output, the RSTZ pin is to be connected to VCC, directly or through a

resis tor. A local VCC supply can be created by tak ing energy from the 1-Wire line, as s hown in Figu re 21.

PACKAGE INFORMATION

For the latest packag e outline informat ion and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates Ro HS status only. Package drawings ma y show a different suffix charact er, but the drawing pertains to the package regardless of RoH S status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

16 SO (150 mils) S16+5

21-0041 90-0097

38 of 39

MAXIM DS2408 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual