MAXIM DS2408 Technical data
PART
TEMP RANGE
PIN-PACKAGE
DS2408S+
-40°C to +85°C
16 SO
DS2408S+T&R
-40°C to +85°C
16 SO
19-5702; 12/10
www.maxim-ic.com
FEATURES
Eight Channels of Programmable I/O with
Open-Drain Outputs
On-Resistance of PIO Pulldown Transistor
100Ω (max); Off-Resistance 10MΩ (typ)
Individual Activity Latches Capture
Asynchronous State Changes at PIO Inputs for
Interrogation by the Bus Master
Data-Strobe Output to Synchronize PIO Logic
States to External Read/Write Circuitry
Built-in Multidrop Controller Ensures
Compatibility with Other Dallas Semiconductor
®
1-Wire
Net Products
Supports 1-Wire Conditional Search Command
with Response Controlled by Programmable
PIO Conditions
Unique Factory-Lasered 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Communicates to Host with a Single Digital
Signal at 15.3kbps or 100kbps using 1-Wire
Protocol
Operating Range: 2.8V to 5.25V, -40°C to
+85°C
DS2408
1-Wire 8-Channel Addressable Switch
PIN CONFIGURATION
150-mil SO
ORDERING INFORMATION
+Denotes a lead(Pb) -free package.
T&R = Tape and reel.
DESCRIPTION
The DS2408 is an 8-channel, programmable I/O 1-Wire chip. PIO outputs are configured as open-drain and
provide an on resistance of 100Ω max. A robust PIO channel-access communication protocol ensures that PIO
output-sett ing c hang es occu r err or-free. A data-vali d st robe ou tput can be used to latch PIO logic state s into
external circuitry such as a D/A converter (DAC) or microcontroller data bus.
DS2408 operation is controlled over the single-conductor 1-Wire bus. Device communication follows the
standard Dallas Semiconductor 1-Wire protocol. Each DS2408 has its own unalterable and unique 64-bit
ROM registration number that is factory lasered into the chip. The registration number guarantees unique
identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS2408
devices can reside on a comm on 1-Wire bus and can operate independently of each other. The DS2408 also
supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity; the
conditions to cause participation in the conditional search are programmable. The DS2408 has an optional V
supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire
bus. When an externa l supply is prese nt, PIO states are maintained in the abse nce of the 1-Wire bus power
source. The RSTZ signal is configurable to serve as either a hard-wired reset for the PIO output or as a strobe
for external circuitry to indicate that a PIO write or PIO read has completed.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
1 of 39
CC
DS2408
P0 to P7, RSTZ, I/O Voltage to GND
-0.5V, +6V
P0 to P7, RSTZ, I/O combined sink current
20mA
Operating Temperat ur e Range
-40°C to +85°C
Junction Temperature
+150°C
Storage Temperatu r e Range
-55°C to +125°C
Lead temperatur e (so lder ing 10s)
+300°C
Soldering Temperature (reflow)
+260°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1-Wire Pullup
Standard speed
2.8
5.25
Overdrive speed
3.3
5.25
Standby Supply
Current
VCC at V
I/O pin at 0.3V
I/O Pin General Data
1-Wire Pullup
Input Capacitance
CIO
(No tes 3, 4)
1200
pF
I/O pin at V
VCC at 0V
High-to-Low
Switching Threshold
Input-Low Voltag e
V
IL
(No tes 1, 7)
0.30
V
Low-to-High
Switching Threshold
Switching Hyster es is
V
HY
(No tes 9, 4)
0.16
0.73
V
Output-Low Voltage
at 4mA
Standard speed, R
=
2.2kΩ
Overdrive speed, R
=
2.2kΩ
Overdrive speed, D irectly
Rising-Edge Hold-off
Standard speed
0.5 5
Overdrive speed
0.5 2
Timeslot Dur ation
Standard speed
65
Overdrive speed
10
ABSOLUTE MAXIMUM RATINGS*
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
ELECTRICAL CHARACTE RISTICS
(V
= 0V or ≥ V
CC
, TA = -40°C or +85°C.)
PUP
Voltage
V
I
Resistance
R
Input L oad C urr ent I
V
V
V
Recovery Time
(Note 1)
t
PUP
CCS
PUP
L
TL
TH
OL
REC
PUP,
(No tes 1, 2)
PUP,
(No tes 4, 5, 6) 0.5
(No tes 4, 5, 8) 0.8
(Note 10)
PUP
PUP
5
2
V
1 µA
2.2
kΩ
1 µA
3.2 V
3.4 V
0.4 V
µs
t
Time (Notes 11, 4)
(No tes 1, 12)
2 of 39
REH
t
SLOT
prior to reset pulse; R
= 2.2kΩ
PUP
5
µs
µs
DS2408
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I/O Pin, 1-Wire Reset, Presence-Detect Cycle
Standard speed, V
>
4.5V
Standard speed
660
720
Overdrive speed
53 80
Presence-Detect High
Time (No te 12 )
Standard speed
15 60
Overdrive speed
2 7
Standard speed, V
>
Standard speed
1 8
Overdrive speed
1
Standard speed, V
>
4.5V
Standard speed
60
280
Overdrive speed
7 27
Standard speed, V
>
4.5V
Standard speed
68 75
Overdrive speed
8 9
I/O Pin, 1-Wire Write
Write-0 Lo w Time
(Notes 1, 12, 14)
Standard speed
60
120
Overdrive speed
8 13
Write-1 Lo w Time
Standard speed
5 15
Overdrive speed
1 1.8
Writ e Sample Time
Standard speed
15 60
I/O Pin, 1-Wire Read
Read-Low Time
Standard speed
5
15 - δ
Overdrive speed
1
Read-0 Low Time
Standard speed
15 60
Read-Sa mple Time
Standard speed
15
Overdrive speed
tRL + δ
1.8
P0 to P7, RSTZ Pin
Input-Low Voltag e
V
IL
(No tes 1, 7)
0.30
V
VX = max (V
)
Output-Low Voltage
Leakage Current
I
LP
5.25V at the pin
1
µA
Output Fall Time
t
FPIO
(No tes 4, 16)
100
ns
Minimum-Sensed
PIO Pulse
1
Reset-Low Time
(No tes 1, 12)
Presence-Detect Fa ll
Time (No te 13 )
Presence-Detect Low
Time (No te 12 )
Presence-Detect
Sa mp le Time (Note 1)
t
RSTL
t
PDH
t
FPD
t
PDL
t
MSP
t
W0L
4.5V
PUP
PUP
PUP
PUP
480
1
60
65
720
µs
µs
5
µs
240
µs
75
µs
µs
(No tes 1, 12, 14)
(Slave Sampling)
t
t
(Note 12)
(Notes 1, 15)
(Data From Slave)
t
(Note 12)
(No tes 1, 12, 15)
t
Input-High Volt ag e V
at 4mA
V
W1L
SLS
t
RL
SPD
MSR
IH
OL
Overdrive speed 1.8
Overdrive speed 1.8
tRL + δ
PUP,VCC
(Note 1)
VX - 0.8
(Note 10)
8
1.8 - δ
8
5.25 V
0.4 V
µs
µs
µs
µs
µs
t
PWMIN
3 of 39
(No tes 4, 17)
5 µs
DS2408
Note 1:
System Requirement
Note 2:
Max imum a llowable pullup re sistanc e is a function of the number o f 1-Wire devices in the
Note 3:
If a 2.2kΩ resistor is used to pull up the data line to V
, 5µs after po wer has been applied,
the parasite capac itance does not affect normal communications.
Note 4:
Guaranteed by design—not pro duction tested.
Note 5:
VTL and VTH are functions of the internal supply v oltage, which in parasitic po w er mode, is a
are valid at V
PUP
= 5.25V. In any case, VTL < VTH < V
PUP
.
Note 6:
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 7:
The voltage on I/O needs to be less or equal to V
whenever t he master d r ives t he line
low.
Note 8:
Voltage above which, dur ing a r ising edge on I/ O, a logic '1' is detected.
Note 9:
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to dr op by VHY to be
detected as logic '0'.
Note 10:
The I-V characterist ic is linear for vo ltages less than 1V.
Note 11:
The earliest reco gnition of a negative edge is possible at t
after VTH has been reached
Note 12:
Highlighted numbers are NOT in compliance with the published 1-Wire standards. S ee
comparis on t able below.
Note 13:
Interval during the negative edge on I/O at the beginning of a presence detect pu lse bet ween
Note 14:
ε in Figure 14 represents the time required for the pu llup circuitry to pull the voltage on I/O
W1LMAX
W0LMAX
Note 15:
the master to pull the lin e low is t
RLMAX
+ tF.
Note 16:
Interval during the device-generated negative edge on any PIO p in or the RSTZ pin between
V
PUP
. PIO pullup resistor = 2.2kΩ.
Note 17:
Width of the narrowest pu lse which tr ips the activity latch (for any PIO pin) or causes a reset
Note 18:
Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requir eme nt fo r curre nt balance among different pins.
syste m and 1-Wire r ecovery times. The specified value here applies to syste ms with only one
devic e and wit h the minimum 1-Wire recovery times. For more heavily loaded s yst ems, an
active pullup such as that found in the DS2480B may be required.
PUP
function of V
and the 1-Wire recovery times. The VTH and VTL max imum speci fi cations
PUP
ILMAX
REH
before.
the time at which the voltage is 90% of V
.
V
PUP
and the time at which the voltage is 10% of
PUP
up from VIL to VTH. The actual maximum durat ion for t he master to pu ll the line low is
t
+ tF - ε and t
+ tF - ε respectively.
δ in Figure 14 represents the time required for the pu llup circu itry to pull the voltage on I/O
up from VIL to the input high thr eshold of the bus master . The actual maximum duration for
the time at which the voltage is 90% of V
(for the RSTZ pin). For a pulse duration tPW: If tPW < t
t
PWMIN(min)
< tPW < t
PWMIN(max)
, the pulse may or may not be reject ed. If tPW > t
and the time at which the voltage is 10% of
PUP
PWMIN(min)
, the pulse will be reject ed. If
pulse will be recognized and latched.
4 of 39
PWMIN(max)
the
STANDARD VALUES
DS2408 VALUES
STANDARD
SPEED
OVERDRIVE
SPEED
STANDARD
SPEED
OVERDRIVE
SPEED
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
SLOT
(incl. t
REC)
61µs
(undef.)
7µs
(undef.)
65µs 1)
(undef.)
10µs
(undef.)
t
RSTL
480µs
(undef.)
48µs
80µs
660µs
720µs
53µs
80µs
t
PDH
15µs
60µs
2µs
6µs
15µs
60µs
2µs
7µs
t
PDL
60µs
240µs
8µs
24µs
60µs
280µs
7µs
27µs
t
W0L
60µs
120µs
6µs
16µs
60µs
120µs
8µs
13µs
t
SLS
, t
SPD
15µs
60µs
2µs
6µs
15µs
60µs
1.8µs
8µs
PIN
NAME
DESCRIPTION
1
N.C.
Not Connected
supervisor IC to the RSTZ pin.
Optional Power Supply Input. Range 2.8V to 5.25V; must be tied to GND
if not used.
4
I/O
1-Wire Interface. Open-dra in, requires external pullup resistor.
5
GND
Ground
6
N.C.
Not Connected
7
P7
I/O Pin of Channel 7. Same charact er ist ics as P0.
8
P6
I/O Pin of Channel 6. Same charact er ist ics as P0.
9
P5
I/O Pin of Channe l 5. S ame chara cteristics as P0.
RST
STRB
RST
STRB
RST
11
P4
I/O pin of channel 4; same charact er ist ics as P0
12
P3
I/O pin of channel 3; same charact er ist ics as P0
13
P2
I/O pin of channel 2; same charact er ist ics as P0
14
P1
I/O pin of channel 1; same charact er ist ics as P0
15
N.C.
Not connected
16
N.C.
Not connected
PARAMETER
NAME
1)
Intentional ch ange , lo nger recovery-t ime require ment due to mod ified 1 -Wire front end.
PIN DESCRIPTION
I/O Pin of Channel 0. Logic input/open-drain output wit h 100Ω maximum
on-resistance; 0V to 5.25V operating range. Power-on default is
2 P0
indeterminate. If it is a pplication-critical for the o utp uts to powe r up in the
"off" state, the user should attach an appropriate pow er -on-reset circuit or
DS2408
3 VCC
10 RSTZ
SW configurable PIO reset input (
(
). When configured as
) or open-drain strobe output
, a LOW input sets all PIO outputs to
the "off" state by setting all bits in the PIO Output Latch State Register.
When configured as
, an output strobe will occur after a P I O write
(see Channel-Access Write command) or after a PIO Read (see Channe lAccess Read command). The power-on default function of this pin is
.
5 of 39
DS2408
V
CC
64-BIT
LASERED ROM
CRC16
GENERATOR
REGISTER
PAGE
REGISTER
FUNCTION
CONTROL
1-WIRE
FUNCTION
CONTROL
PORT
FUNCTION
CONTROL
I/O
GND
PARASITE POWER
INTERNAL V
CC
PORT
INTER-
FACE
RSTZ
P0
P1
P2
P3
P4
P5
P6
P7
APPLICATION
The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers,
remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network
interface o f a microco ntroller. Typical applicat ion circuits and co mmunicat ion examples are found later
in this data sheet (Figures 17 to 22).
OVERVIEW
Figure 1 shows the relationships between the major function blocks of the DS2408. The device has two
main d at a co mponent s: 1) 64-bit lasered ROM, and 2) 64-bit register page o f contro l and st atu s register s.
Figure 2 shows t he hierar chical structure of the 1-Wire protocol. The bus master must first p r ovide one of
the eight ROM funct ion co mmands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional
Search ROM, 5) Skip ROM, 6) Overdrive-Skip ROM, 7) Overdrive-Match ROM, or 8) Resume. Upon
completion of an Overdrive ROM command byte executed at standard speed, the device will enter
overdrive mode, where a ll subseque nt co mmunicat ion occurs at a higher speed. T he proto col require d for
these ROM function co mmands is described in Figure 12. After a ROM funct ion command is successfully executed, the control functions become acc essible and t he master may provide any o ne o f the fiv e
available commands. The protocol for t hese control commands is described in Figure 8. All data is read
and written least significant bit first.
Figure 1. DS2408 BLOCK DIAGRAM
6 of 39
Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL
1-Wire Net
Other
Devices
Bus
Master
Command
Level:
1-Wire ROM Function
Commands
DS2408-Specific
Control Function
Commands
DS2408
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Conditional Search
ROM
Overdrive Match
Overdrive Skip
Resume
Read PIO Registers
Channel Access Read
Channel Access Write
Write Conditional
Search Register
Reset Activity Latches
Data Field
Affected:
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
64-BIT ROM, RC-FLAG
RC-FLAG
64-BIT ROM, RC-FLAG, Port Status,
Cond. Search Settings,
64-BIT ROM, RC-FLAG, OD-Flag
RC-FLAG, OD-Flag
RC-FLAG
PIO Registers
Port Input Latches
Port Output Latches
Conditional Search Register
Activity Latches
Cmd
.
Codes:
33h
55h
F0h
CCh
ECh
69h
3Ch
A5h
F0h
F5h
5Ah
CCh
C3h
MSB
LSB
MSB LSB
MSB LSB
MSB LSB
DS2408
PARASITE POWER
The DS2408 can der ive its power ent irely from the 1-Wire bu s b y st or ing e n er g y o n a n int e r nal ca p a c it o r
during periods of time whe n the signa l line is high. During low times the devic e continues to oper at e from
this “parasite” po wer sour ce until the 1-Wire bus retu rns high to replenish t he parasite (capac ito r) supp ly.
If power is available, the VCC pin sho uld be connec ted t o the e xternal voltage sup ply.
Figure 3. 64-BIT LASERED ROM
8-BIT
CRC CODE
48-BIT SERIAL NUMBER
64-BIT LASERED ROM
Each DS2408 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a uniqu e serial number. The last eight bits are a CRC of the first 56 bits. See F ig u r e 3
for details. The 1-Wire CRC is ge nerated using a polynom ial generator consist ing of a shift register and
XOR g at es as s how n in F igure 4. T he po lyno mia l is X
Dallas 1-Wire Cyc lic Re dund ancy Che c k is ava ilab le in Application Note 27.
7 of 39
8-BIT FAMILY
CODE (29h)
8
5
4
+ X
+ X
+ 1 . A dd it io na l in for mat io n a bo ut t he
DS2408
X0X1X2X3X4X5X6X7X
8
POLYNOMIAL =
X8 + X5 + X4 + 1
1
st
STAGE
2
nd
STAGE
3
rd
STAGE
4
th
STAGE
6
th
STAGE
5
th
STAGE
7
th
STAGE
8
th
STAGE
INPUT DATA
The shift regist er bits are initialized to 0. Then, start ing with the least significant bit of the family co de,
one bit at a t ime is shifted in. After the eighth bit of the family code has been ent ered, the se ria l number is
entered. After the ser ial number has been entered, the shift reg ister contains the CRC value. Shift ing in
the eight bits of CRC returns the shift register to all 0s.
Figure 4. 1 -Wire CRC GENERATOR
REGISTER ACCESS
The registers needed t o operate the DS2408 are organized as a Reg ister Page, as shown in Figure 5. All
registers are volatile, i. e., they lose their state when the device is powered down. PIO, Conditional
Search, and Contro l/Statu s registers are read /written using t he device level Read PIO Registers and Write
Conditional Search Register commands described in subsequent sections and Figure 8 of this document.
Figure 5. DS2408 REGISTER ADDRESS MAP
ADDRESS RANGE ACCESS TYPE DESCRIPTION
0000h to 0087h R Undefined Data
0088h R PIO Logic State
0089h R PIO Output Latch State Register
008Ah R PIO Activity Lat c h State Register
008Bh R/W Conditional S ear c h Channel S election Mask
008Ch R/W Conditional Search Channel Polarity S elec tion
008Dh R/W Control/Status Register
008Eh to 008Fh R These Bytes Always Read FFh
8 of 39
DS2408
STRB
STRB
STRB
STRB
STRB
STRB
008Ah
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
RST
PIO Logic-State Regis ter
The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading t his register does not generate a signal at t he RSTZ pin, even if it is configured as
. See the Channel-Access commands desc ription for deta ils on
.
PIO Logic State Register Bitmap
ADDR b7 b6 b5 b4 b3 b2 b1 b0
0088h P7 P6 P5 P4 P3 P2 P1 P0
This register is read-only. Each bit is as sociated with the p in of the respect ive PIO c han nel a s sho wn in
Figure 6. The data in this register is sampled at the last (most significant ) bit of the byte t hat proceeds
reading the first (least significant ) bit of this reg ister. See the Read PIO Registers command descript ion
for det a ils .
PIO Output Latch State Register
The data in this reg ister represent s the latest data writt en to the PIO thro ugh the Channel-access Write
command. This register is read using t he Read PIO Registers co mmand. Reading this register does no t
generate a signa l at the RSTZ p in, even if it is co nfigured as
description for det ails on
. This register is not affected if the device reinitializes itself after an ESD
. See the Channel-access commands
hit.
PIO Output Latch State Register Bitmap
ADDR b7 b6 b5 b4 b3 b2 b1 b0
0089h PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
This register is read-o nly. Each b it is assoc iated with the output latch of the respect ive PIO channel as
shown in Figu re 6.
The f lip-flops of t his register will power up in a random stat e. If the chip has to power up w ith all PIO
channels off, a LOW pu lse must be generat ed on the RSTZ pin, e.g., by means o f an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure t hat
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
PIO Activity Latch State Register
The data in this regist er repr esent s the curr ent st ate of the PIO activity latches. This reg ister is read using
the Read PIO Regist ers co mmand. Read ing th is reg ister does not generate a signa l at the RSTZ p in, eve n
if it is configured as
. See the Channel-access commands description for details on
.
PIO Activity Latch State Register Bitmap
ADDR b7 b6 b5 b4 b3 b2 b1 b0
This register is read-only. Each b it is associated w ith the activit y latch of the respect ive PIO channel as
show n in Figu re 6. This reg ister is cleared to 00h by a power-o n reset, by a low pulse on the RST Z pin
(only if RSTZ is configured as
input), or by successful execution of the Reset Activity Latches
command.
9 of 39
Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM
PIO
OUTPUT
LATCH
PIO ACTI
VITY
LATCH
EDGE
DETECTOR
PORT
FUNCTION
CONTROL
TO ACTIVITY LATCH
STATE REGISTER
TO PIO LOGIC
STATE REGISTER
TO PIO
OUTPUT LATCH
STATE REG.
R
Q
D
D
Q
S
Q
Q
"1"
CLR ACT LATCH
ROS
STRB
CHANNEL
I/O PIN
RSTZ
PIN
DATA
CLOCK
POWER ON
RESET
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
DS2408
Conditional Search Channel Selection Mask Register
The data in this register controls whether a PIO channel qualifies for participation in the conditional
search command. To include one or more o f the PIO channels, the bits in this register that correspond to
those channe ls n eed to be set t o 1. This reg ist er can o nl y b e writt en t hrough the Write Conditional S ear ch
Reg is ters command .
Conditional Search Channel Selection Mask Register Bitmap
008Bh SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0
This register is read/write. Each bit is assoc iated with the respect ive PIO channel as s hown in Figure 7.
This register is cleared to 00h by a power-on reset
10 of 39
DS2408
AL7
P7
PLS
SP0
SM0
CT
SM7
SP7
AL0
P0
CSR
INPUT FROM
CHANNELS 1 TO 6
(NOT SHOWN)
CHANNEL 0
CHANNEL 7
Conditional Search Channel Polarity Selection Register
The data in t his register speci fies the po larity of each select ed PIO channel for the device to respond to
the conditional searc h co mmand. Within a PIO channel, t he data so ur ce may be either the channel's input
signal (pin) or t he channel's activity latch, as spec ified by the PLS bit in t he Contr ol/St atus regist er at address 008Dh. This regist er can o nly be wr itten throu gh t he Write Co nd it iona l Searc h Regist er s command.
Conditional Search Channel Polarity Selection Register Bitmap
ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Ch SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
This register is read/write. Each bit is associated with t he respective PIO channel as s hown in Fig ure 7.
This register is cleared to 00h by a power-on reset.
Figure 7. Conditional Search Logic
11 of 39
DS2408
BIT DESCRIPTION
BIT(S)
DEFINITION
1: bitwise AND
RST
STRB
RST
STRB
CC
Control/Status Register
The data in this reg ister reports st atus information, d etermines the function o f the RSTZ pin and fur ther
configures the de vice for condit ional search. This re gist er c an o nly be wr itt en t hrou gh t he Wr ite C ond itional Search Registers command.
Control/Status Register Bitmap
ADDR b7 b6 b5 b4 b3 b2 b1 b0
008Dh VCCP 0 0 0 PORL ROS CT PLS
This register is read/wr ite. Withou t VCC supp ly, this register reads 08 h after a po wer-o n r eset . The fu nctional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function;
they wil l always r ead 0 and cannot be set to 1.
Control/Status Register Details
PLS: Pin or Activity
Latch Select
CT: Conditional Search
Logical Term
ROS: RSTZ Pin Mode
Control
PORL: Power-On Reset
Latch
VCCP: VCC Power
Status (Read-Only)
b0 Selects either the PIO pins or the PIO activity latches as input for the
conditional search.
0: pin selected (default)
1: activity latch selected
b1 Specifies whether the data of two or more channels needs to be OR’ed
or AND’ed to meet the qualifyi ng c ondition for the device to respond to a
conditional search. If only a single channel is selected in the channel
selection mask (008B h) this bit is a don't care.
0: bitwise OR (default)
b2
b3 Specifies whether the dev ice has performed a power-on reset. This bi t
b7 For VCC powered operation the VCC pin needs to be tied to a voltage
Configures RSTZ as eit her
0: configured as
1: configured as
can only be cleared to 0 under soft ware cont r ol. As long as this bit is 1
the device will always respond to a conditional search.
source ≥ V
0: V
1: V
.
PUP
pin is grounded
CC
-powered operation
input or
input (default)
output
output
The interaction o f the various s ignals that det ermine whether t he device respo nds to a cond itional search
is illu st rat ed in Figure 7. T he selection mask SM s elects t he part icipating channe ls. The po larity select ion
SP deter mines for each channe l whether the c hannel signa l needs to be 1 or 0 to qualify. T he PLS bit
determines whether all channel signals are t aken from the act ivity latches or I/O p ins. The signals of all
channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or
OR’ed result as the condit ional searc h response signal CSR.
Note on CT bit:
OR The qualifying condition is met if the input (pin state or activity latch) for one o r more se lected
channels matches the corr espond ing polarity.
AND For the qua l ifyin g co ndition to be met, the input (pin sta te or activity latch) for every selected
channel must match the co rresponding pola rity.
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