MAXIM DS2406 User Manual

www.maxim-ic.com

DS2406

Dual Addressable Switch

Plus 1Kb Memory

FEATURES

 Open drain PIO pins are controlled and their

logic level can be determined over 1-Wire®
bus for closed-loop control

 Replaces and is fully compatible with

DS2407 but no user-programmable power-on
settings and no Hidden Mode

 PIO channel A sink capability of 50mA at

0.4V with soft turn-on; channel B 8mA at

0.4V

 Maximum operating voltage of 13V at

PIO-A, 6.5V at PIO-B

 1024 bits user-programmable OTP EPROM
 User-programmable status memory to

control the device

 Multiple DS2406’s can be identified on a

common 1-Wire bus and be turned on or off
independently of other devices on the bus

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures error-free selection and absolute
identity because no two parts are alike

 On-chip CRC16 generator allows detection

of data transfer errors

 Built-in multidrop controller ensures

compatibility with other 1-Wire net products

 Reduces control, address, data, programming

and power to a single data pin

 Directly connects to a single port pin of a

microprocessor and communicates at up to

15.4 kbits/s

 Supports Conditional Search with user-

selectable condition

 V
 1-Wire communication operates over a wide

 Low cost TO-92 and 6-pin TSOC packages

bondout for optional external supply to

cc

the device (TSOC package only)

voltage range of 2.8V to 6.0V from -40°C to
+85°C

PIN ASSIGNMENT

TO-92

DALLAS

DS2406

1 2 3

1 2 3

6-PIN TSOC PACKAGE

1
2
3

TOP VIEW

SIDE VIEW

See Mech. Draw ing s

Section

BOTTOM VIEW

6
5
4

PIN DESCRIPTION

Pin 1 Ground Ground
Pin 2 Data Data
Pin 3 PIO-A PIO-A
Pin 4 --- V
Pin 5 --- NC
Pin 6 --- PIO-B

TO-92 TSOC

cc

ORDERING INFORMATION

DS2406+ TO-92 Package
DS2406+T&R TO-92 Package, Tape & Reel
DS2406P+ 6-pin TSOC Package
DS2406P+T&R TSOC Package, Tape & Reel

+ Indicates lead-free compliance.

1 of 32 033109

DS2406

ADDRESSABLE SWITCH DESCRIPTION

The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of
open drain transistors and to monitor the logic level at each transistor’s output via the 1-Wire bus for
closed loop control. Each DS2406 has its own 64-bit ROM registration number that is factory lasered into
the chip to provide a guaranteed unique identity for absolute traceability. The device’s 1024 bits of
EPROM can be used as electronic label to store information such as switch function, physical location,
and installation date. Communication with the DS2406 follows the standard Dallas Semiconductor
1-Wire protocol and can be accomplished with minimal hardware such as a single port pin of a
microcontroller. Multiple DS2406 devices can reside on a common 1-Wire network and be operated
independently of each other. Individual devices will respond to a Conditional Search command if they
qualify for certain user-specified conditions, which include the state of the output transistor, the static
logic level or a voltage transition at the transistor’s output.

DS2406 BLOCK DIAGRAM Figure 1

PARASITE POWER

INT VDD

V

CC

1-WIRE BUS

PIO-A
PIO-B

DATA

PROGRAM

VOLTAGE

DETECT

1-WIRE

FUNCTION

CONTROL

MEMORY
FUNCTION
CONTROL

CRC16

GENERATOR

DATA MEMORY

1024-BIT EPROM

(4 PAGES OF

32 BYTES EACH)

STATUS MEMORY

5 BYTES EPROM

1 BYTE SRAM

PIO

CONTROL

64-BIT

LASERED ROM

8-BIT

SCRATCHPAD

2 of 32

DS2406

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2406. The device has four major data components: 64-bit lasered ROM, 1024 bits of EPROM data
memory, status memory, and the PIO-control block. The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide one of the five ROM function commands: Read
ROM, Match ROM, Search ROM, Skip ROM, or Conditional Search ROM. The protocol required for
these ROM functions is described in Figure 13. After a ROM functions command is successfully
executed, the PIO-control and memory functions become accessible and the master may provide any one
of the six memory- and control function commands. The protocol for these functions is described in
Figure 7. All data is read and written least significant bit first.

HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL Figure 2

Bus

Master

Command
Level

1-Wire ROM Function

Commands (see Figure 13)

DS2406 specific

Memory Function

Commands (see Figure 7)

1-Wire Bus

DS2406

Available
Commands

Read ROM
Match ROM
Search ROM
Skip ROM
Conditional

Search ROM

Write Memory
Write Status
Read Memory
Read Status
Ext. Read Memory
Channel Access

Other
Devices

Data Fields
Affected

64-bit ROM
64-bit ROM
64-bit ROM
N/A

64-bit ROM,

Conditional Search Settings
at Status Memory Location 7,

Device/Channel Status

1024-bit EPROM
Status Memory
1024-bit EPROM

Status Memory
1024-bit EPROM
PIO Channels

3 of 32

DS2406

PARASITE POWER

The DS2406 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor
during periods of time when the signal line is high. During low times the device continues to operate off
of this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor)
supply. In applications where the device may be temporarily disconnected from the 1-Wire bus or where
the low-times of the 1-Wire bus may be very long the VCC pin may be connected to an external voltage
supply to maintain the device status.

When writing to the EPROM memory, the 1-Wire communication occurs at normal voltage levels and
then is pulsed momentarily to the programming voltage to cause the selected EPROM bits to be
programmed. The bus master must be able to provide 12V and 10mA to adequately program the EPROM
portions of the device. During programming, only EPROM-based devices are allowed to be present on
the 1-Wire bus.

64-BIT LASERED ROM

Each DS2406 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates

as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-

Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are initialized

to zero. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the
8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the
serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC
should return the shift register to all zeros. The 64-bit ROM and the 1-Wire Function Control section
allow the DS2406 to operate as a 1-Wire device and follow the protocol detailed in the section “1-Wire
Bus System”.

64-BIT LASERED ROM Figure 3

MSB LSB

8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (12h)

MSB LSB MSB LSB MSB LSB

1-WIRE CRC GENERATOR Figure 4

Polynomial = X8 + X5 + X4 + 1

0

X

1ST

STAGE

STAGE

1

X

2ND

2

X

3RD

STAGE

3

X

4TH

STAGE

4

X

5TH

STAGE

5

X

R

6TH

STAGE

S

7TH

STAGE

6

X

INPUT DATA

X

8TH

STAGE

7

8

X

4 of 32

DS2406

MEMORY MAP

The DS2406 has two memory sections, called data memory and status memory. The data memory
consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. The
address range of the device’s status memory is 8 bytes. The first seven bytes of status memory (addresses
0 to 6) are implemented as EPROM. The eighth byte (address 7) consists of static RAM. The complete
memory map is shown in Figure 5. The 8-bit scratchpad is an additional register that acts as a buffer when
writing the memory. Data is first written to the scratchpad and then verified by reading a 16-bit CRC
from the DS2406 that confirms proper receipt of the data and address. This process ensures data integrity
when programming the memory. If the buffer contents are correct, the bus master should transmit a
programming pulse (EPROM) or a dummy byte FFh (RAM) to transfer the data from the scratchpad to
the addressed memory location. The details for reading and programming the DS2406 are given in the
Memory Function Commands section.

DS2406 MEMORY MAP Figure 5

8-Bit Scratchpad

Page # Address Range Description

0 0000h to 001Fh 32-Byte final storage Data Memory

1K-Bit

EPROM

8 Bytes

Status

Memory

1 0020h to 003Fh 32-Byte final storage Data Memory

2 0040h to 005Fh 32-Byte final storage Data Memory

3 0060h to 007Fh 32-Byte final storage Data Memory

Valid Device

Settings

(SRAM)

00

Factory

Test Byte

Redirection

Bytes

Bitmap of

Used Pages

Write-Protect

Bits Data

Memory

DS2406 STATUS MEMORY MAP Figure 6

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 (EPROM) BM3 BM2 BM1 BM0 WP3 WP2 WP1 WP0
1 (EPROM) 1 1 1 1 1 1 Redir. 0 Redir. 0
2 (EPROM) 1 1 1 1 1 1 Redir. 1 Redir. 1
3 (EPROM) 1 1 1 1 1 1 Redir 2 Redir 2
4 (EPROM) 1 1 1 1 1 1 Redir 3 Redir 3
5 (EPROM) EPROM Factory Test byte
6 (EPROM) Don’t care, always reads 00
7 (SRAM) Supply

Indication

(read only)

PIO-B

Channel

Flip-flop

PIO-A

Channel

Flip-flop

CSS4

Channel

Select

CSS3

Channel

Select

CSS2

Source

Select

CSS1

Source

Select

CSS0

Polarity

5 of 32

DS2406

STATUS MEMORY

The Status Memory can be read or written to indicate various conditions to the software interrogating the
DS2406. These conditions include special features for the data memory, definition of the settings for the
Conditional Search as well as the channel flip-flops and the external power supply indication. How these
functions are assigned to the bits of the Status Memory is detailed in Figure 6.

The first 4 bits of the Status Memory (address 0, bits 0 to 3) contain the Write Protect Page bits which
inhibit programming of the corresponding page in the 1024-bit data memory area if the appropriate write
protection bit is programmed. Once a bit has been programmed in the Write Protect Page section of the
Status Memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still
be read. The remaining 4 bits of Status Memory location 0 are reserved for use by the 1-Wire File
Structure, indicating which memory pages are already in use. Originally, all of these bits are
unprogrammed, indicating that the device does not contain any data. As soon as data is written to any
page of the device under control of TMEX, the bit inside this bitmap corresponding to that page will be
programmed to 0, marking this page as used. These bits are application flags only and have no impact on
the internal logic of the DS2406.

The next four bytes of the Status Memory (addresses 1 to 4) contain the Page Address Redirection Bytes
which indicate if one or more of the pages of data in the 1024-bits EPROM memory section have been
invalidated by software and redirected to the page address contained in the appropriate redirection byte.
The hardware of the DS2406 makes no decisions based on the contents of the Page Address Redirection
Bytes. Since with EPROM technology bits can only be changed from a logical 1 to a logical 0 by
programming, it is not possible to simply rewrite a page if the data requires changing or updating. But
with space permitting, an entire page of data can be redirected to another page within the DS2406. Under
TMEX, a page is redirected by writing the one’s complement of the new page address into the Page
Address Redirection Byte that corresponds to the original (replaced) page. This architecture allows the
user’s software to make a “data patch” to the EPROM by indicating that a particular page or pages should
be replaced with those indicated in the Page Address Redirection Bytes.

Under TMEX, if a Page Address Redirection Byte has a FFh value, the data in the main memory that
corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value than FFh,
the data in the page corresponding to that redirection byte is invalid. According to the TMEX definitions,
the valid data will now be found at the one’s complement of the page address indicated by the hex value
stored in the associated Page Address Redirection Byte. A value of FDh in the redirection byte for page 1,
for example, would indicate that the updated data is now in page 2. Since the data memory consists of
four pages only, the 6 most significant bits of the redirection bytes cannot be programmed to zeros.

Status Memory location 5 serves as a test byte and is programmed to 00h at the factory. Status Memory
location 6 has no function with the DS2406. It is factory-programmed to 00h to distinguish the DS2406
from the DS2407, which both share the same family code. A DS2407 with Status Memory location 6
programmed to 00h will power-up into hidden mode and will only respond if the bus master addresses it
by a Match ROM command followed by the correct device ROM code. Conversely, a device that does
respond to a Read ROM command with family code 12h can only be a DS2406 if its Status Memory
location 6 reads 00h.

6 of 32

DS2406

Status Memory location 7 serves three purposes: 1) it holds the selection code for the Conditional Search
function, 2) provides the bus master a memory mapped access to the channel flip-flops that control the
PIO output transistors, and 3) allows the bus master to determine whether the device is hooked up to a
VCC power supply. Bit locations 0 to 4 store the conditional search settings. Their codes are explained in
the section “ROM Function Commands” later in this document. The channel flip-flops are accessible
through bit locations 5 and 6 as well as through the Channel Access function. The power-on default for
the conditional search settings and the channel flip-flops is all 1’s. Setting a channel flip-flop to 0 will
make the associated PIO-transistor conducting or on; setting the flip-flop to 1 will switch the transistor
off, which is identical to the power-on default. With the VCC pin connected to a suitable power supply the
power indicator bit 7 will read 1. The power supply indicator can also be read through the Channel
Access function.

MEMORY FUNCTION COMMANDS

The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the
various data fields and PIO channels within the DS2406. The Memory Function Control section, 8-bit
scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus
master and create the correct control signals within the device. A three-byte protocol is issued by the bus
master. It is comprised of a command byte to determine the type of operation and two address bytes to
determine the specific starting byte location within a data field or to supply and exchange setup and status
data when accessing the PIO channels. The command byte indicates if the device is to be read or written
or if the PIO channels are to be accessed. Writing data involves not only issuing the correct command
sequence but also providing a 12-volt programming voltage at the appropriate times. To execute a write
sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address.
Write sequences always occur a byte at a time. To execute a read sequence, the starting address is issued
by the bus master and data is read from the part beginning at that initial location and continuing to the end
of the selected data field or until a reset sequence is issued. All bits transferred to the DS2406 and
received back by the bus master are sent least significant bit first.

Read Memory [F0h]

The Read Memory command is used to read data from the 1024-bit EPROM data memory field. The bus
master follows the command byte with a two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates
a starting byte location within the data field. Since the data memory contains 128 bytes, T15:T8 and T7
should all be zero. With every subsequent read data time slot the bus master receives data from the
DS2406 starting at the initial address and continuing until the end of the 1024-bits data field is reached or
until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may
issue sixteen additional read time slots and the DS2406 will respond with a 16-bit CRC of the command,
address bytes and all data bytes read from the initial starting byte through the last byte of memory. This
CRC is the result of clearing the CRC generator and then shifting in the command byte followed by the
two address bytes and the data bytes beginning at the first addressed memory location and continuing
through to the last byte of the EPROM data memory. After the CRC is received by the bus master, any
subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a
Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available.

Typically the software controlling the device should store a 16-bit CRC with each page of data to insure
rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the

received data is correct or not. (See Application Note 114 for the recommended file structure). If CRC

values are imbedded within the data it is unnecessary to read the end-of-memory CRC. The Read
Memory command can be ended at any point by issuing a Reset Pulse.

7 of 32

DS2406

Extended Read Memory [A5h]

The Extended Read Memory command supports page redirection when reading data from the 1024-bit
EPROM data field. One major difference between the Extended Read Memory and the basic Read
Memory command is that the bus master receives the Redirection Byte (see description of Status
Memory) first before investing time in reading data from the addressed memory location. This allows the
bus master to quickly decide whether to continue and access the data at the selected starting page or to
terminate and restart the reading process at the redirected page address.

In addition to page redirection, the Extended Read Memory command also supports “bit-oriented”
applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications
the EPROM information may change over time within a page boundary making it impossible to include
an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command
concludes each page with the DS2406 generating and supplying a 16-bit CRC that is based on and
therefore always consistent with the current data stored in each page of the 1024-bit EPROM data field.

After having sent the command code of the Extended Read Memory command, the bus master sends a
two-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data
field. By sending eight read data time slots, the master receives the Redirection Byte associated with the
page given by the starting address. With the next sixteen read data time slots, the bus master receives a
16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the
DS2406 and read back by the bus master to check if the command word, starting address and Redirection
Byte were received correctly.

If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and
receives data from the DS2406 starting at the initial address and continuing until the end of a 32-byte
page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16­bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting
byte to the last byte of the current page.

With the next 24 read data time slots the master will receive the Redirection Byte of the next page
followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 1024-bits
EPROM data field starting at the beginning of the new page. This sequence will continue until the final
page and its accompanying CRC are read by the bus master.

The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction
flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end of
the memory page is always the result of clearing the CRC generator and shifting in the data bytes
beginning at the first addressed memory location of the EPROM data page until the last byte of this page.
With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value after the
Redirection Byte is the result of shifting the command byte into the cleared CRC generator, followed by
the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory
flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in
the Redirection Byte only. After the 16-bit CRC of the last page is read, the bus master will receive
logical 1s from the DS2406 until a Reset Pulse is issued. The Extended Read Memory command
sequence can be ended at any point by issuing a Reset Pulse.

8 of 32

DS2406

WRITING EPROM MEMORY

The function flow for writing to the Data Memory and Status Memory is almost identical. After the
appropriate write command has been issued, the bus master will send a two-byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address
bytes, and data byte is computed by the DS2406 and read back by the bus master to confirm that the
correct command word, starting address, and data byte were received.

If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, a programming pulse (12V on the 1-Wire
bus for 480 µs) is issued by the bus master. Prior to programming, the entire unprogrammed EPROM
memory field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set
to a logical 0, the corresponding bit in the selected byte of the EPROM memory is programmed to a
logical 0 after the programming pulse has been applied.

After the 480 µs programming pulse is applied and the data line returns to the idle level (5V), the bus
master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2406
responds with the data from the selected EPROM address sent least significant bit first. This byte contains
the bit-wise logical AND of all data ever written to this address. If the EPROM byte contains 1s in bit
positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current
byte address should be programmed again. If the DS2406 EPROM byte contains 0s in the same bit
positions as the data byte, the programming was successful and the DS2406 will automatically increment
its address counter to select the next byte in the EPROM memory field. The new two-byte address will
also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte
of data using eight write time slots.

As the DS2406 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator
that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2406
with sixteen read time slots to confirm that the address incremented properly and the data byte was
received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the write sequence must be
restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in
memory will be programmed.

Note that the initial pass through the write flow chart will generate an 16-bit CRC value that is the result
of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the
data byte. Subsequent passes through the write flow chart due to the DS2406 automatically incrementing
its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new
(incremented) address into the CRC generator and then shifting in the new data byte.

For both of these cases, the decision to continue (to apply a program pulse to the DS2406) is made
entirely by the bus master, since the DS2406 will not be able to determine if the 16-bit CRC calculated by
the bus master agrees with the 16-bit CRC calculated by the DS2406. If an incorrect CRC is ignored and
the bus master applies a program pulse, incorrect programming could occur within the DS2406. Also note
that the DS2406 will always increment its internal address counter after the receipt of the eight read time
slots used to confirm the programming of the selected EPROM byte. The decision to continue is again
made entirely by the bus master. Therefore if the EPROM data byte does not match the supplied data byte
but the master continues with the write command, incorrect programming could occur within the DS2406.
The write command sequence can be ended at any point by issuing a Reset Pulse.

9 of 32

Memory Function Flow Chart Figure 7

Bus Master TX Memory

Function Command

F0h

Read Memory

?

YY

NN

A5h

Extended Rd.

Memory

?

DS2406

To Figure 7
2nd Part

DS2406

increments

Address

Counter

Bus Master

RX "1"s

Legend:

Bus Master TX

TA1(T7:T0), TA2 (T15:T8)

DS2406 sets Memory

Address = (T15:T0)

Bus Master RX Data

from Data Memory

Master

TX Reset ?

N

N

Bus Master RX CRC16 of

Command, Address, Data

End of

Data Mem.

?

Y

Master

TX Reset ?

N

Master

TX Reset ?

N

Y

Y

Y

Bus Master RX CRC16 of Command,
Address, Redir. Byte (1st pass)
CRC16 of Redir. Byte (subs. passes)

Bus Master TX

Reset Pulse

Bus Master TX

TA1(T7:T0), TA2 (T15:T8)

DS2406 sets Memory

Address = (T15:T0)

Bus Master RX

Redirection Byte

N

Bus Master RX Data

from Data Memory

Y

Bus Master RX CRC16 of
Preceding Page of Data

CRC

Correct ?

Y

Master

TX Reset ?

N

End

of Page ?

Y

N

DS2406

increments

Address

Counter

Decision made

by Bus Master

Decision made

by DS2406

Vertical

Spare

Bus Master TX

DS2406 TX

Presence Pulse

Reset Pulse

S

10 of 32

N

Y

CRC

Correct ?

Y

End of

Data Mem.

?

Y
Master

TX Reset ?

N

R

N

Bus Master

RX "1"s

DS2406

increments

Address

Counter