Maxim DS21Q55 User Manual

Product Preview DS21Q55

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PRODUCT PREVIEW

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DS21Q55 Quad T1/E1/J1 Transceiver

FEATURES:

Complete T1 (DS1)/ISDN–PRI/J1 transceiver functionality

§ Complete E1 (CEPT) PCM-30/ISDN-PRI

transceiver functionality

§ Short- and long-haul line interface for

clock/data recovery and wave shaping

§ CMI coder/decoder

§ Crystal-less jitter attenuator

§ Dual HDLC controllers

§ On-chip programmable BERT generator and

detector

§ Internal software-selectable receive and

transmit side termination resistors

§ Dual two -frame elastic-store slip buffers to

interface backplanes up to 16.384MHz

§ 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output synthesized to recovered network clock

§ Programmable output clocks for fractional

T1, E1, H0, and H12 applications

§ Interleaving PCM bus operation

§ 8-bit parallel control port, multiplexed or

nonmultiplexed, Intel or Motorola

§ IEEE 1149.1 JTAG-boundary scan

§ 3.3V supply with 5V tolerant I/O

§ Signaling System 7 (SS7) support

APPLICATIONS:

§ Routers

§ Channel Service Units (CSUs)

§ Data Service Units (DSUs)

§ Muxes

§ Switches

§ Channel Banks

§ T1/E1 Test Equipment

§ DSL Add/Drop Multiplexers

ORDERING INFORMATION

DS21Q55 27mm BGA (0°C to +70°C) DS21Q55N 27mm BGA (-40°C to +85°C)

1. DESCRIPTION

The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family of products.

Note: This Product Preview contains preliminary information and is subject to change without notice. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm.

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1. DESCRIPTION

The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family of products.

The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary wave shapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX–1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 wave shapes for both 75O coax and 120O twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to optical networks.

On the transmit side, clock data and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane interface section.

Each transceiver has two HDLC controllers. The HDLC controllers transmit and receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has a 128-byte transmit FIFO and a 128-byte receive FIFO, thus reducing the amount of processor overhead required to manage the flow of data. In addition, there is built-in support for reducing the processor time req uired to handle SS7 applications.

The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (two DS21Q55s) to share a high-speed backplane.

The parallel port provides access for control and configuration of all the DS21Q55’s features. The Extended System Information Bus (ESIB) function allows up to eight transceivers, 2 DS21Q55s, to be accessed via a single read for interrupt status or other user selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.

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The device fully meets all of the latest E1 and T1 specifications, including the following:

§ ANSI: T1.403-1995, T1.231-1993, T1.408

§ AT&T: TR54016, TR62411

§ ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161

§ ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12

§ Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only)

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1.1 FEATURE HIGHLIGHTS

The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features.

1.1.1 General

§ 27mm, 1.27 pitch BGA

§ 3.3V supply with 5V tolerant inputs and outputs

§ Pin compatible with DS21x5y family

§ Software compatible with the DS2155

§ Evaluation kits

§ IEEE 1149.1 JTAG-boundary scan

§ Driver source code available from the factory

1.1.2 Line Interface

§ Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be

2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,

6.276MHz, or 12.552MHz for T1 -only operation

§ Fully software configurable

§ Short- and long-haul applications

§ Automatic receive sensitivity adjustments

§ Ranges include 0dB to -43dB or 0dB to -15dB for E1 applications; 0dB to -36dB or 0dB to -15dB

for T1 applications

§ Receive level indication in 2.5dB steps from -42.5dB to -2.5dB

§ Internal receive termination option for 75O, 100O, and 120O lines

§ Monitor application gain sett ings of 20dB, 26dB, and 32dB

§ G.703 receive-synchronization signal-mode

§ Flexible transmit-waveform generation

§ T1 DSX-1 line build-outs

§ T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB

§ E1 waveforms include G.703 waveshapes for both 75O coax and 120O twisted cables

§ AIS generation independent of loopbacks

§ Alternating ones and zeros generation

§ Square-wave output

§ Open-drain output option

§ NRZ format option

§ Transmitter power-down

§ Transmitter 50mA short-circuit limiter with exceeded indication of current limit

§ Transmit open-circuit-detected indication

§ Line interface function can be completely decoupled from the framer/formatter

1.1.3 Clock Synthesizer

§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz

§ Derived from recovered receive clock

1.1.4 Jitter Attenuator

§ 32-bit or 128-bit crystal-less jitter attenuator

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§ Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use

1.544MHz for T1 operation

§ Can be placed in either the receive or transmit path or disabled

§ Limit trip indication

1.1.5 Framer/Formatter

§ Fully independent transmit and receive functionality

§ Full receive- and transmit-path transparency

§ T1 framing formats include D4 (SLC -96) and ESF

§ Detailed alarm- and status-reporting with optional interrupt support

§ Large path- and line-error counters for:

− T1 – BPV, CV, CRC6, and framing bit errors

− E1 – BPV, CV, CRC4, E-bit, and frame alignment errors

− Timed or manual update modes

§ DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths

− User-defined

− Digital mill iwatt

§ ANSI T1.403-1998 support

§ E1ETS 300 011 RAI generation

§ G.965 V5.2 link detect

§ Ability to monitor one DS0 channel in both the transmit and receive paths

§ In -band repeating-pattern generators and detectors

− Three independent generators and detectors

− Patterns from 1 bit to 8 bits or 16 bits in length

§ RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

§ Flexible signaling support

− Software- or hardware-based

− Interrupt generated on change of signaling data

− Receive-signaling freeze o n loss of sync, carrier loss, or frame slip

§ Addition of hardware pins to indicate carrier loss and signaling freeze

§ Automatic RAI generation to ETS 300 011 specifications

§ Expanded access to Sa and Si bits

§ Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233

§ Japanese J1 support

− Ability to calculate and check CRC6 according to the Japanese standard

− Ability to generate yellow alarm according to the Japanese standard

1.1.6 System Interface

§ Dual two -frame, independent receive and transmit elastic stores

− Independent control and clocking

− Controlled-slip capability with status

− Minimum -delay mode supported

§ Maximum 16.384MHz backplane burst rate

§ Supports T1 to CEPT (E1) conversion

§ Programmable output clocks for fractional T1, E1, H0, and H12 applications

§ Interleaving PCM bus operation

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§ Hardware-signaling capability

− Receive-signaling reinsertion to a backplane, multiframe sync

− Availability of signaling in a separate PCM data stream

− Signaling freezing

§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode

§ Access to the data streams in between the framer/formatter and the elastic stores

§ User-selectable synthesized clock output

1.1.7 HDLC Controllers

§ Two independent HDLC controllers

§ Fast load and unload features for FIFOs

§ SS7 support for FISU transmit and receive

§ Independent 128-byte RX and TX buffers with interrupt support

§ Access FDL, Sa, or single/multiple DS0 channels

§ DS0 access includes Nx64 or Nx56

§ Compatible with polled or interrupt-driven environments

§ Bit Oriented Code (BOC) support

1.1.8 Test and Diagnostics

§ Programmable on-chip Bit Error Rate Testing (BERT)

§ Pseudorandom patterns including QRSS

§ User-defined repetitive patterns

§ Daly pattern

§ Error insertion single and continuous

§ Total-bit and errored-bit counts

§ Payload Error Insertion

§ Error insertion in the payload portion of the T1 frame in the transmit path

§ Errors can be inserted over the entire frame or selected channels

§ Insertion options include continuous and absolute number with selectable insertion rates

§ F-bit corruption for line testing

§ Loopbacks (remote, local, analog, and per-channel loopback)

1.1.9 Extended System Information Bus

§ Host can read interrupt and alarm status on up to eight ports with a single-bus read

1.1.10 Control Port

§ 8-bit parallel control port

§ Multiplexed or nonmultiplexed buses

§ Intel or Motorola formats

§ Supports polled or interrupt-driven environments

§ Software access to device ID and silicon revision

§ Software-reset supported

Automatic clear on power-up

§ Flexible register-space resets

§ Hardware reset pin

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Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is

sent first followed by channel 1. Each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).

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TABLE OF CONTENTS

1.1 FEATURE HIGHLIGHTS ............................................................................................................................4

1.1.1 General ..................................................................................................................................................4

1.1.2 Line Interface ....................................................................................................................................... 4

1.1.3 Clock Synthesizer ..............................................................................................................................4

1.1.4 Jitter Attenuator ................................................................................................................................... 4

1.1.5 Framer/Formatter ............................................................................................................................... 5

1.1.6 System Interface.................................................................................................................................5

1.1.7 HDLC Controllers ...............................................................................................................................6

1.1.8 Test and Diagnostics........................................................................................................................6

1.1.9 Extended System Information Bus...............................................................................................6

1.1.10 Control Port ..........................................................................................................................................6

1.2 DOCUMENT REVISION HISTORY .......................................................................................................12

2. BLOCK DIAGRAM ...........................................................................................................................................13

3. PIN FUNCTION DESCRIPTION..................................................................................................................14

3.1 TRANSMIT SIDE PINS.....................................................................................................................................14

3.2 RECEIVE SIDE PINS........................................................................................................................................16

3.3 PARALLEL CONTROL PORT PINS.................................................................................................................18

3.4 EXTENDED SYSTEM INFORMATION BUS.....................................................................................................20

3.5 JTAG TEST ACCESS PORT PINS...................................................................................................................20

3.6 LINE INTERFACE PINS....................................................................................................................................21

3.7 SUPPLY PINS...................................................................................................................................................22

3.8 PINOUT ............................................................................................................................................................23

3.9 PACKAGE.........................................................................................................................................................29

4. PARALLEL PORT ............................................................................................................................................30

4.1 REGISTER MAP...............................................................................................................................................30

5. SPECIAL PER-CHANNEL REGISTER OPERATION .........................................................................36

6. PROGRAMMING MODEL..............................................................................................................................38

6.1 POWER-UP S EQUENCE..................................................................................................................................39

6.1.1 Master Mode Register ....................................................................................................................39

6.2 INTERRUPT HANDLING..................................................................................................................................40

6.3 STATUS REGISTERS........................................................................................................................................40

6.4 INFORMATION REGISTERS............................................................................................................................41

6.5 INTERRUPT INFORMATION REGISTERS ........................................................................................................41

7. CLOCK MAP.......................................................................................................................................................42

8. T1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................43

8.1 T1 CONTROL REGISTERS..............................................................................................................................43

8.2 T1 TRANSMIT TRANSPARENCY ....................................................................................................................48

8.3 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE G ENERATION.................................................................48

8.4 T1 INFORMATION REGISTER........................................................................................................................50

9. E1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................52

9.1 E1 CONTROL REGISTERS..............................................................................................................................52

9.2 AUTOMATIC ALARM G ENERATION.............................................................................................................56

9.3 E1 INFORMATION REGISTERS .......................................................................................................................57

10. COMMON CONTROL AND STATUS REGISTERS.........................................................................59

11. I/O PIN CONFIGURATION OPTIONS...................................................................................................66

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12. LOOPBACK CONFIGURATION .............................................................................................................68

12.1 PER-CHANNEL LOOPBACK...........................................................................................................................70

13. ERROR COUNT REGISTERS .................................................................................................................72

13.1 LINE CODE V IOLATION COUNT REGISTER (LCVCR) ..............................................................................73

13.2 PATH CODE V IOLATION COUNT REGISTER (PCVCR) .............................................................................75

13.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR) ...............................................................................76

13.4 E-BIT COUNTER REGISTER (EBCR) ...........................................................................................................78

14. DS0 MONITORING FUNCTION..............................................................................................................79

14.1 TRANSMIT DS0 MONITOR REGISTERS........................................................................................................79

14.2 RECEIVE DS0 MONITOR REGISTERS...........................................................................................................80

15. SIGNALING OPERATION .........................................................................................................................81

15.1 RECEIVE SIGNALING......................................................................................................................................81

15.1.1 Processor-Based Receive Signaling .........................................................................................82

15.1.2 Hardware-Based Receive Signaling..........................................................................................82

15.2 TRANSMIT SIGNALING...................................................................................................................................87

15.2.1 Processor-Based Transmit Signaling........................................................................................87

15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.......................................93

15.2.3 Software Signaling Insertion Enable Registers, T1 Mode ..................................................95

16. PER-CHANNEL IDLE CODE GENERATION.....................................................................................97

16.1 IDLE CODE PROGRAMMING EXAMPLES......................................................................................................98

17. CHANNEL BLOCKING REGISTERS..................................................................................................103

18. ELASTIC STORES OPERATION .........................................................................................................106

18.1 RECEIVE SIDE..............................................................................................................................................110

18.1.1 T1 Mode............................................................................................................................................110

18.1.2 E1 Mode ............................................................................................................................................110

18.2 TRANSMIT SIDE...........................................................................................................................................111

18.2.1 T1 Mode............................................................................................................................................111

18.2.2 E1 Mode ............................................................................................................................................111

18.3 ELASTIC S TORES INITIALIZATION.............................................................................................................111

18.4 MINIMUM-DELAY MODE...........................................................................................................................111

19. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................113

20. T1 BIT ORIENTED CODE (BOC) CONTROLLER .........................................................................114

20.1 TRANSMIT BOC ..........................................................................................................................................114

20.2 RECEIVE BOC.............................................................................................................................................114

21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) .................118

21.1 HARDWARE SCHEME (METHOD 1)...........................................................................................................118

21.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2)..........................................118

21.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME (METHOD 3)...................................121

22. HDLC CONTROLLERS ............................................................................................................................132

22.1 BASIC OPERATION DETAILS......................................................................................................................132

22.2 HDLC CONFIGURATION............................................................................................................................134

22.2.1 FIFO Control ....................................................................................................................................136

22.3 HDLC MAPPING.........................................................................................................................................137

22.3.1 Receive..............................................................................................................................................137

22.3.2 Transmit.............................................................................................................................................139

22.3.3 FIFO Information............................................................................................................................144

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22.3.4 Receive Packet Bytes Available ...............................................................................................144

22.3.5 HDLC FIFOS ....................................................................................................................................145

22.4 RECEIVE HDLC CODE EXAMPLE.............................................................................................................146

22.5 LEGACY FDL SUPPORT (T1 MODE).........................................................................................................146

22.5.1 Receive Section..............................................................................................................................146

22.5.2 Transmit Section .............................................................................................................................148

22.6 D4/SLC– 96 OPERATION............................................................................................................................148

23. LINE INTERFACE UNIT (LIU)................................................................................................................149

23.1 LIU OPERATION.......................................................................................................................................... 150

23.2 LIU RECEIVER............................................................................................................................................. 150

23.2.1 Receive Level Indicator...............................................................Error! Bookmark not defined.

23.2.2 Receive G.703 Synchronization Signal (E1 Mode) ............................................................151

23.2.3 Monitor Mode...................................................................................................................................151

23.3 LIU TRANSMITTER.....................................................................................................................................152

23.3.1 Transmit Short -Circuit Detector/Limiter..................................................................................152

23.3.2 Transmit Open -Circuit Detector................................................................................................152

23.3.3 Transmit BPV Error Insertion .....................................................................................................152

23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................152

23.4 MCLK PRESCALER.....................................................................................................................................153

23.5 JITTER ATTENUATOR..................................................................................................................................153

23.6 CMI (CODE MARK INVERSION) OPTION.................................................................................................153

23.7 LIU CONTROL REGISTERS......................................................................................................................... 154

23.8 RECOMMENDED CIRCUITS.........................................................................................................................164

23.9 COMPONENT S PECIFICATIONS...................................................................................................................166

24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION................170

25. BERT FUNCTION .......................................................................................................................................177

25.1 BERT REGISTER DESCRIPTION................................................................................................................. 178

25.2 BERT REPETITIVE PATTERN SET............................................................................................................. 183

25.3 BERT BIT COUNTER.................................................................................................................................. 184

25.4 BERT ERROR COUNTER............................................................................................................................ 185

26. PAYLOAD ERROR INSERTION FUNCTION...................................................................................186

26.1 NUMBER OF ERROR REGISTERS...............................................................................................................188

26.1.1 Number Of Errors Left Register................................................................................................189

27. INTERLEAVED PCM BUS OPERATION ...........................................................................................190

27.1 CHANNEL INTERLEAVE MODE..................................................................................................................190

27.2 FRAME INTERLEAVE MODE.......................................................................................................................190

28. EXTENDED SYSTEM INFORMATION BUS (ESIB)......................................................................193

29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER......................................................197

30. FRACTIONAL T1/E1 SUP PORT...........................................................................................................198

31. JTAG-BOUNDARY-SCAN ARCHITECTURE AN D TEST-ACCESS PORT .........................199

31.1 INSTRUCTION REGISTER.............................................................................................................................203

31.2 TEST REGISTERS ..........................................................................................................................................205

31.3 BOUNDARY SCAN REGISTER.....................................................................................................................205

31.4 BYPASS REGISTER ...................................................................................................................................... 205

31.5 IDENTIFICATION REGISTER........................................................................................................................205

32. FUNCTIONAL TIMING DIAGRAMS....................................................................................................208

32.1 T1 MODE......................................................................................................................................................208

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32.2 E1 MODE......................................................................................................................................................218

33. OPERATING PARAMETERS.................................................................................................................231

34. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................233

34.1 MULTIPEXED BUS AC CHARACTERISTICS..............................................................................................233

34.2 NONMULTIPLEXED BUS AC CHARACTERISTICS.................................................................................... 236

34.3 RECEIVE SIDE AC CHARACTERISTICS.....................................................................................................239

34.4 TRANSMIT AC CHARACTERISTICS...........................................................................................................243

35. MECHANICAL DESCRIPTIONS...........................................................................................................247

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1.2 DOCUMENT REVISION HISTORY

1) Initial Preliminary Release

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2. BLOCK DIAGRAM

A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4-1. Details are shown in subsequent figures. The block diagram is then divided into three functional blocks: LIU, framer, and backplane interface.

BLOCK DIAGRAM Figure 4- 1

TRANSCEIVER #4

TRANSCEIVER #3

TRANSCEIVER #2

RCLK

RLOS/LOTC

BPCLK RLINK

RLCLK RCHBLK

RCHCLK

RSER RSYSCLK RSYNC

RMSYNC RSIG RSIGF

RFSYNC TSYNC

TSSYNC

TSYSCLK TSER

TCHBLK TCHCLK

TSIG TLINK TLCLK

TCLK

RRING

RTIP

TRING

TTIP

Clock / Data

Recovery

Line I/F

Transmit

Line I/F

VCO / PLL

Receive

RPOSO

RNEGO

RCLKO

Local Loopback

RNEGI

RCLKI

Either transmit or receive path

MUX

Jitter Attenuator

MUX

RPOSI

Remote Loopback

Receive Side

Framer Loopback

Transmit Side

Formatter

LOTC MUX

Framer

DATA

CLOCK

SYNC

CLOCK

DATA

HDLC/BOC Controller

8.192MHz Clock Synthesizer

Timing Control

Elastic

Store

Signaling Buffer

Sync Control

Elastic

Store

Timing Control Signaling Buffer

CS4*

CS2*

CS3*

ESIBRD ESIBS0 ESIBS1

BTS

CS1*

WR*(R/W*)

MUX

RD*(DS*)

INT*

Common MCLK

MCLK1

MCLK2

LIUCI

TCLKI

TNEGI

TCLKO

TPOSI

TPOSO

TNEGO

JTAG Port

JTTST

JTDO

JTMS

JTDI

JTCLK

D0/AD0

D1/AD1

ESIB

Parallel Control Port (routed to all blocks)

D2/AD2

D3/AD3

D4/AD4

D5/AD5

D6/AD6

D7/AD7

A0

A1A2A3A4A5A6A7/ALE(AS)

TSTRST

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3. PIN FUNCTION DESCRIPTION

3.1 Transmit Side Pins

Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.

Signal Name: TSERx Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.

Signal Name: TCHCLKx Signal Description: Transmit Channel Clock Signal Type: Output A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.

Signal Name: TCHBLKx Signal Description: Transmit Channel Block Signal Type: Output A user -programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per -channel conditioning.

Signal Name: TSYSCLKx Signal Description: Transmit System Clock Signal Type: Input

1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit -side elastic-store function is enabled. Should be ti ed low in applications that do not use the transmit-side elastic store. See Interleaved PCM Bus Operation for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.

Signal Name: TLCLKx Signal Description: Transmit Link Clock Signal Type: Output Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock.

Signal Name: TLINKx Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fsbit position (D4) or the Z–bit position (ZBTSI) or any combination of the Sa bit positions (E1).

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Signal Name: TSYNCx Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1 .3 to output double-wide pulses at signaling frames in T1 mode.

Signal Name: TSSYNCx Signal Description: Transmit System Sync Signal Type: Input Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.

Signal Name: TSIGx Signal Description: Transmit Signaling Input Signal Type: Input When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.

Signal Name: TPOSOx Signal Description: Transmit Positive Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data via the output-data format (IOCR1 .0)-control bit. This pin is normally tied to TPOSI.

Signal Name: TNEGOx Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI.

Signal Name: TCLKOx Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit-side formatter (either TCLK or RCLKI). This pin is normally tied to TCLKI.

Signal Name: TPOSIx Signal Description: Transmit Positive Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

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Signal Name: TNEGIx Signal Description: Transmit Negative Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

Signal Name: TCLKIx Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.

3.2 Receive Side Pins

Signal Name: RLINKx Signal Description: Receive Link Data Signal Type: Output T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.

Signal Name: RLCLKx Signal Description: Receive Link Clock Signal Type: Output T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output. E1 Mode: A 4kHz to 20kHz clock.

Signal Name: RCLKx Signal Description: Receive Clock Signal Type: Output

1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.

Signal Name: RCHCLKx Signal Description: Receive Channel Clock Signal Type: Output A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.

Signal Name: RCHBLKx Signal Description: Receive Channel Block Signal Type: Output A user -programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Also useful for locating individual channels in drop-and-insert applications, for external per -channel loopback, and for per -channel conditioning. See Channel Blocking Registers.

Signal Name: RSERx Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

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Signal Name: RSYNCx Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input via IOCR1.4 at which a frame or multiframe boundary pulse is applied.

Signal Name: RFSYNCx Signal Description: Receive Frame Sync Signal Type: Output An extracted 8k Hz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries.

Signal Name: RMSYNCx Signal Description: Receive Multiframe Sync Signal Type: Output An extracted pulse, one RCLK wide (elastic store disabled) or one RSY SCLK wide (elastic store enabled), is output at this pin, which identifies multiframe boundaries.

Signal Name: RSYSCLKx Signal Description: Receive System Clock Signal Type: Input

1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic-store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. See Interleaved PCM Bus Operation for details on 4.096MHz and 8.192MHz operation using the IBO.

Signal Name: RSIGx Signal Description: Receive Signaling Output Signal Type: Output Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name: RLOS/LOTCx Signal Description: Receive Loss of Sync/Loss of Transmit Clock Signal Type: Output A dual -function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5µsec.

Signal Name: RSIGFx Signal Description: Receive Signaling Freeze Signal Type: Output Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition.

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Signal Name: BPCLKx Signal Description: Back Plane Clock Signal Type: Output A user -selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.

Signal Name: RPOSOx Signal Description: Receive Positive Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.

Signal Name: RNEGOx Signal Description: Receive Negative Data Output Signal Type: Output Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.

Signal Name: RCLKOx Signal Description: Receive Clock Output Signal Type: Output Buffered recovered clock from the network. This pin is normally tied to RCLKI.

Signal Name: RPOSIx Signal Description: Receive Positive Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.

Signal Name: RNEGIx Signal Description: Receive Negative Data Input Signal Type: Input Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.

Signal Name: RCLKIx Signal Description: Receive Clock Input Signal Type: Input Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.

3.3 Parallel Control Port Pins

Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.

Signal Name: TSTRST Signal Description: 3-State Control and Device Reset Signal Type: Input A dual -function pin. A zero-to-one transition issues a hardware reset to the DS21Q55 register set. A reset clears all configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will 3-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in -board level testing.

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Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.

Signal Name: D0/AD0 to D7/AD7 Signal Des cription: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an 8-bit, multiplexed address/data bus.

Signal Name: A0 to A6 Signal Description: Address Bus Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.

Signal Name: BTS Signal Description: Bus Type Select Signal Type: Input Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*), A7/ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis ().

Signal Name: RD*(DS*) Signal Description: Read Input-Data Strobe Signal Type: Input RD* and DS* are active-low signals. DS active HIGH when MUX = 0. See bus timing diagrams.

Signal Name: CS1* Signal Description: Chip Select for transceiver #1 Signal Type: Input Must be low to read or write to transceiver #1 of the device. CS1* is an active-low signal.

Signal Name: CS2* Signal Description: Chip Select for transceiver #2 Signal Type: Input Must be low to read or write to transceiver #2 of the device. CS2* is an active-low signal.

Signal Name: CS3* Signal Description: Chip Select for transceiver #3 Signal Type: Input Must be low to read or write to transc eiver #3 of the device. CS3* is an active-low signal.

Signal Name: CS4* Signal Description: Chip Select for transceiver #4 Signal Type: Input Must be low to read or write to transceiver #4 of the device. CS4* is an active-low signal.

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Signal Name: A7/ALE(AS) Signal Description: A7 or Address Latch Enable(Address Strobe) Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge.

Signal Name: WR*(R/W*) Signal Description: Write Input(Read/Write) Signal Type: Input WR* is an active-low signal.

3.4 Extended System Information Bus

Signal Name: ESIBS0x Signal Description: Extended System Information Bus Select 0 Signal Type: Input/Output Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus (ESIB) for more details.

Signal Name: ESIBS1x Signal Description: Extended System Information Bus Select 1 Signal Type: Input/Output Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus (ESIB) for more details.

Signal Name: ESIBRDx Signal Description: Extended System Information Bus Read Signal Type: Input/Output Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus (ESIB) for more details.

3.5 JTAG Test Access Port Pins

Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST low. JTRST is pulled HIGH internally via a 10k resistor operation.

Signal Name: JTMS Signal Description: IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test -access port into the various defined IEEE 1149.1 states. This pin has a 10k pullup resistor.

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Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.

Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor.

Signal Name: JTDO Signal Description: IEEE 1149.1 Test Data Output Signal Type: Output Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.

3.6 Line Interface Pins

Signal Name: MCLK1 Signal Description: Master Clock Input for Transceivers 1 & 2 Signal Type: Input A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 may be driven from a common clock.

Signal Name: MCLK2 Signal Description: Master Clock Input for Transceivers 3 & 4 Signal Type: Input A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 may be driven from a common clock.

Signal Name: LIUC Signal Description: Line Interface Connect Signal Type: Input Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circu itry to the framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.

Signal Name: RTIPx and RRINGx Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Line Interface Unit for details.

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Signal Name: TTIPx and TRINGx Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Line Interface Unit for details.

3.7 Supply Pins

Signal Name: DVDD Signal Description: Digital Posi tive Supply Signal Type: Supply

3.3V ±5%. Should be tied to the RVDD and TVDD pins.

Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply

3.3V ±5%. Should be tied to the DVDD and TVDD pins.

Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply

3.3V ±5% Should be tied to the RVDD and DVDD pins.

Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply Should be tied to the RVSS and TVSS pins.

Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply

0.0V. Should be tied to DV

Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply

0.0V. Should be tied to DVSS and RVSS.

and TVSS.

SS

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3.8 Pinout

DS21Q55 PIN DESCRIPTION Table 5- 1

NOTE: Signal is common to all transceivers unless otherwise stated

PIN SYMBOL TYPE DESCRIPTION

U3 A0 I Address Bus Bit 0 (lsb). L17 A1 I Address Bus Bit 1. V2 A2 I Address Bus Bit 2. T4 A3 I Address Bus Bit 3. V8 A4 I Address Bus Bit 4. H4 A5 I Address Bus Bit 5. U8 A6 I Address Bus Bit 6. P4 A7/ALE(AS) I Address Bus Bit 7 (msb) / Address Latch Enable. M1 BPCLK1 O Back Plane Clock, Transceiver # 1. H17 BPCLK2 O Back Plane Clock, Transceiver # 2. F4 BPCLK3 O Back Plane Clock, Transceiver # 3. V13 BPCLK4 O Back Plane Clock, Transceiver # 4. P2 BTS I Bus Type Select (0 = Intel / 1 = Motorola), P3 CS1* I Chip Select, Transceiver # 1. A14 CS2* I Chip Select, Transceiver # 2. B5 CS3* I Chip Select, Transceiver # 3. K17 CS4* I Chip Select, Transceiver # 4. U11 D0/AD0 I/O Data Bus Bit 0/ Address/Data Bus Bit 0 (lsb). J19 D1/AD1 I/O Data Bus Bit 1/ Address/Data Bus Bit 1. W15 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus Bit 2. U7 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3. U9 D4/AD4 I/O Data Bus Bit 4/Address/Data Bus Bit 4. U5 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5. V4 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6. U4 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7 (msb). J3 DVDD1 – Digital Positive Supply. N4 DVDD1 – Digital Positive Supply. U2 DVDD1 – Digital Positive Supply. V5 DVDD1 – Digital Positive Supply. B12 DVDD2 – Digital Positive Supply. C12 DVDD2 – Digital Positive Supply. C16 DVDD2 – Digital Positive Supply. D18 DVDD2 – Digital Positive Supply. A9 DVDD3 – Digital Positive Supply. B3 DVDD3 – Digital Positive Supply. B6 DVDD3 – Digital Positive Supply. C4 DVDD3 – Digital Positive Supply. G20 DVDD4 – Digital Positive Supply. M17 DVDD4 – Digital Positive Supply. M20 DVDD4 – Digital Positive Supply. P18 DVDD4 – Digital Positive Supply. H3 DVSS1 – Digital Signal Ground. U6 DVSS1 – Digital Signal Ground. W8 DVSS1 – Digital Signal Ground. A17 DVSS2 – Digital Signal Ground.

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PIN SYMBOL TYPE DESCRIPTION

A20 DVSS2 – Digital Signal Ground. B11 DVSS2 – Digital Signal Ground. A5 DVSS3 – Digital Signal Ground. B7 DVSS3 – Digital Signal Ground. B9 DVSS3 – Digital Signal Ground. H20 DVSS4 – Digital Signal Ground L20 DVSS4 – Digital Signal Ground N17 DVSS4 – Digital Signal Ground J4 ESIBRD1 – Extended System Information Bus Read, Transceiver # 1. C13 ESIBRD2 – Extended System Information Bus Read, Transceiver # 2. C3 ESIBRD3 – Extended System Information Bus Read, Transceiver # 3. U13 ESIBRD4 – Extended System Information Bus Read, Transceiver # 4. W6 ESIBS0_1 I/O Extended System Information Bus 0, Transceiver # 1. F18 ESIBS0_2 I/O Extended System Information Bus 0, Transceiver # 2. D7 ESIBS0_3 I/O Extended System Information Bus 0, Transceiver # 3. T20 ESIBS0_4 I/O Extended System Information Bus 0, Transceiver # 4. V9 ESIBS1_1 I/O Extended System Information Bus 1, Transceiver # 1. B17 ESIBS1_2 I/O Extended System Information Bus 1, Transceiver # 2. A6 ESIBS1_3 I/O Extended System Information Bus 1, Transceiver # 3. J20 ESIBS1_4 I/O Extended System Information Bus 1, Transceiver # 4. U1 INT* O Interrupt. Y15 JTCLK I JTAG Clock. N1 JTDI I JTAG Data Input, Transceiver #1 V19 JTDO O JTAG Data Output. Transceiver #4 W13 JTMS I JTAG Test Mode Select. V18 JTRST* I JTAG Reset. K2 LIUC I Line Interface Connect. T1 MCLK1 I Master Clock, Transceiver #1 and, Transceiver #3. W20 MCLK2 I Master Clock, Transceiver #2 and, Transceiver #4. U10 MUX I Mux Bus Select. M2 RCHBLK1 O Receive Channel Block, Transceiver #1. G17 RCHBLK2 O Receive Channel Block, Transceiver #2. G4 RCHBLK3 O Receive Channel Block, Transceiver #3. Y12 RCHBLK4 O Receive Channel Block, Transceiver #4. J1 RCHCLK1 O Receive Channel Clock, Transceiver #1. D14 RCHCLK2 O Receive Channel Clock, Transceiver #2. F3 RCHCLK3 O Receive Channel Clock, Transceiver #3. U14 RCHCLK4 O Receive Channel Clock, Transceiver #4. N3 RCLK1 O Receive Clock Output from the Framer, Transceiver #1. B13 RCLK2 O Receive Clock Output from the Framer, Transceiver #2. E3 RCLK3 O Receive Clo ck Output from the Framer, Transceiver #3. M18 RCLK4 O Receive Clock Output from the Framer, Transceiver #4. M4 RCLKI1 I Receive Clock Input for the LIU, Transceiver #1. A15 RCLKI2 I Receive Clock Input for the LIU, Transceiver #2. A4 RCLKI3 I Receive Clock Input for the LIU, Transceiver #3. R17 RCLKI4 I Receive Clock Input for the LIU, Transceiver #4. M3 RCLKO1 O Receive Clock Output from the LIU, Transceiver #1. C14 RCLKO2 O Receive Clock Output from the LIU, Transceiver #2. B4 RCLKO3 O Receive Clock Output from the LIU, Transceiver #3. T17 RCLKO4 O Receive Clock Output from the LIU, Transceiver #4. N2 RD*(DS*) I Read Input (Data Strobe) K4 RFSYNC1 O Receive Frame Sync (before the receive elastic store), Transceiver

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PIN SYMBOL TYPE DESCRIPTION

#1.

D17 RFSYNC2 O Receive Frame Sync (before the receive elastic store), Transceiver

#2.

A2 RFSYNC3 O Receive Frame Sync (before the receive elastic store), Transceiver

#3.

V14 RFSYNC4 O Receive Frame Sync (before the receive elastic store), Transceiver

#4. F1 RLCLK1 O Receive Lin k Clock, Transceiver #1. A12 RLCLK2 O Receive Link Clock, Transceiver #2. D3 RLCLK3 O Receive Link Clock, Transceiver #3. K18 RLCLK4 O Receive Link Clock, Transceiver #4. G2 RLINK1 O Receive Link Data, Transceiver #1. A13 RLINK2 O Receive Link Data, Transceiver #2. A3 RLINK3 O Receive Link Data, Transceiver #3. U12 RLINK4 O Receive Link Data, Transceiver #4. H2 RLOS/LOTC1 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #1. E17 RLOS/LOTC2 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #2. E1 RLOS/LOTC3 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #3. V11 RLOS/LOTC4 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #4. L1 RMSYNC1 O Receive Multiframe Sync, Transceiver #1. D16 RMSYNC2 O Receive Multiframe Sync, Transceiver #2. F2 RMSYNC3 O Receive Multiframe Sync, Transceiver #3. W16 RMSYNC4 O Receive Multiframe Sync, Transceiver #4. R3 RNEGI1 I Receive Negative Data for the Framer, Transceiver #1. D13 RNEGI2 I Receive Negative Data for the F ramer, Transceiver #2. A1 RNEGI3 I Receive Negative Data for the Framer, Transceiver #3. P17 RNEGI4 I Receive Negative Data for the Framer, Transceiver #4. L3 RNEGO1 O Receive Negative Data from the LIU, Transceiver #1. B15 RNEGO2 O Receive Negative Da ta from the LIU, Transceiver #2. C2 RNEGO3 O Receive Negative Data from the LIU, Transceiver #3. U17 RNEGO4 O Receive Negative Data from the LIU, Transceiver #4. R4 RPOSI1 I Receive Positive Data for the Framer, Transceiver #1. B14 RPOSI2 I Receive Positive Data for the Framer, Transceiver #2. B2 RPOSI3 I Receive Positive Data for the Framer, Transceiver #3. V15 RPOSI4 I Receive Positive Data for the Framer, Transceiver #4. L4 RPOSO1 O Receive Positive Data from the LIU, Transceiver #1. A16 RPOSO2 O Receive Positive Data from the LIU, Transceiver #2. B1 RPOSO3 O Receive Positive Data from the LIU, Transceiver #3. U15 RPOSO4 O Receive Positive Data from the LIU, Transceiver #4. Y11 RRING1 I Receive Analog Ring Input, Transceiver #1. Y14 RRING2 I Receive Analog Ring Input, Transceiver #2. Y17 RRING3 I Receive Analog Ring Input, Transceiver #3. Y20 RRING4 I Receive Analog Ring Input, Transceiver #4. J2 RSER1 O Receive Serial Data, Transceiver #1. D15 RSER2 O Receive Serial Data, Transceiver #2. E2 RSER3 O Receive Serial Data, Transceiver #3. W17 RSER4 O Receive Serial Data, Transceiver #4. L2 RSIG1 O Receive Signaling Output, Transceiver #1. B16 RSIG2 O Receive Signaling Output, Transceiver #2. C1 RSIG3 O Receive Signaling Output, Transceiver #3. Y18 RSIG4 O Receive Signaling Output, Transceiver #4. K1 RSIGF1 O Receive Signaling Freeze Output, Transceiver #1. C15 RSIGF2 O Receive Signaling Freeze Output, Transceiver #2.

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PIN SYMBOL TYPE DESCRIPTION

D2 RSIGF3 O Receive Signaling Freeze Output, Transceiver #3. V16 RSIGF4 O Receive Signaling Freeze Output, Transceiver #4. G1 RSYNC1 I/O Receive Sync, Transceiver #1. D12 RSYNC2 I/O Receive Sync, Transceiver #2. D1 RSYNC3 I/O Receive Sync, Transceiver #3. V12 RSYNC4 I/O Receive Sync, Transceiver #4. H1 RSYSCLK1 I Receive System Clock, Transceiver #1. F17 RSYSCLK2 I Receive System Clock, Transceiver #2. G3 RSYSCLK3 I Receive System Clock, Transceiver #3. W14 RSYSCLK4 I Receive System Clock, Transceiver #4. Y10 RTIP1 I Receive Analog Tip Input, Transceiver #1. Y13 RTIP2 I Receive Analog Tip Input, Transceiver #2. Y16 RTIP3 I Receive Analog Tip Input, Transceiver #3. Y19 RTIP4 I Receive Analog Tip Input, Transceiver #4. P1 RVDD1 – Receive Analog Positive Supply. J17 RVDD2 – Receive Analog Positive Supply. E4 RVDD3 – Receive Analog Positive Supply. W18 RVDD4 – Receive Analog Positive Supply. R2 RVSS1 – Receive Analog Signal Ground T2 RVSS1 – Receive Analog Signal Ground H19 RVSS2 – Receive Analog Signal Ground J18 RVSS2 – Receive Analog Signal Ground D4 RVSS3 – Receive Analog Signal Ground D5 RVSS3 – Receive Analog Signal Ground V20 RVSS4 – Receive Analog Signal Ground W19 RVSS4 – Receive Analog Signal Ground W1 TCHBLK1 O Transmit Channel Block, Transceiver #1. F20 TCHBLK2 O Transmit Channel Block, Transceiver #2. C11 TCHBLK3 O Transmit Channel Block, Transceiver #3. U20 TCHBLK4 O Transmit Channel Block, Transceiver #4. V10 TCHCLK1 O Transmit Channel Clock, Transceiver #1. A18 TCHCLK2 O Transmit Channel Clock, Transceiver #2. B8 TCHCLK3 O Transmit Channel Clock, Transceiver #3. L18 TCHCLK4 O Transmit Channel Clock, Transceiver #4. Y9 TCLK1 I Transmit Clock, Transceiver #1. B19 TCLK2 I Transmit Clock, Transceiver #2. B10 TCLK3 I Transmit Clock, Transceiver #3. M19 TCLK4 I Transmit Clock, Transceiver #4. V6 TCLKI1 I Transmit Clock Input for the LIU, Transceiver #1. D19 TCLKI2 I Transmit Clock Input for the LIU, Transceiver #2. C8 TCLKI3 I Transmit Clock Input for the LIU, Transceiver #3. P20 TCLKI4 I Transmit Clock Input for the LIU, Transceiver #4. W7 TCLKO1 O Transmit Clock Output from the Framer, Transceiver #1. E18 TCLKO2 O Transmit Clock Output from the Framer, Transceiver #2. A7 TCLKO3 O Transmit Clock Output from the Framer, Transceiver #3. P19 TCLKO4 O Transmit Clock Output from the Framer, Transceiver #4. V3 TLCLK1 O Transmit Link Clock, Transceiver #1. E20 TLCLK2 O Transmit Link Clock, Transceiver #2. D6 TLCLK3 O Transmit Link Clock, Transceiver #3. T18 TLCLK4 O Transmit Link Clock, Transceiver #4. W5 TLINK1 I Transmit Link Data, Transceiver #1. E19 TLINK2 I Transmit Link Data, Transceiver #2.

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PIN SYMBOL TYPE DESCRIPTION

C6 TLINK3 I Transmit Link Data, Transceiver #3. T19 TLINK4 I Transmit Link Data, Transceiver #4. R1 TNEGI1 I Transmit Negative Data Input for the LIU, Transceiver #1. F19 TNEGI2 I Transmit Negative Data Input for the LIU, Transceiver #2. D8 TNEGI3 I Transmit Negative Data Input for the LIU, Transceiver #3. R20 TNEGI4 I Transmit Negative Data Input for the LIU, Transceiver #4. T3 TNEGO1 O Transmit Negative Data Output from Framer, Transceiver #1. B20 TNEGO2 O Transmit Negative Data Output from Framer, Transceiver #2. D9 TNEGO3 O Transmit Negative Data Output from Framer, Transceiver #3. N20 TNEGO4 O Transmit Negative Data Output from Framer, Transceiver #4. W3 TPOSI1 I Transmit Posit ive Data Input for the LIU, Transceiver #1. C20 TPOSI2 I Transmit Positive Data Input for the LIU, Transceiver #2. A8 TPOSI3 I Transmit Positive Data Input for the LIU, Transceiver #3. R19 TPOSI4 I Transmit Positive Data Input for the LIU, Transceiver # 4. V7 TPOSO1 O Transmit Positive Data Output from Framer, Transceiver #1. C19 TPOSO2 O Transmit Positive Data Output from Framer, Transceiver #2. C9 TPOSO3 O Transmit Positive Data Output from Framer, Transceiver #3. N19 TPOSO4 O Transmit Positive Data Output from Framer, Transceiver #4. Y2 TRING1 O Transmit Analog Ring Output, Transceiver #1. Y4 TRING2 O Transmit Analog Ring Output, Transceiver #2. Y6 TRING3 O Transmit Analog Ring Output, Transceiver #3. Y8 TRING4 O Transmit Analog Ring Output, Transceiver #4. W9 TSER1 I Transmit Serial Data, Transceiver #1. C17 TSER2 I Transmit Serial Data, Transceiver #2. C10 TSER3 I Transmit Serial Data, Transceiver #3. K20 TSER4 I Transmit Serial Data, Transceiver #4. W10 TSIG1 I Transmit Signaling Input, Transceiver #1. C18 TSIG2 I Transmit Signaling Input, Transceiver #2. A10 TSIG3 I Transmit Signaling Input, Transceiver #3. L19 TSIG4 I Transmit Signaling Input, Transceiver #4. W12 TSSYNC1 I Transmit System Sync, Transceiver #1. B18 TSSYNC2 I Transmit System Sync, Transceiver #2. D10 TSSYNC3 I Transmit System Sync, Transceiver #3. K19 TSSYNC4 I Transmit System Sync, Transceiver #4. U16 TSTRST I Test/Reset V1 TSYNC1 I/O Transmit Sync, Transceiver #1. D20 TSYNC2 I/O Transmit Sync, Transceiver #2. C7 TSYNC3 I/O Transmit Sync, Transceiver #3. R18 TSYNC4 I/O Transmit Sync, Transceiver #4. W11 TSYSCLK1 I Transmit System Clock, Transceiver #1. A19 TSYSCLK2 I Transmit System Clock, Transceiver #2. A11 TSYSCLK3 I Transmit System Clock, Transceiver #3. N18 TSYSCLK4 I Transmit System Clock, Transceiver #4. Y1 TTIP1 O Transmit Analog Tip Output, Transceiver #1. Y3 TTIP2 O Transmit Analog Tip Output, Transceiver #2. Y5 TTIP3 O Transmit Analog Tip Output, Transceiver #3. Y7 TTIP4 O Transmit Analog Tip Output, Transceiver #4. W2 TVDD1 – Transmit Analog Positive Supply. G19 TVDD2 – Transmit Analog Positive Supply. D11 TVDD3 – Transmit Analog Positive Supply. U19 TVDD4 – Transmit Analog Positive Supply. W4 TVSS1 – Transmit Analog Signal Ground.

27 of 248 012103

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PIN SYMBOL TYPE DESCRIPTION

G18 TVSS2 – Transmit Analog Signal Ground. C5 TVSS3 – Transmit Analog Signal Ground. U18 TVSS4 – Transmit Analog Signal Ground. K3 WR* (R/W*) I Write Input (Read/Write).

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3.9 Package DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5-1

The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed from the top.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

rnegi 3 rfsync

A

rposo 3 rposi 3 dvdd 3 rclko 3 cs

B

rsig 3 rnego

C

rsync 3 rsigf 3 rlclk 3 rvss 3 rvss 3 tlclk 3 esibs0

D

rlos 3 rser 3 rclk 3 rvdd

E

rlclk 1 rmsync

F

rsync 1 rlink 1 rsysclk

G

rsysclk

H

1

rchclk

J

1

rsigf

K

1

rmsync

L

1

bpclk 1 rchblk

M

jtdi rd*

N

rvdd

P

1

tnegi 1 rvss 1 rnegi 1 rposI

R

mclk 1 rvss 1 tnego

T

int*

U

tsync

V

1

tchblk

W

1

ttip 1 tring 1 ttip 2 tring 2 ttip 3 tring

Y

rlink 3 rclki 3 dvss 3 esibs1

3

eisb rd

3

rlos 1 dvss

rser 1 dvdd 1 eisbrd

liuc wr* rsig 1 rnego

1

bts

dvdd

1

A2

tvdd 1 tposi 1 tvss 1 tlink 1 esibs0

dvdd 3 tvss 3 tlink 3 tsync

3

rchclk

bpclk

3

rchblk

3

a5

1

rfsync

1

rposo

1

rclko 1 rclki

1

rclk 1 dvdd

1

cs

A7/AL

1*

E(AS)

1

A3

1

D7/

A0

AD7

tlclk 1 D6/

AD6

3

dvdd 3 dvss 3 tchclk

3*

A1

D5/

dvss 1 D3/

AD5

dvdd 1 tclki 1 tposo

1

3

tclko

3

AD3

1

tclko 1 dvss 1 tser 1 tsig 1 tsysclk

ttip

4

dvdd 3 tsig 3 tsysclk

tposi

3

dvss 3 tclk 3 dvss 2 dvdd 2 rclk 2 rposi 2 rnego

3

tclki 3 tposo

3

tnegi 3 tnego

3

D4/

A6

AD4

esibs1

A4

1

tring 4 tclk 1 rtip 1 rring 1 rchblk

3

tser 3 tchblk

3

tssync

tvdd 3 rsync 2 rnegi 2 rchclk

3

D0/

mux

AD0

tchclk

rlos 4 rsync 4 bpclk

1

rlclk 2 rlink 2 cs

dvdd 2 eisbrd

2

rlink 4 eisbrd

4

tssync

jtms

1

rtip 2 rring

4

rclki 2 rposo 2 dvss 2 tchclk

2*

rsig 2 esibs1

2

rclko 2 rsigf 2 dvdd 2 tser 2 tsig 2 tposo 2 tposi

rser 2 rmsync

2

rchclk

rposo

4

rfsync

rposi 4 rsigf

4

rsysclk

D2/

4

2

rmsync

AD2 jtclk

2

rfsync

2

rlos 2 tclko 2 tlink 2 tlclk

rsysclk

2

rchblk

2

bpclk

2

rvdd 2 rvss 2 D1/

cs 4*

dvdd 4 rclk 4 tclk 4 dvdd

dvss 4 tsys

rnegi 4 dvdd 4 tclko 4 tclki

rclki 4 tsync

rclko 4 tlclk 4 tlink 4 esibs0

rnego

tstrst

4

NC jtrst* jtdo

4

rser 4 rvdd 4 rvss 4 mclk

4

rtip 3 rring 3 rsig 4 rtip 4 rring

tsysclk

2

tssync

tclk 2 tnego

2

dvdd 2 tclki 2 tsync

esibs0

tnegi 2 tchblk

2

tvss 2 tvdd 2 dvdd

rvss 2 dvss

NC

esibs1

AD1

rlclk 4 tssync

4

tchclk

tsig 4 dvss

4

tposo 4 tnego

clk4

tposi 4 tnegi

4

tvss 4 tvdd 4 tchblk

dvss

2

4

tser

4

rvss

4

2

4

NOTE: Locations C3, C13, J4, and U13 are used for the Extended System Information Bus (ESIB). These pin locations on the DS21Q352, DS21Q354, DS21Q552, and DS21Q554 are connected to ground. When replacing a DS21Qx5y with a DS21Q55B, these signals should be routed to control logic in order to gain access to the ESIB. If these pins remain connected to ground, the ESIB function will be disabled.

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4. PARALLEL PORT

The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details. Each of the four transceivers has a complete register set as shown below. There are four individual Chip Select signals (CS1*, CS2*, CS3*, CS4*) that are used select one of the four transceivers.

4.1 Register Map

REGISTER MAP SORTED BY ADDRESS Table 6-1

ADDRESS R/W REGISTER NAME

00 01 I/O Configuration Register 1 IOCR1 * 02 I/O Configuration Register 2 IOCR2 * 03 T1 Receive Control Register 1 T1RCR1 * 04 T1 Receive Control Register 2 T1RCR2 * 05 T1 Transmit Control Register 1 T1TCR1 * 06 T1 Transmit Control Register 2 T1TCR2 * 07 T1 Common Control Register 1 T1CCR1 * 08 Software Signaling Insertion Enable 1 SSIE1 *

09 Software Signaling Insertion Enable 2 SSIE2 * 0A Software Signaling Insertion Enable 3 SSIE3 * 0B Software Signaling Insertion Enable 4 SSIE4 * 0C T1 Receive Digital Milliwatt Enable Register 1 T1RDMR1 * 0D T1 Receive Digital Milliwatt Enable Register 2 T1RDMR2 *

0E T1 Receive Digital Milliwatt Enable Register 3 T1RDMR3 * 0F Device Identification Register IDR *

10 Information Register 1 INFO1 *

11 Information Register 2 INFO2 *

12 Information Register 3 INFO3 *

13 Test Register TEST *

14 Interrupt Information Register 1 IIR1 *

15 Interrupt Information Register 2 IIR2 *

16 Status Register 1 SR1 *

17 Interrupt Mask Register 1 IMR1 *

18 Status Register 2 SR2 *

19 Interrupt Mask Register 2 IMR2 * 1A Status Register 3 SR3 * 1B Interrupt Mask Register 3 IMR3 * 1C Status Register 4 SR4 * 1D Interrupt Mask Register 4 IMR4 *

1E Status Register 5 SR5 * 1F Interrupt Mask Register 5 IMR5 *

20 Status Register 6 SR6 *

21 Interrupt Mask Register 6 IMR6 *

22 Status Register 7 SR7 *

23 Interrupt Mask Register 7 IMR7 *

24 Status Register 8 SR8 *

25 Interrupt Mask Register 8 IMR8 *

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MASTER MODE REGISTER

REGISTER

ABBREVIATION

MSTRREG *

PAGE

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ADDRESS R/W REGISTER NAME

26 Status Register 9 SR9 *

27 Interrupt Mask Register 9 IMR9 *

28 Per-Channel Pointer Register PCPR *

29 Per-Channel Data Register 1 PCDR1 * 2A Per-Channel Data Register 2 PCDR2 * 2B Per-Channel Data Register 3 PCDR3 * 2C Per-Channel Data Register 4 PCDR4 * 2D Information Register 4 INFO4 *

2E Information Register 5 INFO5 * 2F Information Register 6 INFO6 *

30 Information Register 7 INFO7 *

31 HDLC #1 Receive Control H1RC *

32 HDLC #2 Receive Control H2RC *

33 E1 Receive Control Register 1 E1RCR1 *

34 E1 Receive Control Register 2 E1RCR2 *

35 E1 Transmit Contro l Register 1 E1TCR1 *

36 E1 Transmit Control Register 2 E1TCR2 *

37 BOC Control Register BOCC *

38 Receive Signaling Change Of State Information 1 RSINFO1 *

39 Receive Signaling Change Of State Information 2 RSINFO2 * 3A Receive Signaling Change Of State Information 3 RSINFO3 * 3B Receive Signaling Change Of State Information 4 RSINFO4 * 3C Receive Signaling Change Of State Interrupt Enable 1 RSCSE1 * 3D Receive Signaling Change Of State Interrupt Enable 2 RSCSE2 *

3E Receive Signaling Change Of State Interrupt Enable 3 RSCSE3 * 3F Receive Signaling Change Of State Interrupt Enable 4 RSCSE4 *

40 Signaling Control Register SIGCR *

41 Error Count Configuration Register ERCNT *

42 Line Code Violation Count Register 1 LCVCR1 *

43 Line Code Violation Count Register 2 LCVCR2 *

44 Path Code Violation Count Register 1 PCVCR1 *

45 Path Code Violation Count Register 2 PCVCR2 *

46 Frames Out of Sync Count Register 1 FOSCR1 *

47 Frames Out of Sync Count Register 2 FOSCR2 *

48 E-Bit Count Register 1 EBCR1 *

49 E-Bit Count Register 2 EBCR2 * 4A Loopback Control Register LBCR * 4B Per-Channel Loopback Enable Register 1 PCLR1 * 4C Per-Channel Loopback Enable Register 2 PCLR2 * 4D Per-Channel Loopback Enable Register 3 PCLR3 *

4E Per-Channel Loopback Enable Register 4 PCLR4 * 4F Elastic Store Control Register ESCR *

50 Transmit Signaling Register 1 TS1 *

51 Transmit Signaling Register 2 TS2 *

52 Transmit Signaling Register 3 TS3 *

53 Transmit Signaling Register 4 TS4 *

54 Transmit Signaling Register 5 TS5 *

55 Transmit Signaling Register 6 TS6 *

56 Transmit Signaling Register 7 TS7 *

57 Transmit Signaling Register 8 TS8 *

58 Transmit Signaling Register 9 TS9 *

59 Transmit Signaling Register 10 TS10 *

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REGISTER

ABBREVIATION

PAGE

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ADDRESS R/W REGISTER NAME

5A Transmit Signaling Register 11 TS11 * 5B Transmit Signaling Register 12 TS12 * 5C Transmit Signaling Register 13 TS13 * 5D Transmit Signaling Register 14 TS14 *

5E Transmit Signaling Register 15 TS15 * 5F Transmit Signaling Register 16 TS16 *

60 Receive Signaling Register 1 RS1 *

61 Receive Signaling Register 2 RS2 *

62 Receive Signaling Register 3 RS3 *

63 Receive Signaling Register 4 RS4 *

64 Receive Signaling Register 5 RS5 *

65 Receive Signaling Register 6 RS6 *

66 Receive Signaling Register 7 RS7 *

67 Receive Signaling Register 8 RS8 *

68 Receive Signaling Register 9 RS9 *

69 Receive Signaling Register 10 RS10 * 6A Receive Signaling Register 11 RS11 * 6B Receive Signaling Register 12 RS12 * 6C Receive Signaling Register 13 RS13 * 6D Receive Signaling Register 14 RS14 *

6E Receive Signaling Register 15 RS15 * 6F Receive Signaling Register 16 RS16 *

70 Common Control Register 1 CCR1 *

71 Common Control Register 2 CCR2 *

72 Common Control Register 3 CCR3 *

73 Common Control Register 4 CCR4 *

74 Transmit Channel Monitor Select TDS0SEL *

75 Transmit DS0 Monitor Register TDS0M *

76 Receive Channel Monitor Select RDS0SEL *

77 Receive DS0 Monitor Register RDS0M *

78 Line Interface Control 1 LIC1 *

79 Line Interface Control 2 LIC2 * 7A Line Interface Control 3 LIC3 * 7B Line Interface Control 4 LIC4 * 7C Test Register TEST * 7D Transmit Line Build -Out Control TLBC *

7E Idle Array Address Register IAAR * 7F Per-Channel Idle Code Value Register PCICR *

80 Transmit Idle Code Enable Register 1 TCICE1 *

81 Transmit Idle Code Enable Register 2 TCICE2 *

82 Transmit Idle Code Enable Register 3 TCICE3 *

83 Transmit Idle Code Enable Register 4 TCICE4 *

84 Receive Idle Code Enable Register 1 RCICE1 *

85 Receive Idle Code Enable Register 2 RCICE2 *

86 Receive Idle Code Enable Register 3 RCICE3 *

87 Receive Idle Code Enable Register 4 RCICE4 *

88 Receive Channel Blocking Register 1 RCBR1 *

89 Receive Channel Blocking Register 2 RCBR2 * 8A Receive Channel Blocking Register 3 RCBR3 * 8B Receive Channel Blocking Register 4 RCBR4 * 8C Transmit Channel Blocking Register 1 TCBR1 * 8D Transmit Channel Blocking Register 2 TCBR2 *

32 of 248 012103

REGISTER

ABBREVIATION

PAGE

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ADDRESS R/W REGISTER NAME

8E Transmit Channel Blocking Register 3 TCBR3 * 8F Transmit Channel Blocking Register 4 TCBR4 *

90 HDLC #1 Transmit Control H1TC *

91 HDLC #1 FIFO Control H1FC *

92 HDLC #1 Receive Channel Select 1 H1RCS1 *

93 HDLC #1 Receive Channel Select 2 H1RCS2 *

94 HDLC #1 Receive Channel Select 3 H1RCS3 *

95 HDLC #1 Receive Channel Select 4 H1RCS4 *

96 HDLC #1 Receive Time Slot Bits/Sa Bits Select H1RTSBS *

97 HDLC #1 Transmit Channel Select1 H1TCS1 *

98 HDLC #1 Transmit Channel Select 2 H1TCS2 *

99 HDLC #1 Transmit Channel Select 3 H1TCS3 * 9A HDLC #1 Transmit Channel Select 4 H1TCS4 * 9B HDLC #1 Transmit Time Slot Bits/Sa Bits Select H1TTSBS * 9C HDLC #1 Receive Packet Bytes Available H1RPBA * 9D HDLC #1 Transmit FIFO H1TF *

9E HDLC #1 Receive FIFO H1RF *

9F HDLC #1 Transmit FIFO Buffer Available H1TFBA * A0 HDLC #2 Transmit Control H2TC * A1 HDLC #2 FIFO Control H2FC * A2 HDLC #2 Receive Channel Select 1 H2RCS1 * A3 HDLC #2 Receive Channel Select 2 H2RCS2 * A4 HDLC #2 Receive Channel Select 3 H2RCS3 * A5 HDLC #2 Receive Channel Select 4 H2RCS4 * A6 HDLC #2 Receive Time Slot Bits/Sa Bits Select H2RTSBS * A7 HDLC #2 Transmit Channel Select 1 H2TCS1 * A8 HDLC #2 Transmit Channel Select 2 H2TCS2 * A9 HDLC #2 Transmit Channel Select 3 H2TCS3 *

AA HDLC #2 Transmit Channel Select 4 H2TCS4 *

AB HDLC #2 Transmit Time Slot Bits/Sa Bits Select H2TTSBS * AC HDLC #2 Receive Packet Bytes Available H2RPBA *

AD HDLC #2 Transmit FIFO H2TF *

AE HDLC #2 Receive FIFO H2RF * AF HDLC #2 Transmit FIFO Buffer Available H2TFBA *

B0 Extend System Information Bus Control Register 1 ESIBCR1 * B1 Extend System Information Bus Control Register 2 ESIBCR2 * B2 Extend System Information Bus Register 1 ESIB1 * B3 Extend System Information Bus Register 2 ESIB2 * B4 Extend System Information Bus Register 3 ESIB3 * B5 Extend System Information Bus Register 4 ESIB4 * B6 In-Band Code Control Register IBCC * B7 Transmit Code Definition Register 1 TCD1 * B8 Transmit Code Definition Register 2 TCD2 * B9 Receive Up Code Definition Re gister 1 RUPCD1 *

BA Receive Up Code Definition Register 2 RUPCD2 * BB Receive Down Code Definition Register 1 RDNCD1 * BC Receive Down Code Definition Register 2 RDNCD2 * BD In-Band Receive Spare Control Register RSCC *

BE Receive Spare Code Definition Register 1 RSCD1 * BF Receive Spare Code Definition Register 2 RSCD2 * C0 Receive FDL Register RFDL * C1 Transmit FDL Register TFDL *

33 of 248 012103

REGISTER

ABBREVIATION

PAGE

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ADDRESS R/W REGISTER NAME

C2 Receive FDL Match Register 1 RFDLM1 * C3 Receive FDL Match Register 2 RFDLM2 * C4 Test Register TEST * C5 Interleave Bus Operation Control Register IBOC * C6 Receive Align Frame Register RAF * C7 Receive Nonalign Frame Register RNAF * C8 Receive Si Align Frame RSiAF * C9 Receive Si Nonalign Frame RSiNAF *

CA Receive Remote Alarm Bits RRA * CB Receive Sa4 Bits RSa4 * CC Receive Sa5 Bits RSa5 * CD Receive Sa6 Bits RSa6 *

CE Receive Sa7 Bits RSa7 * CF Receive Sa8 Bits RSa8 * D0 Transmit Align Frame Register TAF * D1 Transmit Nonalign Frame Register TNAF * D2 Transmit Si Align Frame TSiAF * D3 Transmit Si Nonalign Frame TSiNAF * D4 Transmit Remote Alarm Bits TRA * D5 Transmit Sa4 Bits TSa4 * D6 Transmit Sa5 Bits TSa5 * D7 Transmit Sa6 Bits TSa6 * D8 Transmit Sa7 Bits TSa7 * D9 Transmit Sa8 Bits TSa8 *

DA Transmit Sa Bit Control Register TSACR *

DB BERT Alternating Word Count Rate BAWC * DC BERT Repetitive Pattern Set Register 1 BRP1 * DD BERT Repetitive Pattern Set Register 2 BRP2 * DE BERT Repetitive Pattern Set Register 3 BRP3 *

DF BERT Repetitive Pattern Set Register 4 BRP4 *

E0 BERT Control Register 1 BC1 *

E1 BERT Control Register 2 BC2 *

E2 Test Register TEST *

E3 BERT Bit Count Register 1 BBC1 *

E4 BERT Bit Count Register 2 BBC2 *

E5 BERT Bit Count Register 3 BBC3 *

E6 BERT Bit Count Register 4 BBC4 *

E7 BERT Error Count Register 1 BEC1 *

E8 BERT Error Count Register 2 BEC2 *

E9 BERT Error Count Register 3 BEC3 *

EA BERT Interface Control Register BIC *

EB Error Rate Control Register ERC * EC Number Of Errors 1 NOE1 *

ED Number Of Errors 2 NOE2 *

EE Number Of Errors Left 1 NOEL1 * EF Number Of Errors Left 2 NOEL2 *

F0 Test Register TEST *

F1 Test Register TEST *

F2 Test Register TEST *

F3 Test Register TEST *

F4 Test Register TEST *

F5 Test Register TEST *

34 of 248 012103

REGISTER

ABBREVIATION

PAGE

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ADDRESS R/W REGISTER NAME

F6 Test Register TEST *

F7 Test Register TEST *

F8 Test Register TEST *

F9 Test Register TEST *

FA Test Register TEST *

FB Test Register TEST * FC Test Register TEST * FD Test Register TEST * FE Test Register TEST *

FF Test Register TEST *

*TEST1 to TEST16 registers are used only by the factory.

REGISTER

ABBREVIATION

PAGE

35 of 248 012103

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5. SPECIAL PER -CHANNEL REGISTER OPERATION

Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. The registers involved are the per-channel pointer registers (PCPR) and per-channel data registers 1 to 4 (PCDR1 –4). The user selects the function(s) that are to be applied on a per-channel basis by setting the appropriate bit(s) in the PCPR register. The user then writes to the PCDR registers to select the channels for that function. The following is an example of mapping the transmit and receive BERT function to channels 9, 10, 11, 12, 20, and 21:

Write 11h to PCPR Write 00h to PCDR1 Write 0fh to PCDR2 Write 18h to PCDR3 Write 00h to PCDR4

More information about how to use these per-channel features can be found in their respective sections in the data sheet.

Register Name: PCPR Register Description: Per-Channel Pointer Register Register Address: 28h

Bit # 7 6 5 4 3 2 1 0 Name RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS Default 0 0 0 0 0 0 0 0

Bit 0/BERT Transmit Channel Select (BTCS). Bit 1/Transmit Fractional Channel Select (TFCS).

Bit 2/Payload Error Insert Channel Select (PEICS).

Bit 3/Transmit Hardware Signaling Channel Select (THSCS).

Bit 4/BERT Receive Channel Select (BRCS).

Bit 5/Receive Fractional Channel Select (RFCS).

Bit 6/Receive Signaling Reinsertion Channel Select (RSRCS).

Bit 7/Receive Signaling All Ones Insertion Channel Select (RSAOI CS).

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Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h

Bit # 7 6 5 4 3 2 1 0 Name Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

Register Name: PCDR2 Register Description: Per-Channel Data Register 2 Register Address: 2Ah

Bit # 7 6 5 4 3 2 1 0 Name Default CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9

Register Name: PCDR3 Register Description: Per-Channel Data Register 3 Register Address: 2Bh

Bit # 7 6 5 4 3 2 1 0 Name Default CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

Register Name: PCDR4 Register Description: Per-Channel Data Register 4 Register Address: 2Ch

Bit # 7 6 5 4 3 2 1 0 Name Default CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25

37 of 248 012103

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Power

-On

6. PROGRAMMING MODEL

The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions, and enabling the common functions. The act of resetting the device automatically clears all configuration and status registers. Therefore, it is not necessary to load unused registers with zeros.

PROGRAMMING SEQUENCE Figure 8-1

Select T1 or E1 Operation in Master Mode Register

Issue Reset

Program T1 Specific Registers

Program Common Registers

Program E1 Specific Registers

DS21Q55 Operational

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6.1 Power-Up Sequence

The DS21Q55 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt traffic until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the line interface circuitry. (It will take the DS21Q55 about 40ms to recover from the LIRST bit being toggled.) Finally, after the TSYSCLK and RSYSCLK inputs are stable, the receive and transmit elastic stores sho uld be reset (this step can be skipped if the elastic stores are disabled).

6.1.1 Master Mode Register

Register Name: MSTRREG Register Description: Master Mode Register Register Address: 00h

Bit # 7 6 5 4 3 2 1 0 Name - - - - TEST1 TEST0 T1/E1 SFTRST Default 0 0 0 0 0 0 0 0

Bit 0/Software Issued Reset (SFTRST).

A 0 to 1 transition causes the register space to be cleared. A reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.

Bit 1/Operating Mode (T1/E1).

Used to select the operating mode of the framer/formatter (digital) portion of the 21Q55. The operating mode of the LIU must also be programmed.

0 = T1 operation 1 = E1 operation

Bits 2, 3/Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the 21Q55 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses.

TEST1 TEST0 EFFECT ON OUTPUT PINS

0 0 Operate normally 0 1 Force all output pins into tristate (including all I/O pins and parallel port pins) 1 0 Force all output pins low (including all I/O pins except parallel port pins) 1 1 Force all output pins high (including all I/O pins except parallel port pins)

Bits 4–7/Unused, must be set to zero for proper operation.

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6.2 Interrupt Handling

Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only so urces of interrupts. On power-up, all writeable registers are automatically cleared. Since bits in the IMRx registers have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host selects which events are to product interrupts. Since there are potentially many sources of interrupts, several features are available to help sort out and identify which event is causing an interrupt. When an interrupt occurs, the host should first read the IIR1, IIR2, and IIR3 registers (interrupt information registers) to identify which status register(s) is producing the interrupt. Once that is determined, the individual status register or registers can be examined to determine the exact source. In eight port configurations, two DS21Q55s can be connected together via the 3-wire ESIB feature. This allows all eight transceivers to be interrogated by a single CPU port read cycle. The host can determine the synchronization status or interrupt status of all eight devices with a single read. The ESIB feature also allows the user to select from various events to be examined via this method. For more information, see the ESIB section in this data sheet.

Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt hander routine should re-enable interrupts by setting the INTDIS bit = 0.

6.3 Status Registers

When a particular event or condition has occurred (or is still occurring in the case of conditions), the appropriate bit in a status register will be set to a one. All of the status registers operate in a latched fashion, which means that if an event or condition occurs a bit is set to a one . It will remain set until the user reads that bit. An event bit will be cleared when it is read and it will not be set again until the event has occurred again. Condition bits such as RBL, RLOS, etc., will remain set if the alarm is still present.

The user will always proceed a read of any of the status registers with a write. The byte written to the register will inform the DS21Q55 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status registers will be immediately followed by a read of the same register. This write-read scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q55 with higher order languages.

Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically network conditions such as loss of sync, or all ones detect. Event bits are typically markers such as the one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit. Some of the status registers have bits for both the detection of a condition and the clearance of the condition. For example, SR2 has a bit that is set when the device goes into a loss of sync state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit ) when the loss of sync condition clears (goes in sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce interrupts on both edges, setting, and clearing. These bits are

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marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it clears.

6.4 Information Registers

Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read only register and it reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6 and INFO5 are not latched and it is not necessary to precede a read of these bits with a write.

6.5 Interrupt Information Registers

The Interrupt Information Registers provide an indication of which Status Registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read IIR1 and IIR2 to quickly identify which of the 9 status registers are causing the interrupt.

Register Name: IIR1 Register Description: Interrupt Information Register 1 Register Address: 14h

Bit # 7 6 5 4 3 2 1 0 Name SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 Default 0 0 0 0 0 0 0 0

Register Name: IIR2 Register Description: Interrupt Information Register 2 Register Address: 15h

Bit # 7 6 5 4 3 2 1 0 Name - - - - - - - SR9 Default 0 0 0 0 0 0 0 0

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BPCLK

7. CLOCK MAP

Figure 9-1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity.

CLOCK MAP Figure 9- 1

MCLK

LLB = 0

LLB = 1

LIC4.MPS0 LIC4.MPS1

LIC2.3

JITTER ATTENUATOR SEE LIC1 REGISTER

LTCA

JAS = 0 OR DJA = 1

JAS = 1 AND DJA = 0

JAS = 0 AND DJA = 0

JAS = 1 OR DJA = 1

LTCA

REMOTE LOOPBACK

RLB = 1

RLB = 0

DJA = 1

DJA = 0

FRAMER LOOPBACK

FLB = 0

FLB = 1

RECEIVE FRAMER

TRANSMIT FORMATTER

PAYLOAD LOOPBACK (SEE NOTES)

PLB = 1

PLB = 0

BPCLK SYNTH

8XCLK8 x PLL

RCLK

RXCLK

TO LIU

TXCLK

PRE-SCALER

2.048 TO 1.544 SYNTHESIZER

RCL = 1

RCL = 0

LOCAL LOOPBACK

TCLK MUX

BA

C

TCLK

The TCLK MUX is dependent on the state of the TCSS0 and TCSS1 bits in the LIC1 register and the state of the TCLK pin.

TCSS1 TCSS0 TRANSMIT CLOCK SOURCE

0 0 The TCLK pin (C) is always the source of Transmit Clock. 0 1 Switch to the recovered clock (B) when the signal at the TCLK pin fails to

transition after 1 channel time.

1 0 Use the scaled signal (A) derived from MCLK as the Transmit Clock. The TCLK

pin is ignored.

1 1 Use the recovered clock (B) as the Transmit Clock. The TCLK pin is ignored.

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8. T1 FRAMER/FORMATTER CONTROL REGISTERS

The T1 framer portion of the DS21Q55 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two receive-control registers (T1RCR1 and T1RCR2), two transmit control registers (T1TCR1 and T1TCR2), and a common control register (T1CCR1). Each of these registers is described in this section.

8.1 T1 Control Registers

Register Name: T1RCR1 Register Description: T1 Receive Control Register 1 Register Address: 03h

Bit # 7 6 5 4 3 2 1 0 Name - ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC Default 0 0 0 0 0 0 0 0

Bit 0/Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.

Bit 1/Sync Enable (SYNCE).

0 = auto resync enabled 1 = auto resync disabled

Bit 2/Sync Time (SYNCT).

0 = qualify 10 bits 1 = qualify 24 bits

Bit 3/Sync Criteria (SYNCC).

In D4 Framing Mode.

0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6

Bits 4 to 5/Out Of Frame Select Bits (OOF2, OOF1).

OOF2 OOF1 OUT OF FRAME CRITERIA

0 0 2/4 frame bits in error 0 1 2/5 frame bits in error 1 0 2/6 frame bits in error 1 1 2/6 frame bits in error

Bit 6/Auto Resync Criteria (ARC).

0 = resync on OOF or RCL event 1 = resync on OOF only

Bit 7/Unused, must be set to zero for proper operation.

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Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 04h

Bit # 7 6 5 4 3 2 1 0 Name - RFM RB8ZS RSLC96 RZSE RZBTSI RJC RD4YM Default 0 0 0 0 0 0 0 0

Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM).

0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)

Bit 1/Receive Japanese CRC6 Enable (RJC).

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation

Bit 2/Receive Side ZBTSI Support Enable (RZBTSI). Allows ZBTSI information to be output on RLINK pin.

0 = ZBTSI disabled 1 = ZBTSI enabled

Bit 3/Receive FDL Zero Destuffer Enable (RZSE). Set this bit to zero if using the internal HDLC/BOC controller instead of the legacy support for the FDL. See Legacy FDL Support (T1 Mode) for details.

0 = zero destuffer disabled 1 = zero destuffer enabled

Bit 4/Receive SLC –96 Enable (RSLC96). Only set this bit to a one in SLC–96 framing applications. See D4/SLC–96 Operation for details.

0 = SLC– 96 disabled 1 = SLC– 96 enabled

Bit 5/Receive B8ZS Enable (RB8ZS).

0 = B8ZS disabled 1 = B8ZS enabled

Bit 6/Receive Frame Mode Select (RFM).

0 = D4 framing mode 1 = ESF framing mode

Bit 7/Unused, must be set to zero for proper operation.

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Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h

Bit # 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL Default 0 0 0 0 0 0 0 0

Bit 0/Transmit Yellow Alarm (TYEL).

0 = do not transmit yellow alarm 1 = transmit yellow alarm

Bit 1/Transmit Blue Alarm (TBL).

0 = transmit data normally 1 = transmit an unframed all one’s code at TPOS and TNEG

Bit 2/TFDL Register Select (TFDLS).

0 = source FDL or Fs bits from the internal TFDL register (legacy FDL support mode) 1 = source FDL or Fs bits from the internal HDLC controller or the TLINK pin

Bit 3/Global Bit 7 Stuffing (GB7S).

0 = allow the SSIEx registers to determine which channels containing all zeros are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all zero byte channels regardless of how the SSIEx registers are programmed

Bit 4/Transmit Software Signaling Enable (TSSE).

0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still define which channels are to have B7 stuffing preformed 1 = source signaling data as enabled by the SSIEx registers

Bit 5/Transmit CRC Pass Through (TCPT).

0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time

Bit 6/Transmit F-Bit Pass Through (TFPT).

0 = F bits sourced internally 1 = F bits sampled at TSER

Bit 7/Transmit Japanese CRC6 Enable (TJC).

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation

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Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h

Bit # 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM TZBTSI TB7ZS Default 0 0 0 0 0 0 0 0

Bit 0/Transmit Side Bit 7 Zero Suppression Enable (TB7ZS).

0 = no stuffing occurs 1 = Bit 7 force to a one in channels with all zeros

Bit 1/Transmit Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.

0 = ZBTSI disabled 1 = ZBTSI enabled

Bit 2/Transmit Side D4 Yellow Alarm Select (TD4YM).

0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12

Bit 3/F -Bit Corruption Type 1. (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted, causing the remote end to experience a loss of synchronization.

Bit 4/F -Bit Corruption Type 2. (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.

Bit 5/Transmit FDL Zero Stuffer Enable (TZSE). Set this bit to zero if using the internal HDLC controller instead of the legacy support for the FDL. See I/O Pin Configuration Options for details.

0 = ze ro stuffer disabled 1 = zero stuffer enabled

Bit 6/Transmit SLC–96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a one in D4 framing and SLC-96 applications. Must be set to one to source the Fs pattern from the TFDL register. See D4/SLC –96 Operation for details.

0 = SLC– 96/Fs-bit insertion disabled 1 = SLC– 96/Fs-bit insertion enabled

Bit 7/Transmit B8ZS Enable (TB8ZS).

0 = B8ZS disabled 1 = B8ZS enabled

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Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h

Bit # 7 6 5 4 3 2 1 0 Name - - - - - TFM PDE TLOOP Default 0 0 0 0 0 0 0 0

Bit 0/Transmit Loop Code Enable (TLOOP). See Programmable In-Band Loop Codes Generation and Detection for details.

0 = transmit data normally 1 = repla ce normal transmitted data with repeating code as defined in registers TCD1 and TCD2

Bit 1/Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data streams for violations of the following rules, which are required by ANSI T1.403: no more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and receive data streams are reported in the INFO1.6 and INFO1.7 bits respectively. When this bit is set to one, the device will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.

0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer

Bit 2/Transmit Frame Mode Select (TFM).

0 = D4 framing mode 1 = ESF framing mode

Bit 3/Unused, must be set to zero for proper operation.

Bit 4/U nused, must be set to zero for proper operation.

Bit 5/Unused, must be set to zero for proper operation.

Bit 6/Unused, must be set to zero for proper operation.

Bit 7/Unused, must be set to zero for proper operation.

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8.2 T1 Transmit Transparency

The software-signaling insertion-enable registers, SSIE1 –SSIE4, can be used to select signaling insertion from the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signa ling registers for that channel.

In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels. If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a zero when a yellow alarm is transmitted. Also, the user has the option to globally override the SSIEx registers from determining which channels are to have bit 7 stuffing performed. If the T1TCR1.3 and T1TCR2.0 bits are set to one, then all 24 T1 channels will have bit 7 stuffing performed on them, regardless of how the SSIEx registers are programmed. In this manner, the SSIEx registers are only affecting channels that are to have robbed-bit signaling inserted into them.

8.3 T1 Receive- Side Digital-Milliwatt Code Generation

Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers represents a particular channel. If a bit is set to a one, then the receive data in that channel will be replaced with the digital-milliwatt code. If a bit is set to zero, no replacement occurs.

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Register Name: T1RDMR1 Register Description: T1 Receive Digital Milliwatt Enable Register 1 Register Address: 0Ch

Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 1 to 8 (CH1 to CH8).

0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code

Register Name: T1RDMR2 Register Description: T1 Receive Digital Milliwatt Enable Register 2 Register Address: 0Dh

Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 9 to 16 (CH9 to CH16).

0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code

Register Name: T1RDMR3 Register Description: T1 Receive Digital Milliwatt Enable Register 3 Register Address: 0Eh

Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 17 to 24 (CH17 to CH24).

0 = do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital-milliwatt code

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8.4 T1 Information Register

Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h

Bit # 7 6 5 4 3 2 1 0 Name RPDV TPDV COFA 8ZD 16ZD SEFE B8ZS FBE Default 0 0 0 0 0 0 0 0

Bit 0/Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.

Bit 1/B8ZS Code Word Detect Event (B8ZS). Set when a B8ZS code word is detected at RPOS and RNEG independent of

whether the B8ZS mode is selected or not via T1TCR2.7. Useful for automatically setting the line coding.

Bit 2/Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in error.

Bit 3/Sixteen Zero Detect Event (16ZD). Set when a string of at least 16 consecutive zeros (regardless of the length of the

string) have been received at RPOSI and RNEGI.

Bit 4/Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RPOSI and RNEGI.

Bit 5/Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe alignment.

Bit 6/Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the AN SI T1.403 requirements for pulse density.

Bit 7/Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density.

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T1 ALARM CRITERIA Table 10- 1

ALARM SET CRITERIA CLEAR CRITERIA

Blue Alarm (AIS) (Note 1) Over a 3ms window, five or fewer

zeros are received

Yellow Alarm (RAI)

D4 Bit -2 Mode (T1RCR2.0 = 0)

D4 12th F-bit Mode (T1RCR2.0 = 1; this mode is also referred to as the “Japanese Yellow Alarm”)

ESF Mode

Red Alarm (LRCL) (Also referred to as Loss Of Signal)

Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences

12th framing bit is set to one for two consecutive occurrences

16 consecutive patterns of 00FF appear in the FDL

192 consecutive zeros are received

Over a 3ms window, six or more zeros are received

Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences

12th framing bit is set to zero for two consecutive occurrences

14 or fewer patterns of 00FF hex out of 16 possible appear in the FDL

14 or more ones out of 112 possible bit positions are received, starting with the first one received

NOTES:

1) The definition of blue alarm (or alarm indication signal) is an unframed, all-ones signal. Blue alarm

detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not

falsely trigger on a framed, all-ones signal. The blue alarm criteria in the DS21Q55 has been set to

achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.

2) ANSI specifications use a different nomenclature than this data sheet does; the following terms are

equivalent:

RBL = AIS RCL = LOS RLOS = LOF RYEL = RAI

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9. E1 FRAMER/FORMATTER CONTROL REGISTERS

The E1 framer portion of the DS21Q55 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two receive control registers (E1RCR1 and E1RCR2) and two transmit control registers (E1TCR1 and E1TCR2). There are also four status and information registers. Each of these eight registers are described in this section.

9.1 E1 Control Registers

Register Name: E1RCR1 Register Description: E1 Receive Control Register 1 Register Address: 33h

Bit # 7 6 5 4 3 2 1 0 Name RSERC RSIGM RHDB3 RG802 RCRC4 FRC SYNCE RESYNC Default 0 0 0 0 0 0 0 0

Bit 0/Resync (RESYNC). When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.

Bit 1/Sync Enable (SYNCE).

0 = auto resync enabled 1 = auto resync disabled

Bit 2/Frame Resync Criteria (FRC).

0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times

Bit 3/Receive CRC4 Enable (RCRC4).

0 = CRC4 disabled 1 = CRC4 enabled

Bit 4/Receive G.802 Enable (RG802). See Signaling Operation for details.

0 = do not force RCHBLK high during bit 1 of timeslot 26 1 = force RCHBLK high during bit 1 of timeslot 26

Bit 5/Receive HDB3 Enable (RHDB3).

0 = HDB3 disabled 1 = HDB3 enabled

Bit 6/Receive Signaling Mode Select (RSIGM).

0 = CAS signaling mode 1 = CCS signaling mode

Bit 7/RSER Control (RSERC).

0 = allow RSER to output data as received under all conditions 1 = force RSER to one under loss of frame alignment conditions

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E1 SYNC/RESYNC CRITERIA Table 11-1

FRAME OR

MULTIFRAME

LEVEL

FAS FAS present in frame N

CRC4 Two valid MF alignment

CAS Valid MF alignment word

Register Name: E1RCR2 Register Description: E1 Receive Control Register 2 Register Address: 34h

Bit # 7 6 5 4 3 2 1 0 Name Sa8S Sa7S Sa6S Sa5S Sa4S - - RCLA Default 0 0 0 0 0 0 0 0

Bit 0/Receive Carrier Loss (RCL) Alte rnate Criteria (RCLA). Defines the criteria for a Receive Carrier Loss condition for both the framer and Line Interface (LIU)

0 = RCL declared upon 255 consecutive zeros (125µs) 1 = RCL declared upon 2048 consecutive zeros (1ms)

Bit 1/Unused, must be set to zero for proper operation.

Bit 2/Unused, must be set to zero for proper operation.

Bit 3/Sa4-Bit Select(Sa4S). Set to one to have RLCLK pulse at the Sa4-bit position; set to zero to force RLCLK low during Sa4-bit position. See Functional Timing Diagrams for details.

Bit 4/Sa5-Bit Select(Sa5S). Set to one to have RLCLK pulse at the Sa5-bit position; set to zero to force RLCLK low during Sa5-bit position. See Functional Timing Diagrams for details.

Bit 5/Sa6-Bit Select(Sa6S). Set to one to have RLCLK pulse at the Sa6-bit position; set to zero to force RLCLK low during

Sa6-bit position. See Functional Timing Diagrams for details.

Bit 6/Sa7-Bit Select(Sa7S). Set to one to have RLCLK pulse at the Sa7-bit position; set to zero to force RLCLK low during Sa7-bit position. See Functional Timing Diagrams for details.

Bit 7/Sa8-Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8 -bit position; set to zero to force RLCLK low during Sa8-bit position. See Functional Timing Diagrams for details.

SYNC CRITERIA RESYNC CRITERIA ITU SPEC.

and N + 2, and FAS not present in frame N + 1

Three consecutive incorrect FAS received

G.706

Alternate: (E1RCR1.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of nonFAS received

words found within 8ms

found and previous

915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error

G.706

4.2 and 4.3.2 G.732 5.2

timeslot 16 contains code other than all zeros

4.1.1

4.1.2

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Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h

Bit # 7 6 5 4 3 2 1 0 Name TFPT T16S TUA1 TSiS TSA1 THDB3 TG802 TCRC4 Default 0 0 0 0 0 0 0 0

Bit 0/Transmit CRC4 Enable (TCRC4).

0 = CRC4 disabled 1 = CRC4 enabled

Bit 1/Transmit G.802 Enable (TG802). See Functional Timing Diagrams for details.

0 = do not force TCHBLK high during bit 1 of timeslot 26 1 = force TCHBLK high during bit 1 of timeslot 26

Bit 2/Transmit HDB3 Enable (THDB3).

0 = HDB3 disabled 1 = HDB3 enabled

Bit 3/Transmit Signaling All Ones (TSA1).

0 = normal operation 1 = force timeslot 16 in every frame to all ones

Bit 4/Transmit International Bit Select (TSiS).

0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, E1TCR1.7 must be set to zero)

Bit 5/Transmit Unframed All Ones (TUA1).

0 = transmit data normally 1 = transmit an unframed all one’s code at TPOSO and TNEGO

Bit 6/Transmit Timeslot 16 Data Select (T16S). See Transmit Signaling for details

0 = timeslot 16 determined by the SSIEx registers and the THSCS function in the PCPR register 1 = source timeslot 16 from TS1 to TS16 registers

Bit 7/Transmit Timeslot 0 Pass Through (TFPT).

0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

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Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h

Bit # 7 6 5 4 3 2 1 0 Name Sa8S Sa7S Sa6S Sa5S Sa4S AEBE AAIS ARA Default 0 0 0 0 0 0 0 0

Bit 0/Automatic Remote Alarm Generation (ARA).

0 = disabled 1 = enabled

Bit 1/Automatic AIS Generation (AAIS).

0 = disabled 1 = enabled

Bit 2/Automatic E-Bit Enable (AEBE).

0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction

Bit 3/Sa4-Bit Select (Sa4S). Set to one to source the Sa4 bit from the TLINK pin; set to zero to not source the Sa4 bit. See Functional Timing Diagrams for details.

Bit 4/Sa5-Bit Select (Sa5S). Set to one to source the Sa5 bit from the TLINK pin; set to zero to not source the Sa5 bit. See Functional Timing Diagrams for details.

Bit 5/Sa6-Bit Select (Sa6S). Set to one to source the Sa6 bit from the TLINK pin; set to zero to not source the Sa6 bit. See

Functional Timing Diagrams for details.

Bit 6/Sa7-Bit Select (Sa7S). Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. See Functional Timing Diagrams for details.

Bit 7/Sa8-Bit Select (Sa8S). Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit. See

Functional Timing Diagrams for details.

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9.2 Automatic Alarm Generation

The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS or remote alarm.

When automatic RAI generation is enabled (E1TCR2.0 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm will be transmitted if the DS21Q55 cannot find CRC4 multiframe synchronization within 400ms as per G.706.

Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled at the same time.

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9.3 E1 Information Registers

Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h

Bit # 7 6 5 4 3 2 1 0 Name - - - - - CRCRC FASRC CASRC Default 0 0 0 0 0 0 0 0

Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error.

Bit 1/FAS Resync Criteria Me t Event (FASRC. Set when three consecutive FAS words are received in error.

Bit 2/CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 code words are received in error.

Register Name: INFO7 Register Description: Information Register 7 (Real Time) Register Address: 30h

Bit # 7 6 5 4 3 2 1 0 Name CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA Default 0 0 0 0 0 0 0 0

Bit 0/CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word.

Bit 1/CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.

Bit 2/FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.

Bit 3 to 7/CRC4 Sync Counter Bits (CSC0 and CSC2 to CSC4 ). The CRC4 sync counter increments each time the 8ms-

CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then the search should be ab andoned and proper action taken. The CRC4 sync counter will rollover. CSC0 is the LSB of the 6-bit counter. (Note: The second LSB, CSC1, is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits.)

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E1 ALARM CRITERIA Table 11- 2

ALARM SET CRITERIA CLEAR CRITERIA

RLOS An RLOS condition exists on power-

up prior to initial synchronization, when a re-sync criteria has been met, or when a manual re-sync has been initiated via E1RCR1.0

RCL

RRA Bit 3 of nonalign frame set to one for

255 or 2048 consecutive zeros received as determined by E1RCR2.0

three consecutive occasions

In 255-bit times, at least 32 ones are received

Bit 3 of nonalign frame set to zero for three consecutive occasions

RUA1 Fewer than three zeros in two frames

(512 bits)

RDMA Bit 6 of timeslot 16 in frame 0 has

More than two zeros in two frames (512 bits)

been set for two consecutive multiframes

V52LNK Two out of three Sa7 bits are zero G.965

ITU

SPEC.

G.775/G.962

O.162

2.1.4

O.162

1.6.1.2

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10. COMMON CONTROL AND STATUS REGISTERS

Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h

Bit # 7 6 5 4 3 2 1 0 Name - CRC4R SIE ODM DICAI TCSS1 TCSS0 RLOSF Default 0 0 0 0 0 0 0 0

Bit 0/Function of the RLOS/LOTC Output (RLOSF).

0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC)

Bit 1/Transmit Clock Source Select bit 0 (TCSS0).

Bit 2/Transmit Clock Source Select bit 1 (TCSS1).

TCSS1 TCSS0 TRANSMIT CLOCK SOURCE

0 0 The TCLK pin is always the source of transmit clock.

0 1 Switch to the clock present at RCLK when the signal at the TCLK pin fails to

transition after one channel time.

1 0 Use the scaled signal present at MCLK as the transmit clock. The TCLK pin is

ignored.

1 1 Use the signal present at RCLK as the transmit clock. The TCLK pin is ignored.

Bit 3/Disable Idle Code Auto Increment (DICAI) Selects/deselects the auto increment feature for the transmit and receive idle code array address register.

0 = addresses in IAAR register automatically increment on every read/write operation to the PCICR register 1 = addresses in IAAR register do not automatically increment

Bit 4/Output Data Mode (ODM).

0 = pulses at TPOSO and TNEGO are one full TCLKO period wide 1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide

Bit 5/Signaling Integration Enable (SIE).

0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for three multiframes in order for a change of state to be reported

Bit 6/CRC -4 Recalcul ate (CRC4R). (E1 Only) 0 = transmit CRC-4 generation and insertion operates in normal mode

1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method

Bit 7/Unused, must be set to zero for proper operation.

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Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh

Bit # 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default 1 0 1 1 X X X X

Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision.

Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the device ID.

Register Name: SR2 Register Description: Status Register 2 Register Address: 18h

Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0

Bit 0/Receive Loss of Sync Condition (RLOS). Set when the device is not synchronized to the received data stream.

Bit 1/Framer Receive Carrier Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2.0 = 1) E1 mode or 192 T1 mode

consecutive zeros have been detected at RPOSI and RNEGI.

Bit 2/Receive Unframed All Ones (T1, Blue Alarm, E1 , AIS) Condition (RUA1). Set when an unframed all ones code is received at RPOSI and RNEGI.

Bit 3/Receive Yellow Alarm Condition (RYEL). (T1 only) Set when a yellow alarm is received at RPOSI and RNEGI.

Bit 4/Receive Loss of Sync Clear Event (RLOSC). Set when the framer achieves synchronization; will remain set until read.

Bit 5/Framer Receive Carrier Loss Clear Event (FRCLC). Set when carrier loss condition at RPOSI and RNEGI is no

longer detected.

Bit 6/Receive Unframed All Ones Clear Event (RUA1C). Set when the unframed all ones condition is no longer detected.

Bit 7/Receive Yellow Alarm Clear Event (RYELC). (T1 only) Set when the yellow alarm condition is no longer detected.

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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h

Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0

Bit 0/Receive Loss of Sync Condition (RLOS). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only

Bit 1/Framer Receive Carrier Loss Condition (FRCL).

0 = interrupt masked

1 = interrupt enabled–interrupts on rising edge only

Bit 2/Receive Unframed All Ones (Blue Alarm) Condition (RUA1).

0 = interrupt masked

1 = interrupt enabled–interrupts on rising edge only

Bit 3/Receive Yellow Alarm Condition (RYEL).

0 = interrupt masked

1 = interrupt enabled–interrupts on rising edge only

Bit 4/Receive Loss of Sync Clear Event (RLOSC).

0 = interrupt masked

1 = interrupt enabled

Bit 5/Framer Receive Carrier Loss Condition Clear (FRCLC).

0 = interrupt masked

1 = interrupt enabled

Bit 6/Receive Unframed All Ones Condition Clear Event (RUA1C).

0 = interrupt masked

1 = interrupt enabled

Bit 7/Receive Yellow Alarm Clear Event (RYELC).

0 = interrupt masked

1 = interrupt enabled

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Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah

Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0

Bit 0/Receive Remote Alarm Condition (RRA). (E1 only) Set when a remote alarm is received at RPOSI and RNEGI

Bit 1/Receive Distant MF Alarm Condition (RDMA). (E1 only) Set when bit 6 of timeslot 16 in frame 0 has been set for

two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.

Bit 2/V5.2 Link Detected Condition (V52LNK). (E1 only) Set on detection of a V5.2 link identification signal. (G.965).

Bit 3/Loss of Receive Clock Condition (LORC). Set when the RCLKI pin has not transitioned for one channel time.

Bit 4/Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for one channel time. Will

force the LOTC pin high if enabled via CCR1.0.

Bit 5/Loop Up Code Detected Condition (LUP). (T1 only) Set when the loop up code as defined in the RUPCD1/2 register is being received. See Programmable In-Band Loop Code Generation and Detection for details.

Bit 6/Loop Down Code Detected Condition (LDN). (T1 only) Set when the loop down code as defined in the RDNCD1/2 register is bei ng received. See Programmable In-Band Loop Code Generation and Detection for details.

Bit 7/Spare Code Detected Condition (LSPARE). (T1 only) Set when the spare code as defined in the RSCD1/2 registers is being received. See Programmable In-Band Loop Code Generation and Detection for details.

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Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh

Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0

Bit 0/Receive Remote Alarm Condition (RRA).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 1/Receive Distant MF Alarm Condition (RDMA).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 2/V 5.2 Link Detected Condition (V52LNK).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 3/Loss of Receive Clock Condition (LORC).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 4/Loss of Transmit Clock Condition (LOTC).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 5/Loop Up Code Detected Condition (LUP).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 6/Loop Down Code Detected Condition (LDN).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

Bit 7/Spare Code Detected Condition (LSPARE).

0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges

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Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch

Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0

Bit 0/Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers.

Bit 1/Receive CRC4 Multiframe Event (RCMF). (E1 only) Set on CRC4 multiframe boundaries; will continue to be set every 2ms on an arbi trary boundary if CRC4 is disabled.

Bit 2/Receive Multiframe Event (RMF). E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.

Bit 3/Transmit Align Frame Event (TAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated.

Bit 4/Transmit Multiframe Event (TMF). E1 Mode: Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.

Bit 5/Receive Signaling All Zeros Event (RSA0). (E1 only) Set when over a full MF, timeslot 16 contains all zeros.

Bit 6/Receive Signaling All Ones Event (RSA1). (E1 only) Set when the contents of timeslot 16 contains fewer than three

zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.

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Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh

Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0

Bit 0/Receive Align Frame Event (RAF).

0 = interrupt masked 1 = interrupt enabled

Bit 1/Receive CRC4 Multiframe Event (RCMF).

0 = interrupt masked 1 = interrupt enabled

Bit 2/Receive Multiframe Event (RMF).

0 = interrupt masked 1 = interrupt enabled

Bit 3/Transmit Align Frame Event (TAF).

0 = interrupt masked 1 = interrupt enabled

Bit 4/Transmit Multiframe Event (TMF).

0 = interrupt masked 1 = interrupt enabled

Bit 5/Receive Signaling All Zeros Event (RSA0).

0 = interrupt masked 1 = interrupt enabled

Bit 6/Receive Signaling All Ones Event (RSA1).

0 = interrupt masked 1 = interrupt enabled

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11. I/O PIN CONFIGURATION OPTIONS

Register Name: IOCR1 Register Description: I/O Configuration Register 1 Register Address: 01h

Bit # 7 6 5 4 3 2 1 0 Name RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF Default 0 0 0 0 0 0 0 0

Bit 0/Output Data Format (ODF).

0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0

Bit 1/TSYNC I/O Select (TSIO).

0 = TSYNC is an input 1 = TSYNC is an output

Bit 2/TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin.

0 = frame mode 1 = multiframe mode

Bit 3/TSYNC Double -Wide (TSDW). (T1 only) (Note: this bit must be set to zero when IOCR1.2 = 1 or when IOCR1.1 = 0)

0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames

Bit 4/RSYNC I/O Select (RSIO). (Note: this bit must be set to zero when ESCR.0 = 0)

0 = RSYNC is an output 1 = RSYNC is an input (only valid if ela stic store enabled)

Bit 5/RSYNC Mode Select 1(RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling re-insertion is enabled.

0 = frame mode 1 = multiframe mode

Bit 6/RSYNC Mode Select 2(RSMS2). T1 Mode: RSYNC pin must be programmed in the output frame mode (IOCR1.5 = 0, IOCR1.4 = 0).

0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames

E1 Mode: RSYNC pin must be programmed in the output multiframe mode

(IOCR1.5 = 1, IOCR1.4 = 0). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries

Bit 7/RSYNC Multiframe Skip Control (RSMS). Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (IOCR1.5 = 1 and IOCR1.4 = 0).

0 = RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe

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Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h

Bit # 7 6 5 4 3 2 1 0 Name Default 0 0 0 0 0 0 0 0

Bit 0/RSYSCLK Mode Select (RSCLKM).

0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled (See Interleaved PCM Bus Operation.)

Bit 1/TSYSCLK Mode Select (TSCLKM).

0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048MHz o r IBO enabled (See Interleaved PCM Bus Operation.)

Bit 2/H.100 SYNC Mode (H100EN).

0 = normal operation 1 = SYNC shift

Bit 3/TSSYNC Invert (TSSYNCINV).

0 = no inversion 1 = invert

Bit 4/TSYNC Invert (TSYNCINV).

0 = no inversion 1 = invert

Bit 5/RSYNC Invert (RSYNCINV).

0 = no inversion 1 = invert

Bit 6/TCLK Invert (TCLKINV).

0 = no inversion 1 = invert

Bit 7/RCLK Invert (RCLKINV).

0 = no inversion 1 = invert

RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM

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12. LOOPBACK CONFIGURATION

Register Name: LBCR Register Description: Loopback Control Register Register Address: 4Ah

Bit # 7 6 5 4 3 2 1 0 Name - - - LIUC LLB RLB PLB FLB Default 0 0 0 0 0 0 0 0

Bit 0/Framer Loopback (FLB).

0 = loopback disabled 1 = loopback enabled

This loopback is useful in testing and debugging applications. In FLB, the device will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur:

1) T1 Mode: An unframed all ones code will be transmitted at TPOSO and TNEGO.

E1 Mode: Normal data will be transmitted at TPOSO and TNEGO.

2) Data at RPOSI and RNEGI will be ignored.

3) All receive side signals will take on timing synchronous with TCLK instead of RCLKI.

4) Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unst able

condition.

Bit 1/Payload Loopback (PLB).

0 = loopback disabled 1 = loopback enabled

When PLB is enabled, the following will occur:

1) Data will be transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK.

2) All of the receive side signals will continue to operate normally.

3) The TCHCLK and TCHBLK signals are forced low.

4) Data at the TSER and TSIG pins is ignored.

5) The TLCLK signal will become synchronous with RCLK instead of TCLK.

T1 Mode: Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications. In a PLB situation, the device will loop the 192 bits of pay-load data (with BPVs corrected) from the receive section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are reinserted by the device.

E1 Mode: In a PLB situation, the device will loop the 248 bits of payload data (with BPVs corrected) from the receive section back to the transmit section. The transmit section will modify the payload as if it was input at TSER. The FAS word, Si, Sa and E bits, and CRC4 are not looped back, they are reinserted by the device.

Bit 2/Remote Loopback (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive side framer of the device as it would normally and the data from the transmit side formatter will be ignored.

0 = loopback disabled 1 = loopback enabled

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Product Preview DS21Q55 Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the device. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. (See Figure 1-1 Line Interface Unit.)

0 = loopback disabled 1 = loopback enabled

Bit 4/Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high the LIUC bit has control. When the LIUC pin is connected low the framer and LIU are separated and the LIUC bit has no effect.

0 = if LIUC pin connected high, LIU internally connected to framer block and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. 1 = if LIUC p in connected high, disconnect LIU from framer block and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins.

LIUC pin LIUC bit

0 0 LIU and Framer Separated 0 1 LIU and Framer Separated 1 0 LIU and Framer Connected 1 1 LIU and Framer Separated

Bit 5/Unused, must be set to zero for proper operation.

Bit 6/Unused, must be set to zero for proper operation.

Bit 7/Unused, must be set to zero for proper operation.

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12.1 Per-Channel Loopback

The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back.

Each of the bit position in the PCLRs (PCLR1 /PCLR2/PCLR3/PCLR4) represent a DS0 channel in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel.

Register Name: PCLR1 Register Description: Per-Channel Loopback Enable Register 1 Register Address: 4Bh

Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Per-Channel Loopback Enable for Channels 1 to 8 (CH1 to CH8).

0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel

Register Name: PCLR2 Register Description: Per-Channel Loopback Enable Register 2 Register Address: 4Ch

Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Per-Channel Loopback Enable for Channels 9 to 16 (CH9 to CH16).

0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel

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Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Address: 4Dh

Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24).

0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel

Register Name: PCLR4 Register Description: Per-Channel Loopback Enable Register 4 Register Address: 4Eh

Bit # 7 6 5 4 3 2 1 0 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Per-Channel Loopback Enable for Channels 25 to 32 (CH25 to CH32).

0 = loopback disabled 1 = enable loopback. Source data from the corresponding receive channel

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13. ERROR COUNT REGISTERS

The DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at their respective maximum counts and they will not rollover (Note: Only the line-code violation-count register has the potential to overflow but the bit error would have to exceed 10E-2 before this would occur).

Register Name: ERCNT Register Description: Error Counter Configuration Register Register Address: 41h

Bit # 7 6 5 4 3 2 1 0 Name - MECU ECUS EAMS VCRFS FSBE MOSCRF LCVCRF Default 0 0 0 0 0 0 0 0

Bit 0/T1 Line Code Violation Count Register Function Select (LCVCRF).

0 = do not count excessive zeros 1 = count excessive zeros

Bit 1/Multiframe Out of Sync Count Register Function Select (MOSCRF).

0 = count errors in the framing bit position 1 = count the number of multiframes out of sync

Bit 2/PCVCR Fs-Bit Error Report Enable (FSBE).

0 = do not report bit errors in Fs-bit position; only Ft-bit position 1 = report bit errors in Fs-bit position as well as Ft-bit position

Bit 3/E1 Line Code Violation Count Register Function Select (VCRFS).

0 = count BiPolar Violations (BPVs) 1 = count Code Violations (CVs)

Bit 4/Error Accumulation Mode Select (EAMS).

0 = ERCNT.5 determines accumulation time 1 = ERCNT.6 determines accumulation time

Bit 5/Error Counter Update Select (ECUS). T1 Mode: 0 = Update error counters once a second

1 = Update error counters every 42ms (333 frames)

E1 Mode: 0 = Update error counters once a second

1 = Update error counters every 62.5ms (500 frames)

Bit 6/Manual Error Counter Update (MECU). When enabled by ERCNT.4, the changing of this bit from a zero to a one allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 1.5 RCLK clock periods before reading the error count registers to allow for proper update.

Bit 7/Unused, must be set to zero for proper operation.

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13.1 Line Code Violation Count Register (LCVCR)

T1 Operation

T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS code words are not counted. This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions (Table 15-1).

T1 LINE CODE VIOLATION COUNTING OPTIONS Table 15-1

COUNT EXCESSIVE

ZEROS?

(ERCNT.0)

B8ZS ENABLED?

(T1RCR2.5)

WHAT IS COUNTED IN THE LCVCRs

No No BPVs

Yes No BPVs + 16 Consecutive Zeros

No Yes BPVs (B8ZS Code Words Not Counted)

Yes Yes BPVs + 8 Consecutive Zeros

E1 Operation

Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mo de is set for the receive side, then HDB3 code words are not counted as BPVs. If ERCNT.3 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** -2 before the VCR would saturate (Table 15-2).

E1 LINE CODE VIOLATION COUNTING OPTIONS Table 15-2

E1 CODE VIOLATION SELECT

(ERCNT.3)

0 BPVs 1 CVs

WHAT IS COUNTED IN THE

LCVCRs

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Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 42h

Bit # 7 6 5 4 3 2 1 0 Name LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCCV8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Line Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count.

Register Name: LCVCR2 Register Description: Line Code Violation Count Register 2 Register Address: 43h

Bit # 7 6 5 4 3 2 1 0 Name LCVC7 LCVC6 LCVC5 LCVC4 LCVC3 LCVC2 LCVC1 LCVC0 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Line Code Violation Counter Bits 0 to 7 (LCVC0 to LCVC7). LCV0 is the LSB of the 16 -bit code violation count.

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13.2 Path Code Violation Count Register (PCVCR)

T1 Operation

The path-code violation-count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC6 code words. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 15-3 for a detailed description of exactly what errors the PCVCR counts.

T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS Table 15-3

FRAMING MODE COUNT Fs ERRORS? WHAT IS COUNTED IN THE PCVCRs

D4 No Errors in the Ft Pattern D4 Yes Errors in Both the Ft and Fs Patterns

ESF Don’t Care Errors in the CRC6 Code Words

E1 Operation

The PCVCR records CRC4 errors. Since the maximum CRC4 count in a one -second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.

The PCVCR1 is the most significant word and PCVCR2 is the least significant word of a 16-bit counter that records path violat ions (PVs).

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Register Name: PCVCR1 Register Description: Path Code Violation Count Register 1 Register Address: 44h

Bit # 7 6 5 4 3 2 1 0 Name PCVC15 PCVC14 PCVC13 PCVC12 PCVC11 PCVC10 PCVC9 PCVC8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path code violation count.

Register Name: PCVCR2 Register Description: Path Code Violation Count Register 2 Register Address: 45h

Bit # 7 6 5 4 3 2 1 0 Name PCVC7 PCVC6 PCVC5 PCVC4 PCVC3 PCVC2 PCVC1 PCVC0 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Path Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit path code violation count.

13.3 Frames Out Of Sync Count Register (FOSCR)

T1 Operation

The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS = 1) conditions. The FOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1) conditions. See Table 15-4 for a detailed description of what the FOSCR is capable of counting.

T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 15-4

FRAMING MODE

(T1RCR1.3)

D4 MOS Number of Multiframes Out of Sync

D4 F-Bit Errors in the Ft Pattern ESF MOS Number of Multiframes Out of Sync ESF F-Bit Errors in the FPS Pattern

E1 Operation

The FOSCR counts word errors in the frame alignment signal in timeslot 0. This counter is disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one -second period is 4000, this counter cannot saturate.

COUNT MOS OR F-BIT ERRORS

(ERCNT.1)

WHAT IS COUNTED IN THE

FOSCRs

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The FOSCR1 (FOSCR1 ) is the most significant word and FOSCR2 is the least significant word of a 16bit counter that records frames out of sync.

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Register Name: FOSCR1 Register Description: Frames Out Of Sync Count Register 1 Register Address: 46h

Bit # 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Frames Out of Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out of sync count.

Register Name: FOSCR2 Register Description: Frames Out Of Sync Count Register 2 Register Address: 47h

Bit # 7 6 5 4 3 2 1 0 Name FOS7 FOS6 FOS5 FOS4 FOS3 FOS2 FOS1 FOS0 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Frames Out of Sync Counter Bits 0 to 7 (FOS0 to FOS7). FOS0 is the LSB of the 16 -bit frames out of sync count.

13.4 E-Bit Counter Register (EBCR)

This counter is only available in the E1 mode. EBCR1 (EBCR1 ) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far end block errors (FEBE), as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a onesecond period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.

Register Name: EBCR1 Register Description: E-Bit Count Register 1 Register Address: 48h

Bit # 7 6 5 4 3 2 1 0 Name EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/E-Bit Counter Bits 8 to 15 (EB8 to EB15). EB15 is the MSB of the 16-bit E-bit count.

Register Name: EBCR2 Register Description: E-Bit Count Register 2 Register Address: 49h

Bit # 7 6 5 4 3 2 1 0 Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/E-Bit Counter Bits 0 to 7 (EB0 to EB7). EB0 is the LSB of the 16-bit E-bit count.

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14. DS0 MONITORING FUNCTION

The DS21Q55 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TC M0 to TCM4 bits will appear in the transmit DS0 monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1 or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL:

TCM4 = 0 RCM4 = 0 TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1 TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0

14.1 Transmit DS0 Monitor Registers

Register Name: TDS0SEL Register Description: Transmit Channel Monitor Select Register Address: 74h

Bit # 7 6 5 4 3 2 1 0 Name - - - TCM4 TCM3 TCM2 TCM1 TCM0 Default 0 0 0 0 0 0 0 0

Bits 0 to 4 Transmit Channel Monitor Bits (TCM0 to TCM4). TCM0 is the LSB of a 5-bit channel select that determines which transmit channel data will appear in the TDS0M register.

Bits 5 to 7/Unused, must be set to zero for proper operation.

Register Name: TDS0M Register Description: Transmit DS0 Monitor Register Register Address: 75h

Bit # 7 6 5 4 3 2 1 0 Name B1 B2 B3 B4 B5 B6 B7 B8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the tr ansmit channel monitor select register. B8 is the LSB of the DS0 channel (last bit to be transmitted).

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14.2 Receive DS0 Monitor Registers

Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h

Bit # 7 6 5 4 3 2 1 0 Name - - - RCM4 RCM3 RCM2 RCM1 RCM0 Default 0 0 0 0 0 0 0 0

Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel -select that determines which receive DS0 channel data will appear in the RDS0M register.

Bits 5 to 7/Unused, must be set to zero for proper operation.

Register Name: RDS0M Register Description: Receive DS0 Monitor Register Register Address: 77h

Bit # 7 6 5 4 3 2 1 0 Name B1 B2 B3 B4 B5 B6 B7 B8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Receive DS0 Channel Bits (B1 to B8). Receive-channel data that has been selected by the receive-channel monitor-select register. B8 is the LSB of the DS0 channel (last bit to be received).

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15. SIGNALING OPERATION

There are two methods to access receive signaling data and provide transmit signaling data: processorbased (i.e., software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers, RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously.

15.1 Receive Signaling

SIMPLIFIED DIAGRAM OF RECEIVE SIGNALING PATH Figure 17- 1

PER-CHANNEL

CONTROL

T1/E1 DATA STREAM

SIGNALING

EXTRACTION

RECEIVE SIGNALING

REGISTERS

CHANGE OF STATE

INDICATION REGISTERS

ALL

ONES

RE-INSERTION

CONTROL SIGNALING

BUFFERS

RSER

RSYNC

RSIG

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15.1.1 Processor-Based Receive Signaling

The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are used. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled.

15.1.1.1 Change Of State

In order to avoid constant monitoring of the receive signaling registers, the DS21Q55 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 for E1 and RSCSE1 through RSCSE3 for T1 are used to select which channels can cause a change of state indication. The change of state is indicated in Status Register 5 (SR1.5). If signaling integration, CCR1.5, is enabled then the new signaling state must be constant for three multiframes before a change of state indication is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the IMR1 .5 bit. The signaling integration mode is global and cannot be enabled on a channel by channel basis.

The user can identity which channels have undergone a signaling change of state by reading the RSINFO1 through RSINFO4 registers . The information from this registers will tell the user which RSx register to read for the new signaling data. All changes are indicated in the RSINFO1–RSINFO4 register regardless of the RSCSE1 –RSCSE4 registers.

15.1.2 Hardware-Based Receive Signaling

In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM-stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store can be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a freeze is in e ffect. See the Functional Timing Diagrams for some examples.

15.1.2.1 Receive-Signaling Reinsertion at RSER

In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the elastic store must be enabled; however, the backplane clock can be either 1.544MHz or 2.048MHz.

Signaling reinsertion mode is enabled, on a per-channel basis by setting the RSRCS bit high in the PCPR register. The channels that are to have signaling reinserted are selected by writing to the PCDR1 -PCDR3

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registers for T1 mode and PCDR1-PCDR4 registers for E1 mode. In E1 mode, the user will generally select all channels when doing reinsertion.

15.1.2.2 Force Receive Signaling All Ones

In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling-bit positions to a one. This is done by using the per-channel register, which is described in the Special Per-Channel Operation section. The user sets the BTCS bit in the PCPR register. The channels that are to be forced to one are selected by writing to the PCDR1 -PCDR3 registers.

15.1.2.3 Receive-Signaling Freeze

The signaling data in the four-multiframe signaling buffer will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore TR–TSY–000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit (SIGCR.4) should be set high. The user can force a freeze by setting the RFF control bit (SIGCR.3) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receive signaling reinsertion is enabled). When freezing is enabled (RFE = 1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before being allowed to be updated with new signaling data.

Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h

Bit # 7 6 5 4 3 2 1 0 Name - - - RFE RFF - - Default 0 0 0 0 0 0 0 0

Bit 0/Unused, must be set to zero for proper operation.

Bit 1/Unused, must be set to zero for proper operation.

Bit 2/Unused, must be set to zero for proper operation.

Bit 3/Receive Force Freeze (RFF). Freezes receive-side signaling at RSIG (and RSER if receive signaling reinsertion is

enabled); will override receive-freeze enable (RFE). See Receive Signaling Freeze.

0 = do not force a freeze event 1 = force a freeze event

Bit 4/Receive Freeze Enable (RFE). See Receive Signaling Freeze.

0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG (and RSER if receive signaling reinsertion is enabled).

Bit 5/Unused, must be set to zero for proper operation.

Bit 6/Unused, must be set to zero for proper operation.

Bit 7/Unused, must be set to zero for proper operation.

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Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh

(MSB) (LSB)

CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D RS1 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D RS2 CH6-A CH6-B CH6-C CH6-D CH5-A CH5-B CH5-C CH5-D RS3 CH8-A CH8-B CH8-C CH8-D CH7-A CH7-B CH7-C CH7-D RS4 CH10-A CH10-B CH10-C CH10-D CH9-A CH9-B CH9-C CH9-D RS5 CH12-A CH12-B CH12-C CH12-D CH11-A CH11-B CH11-C CH11-D RS6 CH14-A CH14-B CH14-C CH14-D CH13-A CH13-B CH13-C CH13-D RS7 CH16-A CH16-B CH16-C CH16-D CH15-A CH15-B CH15-C CH15-D RS8 CH18-A CH18-B CH18-C CH18-D CH17-A CH17-B CH17-C CH17-D RS9 CH20-A CH20-B CH20-C CH20-D CH19-A CH19-B CH19-C CH19-D RS10 CH22-A CH22-B CH22-C CH22-D CH21-A CH21-B CH21-C CH21-D RS11 CH24-A CH24-B CH24-C CH24-D CH23-A CH23-B CH23-C CH23-D RS12

Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, D4 Format) Register Address: 60h to 6Bh

(MSB) (LSB) CH2-A CH2-B CH2-A CH2-B CH1-A CH1-B CH1-A CH1-B RS1 CH4-A CH4-B CH4-A CH4-B CH3-A CH3-B CH3-A CH3-B RS2 CH6-A CH6-B CH6-A CH6-B CH5-A CH5-B CH5-A CH5-B RS3 CH8-A CH8-B CH8-A CH8-B CH7-A CH7-B CH7-A CH7-B RS4 CH10-A CH10-B CH10-A CH10-B CH9-A CH9-B CH9-A CH9-B RS5 CH12-A CH12-B CH12-A CH12-B CH11-A CH11-B CH11-A CH11-B RS6 CH14-A CH14-B CH14-A CH14-B CH13-A CH13-B CH13-A CH13-B RS7 CH16-A CH16-B CH16-A CH16-B CH15-A CH15-B CH15-A CH15-B RS8 CH18-A CH18-B CH18-A CH18-B CH17-A CH17-B CH17-A CH17-B RS9 CH20-A CH20-B CH20-A CH20-B CH19-A CH19-B CH19-A CH19-B RS10 CH22-A CH22-B CH22-A CH22-B CH21-A CH21-B CH21-A CH21-B RS11 CH24-A CH24-B CH24-A CH24-B CH23-A CH23-B CH23-A CH23-B RS12

Note: In D4 format, TS1-TS12 contain signaling data for two frames. Bold type indicates data for second frame.

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Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh

(MSB) (LSB)

0 0 0 0 X Y X X RS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D RS2 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D RS3 CH6-A CH6-B CH6-C CH6-D CH5-A CH5-B CH5-C CH5-D RS4 CH8-A CH8-B CH8-C CH8-D CH7-A CH7-B CH7-C CH7-D RS5 CH10-A CH10-B CH10-C CH10-D CH9-A CH9-B CH9-C CH9-D RS6 CH12-A CH12-B CH12-C CH12-D CH11-A CH11-B CH11-C CH11-D RS7 CH14-A CH14-B CH14-C CH14-D CH13-A CH13-B CH13-C CH13-D RS8 CH16-A CH16-B CH16-C CH16-D CH15-A CH15-B CH15-C CH15-D RS9 CH18-A CH18-B CH18-C CH18-D CH17-A CH17-B CH17-C CH17-D RS10 CH20-A CH20-B CH20-C CH20-D CH19-A CH19-B CH19-C CH19-D RS11 CH22-A CH22-B CH22-C CH22-D CH21-A CH21-B CH21-C CH21-D RS12 CH24-A CH24-B CH24-C CH24-D CH23-A CH23-B CH23-C CH23-D RS13 CH26-A CH26-B CH26-C CH26-D CH25-A CH25-B CH25-C CH25-D RS14 CH28-A CH28-B CH28-C CH28-D CH27-A CH27-B CH27-C CH27-D RS15 CH30-A CH30-B CH30-C CH30-D CH29-A CH29-B CH29-C CH29-D RS16

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Register Name: RSCSE1, RSCSE2, RSCSE3 , RSCSE4 Register Description: Receive Signaling Change Of State Interrupt Enable Register Address: 3Ch, 3Dh, 3Eh, 3Fh

(MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RSCSE1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RSCSE2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RSCSE3 CH30 CH29 CH28 CH27 CH26 CH25 RSCSE4

Setting any of the CH1 through CH30 bits in the RSCSE1 through RSCSE4 registers will cause an interrupt when that channel’s signaling data changes state.

Register Name: RSINFO1, RSINFO2, RSINFO3 , RSINFO4 Register Description: Receive Signaling Change Of State Information Register Address: 38h, 39h, 3Ah, 3Bh

(MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RSINFO1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RSINFO2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RSINFO3 CH30 CH29 CH28 CH27 CH26 CH25 RSINFO4

When a channel’s signaling data changes state, the respective bit in registers RSINFO1-4 will be set. If the channel was also enabled as an interrupt source by setting the appropriate bit in RSCSE1–4, an interrupt is generated. The bit will remain set until read.

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ONLY APPLIES TO T1 MODE

15.2 Transmit Signaling SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH Figure 17-2

TRANSMIT

SIGNALING

REGISTERS

1

0

1

SIGNALING

BUFFERS

TSER

TSIG

T1/E1 DATA

STREAM

0

1

B7

PER-CHANNEL

CONTROL

SSIE1 - SSIE4

0

T1TCR1.4

PER-CHANNEL

CONTROL

PCPR.3

15.2.1 Processor-Based Transmit Signaling

In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1–TS16) via the host interface. On multiframe boundaries, the contents of these registers is loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the transmit multiframe interrupt in status register 4 (SR4 .4) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register.

Each transmit signaling register contains the robbed-bit signaling (T1) or TS16 CAS signaling (E1) for two timeslots that will be inserted into the outgoing stream if enabled to do so via T1TCR1 .4 (T1 Mode) or E1TCR1.6 (E1 Mode). In T1 mode, only TS1 through TS12 are used.

Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the softwaresignaling insertion-enable registers, SSIE1 through SSIE4.

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15.2.1.1 T1 Mode

In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1–TS12.

The framer will load the contents of TS1–TS12 into the outgoing shift register every other D4 multiframe. In D4 mode the host should load new contents into TS1–TS12 on every other multiframe boundary and no later than 120µs after the boundary.

15.2.1.2 E1 Mode

In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In channel numbering, TS0 thro ugh TS31 are labeled channels 1 through 32. In phone -channel numbering, TS1 through TS15 are labeled channel 1 through channel 15, and TS17 through TS31 are labeled channel 15 through channel 30.

TIME SLOT NUMBERING SCHEMES Table 17-1

TS

Channel

Phone

Channel

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh

(MSB) (LSB)

0 0 0 0 X Y X X TS1 CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D TS2 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D TS3 CH6-A CH6-B CH6-C CH6-D CH5-A CH5-B CH5-C CH5-D TS4 CH8-A CH8-B CH8-C CH8-D CH7-A CH7-B CH7-C CH7-D TS5 CH10-A CH10-B CH10-C CH10-D CH9-A CH9-B CH9-C CH9-D TS6 CH12-A CH12-B CH12-C CH12-D CH11-A CH11-B CH11-C CH11-D TS7 CH14-A CH14-B CH14-C CH14-D CH13-A CH13-B CH13-C CH13-D TS8 CH16-A CH16-B CH16-C CH16-D CH15-A CH15-B CH15-C CH15-D TS9 CH18-A CH18-B CH18-C CH18-D CH17-A CH17-B CH17-C CH17-D TS10 CH20-A CH20-B CH20-C CH20-D CH19-A CH19-B CH19-C CH19-D TS11 CH22-A CH22-B CH22-C CH22-D CH21-A CH21-B CH21-C CH21-D TS12 CH24-A CH24-B CH24-C CH24-D CH23-A CH23-B CH23-C CH23-D TS13 CH26-A CH26-B CH26-C CH26-D CH25-A CH25-B CH25-C CH25-D TS14 CH28-A CH28-B CH28-C CH28-D CH27-A CH27-B CH27-C CH27-D TS15 CH30-A CH30-B CH30-C CH30-D CH29-A CH29-B CH29-C CH29-D TS16

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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h to 5Fh

(MSB) (LSB)

1 2 3 4 5 6 7 8 TS1

17 18 19 20 9 10 11 12 TS2 33 34 35 36 25 26 27 28 TS3 49 50 51 52 41 42 43 44 TS4 65 66 67 68 57 58 59 60 TS5 81 82 83 84 73 74 75 76 TS6 97 98 99 100 89 90 91 92 TS7

113 114 115 116 105 106 107 108 TS8

13 14 15 16 121 122 123 124 TS9 29 30 31 32 21 22 23 24 TS10 45 46 47 48 37 38 39 40 TS11 61 62 63 64 53 54 55 56 TS12 77 78 89 80 69 70 71 72 TS13

93 94 95 96 85 86 87 88 TS14 109 110 111 112 101 102 103 104 TS15 125 126 127 128 117 118 119 120 TS16

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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh

(MSB) (LSB)

CH2-A CH2-B CH2-C CH2-D CH1-A CH1-B CH1-C CH1-D TS1 CH4-A CH4-B CH4-C CH4-D CH3-A CH3-B CH3-C CH3-D TS2 CH6-A CH6-B CH6-C CH6-D CH5-A CH5-B CH5-C CH5-D TS3 CH8-A CH8-B CH8-C CH8-D CH7-A CH7-B CH7-C CH7-D TS4 CH10-A CH10-B CH10-C CH10-D CH9-A CH9-B CH9-C CH9-D TS5 CH12-A CH12-B CH12-C CH12-D CH11-A CH11-B CH11-C CH11-D TS6 CH14-A CH14-B CH14-C CH14-D CH13-A CH13-B CH13-C CH13-D TS7 CH16-A CH16-B CH16-C CH16-D CH15-A CH15-B CH15-C CH15-D TS8 CH18-A CH18-B CH18-C CH18-D CH17-A CH17-B CH17-C CH17-D TS9 CH20-A CH20-B CH20-C CH20-D CH19-A CH19-B CH19-C CH19-D TS10 CH22-A CH22-B CH22-C CH22-D CH21-A CH21-B CH21-C CH21-D TS11 CH24-A CH24-B CH24-C CH24-D CH23-A CH23-B CH23-C CH23-D TS12

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Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (T1 Mode, D4 Format) Register Address: 50h to 5Bh

(MSB) (LSB) CH2-A CH2-B CH2-A CH2-B CH1-A CH1-B CH1-A CH1-B TS1 CH4-A CH4-B CH4-A CH4-B CH3-A CH3-B CH3-A CH3-B TS2 CH6-A CH6-B CH6-A CH6-B CH5-A CH5-B CH5-A CH5-B TS3 CH8-A CH8-B CH8-A CH8-B CH7-A CH7-B CH7-A CH7-B TS4 CH10-A CH10-B CH10-A CH10-B CH9-A CH9-B CH9-A CH9-B TS5 CH12-A CH12-B CH12-A CH12-B CH11-A CH11-B CH11-A CH11-B TS6 CH14-A CH14-B CH14-A CH14-B CH13-A CH13-B CH13-A CH13-B TS7 CH16-A CH16-B CH16-A CH16-B CH15-A CH15-B CH15-A CH15-B TS8 CH18-A CH18-B CH18-A CH18-B CH17-A CH17-B CH17-A CH17-B TS9 CH20-A CH20-B CH20-A CH20-B CH19-A CH19-B CH19-A CH19-B TS10 CH22-A CH22-B CH22-A CH22-B CH21-A CH21-B CH21-A CH21-B TS11 CH24-A CH24-B CH24-A CH24-B CH23-A CH23-B CH23-A CH23-B TS12 Note: In D4 format, TS1–TS12 contain signaling data for two frames. Bold type indicates data for second frame.

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15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode

In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data.

Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h

Bit # 7 6 5 4 3 2 1 0 Name CH7 CH6 CH5 CH4 CH3 CH2 CH1 UCAW Default 0 0 0 0 0 0 0 0

Bit 0/Upper CAS Align/Alarm Word (UCAW). Selects the upper CAS align/alarm pattern (0000) to be sourced from the upper 4 bits of the TS1 register.

0 = do not source the upper CAS align/alarm pattern from the TS1 register 1 = source the upper CAS align/alarm pattern from the TS1 register

Bits 1 to 7/Software Signaling Insertion Enable for Channels 1 to 7 (CH1 to CH7 ). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers.

0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel

Register Name: SSIE2 Register Descripti on: Software Signaling Insertion Enable 2 Register Address: 09h

Bit # 7 6 5 4 3 2 1 0 Name CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Software Signaling Insertion Enable for Channels 8 to 15 (CH8 to CH15). These bits determine which channels are to have signaling inserted form the transmit signaling registers.

0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel

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Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah

Bit # 7 6 5 4 3 2 1 0 Name CH22 CH21 CH20 CH19 CH18 CH17 CH16 LCAW Default 0 0 0 0 0 0 0 0

Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower 4 bits of the TS1 register.

0 = do not source the lower CAS align/alarm bits from the TS1 register 1 = source the lower CAS alarm align/bits from the TS1 register

Bits 1 to 7/Software Signaling Insertion Enable for LCAW and Channels 16 to 22 (CH16 to CH22). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers.

0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel

Register Name: SSIE4 Register Description: Software Signaling Insertion Enable 4 Register Address: 0Bh

Bit # 7 6 5 4 3 2 1 0 Name CH30 CH29 CH28 CH27 CH26 CH25 CH24 CH23 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Software Signaling Insertion Enable for Channels 23 to 30 (CH23 to CH30). These bits determine which channels are to have signaling inserted form the transmit signaling registers.

0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel

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15.2.3 Software Signaling Insertion Enable Registers, T1 Mode

In T1 mode, only registers SSIE1 through SSIE3 are used since t here are only 24 channels in a T1 frame.

Register Name: SSIE1 Register Description: Software Signaling Insertion Enable 1 Register Address: 08h

Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Software Signaling Insertion Enable for and Channels 1 to 8 (CH1 to CH8 ). These bits determine what channels are to have signaling inserted form the transmit signaling registers.

0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel

Register Name: SSIE2 Register Description: Software Signaling Insertion Enable 2 Register Address: 09h

Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Software Signaling Insertion Enable for Channels 9 to 16 (CH9 to CH16). These bits determine what channels are to have signaling inserted form the transmit signaling registers.

0 = do not source signaling data from the TSx registers for this channel 1 = source signaling data from the TSx registers for this channel

Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah

Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Software Signaling Insertion Enable for and Channels 17 to 24 (CH17 to CH24). These bits determine what channels are to have signaling inserted form the transmit signaling registers.

0 = do not source signaling data from the TSx registers for this channel

1 = source signaling data from the TSx registers for this channel

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17.2.4 Hardware-Based Transmit Signaling

In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin.

Signaling data can be input on a per-channel basis via the transmit-hardware signaling-channel select (THSCS) function. The framer can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user has the ability to control what channels are to have signaling data from the TSIG pin inserted into them on a perchannel basis. See the Special Per -Channel Operation section. The signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz.

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16. PER-CHANNEL IDLE CODE GENERATION

Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used; the remaining channels, CH25–CH32 are not used.

The DS21Q55 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR). The contents of the array contain the idle codes to be substituted into the appropriate transmit or receive channels. This substitution can be enabled and disabled on a per-channel basis by the transmit-channel idle-code enable registers (TCICE1–4) and receive-channel idle -code enable registers (RCICE1–4).

To program idle codes, first select a channel by writing to the IAAR register. Then write the idle code to the PCICR register. For successive writes there is no need to load the IAAR with the next consecutive address. The IAAR register will automatically increment after a write to the PCICR register. The auto increment feature can be used for read operations as well.

Bits 6 and 7 (GTIC, GRIC) of the IAAR register can be used to block write a common idle code to all transmit or receive positions in the array with a single write to the PCICR register. The user can use the block write feature to set a common idle code for all transmit and receive channels in the IAAR by setting both GTIC and GRIC = 1. When a block write is enabled by GTIC or GRIC, the value placed in the PCICR register will be written to all addresses in the transmit or receive idle array and to whatever address is in the lower 6 bits of the IAAR register. Therefore, when enabling only one of the block functions, GTIC or GRIC, the user must set the lower 6 bits of the IAAR register to any address in that block. Bits 6 and 7 of the IAAR register must be set = 0 for read operations.

The TCICE1 –4 and RCICE1 –4 are used to enable idle-code replacement on a per-channel basis.

IDLE CODE ARRAY ADDRESS MAPPING Table 18-1

BITS 0–5 OF IAAR REGISTER MAPS TO CHANNEL

0 Transmit Channel 1 1 Transmit Channel 2 2 Transmit Channel 3

-

- 30 Transmit Channel 31 31 Transmit Channel 32 32 Receive Channel 1 33 Receive Channel 2 34 Receive Channel 3

-

- 62 Receive Channel 31

63

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Receive Channel 32

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16.1 Idle Code Programming Examples

The following e xample sets transmit channel 3 idle code to 7Eh:

Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh

The following example sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels :

Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set channel 3 idle code to 7Eh Write PCICR = 7Eh ;set channel 4 idle code to 7Eh Write PCICR = 7Eh ;set channel 5 idle code to 7Eh Write PCICR = 7Eh ;set channel 6 idle code to 7Eh Write TCICE1 = 3Ch ;enable transmission of idle codes for channels 3, 4, 5, and 6

The following example sets transmit channels 3, 4, 5, and 6 idle code to 7Eh, EEh, FFh, and 7Eh respectively:

Write IAAR = 02h Write PCICR = 7Eh Write PCICR = EEh Write PCICR = FFh Write PCICR = 7Eh

The following example sets all transmit idle codes to 7Eh:

Write IAAR = 40h Write PCICR = 7Eh

The following example sets all receive and transmit idle codes to 7Eh and enables idle code substitution in all E1 transmit and receive channels:

Write IAAR = C0 h ;enable block write to all transmit and receive positions in the array Write PCICR = 7Eh ;7Eh is idle code Write TCICE1 = FEh ;enable idle code substitution for transmit channels 2 through 8

;Although an idle code was programmed for channel 1 by the block write ;function above,

enabling it for channel 1 would step on the frame ;alignment, alarms, and Sa bits Write TCICE2 = FFh ;enable idle code substitution for transmit channels 9 through 16 Write TCICE3 = FEh ;enable idle code substitut ion for transmit channels 18 through 24

;Although an idle code was programmed for channel 17 by the block write ;function above,

enabling it for channel 17 would step on the CAS frame ;alignment, and signaling information Write TCICE4 = FFh ;enable idle code substitution for transmit channels 25 through 32 Write RCICE1 = FEh ;enable idle code substitution for receive channels 2 through 8 Write RCICE2 = FFh ;enable idle code substitution for receive channels 9 through 16 Write RCICE3 = FEh ;enable idle code substitution for receive channels 18 through 24 Write RCICE4 = FFh ;enable idle code substitution for receive channels 25 through 32

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Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh

Bit # 7 6 5 4 3 2 1 0 Name GRIC GTIC IAA5 IAA4 IAA3 IAA2 IAA1 IAA0 Default 0 0 0 0 0 0 0 0

Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). IAA0 is the LSB of the 5-bit Channel Code.

Bit 6/Global Transmit Idle Code (GTIC). Setting this bit will cause all transmit idle codes to be set to the value written to

the PCICR register. When using this bit, the user must place any transmit address in the IAA0 through IAA5 bits (00h–1Fh). This bit must be set = 0 for read operations.

Bit 7/Global Receive Idle Code (GRIC). Setting this bit will cause all receive idle codes to be set to the value written to the PCICR register. When using this bit, the user must place any receive address in the IAA0 through IAA5 bits (20h–3Fh). This bit must be set = 0 for read operations.

Register Name: PCICR Register Description: Per-Channel Idle Code Register Register Address: 7Fh

Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Per-Channel Idle Code Bits (C0 to C7). C0 is the LSB of the code (this bit is transmitted last).

The TCICE1/2/3/4 are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code plac ed in the per-channel code array.

Register Name: TCICE1 Register Description: Transmit Channel Idle Code Enable Register 1 Register Address: 80h

Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Transmit Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8).

0 = do not insert data from the idle code array into the transmit data stream 1 = insert data from the idle code array into the transmit data stream

Register Name: TCICE2 Register Description: Transmit Channel Idle Code Enable Register 2 Register Address: 81h

Bit # 7 6 5 4 3 2 1 0 Name CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Default 0 0 0 0 0 0 0 0

Bits 0 to 7/Transmit Channels 9 to 16 Code Insertion Control B its (CH9 to CH16).

0 = do not insert data from the idle code array into the transmit data stream

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1 = insert data from the idle code array into the transmit data stream

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Maxim DS21Q55 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual