Maxim DS21Q55 User Manual

Product Preview DS21Q55

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PRODUCT PREVIEW

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DS21Q55 Quad T1/E1/J1 Transceiver

FEATURES:

Complete T1 (DS1)/ISDN–PRI/J1 transceiver
functionality

§ Complete E1 (CEPT) PCM-30/ISDN-PRI

transceiver functionality

§ Short- and long-haul line interface for

clock/data recovery and wave shaping

§ CMI coder/decoder

§ Crystal-less jitter attenuator

§ Dual HDLC controllers

§ On-chip programmable BERT generator and

detector

§ Internal software-selectable receive and

transmit side termination resistors

§ Dual two -frame elastic-store slip buffers to

interface backplanes up to 16.384MHz

§ 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output synthesized to
recovered network clock

§ Programmable output clocks for fractional

T1, E1, H0, and H12 applications

§ Interleaving PCM bus operation

§ 8-bit parallel control port, multiplexed or

nonmultiplexed, Intel or Motorola

§ IEEE 1149.1 JTAG-boundary scan

§ 3.3V supply with 5V tolerant I/O

§ Signaling System 7 (SS7) support

APPLICATIONS:

§ Routers

§ Channel Service Units (CSUs)

§ Data Service Units (DSUs)

§ Muxes

§ Switches

§ Channel Banks

§ T1/E1 Test Equipment

§ DSL Add/Drop Multiplexers

ORDERING INFORMATION

DS21Q55 27mm BGA (0°C to +70°C)
DS21Q55N 27mm BGA (-40°C to +85°C)

1. DESCRIPTION

The DS21Q55 is a quad MCM device featuring independent transceivers that can be software configured
for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is
pin compatible with the DS21Qx5y family of products.

Note: This Product Preview contains preliminary information and is subject to change without notice.
Some revisions of this device may incorporate deviations from published specifications known as errata.
Multiple revisions of any device may be simultaneously available through various sales channels. For
information about device errata, visit: http://dbserv.maxim-ic.com/errata.cfm.

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1. DESCRIPTION

The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured
for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers,
and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is
pin compatible with the DS21Qx5y family of products.

The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit
interface is responsible for generating the necessary wave shapes for driving the network and providing
the correct source impedance depending on the type of media used. T1 waveform generation includes
DSX–1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 wave shapes for both 75O coax and 120O twisted cables. The receive interface
provides network termination and recovers clock and data from the network. The receive sensitivity
adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for
E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase
jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications)
and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI
coder/decoder for interfacing to optical networks.

On the transmit side, clock data and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns, alarm information,
calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI
line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the
data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and
frame-sync signals to the backplane interface section.

Each transceiver has two HDLC controllers. The HDLC controllers transmit and receive data via the
framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a
time slot or to FDL (T1) or Sa bits (E1). Each controller has a 128-byte transmit FIFO and a 128-byte
receive FIFO, thus reducing the amount of processor overhead required to manage the flow of data. In
addition, there is built-in support for reducing the processor time req uired to handle SS7 applications.

The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers (two DS21Q55s) to share a high-speed backplane.

The parallel port provides access for control and configuration of all the DS21Q55’s features. The
Extended System Information Bus (ESIB) function allows up to eight transceivers, 2 DS21Q55s, to be
accessed via a single read for interrupt status or other user selectable alarm status information.
Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and
loop-down code generation and detection.

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The device fully meets all of the latest E1 and T1 specifications, including the following:

§ ANSI: T1.403-1995, T1.231-1993, T1.408

§ AT&T: TR54016, TR62411

§ ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161

§ ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12

§ Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only)

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1.1 FEATURE HIGHLIGHTS

The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and
E1 transceivers plus many new features.

1.1.1 General

§ 27mm, 1.27 pitch BGA

§ 3.3V supply with 5V tolerant inputs and outputs

§ Pin compatible with DS21x5y family

§ Software compatible with the DS2155

§ Evaluation kits

§ IEEE 1149.1 JTAG-boundary scan

§ Driver source code available from the factory

1.1.2 Line Interface

§ Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be

2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,

6.276MHz, or 12.552MHz for T1 -only operation

§ Fully software configurable

§ Short- and long-haul applications

§ Automatic receive sensitivity adjustments

§ Ranges include 0dB to -43dB or 0dB to -15dB for E1 applications; 0dB to -36dB or 0dB to -15dB

for T1 applications

§ Receive level indication in 2.5dB steps from -42.5dB to -2.5dB

§ Internal receive termination option for 75O, 100O, and 120O lines

§ Monitor application gain sett ings of 20dB, 26dB, and 32dB

§ G.703 receive-synchronization signal-mode

§ Flexible transmit-waveform generation

§ T1 DSX-1 line build-outs

§ T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB

§ E1 waveforms include G.703 waveshapes for both 75O coax and 120O twisted cables

§ AIS generation independent of loopbacks

§ Alternating ones and zeros generation

§ Square-wave output

§ Open-drain output option

§ NRZ format option

§ Transmitter power-down

§ Transmitter 50mA short-circuit limiter with exceeded indication of current limit

§ Transmit open-circuit-detected indication

§ Line interface function can be completely decoupled from the framer/formatter

1.1.3 Clock Synthesizer

§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz

§ Derived from recovered receive clock

1.1.4 Jitter Attenuator

§ 32-bit or 128-bit crystal-less jitter attenuator

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§ Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use

1.544MHz for T1 operation

§ Can be placed in either the receive or transmit path or disabled

§ Limit trip indication

1.1.5 Framer/Formatter

§ Fully independent transmit and receive functionality

§ Full receive- and transmit-path transparency

§ T1 framing formats include D4 (SLC -96) and ESF

§ Detailed alarm- and status-reporting with optional interrupt support

§ Large path- and line-error counters for:

− T1 – BPV, CV, CRC6, and framing bit errors

− E1 – BPV, CV, CRC4, E-bit, and frame alignment errors

− Timed or manual update modes

§ DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths

− User-defined

− Digital mill iwatt

§ ANSI T1.403-1998 support

§ E1ETS 300 011 RAI generation

§ G.965 V5.2 link detect

§ Ability to monitor one DS0 channel in both the transmit and receive paths

§ In -band repeating-pattern generators and detectors

− Three independent generators and detectors

− Patterns from 1 bit to 8 bits or 16 bits in length

§ RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

§ Flexible signaling support

− Software- or hardware-based

− Interrupt generated on change of signaling data

− Receive-signaling freeze o n loss of sync, carrier loss, or frame slip

§ Addition of hardware pins to indicate carrier loss and signaling freeze

§ Automatic RAI generation to ETS 300 011 specifications

§ Expanded access to Sa and Si bits

§ Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233

§ Japanese J1 support

− Ability to calculate and check CRC6 according to the Japanese standard

− Ability to generate yellow alarm according to the Japanese standard

1.1.6 System Interface

§ Dual two -frame, independent receive and transmit elastic stores

− Independent control and clocking

− Controlled-slip capability with status

− Minimum -delay mode supported

§ Maximum 16.384MHz backplane burst rate

§ Supports T1 to CEPT (E1) conversion

§ Programmable output clocks for fractional T1, E1, H0, and H12 applications

§ Interleaving PCM bus operation

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§ Hardware-signaling capability

− Receive-signaling reinsertion to a backplane, multiframe sync

− Availability of signaling in a separate PCM data stream

− Signaling freezing

§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode

§ Access to the data streams in between the framer/formatter and the elastic stores

§ User-selectable synthesized clock output

1.1.7 HDLC Controllers

§ Two independent HDLC controllers

§ Fast load and unload features for FIFOs

§ SS7 support for FISU transmit and receive

§ Independent 128-byte RX and TX buffers with interrupt support

§ Access FDL, Sa, or single/multiple DS0 channels

§ DS0 access includes Nx64 or Nx56

§ Compatible with polled or interrupt-driven environments

§ Bit Oriented Code (BOC) support

1.1.8 Test and Diagnostics

§ Programmable on-chip Bit Error Rate Testing (BERT)

§ Pseudorandom patterns including QRSS

§ User-defined repetitive patterns

§ Daly pattern

§ Error insertion single and continuous

§ Total-bit and errored-bit counts

§ Payload Error Insertion

§ Error insertion in the payload portion of the T1 frame in the transmit path

§ Errors can be inserted over the entire frame or selected channels

§ Insertion options include continuous and absolute number with selectable insertion rates

§ F-bit corruption for line testing

§ Loopbacks (remote, local, analog, and per-channel loopback)

1.1.9 Extended System Information Bus

§ Host can read interrupt and alarm status on up to eight ports with a single-bus read

1.1.10 Control Port

§ 8-bit parallel control port

§ Multiplexed or nonmultiplexed buses

§ Intel or Motorola formats

§ Supports polled or interrupt-driven environments

§ Software access to device ID and silicon revision

§ Software-reset supported

Automatic clear on power-up

§ Flexible register-space resets

§ Hardware reset pin

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Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In
each 125µs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is

sent first followed by channel 1. Each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the
MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two
clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz
clock can be locked to a 2.048MHz clock if they share the same 8kHz component).

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TABLE OF CONTENTS

1.1 FEATURE HIGHLIGHTS ............................................................................................................................4

1.1.1 General ..................................................................................................................................................4

1.1.2 Line Interface ....................................................................................................................................... 4

1.1.3 Clock Synthesizer ..............................................................................................................................4

1.1.4 Jitter Attenuator ................................................................................................................................... 4

1.1.5 Framer/Formatter ............................................................................................................................... 5

1.1.6 System Interface.................................................................................................................................5

1.1.7 HDLC Controllers ...............................................................................................................................6

1.1.8 Test and Diagnostics........................................................................................................................6

1.1.9 Extended System Information Bus...............................................................................................6

1.1.10 Control Port ..........................................................................................................................................6

1.2 DOCUMENT REVISION HISTORY .......................................................................................................12

2. BLOCK DIAGRAM ...........................................................................................................................................13

3. PIN FUNCTION DESCRIPTION..................................................................................................................14

3.1 TRANSMIT SIDE PINS.....................................................................................................................................14

3.2 RECEIVE SIDE PINS........................................................................................................................................16

3.3 PARALLEL CONTROL PORT PINS.................................................................................................................18

3.4 EXTENDED SYSTEM INFORMATION BUS.....................................................................................................20

3.5 JTAG TEST ACCESS PORT PINS...................................................................................................................20

3.6 LINE INTERFACE PINS....................................................................................................................................21

3.7 SUPPLY PINS...................................................................................................................................................22

3.8 PINOUT ............................................................................................................................................................23

3.9 PACKAGE.........................................................................................................................................................29

4. PARALLEL PORT ............................................................................................................................................30

4.1 REGISTER MAP...............................................................................................................................................30

5. SPECIAL PER-CHANNEL REGISTER OPERATION .........................................................................36

6. PROGRAMMING MODEL..............................................................................................................................38

6.1 POWER-UP S EQUENCE..................................................................................................................................39

6.1.1 Master Mode Register ....................................................................................................................39

6.2 INTERRUPT HANDLING..................................................................................................................................40

6.3 STATUS REGISTERS........................................................................................................................................40

6.4 INFORMATION REGISTERS............................................................................................................................41

6.5 INTERRUPT INFORMATION REGISTERS ........................................................................................................41

7. CLOCK MAP.......................................................................................................................................................42

8. T1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................43

8.1 T1 CONTROL REGISTERS..............................................................................................................................43

8.2 T1 TRANSMIT TRANSPARENCY ....................................................................................................................48

8.3 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE G ENERATION.................................................................48

8.4 T1 INFORMATION REGISTER........................................................................................................................50

9. E1 FRAMER/FORMATTER CONTROL REGISTERS .........................................................................52

9.1 E1 CONTROL REGISTERS..............................................................................................................................52

9.2 AUTOMATIC ALARM G ENERATION.............................................................................................................56

9.3 E1 INFORMATION REGISTERS .......................................................................................................................57

10. COMMON CONTROL AND STATUS REGISTERS.........................................................................59

11. I/O PIN CONFIGURATION OPTIONS...................................................................................................66

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12. LOOPBACK CONFIGURATION .............................................................................................................68

12.1 PER-CHANNEL LOOPBACK...........................................................................................................................70

13. ERROR COUNT REGISTERS .................................................................................................................72

13.1 LINE CODE V IOLATION COUNT REGISTER (LCVCR) ..............................................................................73

13.2 PATH CODE V IOLATION COUNT REGISTER (PCVCR) .............................................................................75

13.3 FRAMES OUT OF SYNC COUNT REGISTER (FOSCR) ...............................................................................76

13.4 E-BIT COUNTER REGISTER (EBCR) ...........................................................................................................78

14. DS0 MONITORING FUNCTION..............................................................................................................79

14.1 TRANSMIT DS0 MONITOR REGISTERS........................................................................................................79

14.2 RECEIVE DS0 MONITOR REGISTERS...........................................................................................................80

15. SIGNALING OPERATION .........................................................................................................................81

15.1 RECEIVE SIGNALING......................................................................................................................................81

15.1.1 Processor-Based Receive Signaling .........................................................................................82

15.1.2 Hardware-Based Receive Signaling..........................................................................................82

15.2 TRANSMIT SIGNALING...................................................................................................................................87

15.2.1 Processor-Based Transmit Signaling........................................................................................87

15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.......................................93

15.2.3 Software Signaling Insertion Enable Registers, T1 Mode ..................................................95

16. PER-CHANNEL IDLE CODE GENERATION.....................................................................................97

16.1 IDLE CODE PROGRAMMING EXAMPLES......................................................................................................98

17. CHANNEL BLOCKING REGISTERS..................................................................................................103

18. ELASTIC STORES OPERATION .........................................................................................................106

18.1 RECEIVE SIDE..............................................................................................................................................110

18.1.1 T1 Mode............................................................................................................................................110

18.1.2 E1 Mode ............................................................................................................................................110

18.2 TRANSMIT SIDE...........................................................................................................................................111

18.2.1 T1 Mode............................................................................................................................................111

18.2.2 E1 Mode ............................................................................................................................................111

18.3 ELASTIC S TORES INITIALIZATION.............................................................................................................111

18.4 MINIMUM-DELAY MODE...........................................................................................................................111

19. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................113

20. T1 BIT ORIENTED CODE (BOC) CONTROLLER .........................................................................114

20.1 TRANSMIT BOC ..........................................................................................................................................114

20.2 RECEIVE BOC.............................................................................................................................................114

21. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) .................118

21.1 HARDWARE SCHEME (METHOD 1)...........................................................................................................118

21.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2)..........................................118

21.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME (METHOD 3)...................................121

22. HDLC CONTROLLERS ............................................................................................................................132

22.1 BASIC OPERATION DETAILS......................................................................................................................132

22.2 HDLC CONFIGURATION............................................................................................................................134

22.2.1 FIFO Control ....................................................................................................................................136

22.3 HDLC MAPPING.........................................................................................................................................137

22.3.1 Receive..............................................................................................................................................137

22.3.2 Transmit.............................................................................................................................................139

22.3.3 FIFO Information............................................................................................................................144

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22.3.4 Receive Packet Bytes Available ...............................................................................................144

22.3.5 HDLC FIFOS ....................................................................................................................................145

22.4 RECEIVE HDLC CODE EXAMPLE.............................................................................................................146

22.5 LEGACY FDL SUPPORT (T1 MODE).........................................................................................................146

22.5.1 Receive Section..............................................................................................................................146

22.5.2 Transmit Section .............................................................................................................................148

22.6 D4/SLC– 96 OPERATION............................................................................................................................148

23. LINE INTERFACE UNIT (LIU)................................................................................................................149

23.1 LIU OPERATION.......................................................................................................................................... 150

23.2 LIU RECEIVER............................................................................................................................................. 150

23.2.1 Receive Level Indicator...............................................................Error! Bookmark not defined.

23.2.2 Receive G.703 Synchronization Signal (E1 Mode) ............................................................151

23.2.3 Monitor Mode...................................................................................................................................151

23.3 LIU TRANSMITTER.....................................................................................................................................152

23.3.1 Transmit Short -Circuit Detector/Limiter..................................................................................152

23.3.2 Transmit Open -Circuit Detector................................................................................................152

23.3.3 Transmit BPV Error Insertion .....................................................................................................152

23.3.4 Transmit G.703 Synchronization Signal (E1 Mode)...........................................................152

23.4 MCLK PRESCALER.....................................................................................................................................153

23.5 JITTER ATTENUATOR..................................................................................................................................153

23.6 CMI (CODE MARK INVERSION) OPTION.................................................................................................153

23.7 LIU CONTROL REGISTERS......................................................................................................................... 154

23.8 RECOMMENDED CIRCUITS.........................................................................................................................164

23.9 COMPONENT S PECIFICATIONS...................................................................................................................166

24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION................170

25. BERT FUNCTION .......................................................................................................................................177

25.1 BERT REGISTER DESCRIPTION................................................................................................................. 178

25.2 BERT REPETITIVE PATTERN SET............................................................................................................. 183

25.3 BERT BIT COUNTER.................................................................................................................................. 184

25.4 BERT ERROR COUNTER............................................................................................................................ 185

26. PAYLOAD ERROR INSERTION FUNCTION...................................................................................186

26.1 NUMBER OF ERROR REGISTERS...............................................................................................................188

26.1.1 Number Of Errors Left Register................................................................................................189

27. INTERLEAVED PCM BUS OPERATION ...........................................................................................190

27.1 CHANNEL INTERLEAVE MODE..................................................................................................................190

27.2 FRAME INTERLEAVE MODE.......................................................................................................................190

28. EXTENDED SYSTEM INFORMATION BUS (ESIB)......................................................................193

29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER......................................................197

30. FRACTIONAL T1/E1 SUP PORT...........................................................................................................198

31. JTAG-BOUNDARY-SCAN ARCHITECTURE AN D TEST-ACCESS PORT .........................199

31.1 INSTRUCTION REGISTER.............................................................................................................................203

31.2 TEST REGISTERS ..........................................................................................................................................205

31.3 BOUNDARY SCAN REGISTER.....................................................................................................................205

31.4 BYPASS REGISTER ...................................................................................................................................... 205

31.5 IDENTIFICATION REGISTER........................................................................................................................205

32. FUNCTIONAL TIMING DIAGRAMS....................................................................................................208

32.1 T1 MODE......................................................................................................................................................208

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32.2 E1 MODE......................................................................................................................................................218

33. OPERATING PARAMETERS.................................................................................................................231

34. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................233

34.1 MULTIPEXED BUS AC CHARACTERISTICS..............................................................................................233

34.2 NONMULTIPLEXED BUS AC CHARACTERISTICS.................................................................................... 236

34.3 RECEIVE SIDE AC CHARACTERISTICS.....................................................................................................239

34.4 TRANSMIT AC CHARACTERISTICS...........................................................................................................243

35. MECHANICAL DESCRIPTIONS...........................................................................................................247

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1.2 DOCUMENT REVISION HISTORY

1) Initial Preliminary Release

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2. BLOCK DIAGRAM

A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4-1.
Details are shown in subsequent figures. The block diagram is then divided into three functional blocks:
LIU, framer, and backplane interface.

BLOCK DIAGRAM Figure 4- 1

TRANSCEIVER #4

TRANSCEIVER #3

TRANSCEIVER #2

RCLK

RLOS/LOTC

BPCLK
RLINK

RLCLK
RCHBLK

RCHCLK

RSER
RSYSCLK
RSYNC

RMSYNC
RSIG
RSIGF

RFSYNC
TSYNC

TSSYNC

TSYSCLK
TSER

TCHBLK
TCHCLK

TSIG
TLINK
TLCLK

TCLK

RRING

RTIP

TRING

TTIP

Clock / Data

Recovery

Line I/F

Transmit

Line I/F

VCO / PLL

Receive

RPOSO

RNEGO

RCLKO

Local Loopback

RNEGI

RCLKI

Either transmit or receive path

MUX

Jitter Attenuator

MUX

RPOSI

Remote Loopback

Receive Side

Framer Loopback

Transmit Side

Formatter

LOTC
MUX

Framer

DATA

CLOCK

SYNC

SYNC

CLOCK

DATA

HDLC/BOC
Controller

HDLC/BOC
Controller

8.192MHz Clock
Synthesizer

Timing
Control

Elastic

Store

Signaling Buffer

Sync Control

Elastic

Store

Timing Control
Signaling Buffer

CS4*

CS2*

CS3*

ESIBRD
ESIBS0
ESIBS1

BTS

CS1*

WR*(R/W*)

MUX

RD*(DS*)

INT*

Common
MCLK

MCLK1

MCLK2

LIUCI

TCLKI

TNEGI

TCLKO

TPOSI

TPOSO

TNEGO

JTAG Port

JTTST

JTDO

JTMS

JTDI

JTCLK

D0/AD0

D1/AD1

ESIB

Parallel Control Port (routed to all blocks)

D2/AD2

D3/AD3

D4/AD4

D5/AD5

D6/AD6

D7/AD7

A0

A1A2A3A4A5A6A7/ALE(AS)

TSTRST

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3. PIN FUNCTION DESCRIPTION

3.1 Transmit Side Pins

Signal Name: TCLKx
Signal Description: Transmit Clock
Signal Type: Input
A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.

Signal Name: TSERx
Signal Description: Transmit Serial Data
Signal Type: Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on
the falling edge of TSYSCLK when the transmit-side elastic store is enabled.

Signal Name: TCHCLKx
Signal Description: Transmit Channel Clock
Signal Type: Output
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a
gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is
disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.

Signal Name: TCHBLKx
Signal Description: Transmit Channel Block
Signal Type: Output
A user -programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the
transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for
locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per -channel
conditioning.

Signal Name: TSYSCLKx
Signal Description: Transmit System Clock
Signal Type: Input

1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit -side elastic-store function
is enabled. Should be ti ed low in applications that do not use the transmit-side elastic store. See Interleaved PCM Bus
Operation for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.

Signal Name: TLCLKx
Signal Description: Transmit Link Clock
Signal Type: Output
Demand clock for the transmit link data [TLINK] input.
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock.
E1 Mode: A 4kHz to 20kHz clock.

Signal Name: TLINKx
Signal Description: Transmit Link Data
Signal Type: Input
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs­bit position (D4) or the Z–bit position (ZBTSI) or any combination of the Sa bit positions (E1).

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Signal Name: TSYNCx
Signal Description: Transmit Sync
Signal Type: Input/Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output
either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1 .3 to
output double-wide pulses at signaling frames in T1 mode.

Signal Name: TSSYNCx
Signal Description: Transmit System Sync
Signal Type: Input
Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe
boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.

Signal Name: TSIGx
Signal Description: Transmit Signaling Input
Signal Type: Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge
of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side
elastic store is enabled.

Signal Name: TPOSOx
Signal Description: Transmit Positive Data Output
Signal Type: Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source
NRZ data via the output-data format (IOCR1 .0)-control bit. This pin is normally tied to TPOSI.

Signal Name: TNEGOx
Signal Description: Transmit Negative Data Output
Signal Type: Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to
TNEGI.

Signal Name: TCLKOx
Signal Description: Transmit Clock Output
Signal Type: Output
Buffered clock that is used to clock data through the transmit-side formatter (either TCLK or RCLKI). This pin is normally
tied to TCLKI.

Signal Name: TPOSIx
Signal Description: Transmit Positive Data Input
Signal Type: Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

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Signal Name: TNEGIx
Signal Description: Transmit Negative Data Input
Signal Type: Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

Signal Name: TCLKIx
Signal Description: Transmit Clock Input
Signal Type: Input
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.

3.2 Receive Side Pins

Signal Name: RLINKx
Signal Description: Receive Link Data
Signal Type: Output
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.

Signal Name: RLCLKx
Signal Description: Receive Link Clock
Signal Type: Output
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.

Signal Name: RCLKx
Signal Description: Receive Clock
Signal Type: Output

1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.

Signal Name: RCHCLKx
Signal Description: Receive Channel Clock
Signal Type: Output
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a
gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is
disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.

Signal Name: RCHBLKx
Signal Description: Receive Channel Block
Signal Type: Output
A user -programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with
RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Also useful for locating individual channels in drop-and-insert applications, for external per -channel loopback, and
for per -channel conditioning. See Channel Blocking Registers.

Signal Name: RSERx
Signal Description: Receive Serial Data
Signal Type: Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.

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Signal Name: RSYNCx
Signal Description: Receive Sync
Signal Type: Input/Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide
pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input
via IOCR1.4 at which a frame or multiframe boundary pulse is applied.

Signal Name: RFSYNCx
Signal Description: Receive Frame Sync
Signal Type: Output
An extracted 8k Hz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries.

Signal Name: RMSYNCx
Signal Description: Receive Multiframe Sync
Signal Type: Output
An extracted pulse, one RCLK wide (elastic store disabled) or one RSY SCLK wide (elastic store enabled), is output at this pin,
which identifies multiframe boundaries.

Signal Name: RSYSCLKx
Signal Description: Receive System Clock
Signal Type: Input

1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic-store function is enabled.
Should be tied low in applications that do not use the receive-side elastic store. See Interleaved PCM Bus Operation for details
on 4.096MHz and 8.192MHz operation using the IBO.

Signal Name: RSIGx
Signal Description: Receive Signaling Output
Signal Type: Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.

Signal Name: RLOS/LOTCx
Signal Description: Receive Loss of Sync/Loss of Transmit Clock
Signal Type: Output
A dual -function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5µsec.

Signal Name: RSIGFx
Signal Description: Receive Signaling Freeze
Signal Type: Output
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of
the condition.

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Signal Name: BPCLKx
Signal Description: Back Plane Clock
Signal Type: Output
A user -selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.

Signal Name: RPOSOx
Signal Description: Receive Positive Data Output
Signal Type: Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.

Signal Name: RNEGOx
Signal Description: Receive Negative Data Output
Signal Type: Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.

Signal Name: RCLKOx
Signal Description: Receive Clock Output
Signal Type: Output
Buffered recovered clock from the network. This pin is normally tied to RCLKI.

Signal Name: RPOSIx
Signal Description: Receive Positive Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.

Signal Name: RNEGIx
Signal Description: Receive Negative Data Input
Signal Type: Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.

Signal Name: RCLKIx
Signal Description: Receive Clock Input
Signal Type: Input
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC pin high.

3.3 Parallel Control Port Pins

Signal Name: INT*
Signal Description: Interrupt
Signal Type: Output
Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.

Signal Name: TSTRST
Signal Description: 3-State Control and Device Reset
Signal Type: Input
A dual -function pin. A zero-to-one transition issues a hardware reset to the DS21Q55 register set. A reset clears all
configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will 3-state all output and I/O
pins (including the parallel control port). Set low for normal operation. Useful in -board level testing.

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Signal Name: MUX
Signal Description: Bus Operation
Signal Type: Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.

Signal Name: D0/AD0 to D7/AD7
Signal Des cription: Data Bus [D0 to D7] or Address/Data Bus
Signal Type: Input/Output
In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an
8-bit, multiplexed address/data bus.

Signal Name: A0 to A6
Signal Description: Address Bus
Signal Type: Input
In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins
are not used and should be tied low.

Signal Name: BTS
Signal Description: Bus Type Select
Signal Type: Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*),
A7/ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis ().

Signal Name: RD*(DS*)
Signal Description: Read Input-Data Strobe
Signal Type: Input
RD* and DS* are active-low signals. DS active HIGH when MUX = 0. See bus timing diagrams.

Signal Name: CS1*
Signal Description: Chip Select for transceiver #1
Signal Type: Input
Must be low to read or write to transceiver #1 of the device. CS1* is an active-low signal.

Signal Name: CS2*
Signal Description: Chip Select for transceiver #2
Signal Type: Input
Must be low to read or write to transceiver #2 of the device. CS2* is an active-low signal.

Signal Name: CS3*
Signal Description: Chip Select for transceiver #3
Signal Type: Input
Must be low to read or write to transc eiver #3 of the device. CS3* is an active-low signal.

Signal Name: CS4*
Signal Description: Chip Select for transceiver #4
Signal Type: Input
Must be low to read or write to transceiver #4 of the device. CS4* is an active-low signal.

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Signal Name: A7/ALE(AS)
Signal Description: A7 or Address Latch Enable(Address Strobe)
Signal Type: Input
In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it
serves to demultiplex the bus on a positive-going edge.

Signal Name: WR*(R/W*)
Signal Description: Write Input(Read/Write)
Signal Type: Input
WR* is an active-low signal.

3.4 Extended System Information Bus

Signal Name: ESIBS0x
Signal Description: Extended System Information Bus Select 0
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.

Signal Name: ESIBS1x
Signal Description: Extended System Information Bus Select 1
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.

Signal Name: ESIBRDx
Signal Description: Extended System Information Bus Read
Signal Type: Input/Output
Used to group two DS21Q55s into a bus-sharing mode for alarm and status reporting. See Extended System Information Bus
(ESIB) for more details.

3.5 JTAG Test Access Port Pins

Signal Name: JTRST
Signal Description: IEEE 1149.1 Test Reset
Signal Type: Input
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to
high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST
low. JTRST is pulled HIGH internally via a 10k resistor operation.

Signal Name: JTMS
Signal Description: IEEE 1149.1 Test Mode Select
Signal Type: Input
This pin is sampled on the rising edge of JTCLK and is used to place the test -access port into the various defined IEEE 1149.1
states. This pin has a 10k pullup resistor.

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Signal Name: JTCLK
Signal Description: IEEE 1149.1 Test Clock Signal
Signal Type: Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.

Signal Name: JTDI
Signal Description: IEEE 1149.1 Test Data Input
Signal Type: Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor.

Signal Name: JTDO
Signal Description: IEEE 1149.1 Test Data Output
Signal Type: Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.

3.6 Line Interface Pins

Signal Name: MCLK1
Signal Description: Master Clock Input for Transceivers 1 & 2
Signal Type: Input
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate
can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation a 1.544MHz
(50ppm) clock source can be used. MCLK1 and MCLK2 may be driven from a common clock.

Signal Name: MCLK2
Signal Description: Master Clock Input for Transceivers 3 & 4
Signal Type: Input
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate
can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21Q55 in T1-only operation a 1.544MHz
(50ppm) clock source can be used. MCLK1 and MCLK2 may be driven from a common clock.

Signal Name: LIUC
Signal Description: Line Interface Connect
Signal Type: Input
Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circu itry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, the
TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.

Signal Name: RTIPx and RRINGx
Signal Description: Receive Tip and Ring
Signal Type: Input
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Line Interface Unit for
details.

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Signal Name: TTIPx and TRINGx
Signal Description: Transmit Tip and Ring
Signal Type: Output
Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Line Interface Unit for details.

3.7 Supply Pins

Signal Name: DVDD
Signal Description: Digital Posi tive Supply
Signal Type: Supply

3.3V ±5%. Should be tied to the RVDD and TVDD pins.

Signal Name: RVDD
Signal Description: Receive Analog Positive Supply
Signal Type: Supply

3.3V ±5%. Should be tied to the DVDD and TVDD pins.

Signal Name: TVDD
Signal Description: Transmit Analog Positive Supply
Signal Type: Supply

3.3V ±5% Should be tied to the RVDD and DVDD pins.

Signal Name: DVSS
Signal Description: Digital Signal Ground
Signal Type: Supply
Should be tied to the RVSS and TVSS pins.

Signal Name: RVSS
Signal Description: Receive Analog Signal Ground
Signal Type: Supply

0.0V. Should be tied to DV

Signal Name: TVSS
Signal Description: Transmit Analog Signal Ground
Signal Type: Supply

0.0V. Should be tied to DVSS and RVSS.

and TVSS.

SS

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3.8 Pinout

DS21Q55 PIN DESCRIPTION Table 5- 1

NOTE: Signal is common to all transceivers unless otherwise stated

PIN SYMBOL TYPE DESCRIPTION

U3 A0 I Address Bus Bit 0 (lsb).
L17 A1 I Address Bus Bit 1.
V2 A2 I Address Bus Bit 2.
T4 A3 I Address Bus Bit 3.
V8 A4 I Address Bus Bit 4.
H4 A5 I Address Bus Bit 5.
U8 A6 I Address Bus Bit 6.
P4 A7/ALE(AS) I Address Bus Bit 7 (msb) / Address Latch Enable.
M1 BPCLK1 O Back Plane Clock, Transceiver # 1.
H17 BPCLK2 O Back Plane Clock, Transceiver # 2.
F4 BPCLK3 O Back Plane Clock, Transceiver # 3.
V13 BPCLK4 O Back Plane Clock, Transceiver # 4.
P2 BTS I Bus Type Select (0 = Intel / 1 = Motorola),
P3 CS1* I Chip Select, Transceiver # 1.
A14 CS2* I Chip Select, Transceiver # 2.
B5 CS3* I Chip Select, Transceiver # 3.
K17 CS4* I Chip Select, Transceiver # 4.
U11 D0/AD0 I/O Data Bus Bit 0/ Address/Data Bus Bit 0 (lsb).
J19 D1/AD1 I/O Data Bus Bit 1/ Address/Data Bus Bit 1.
W15 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus Bit 2.
U7 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3.
U9 D4/AD4 I/O Data Bus Bit 4/Address/Data Bus Bit 4.
U5 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5.
V4 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6.
U4 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7 (msb).
J3 DVDD1 – Digital Positive Supply.
N4 DVDD1 – Digital Positive Supply.
U2 DVDD1 – Digital Positive Supply.
V5 DVDD1 – Digital Positive Supply.
B12 DVDD2 – Digital Positive Supply.
C12 DVDD2 – Digital Positive Supply.
C16 DVDD2 – Digital Positive Supply.
D18 DVDD2 – Digital Positive Supply.
A9 DVDD3 – Digital Positive Supply.
B3 DVDD3 – Digital Positive Supply.
B6 DVDD3 – Digital Positive Supply.
C4 DVDD3 – Digital Positive Supply.
G20 DVDD4 – Digital Positive Supply.
M17 DVDD4 – Digital Positive Supply.
M20 DVDD4 – Digital Positive Supply.
P18 DVDD4 – Digital Positive Supply.
H3 DVSS1 – Digital Signal Ground.
U6 DVSS1 – Digital Signal Ground.
W8 DVSS1 – Digital Signal Ground.
A17 DVSS2 – Digital Signal Ground.

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PIN SYMBOL TYPE DESCRIPTION

A20 DVSS2 – Digital Signal Ground.
B11 DVSS2 – Digital Signal Ground.
A5 DVSS3 – Digital Signal Ground.
B7 DVSS3 – Digital Signal Ground.
B9 DVSS3 – Digital Signal Ground.
H20 DVSS4 – Digital Signal Ground
L20 DVSS4 – Digital Signal Ground
N17 DVSS4 – Digital Signal Ground
J4 ESIBRD1 – Extended System Information Bus Read, Transceiver # 1.
C13 ESIBRD2 – Extended System Information Bus Read, Transceiver # 2.
C3 ESIBRD3 – Extended System Information Bus Read, Transceiver # 3.
U13 ESIBRD4 – Extended System Information Bus Read, Transceiver # 4.
W6 ESIBS0_1 I/O Extended System Information Bus 0, Transceiver # 1.
F18 ESIBS0_2 I/O Extended System Information Bus 0, Transceiver # 2.
D7 ESIBS0_3 I/O Extended System Information Bus 0, Transceiver # 3.
T20 ESIBS0_4 I/O Extended System Information Bus 0, Transceiver # 4.
V9 ESIBS1_1 I/O Extended System Information Bus 1, Transceiver # 1.
B17 ESIBS1_2 I/O Extended System Information Bus 1, Transceiver # 2.
A6 ESIBS1_3 I/O Extended System Information Bus 1, Transceiver # 3.
J20 ESIBS1_4 I/O Extended System Information Bus 1, Transceiver # 4.
U1 INT* O Interrupt.
Y15 JTCLK I JTAG Clock.
N1 JTDI I JTAG Data Input, Transceiver #1
V19 JTDO O JTAG Data Output. Transceiver #4
W13 JTMS I JTAG Test Mode Select.
V18 JTRST* I JTAG Reset.
K2 LIUC I Line Interface Connect.
T1 MCLK1 I Master Clock, Transceiver #1 and, Transceiver #3.
W20 MCLK2 I Master Clock, Transceiver #2 and, Transceiver #4.
U10 MUX I Mux Bus Select.
M2 RCHBLK1 O Receive Channel Block, Transceiver #1.
G17 RCHBLK2 O Receive Channel Block, Transceiver #2.
G4 RCHBLK3 O Receive Channel Block, Transceiver #3.
Y12 RCHBLK4 O Receive Channel Block, Transceiver #4.
J1 RCHCLK1 O Receive Channel Clock, Transceiver #1.
D14 RCHCLK2 O Receive Channel Clock, Transceiver #2.
F3 RCHCLK3 O Receive Channel Clock, Transceiver #3.
U14 RCHCLK4 O Receive Channel Clock, Transceiver #4.
N3 RCLK1 O Receive Clock Output from the Framer, Transceiver #1.
B13 RCLK2 O Receive Clock Output from the Framer, Transceiver #2.
E3 RCLK3 O Receive Clo ck Output from the Framer, Transceiver #3.
M18 RCLK4 O Receive Clock Output from the Framer, Transceiver #4.
M4 RCLKI1 I Receive Clock Input for the LIU, Transceiver #1.
A15 RCLKI2 I Receive Clock Input for the LIU, Transceiver #2.
A4 RCLKI3 I Receive Clock Input for the LIU, Transceiver #3.
R17 RCLKI4 I Receive Clock Input for the LIU, Transceiver #4.
M3 RCLKO1 O Receive Clock Output from the LIU, Transceiver #1.
C14 RCLKO2 O Receive Clock Output from the LIU, Transceiver #2.
B4 RCLKO3 O Receive Clock Output from the LIU, Transceiver #3.
T17 RCLKO4 O Receive Clock Output from the LIU, Transceiver #4.
N2 RD*(DS*) I Read Input (Data Strobe)
K4 RFSYNC1 O Receive Frame Sync (before the receive elastic store), Transceiver

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PIN SYMBOL TYPE DESCRIPTION

#1.

D17 RFSYNC2 O Receive Frame Sync (before the receive elastic store), Transceiver

#2.

A2 RFSYNC3 O Receive Frame Sync (before the receive elastic store), Transceiver

#3.

V14 RFSYNC4 O Receive Frame Sync (before the receive elastic store), Transceiver

#4.
F1 RLCLK1 O Receive Lin k Clock, Transceiver #1.
A12 RLCLK2 O Receive Link Clock, Transceiver #2.
D3 RLCLK3 O Receive Link Clock, Transceiver #3.
K18 RLCLK4 O Receive Link Clock, Transceiver #4.
G2 RLINK1 O Receive Link Data, Transceiver #1.
A13 RLINK2 O Receive Link Data, Transceiver #2.
A3 RLINK3 O Receive Link Data, Transceiver #3.
U12 RLINK4 O Receive Link Data, Transceiver #4.
H2 RLOS/LOTC1 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #1.
E17 RLOS/LOTC2 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #2.
E1 RLOS/LOTC3 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #3.
V11 RLOS/LOTC4 O Receive Loss Of Sync / Loss Of Transmit Clock, Transceiver #4.
L1 RMSYNC1 O Receive Multiframe Sync, Transceiver #1.
D16 RMSYNC2 O Receive Multiframe Sync, Transceiver #2.
F2 RMSYNC3 O Receive Multiframe Sync, Transceiver #3.
W16 RMSYNC4 O Receive Multiframe Sync, Transceiver #4.
R3 RNEGI1 I Receive Negative Data for the Framer, Transceiver #1.
D13 RNEGI2 I Receive Negative Data for the F ramer, Transceiver #2.
A1 RNEGI3 I Receive Negative Data for the Framer, Transceiver #3.
P17 RNEGI4 I Receive Negative Data for the Framer, Transceiver #4.
L3 RNEGO1 O Receive Negative Data from the LIU, Transceiver #1.
B15 RNEGO2 O Receive Negative Da ta from the LIU, Transceiver #2.
C2 RNEGO3 O Receive Negative Data from the LIU, Transceiver #3.
U17 RNEGO4 O Receive Negative Data from the LIU, Transceiver #4.
R4 RPOSI1 I Receive Positive Data for the Framer, Transceiver #1.
B14 RPOSI2 I Receive Positive Data for the Framer, Transceiver #2.
B2 RPOSI3 I Receive Positive Data for the Framer, Transceiver #3.
V15 RPOSI4 I Receive Positive Data for the Framer, Transceiver #4.
L4 RPOSO1 O Receive Positive Data from the LIU, Transceiver #1.
A16 RPOSO2 O Receive Positive Data from the LIU, Transceiver #2.
B1 RPOSO3 O Receive Positive Data from the LIU, Transceiver #3.
U15 RPOSO4 O Receive Positive Data from the LIU, Transceiver #4.
Y11 RRING1 I Receive Analog Ring Input, Transceiver #1.
Y14 RRING2 I Receive Analog Ring Input, Transceiver #2.
Y17 RRING3 I Receive Analog Ring Input, Transceiver #3.
Y20 RRING4 I Receive Analog Ring Input, Transceiver #4.
J2 RSER1 O Receive Serial Data, Transceiver #1.
D15 RSER2 O Receive Serial Data, Transceiver #2.
E2 RSER3 O Receive Serial Data, Transceiver #3.
W17 RSER4 O Receive Serial Data, Transceiver #4.
L2 RSIG1 O Receive Signaling Output, Transceiver #1.
B16 RSIG2 O Receive Signaling Output, Transceiver #2.
C1 RSIG3 O Receive Signaling Output, Transceiver #3.
Y18 RSIG4 O Receive Signaling Output, Transceiver #4.
K1 RSIGF1 O Receive Signaling Freeze Output, Transceiver #1.
C15 RSIGF2 O Receive Signaling Freeze Output, Transceiver #2.

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PIN SYMBOL TYPE DESCRIPTION

D2 RSIGF3 O Receive Signaling Freeze Output, Transceiver #3.
V16 RSIGF4 O Receive Signaling Freeze Output, Transceiver #4.
G1 RSYNC1 I/O Receive Sync, Transceiver #1.
D12 RSYNC2 I/O Receive Sync, Transceiver #2.
D1 RSYNC3 I/O Receive Sync, Transceiver #3.
V12 RSYNC4 I/O Receive Sync, Transceiver #4.
H1 RSYSCLK1 I Receive System Clock, Transceiver #1.
F17 RSYSCLK2 I Receive System Clock, Transceiver #2.
G3 RSYSCLK3 I Receive System Clock, Transceiver #3.
W14 RSYSCLK4 I Receive System Clock, Transceiver #4.
Y10 RTIP1 I Receive Analog Tip Input, Transceiver #1.
Y13 RTIP2 I Receive Analog Tip Input, Transceiver #2.
Y16 RTIP3 I Receive Analog Tip Input, Transceiver #3.
Y19 RTIP4 I Receive Analog Tip Input, Transceiver #4.
P1 RVDD1 – Receive Analog Positive Supply.
J17 RVDD2 – Receive Analog Positive Supply.
E4 RVDD3 – Receive Analog Positive Supply.
W18 RVDD4 – Receive Analog Positive Supply.
R2 RVSS1 – Receive Analog Signal Ground
T2 RVSS1 – Receive Analog Signal Ground
H19 RVSS2 – Receive Analog Signal Ground
J18 RVSS2 – Receive Analog Signal Ground
D4 RVSS3 – Receive Analog Signal Ground
D5 RVSS3 – Receive Analog Signal Ground
V20 RVSS4 – Receive Analog Signal Ground
W19 RVSS4 – Receive Analog Signal Ground
W1 TCHBLK1 O Transmit Channel Block, Transceiver #1.
F20 TCHBLK2 O Transmit Channel Block, Transceiver #2.
C11 TCHBLK3 O Transmit Channel Block, Transceiver #3.
U20 TCHBLK4 O Transmit Channel Block, Transceiver #4.
V10 TCHCLK1 O Transmit Channel Clock, Transceiver #1.
A18 TCHCLK2 O Transmit Channel Clock, Transceiver #2.
B8 TCHCLK3 O Transmit Channel Clock, Transceiver #3.
L18 TCHCLK4 O Transmit Channel Clock, Transceiver #4.
Y9 TCLK1 I Transmit Clock, Transceiver #1.
B19 TCLK2 I Transmit Clock, Transceiver #2.
B10 TCLK3 I Transmit Clock, Transceiver #3.
M19 TCLK4 I Transmit Clock, Transceiver #4.
V6 TCLKI1 I Transmit Clock Input for the LIU, Transceiver #1.
D19 TCLKI2 I Transmit Clock Input for the LIU, Transceiver #2.
C8 TCLKI3 I Transmit Clock Input for the LIU, Transceiver #3.
P20 TCLKI4 I Transmit Clock Input for the LIU, Transceiver #4.
W7 TCLKO1 O Transmit Clock Output from the Framer, Transceiver #1.
E18 TCLKO2 O Transmit Clock Output from the Framer, Transceiver #2.
A7 TCLKO3 O Transmit Clock Output from the Framer, Transceiver #3.
P19 TCLKO4 O Transmit Clock Output from the Framer, Transceiver #4.
V3 TLCLK1 O Transmit Link Clock, Transceiver #1.
E20 TLCLK2 O Transmit Link Clock, Transceiver #2.
D6 TLCLK3 O Transmit Link Clock, Transceiver #3.
T18 TLCLK4 O Transmit Link Clock, Transceiver #4.
W5 TLINK1 I Transmit Link Data, Transceiver #1.
E19 TLINK2 I Transmit Link Data, Transceiver #2.

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PIN SYMBOL TYPE DESCRIPTION

C6 TLINK3 I Transmit Link Data, Transceiver #3.
T19 TLINK4 I Transmit Link Data, Transceiver #4.
R1 TNEGI1 I Transmit Negative Data Input for the LIU, Transceiver #1.
F19 TNEGI2 I Transmit Negative Data Input for the LIU, Transceiver #2.
D8 TNEGI3 I Transmit Negative Data Input for the LIU, Transceiver #3.
R20 TNEGI4 I Transmit Negative Data Input for the LIU, Transceiver #4.
T3 TNEGO1 O Transmit Negative Data Output from Framer, Transceiver #1.
B20 TNEGO2 O Transmit Negative Data Output from Framer, Transceiver #2.
D9 TNEGO3 O Transmit Negative Data Output from Framer, Transceiver #3.
N20 TNEGO4 O Transmit Negative Data Output from Framer, Transceiver #4.
W3 TPOSI1 I Transmit Posit ive Data Input for the LIU, Transceiver #1.
C20 TPOSI2 I Transmit Positive Data Input for the LIU, Transceiver #2.
A8 TPOSI3 I Transmit Positive Data Input for the LIU, Transceiver #3.
R19 TPOSI4 I Transmit Positive Data Input for the LIU, Transceiver # 4.
V7 TPOSO1 O Transmit Positive Data Output from Framer, Transceiver #1.
C19 TPOSO2 O Transmit Positive Data Output from Framer, Transceiver #2.
C9 TPOSO3 O Transmit Positive Data Output from Framer, Transceiver #3.
N19 TPOSO4 O Transmit Positive Data Output from Framer, Transceiver #4.
Y2 TRING1 O Transmit Analog Ring Output, Transceiver #1.
Y4 TRING2 O Transmit Analog Ring Output, Transceiver #2.
Y6 TRING3 O Transmit Analog Ring Output, Transceiver #3.
Y8 TRING4 O Transmit Analog Ring Output, Transceiver #4.
W9 TSER1 I Transmit Serial Data, Transceiver #1.
C17 TSER2 I Transmit Serial Data, Transceiver #2.
C10 TSER3 I Transmit Serial Data, Transceiver #3.
K20 TSER4 I Transmit Serial Data, Transceiver #4.
W10 TSIG1 I Transmit Signaling Input, Transceiver #1.
C18 TSIG2 I Transmit Signaling Input, Transceiver #2.
A10 TSIG3 I Transmit Signaling Input, Transceiver #3.
L19 TSIG4 I Transmit Signaling Input, Transceiver #4.
W12 TSSYNC1 I Transmit System Sync, Transceiver #1.
B18 TSSYNC2 I Transmit System Sync, Transceiver #2.
D10 TSSYNC3 I Transmit System Sync, Transceiver #3.
K19 TSSYNC4 I Transmit System Sync, Transceiver #4.
U16 TSTRST I Test/Reset
V1 TSYNC1 I/O Transmit Sync, Transceiver #1.
D20 TSYNC2 I/O Transmit Sync, Transceiver #2.
C7 TSYNC3 I/O Transmit Sync, Transceiver #3.
R18 TSYNC4 I/O Transmit Sync, Transceiver #4.
W11 TSYSCLK1 I Transmit System Clock, Transceiver #1.
A19 TSYSCLK2 I Transmit System Clock, Transceiver #2.
A11 TSYSCLK3 I Transmit System Clock, Transceiver #3.
N18 TSYSCLK4 I Transmit System Clock, Transceiver #4.
Y1 TTIP1 O Transmit Analog Tip Output, Transceiver #1.
Y3 TTIP2 O Transmit Analog Tip Output, Transceiver #2.
Y5 TTIP3 O Transmit Analog Tip Output, Transceiver #3.
Y7 TTIP4 O Transmit Analog Tip Output, Transceiver #4.
W2 TVDD1 – Transmit Analog Positive Supply.
G19 TVDD2 – Transmit Analog Positive Supply.
D11 TVDD3 – Transmit Analog Positive Supply.
U19 TVDD4 – Transmit Analog Positive Supply.
W4 TVSS1 – Transmit Analog Signal Ground.

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PIN SYMBOL TYPE DESCRIPTION

G18 TVSS2 – Transmit Analog Signal Ground.
C5 TVSS3 – Transmit Analog Signal Ground.
U18 TVSS4 – Transmit Analog Signal Ground.
K3 WR* (R/W*) I Write Input (Read/Write).

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3.9 Package
DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5-1

The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen
as viewed from the top.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

rnegi 3 rfsync

A

rposo 3 rposi 3 dvdd 3 rclko 3 cs

B

rsig 3 rnego

C

rsync 3 rsigf 3 rlclk 3 rvss 3 rvss 3 tlclk 3 esibs0

D

rlos 3 rser 3 rclk 3 rvdd

E

rlclk 1 rmsync

F

rsync 1 rlink 1 rsysclk

G

rsysclk

H

1

rchclk

J

1

rsigf

K

1

rmsync

L

1

bpclk 1 rchblk

M

jtdi rd*

N

rvdd

P

1

tnegi 1 rvss 1 rnegi 1 rposI

R

mclk 1 rvss 1 tnego

T

int*

U

tsync

V

1

tchblk

W

1

ttip 1 tring 1 ttip 2 tring 2 ttip 3 tring

Y

rlink 3 rclki 3 dvss 3 esibs1

3

eisb rd

3

3

rlos 1 dvss

rser 1 dvdd 1 eisbrd

liuc wr*
rsig 1 rnego

1

bts

dvdd

1

A2

tvdd 1 tposi 1 tvss 1 tlink 1 esibs0

dvdd 3 tvss 3 tlink 3 tsync

3

3

rchclk

bpclk

3

3

rchblk

3

3

a5

1

1

rfsync

1

rposo

1

1

rclko 1 rclki

1

rclk 1 dvdd

1

cs

A7/AL

1*

E(AS)

1

A3

1

D7/

A0

AD7

tlclk 1 D6/

AD6

3

dvdd 3 dvss 3 tchclk

3*

A1

D5/

dvss 1 D3/

AD5

dvdd 1 tclki 1 tposo

1

3

tclko

3

3

3

AD3

1

tclko 1 dvss 1 tser 1 tsig 1 tsysclk

ttip

4

dvdd 3 tsig 3 tsysclk

tposi

3

dvss 3 tclk 3 dvss 2 dvdd 2 rclk 2 rposi 2 rnego

3

tclki 3 tposo

3

tnegi 3 tnego

3

D4/

A6

AD4

esibs1

A4

1

tring 4 tclk 1 rtip 1 rring 1 rchblk

3

tser 3 tchblk

3

tssync

tvdd 3 rsync 2 rnegi 2 rchclk

3

D0/

mux

AD0

tchclk

rlos 4 rsync 4 bpclk

1

1

rlclk 2 rlink 2 cs

dvdd 2 eisbrd

2

rlink 4 eisbrd

4

4

tssync

jtms

1

rtip 2 rring

4

rclki 2 rposo 2 dvss 2 tchclk

2*

rsig 2 esibs1

2

rclko 2 rsigf 2 dvdd 2 tser 2 tsig 2 tposo 2 tposi

rser 2 rmsync

2

rchclk

rposo

4

4

rfsync

rposi 4 rsigf

4

rsysclk

D2/

4

2

rmsync

AD2
jtclk

2

rfsync

2

2

rlos 2 tclko 2 tlink 2 tlclk

rsysclk

2

rchblk

2

bpclk

2

rvdd 2 rvss 2 D1/

cs
4*

dvdd 4 rclk 4 tclk 4 dvdd

dvss 4 tsys

rnegi 4 dvdd 4 tclko 4 tclki

rclki 4 tsync

rclko 4 tlclk 4 tlink 4 esibs0

rnego

tstrst

4

NC jtrst* jtdo

4

rser 4 rvdd 4 rvss 4 mclk

4

rtip 3 rring 3 rsig 4 rtip 4 rring

tsysclk

2

2

tssync

tclk 2 tnego

2

dvdd 2 tclki 2 tsync

esibs0

tnegi 2 tchblk

2

tvss 2 tvdd 2 dvdd

rvss 2 dvss

NC

esibs1

AD1

rlclk 4 tssync

4

tchclk

tsig 4 dvss

4

tposo 4 tnego

clk4

tposi 4 tnegi

4

tvss 4 tvdd 4 tchblk

dvss

2

2

2

2

2

2

4

4

4

tser

4

4

4

4

4

4

4

4

rvss

4

2

4

NOTE: Locations C3, C13, J4, and U13 are used for the Extended System Information Bus (ESIB). These pin locations on the
DS21Q352, DS21Q354, DS21Q552, and DS21Q554 are connected to ground. When replacing a DS21Qx5y with a
DS21Q55B, these signals should be routed to control logic in order to gain access to the ESIB. If these pins remain connected
to ground, the ESIB function will be disabled.

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4. PARALLEL PORT

The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an
external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the AC Electrical Characteristics for more details. Each of the four transceivers has a complete register
set as shown below. There are four individual Chip Select signals (CS1*, CS2*, CS3*, CS4*) that are
used select one of the four transceivers.

4.1 Register Map

REGISTER MAP SORTED BY ADDRESS Table 6-1

ADDRESS R/W REGISTER NAME

00
01 I/O Configuration Register 1 IOCR1 *
02 I/O Configuration Register 2 IOCR2 *
03 T1 Receive Control Register 1 T1RCR1 *
04 T1 Receive Control Register 2 T1RCR2 *
05 T1 Transmit Control Register 1 T1TCR1 *
06 T1 Transmit Control Register 2 T1TCR2 *
07 T1 Common Control Register 1 T1CCR1 *
08 Software Signaling Insertion Enable 1 SSIE1 *

09 Software Signaling Insertion Enable 2 SSIE2 *
0A Software Signaling Insertion Enable 3 SSIE3 *
0B Software Signaling Insertion Enable 4 SSIE4 *
0C T1 Receive Digital Milliwatt Enable Register 1 T1RDMR1 *
0D T1 Receive Digital Milliwatt Enable Register 2 T1RDMR2 *

0E T1 Receive Digital Milliwatt Enable Register 3 T1RDMR3 *
0F Device Identification Register IDR *

10 Information Register 1 INFO1 *

11 Information Register 2 INFO2 *

12 Information Register 3 INFO3 *

13 Test Register TEST *

14 Interrupt Information Register 1 IIR1 *

15 Interrupt Information Register 2 IIR2 *

16 Status Register 1 SR1 *

17 Interrupt Mask Register 1 IMR1 *

18 Status Register 2 SR2 *

19 Interrupt Mask Register 2 IMR2 *
1A Status Register 3 SR3 *
1B Interrupt Mask Register 3 IMR3 *
1C Status Register 4 SR4 *
1D Interrupt Mask Register 4 IMR4 *

1E Status Register 5 SR5 *
1F Interrupt Mask Register 5 IMR5 *

20 Status Register 6 SR6 *

21 Interrupt Mask Register 6 IMR6 *

22 Status Register 7 SR7 *

23 Interrupt Mask Register 7 IMR7 *

24 Status Register 8 SR8 *

25 Interrupt Mask Register 8 IMR8 *

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MASTER MODE REGISTER

REGISTER

ABBREVIATION

MSTRREG *

PAGE

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