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GENERAL DESCRIPTION
The DS21600/DS21602/DS21604 are multiple-rate
clock adapters that convert between E-carrier and Tcarrier clocks rates. A T1 or E1 clock output,
CLKOUT1, is available, along with a higher multiple
rate clock output, CLKOUT2. CLKOUT1 and
CLKOUT2 are frequency locked to the clock input
CLKIN. The clock outputs, along with frame-sync
output, can be phase-aligned to a frame-sync input.
The devices are fully compatible with the LXP600A,
LXP602, and LXP604, and operate from either a 5V
or 3.3V supply. All operation modes include a
standard 8kHz output.
The DS21600/DS21602/DS21604 are available in
16-pin SO, and are rated for industrial temperatures.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS21600SN
DS21600SN+ -40°C to +85°C 16 SO
DS21600N -40°C to +85°C 8 DIP
DS21600N+ -40°C to +85°C 8 DIP
DS21602SN
DS21602SN+ -40°C to +85°C 16 SO
DS21602N -40°C to +85°C 8 DIP
DS21602N+ -40°C to +85°C 8 DIP
DS21604SN
DS21604SN+ -40°C to +85°C 16 SO
DS21604N -40°C to +85°C 8 DIP
DS21604N+ -40°C to +85°C 8 DIP
+ Denotes a lead(Pb)-free/RoHS-compliant device.
-40°C to +85°C 16 SO
-40°C to +85°C
-40°C to +85°C
16 SO
16 SO
FREQUENCY CONVERSIONS (MHz)
PART CLKIN CLKOUT1 CLKOUT2
DS21600
DS21602
DS21604
1.544 2.048 6.144
2.048 1.544 6.176
1.544 2.048 8.192
2.048 1.544 6.176
1.544 4.096 8.192
4.096 1.544 6.176
DS21600/DS21602/DS21604
3.3V/5V Clock Rate Adapte
FEATURES
Direct Drop-In Replacement for LXP600ASE,
LXP602SE, and LXP604SE
Converts E-Carrier Clock Rates to T-Carrier
Clock Rates
Converts T-Carrier Clock Rates to E-Carrier
Clock Rates
3.3V or 5V Supply
Low Jitter Output
Multiple Output Clocks Synchronized to
Input Clock
8kHz Frequency-Locked Output for All
Operation Modes
No External Components Required
16-Pin SO and 8-Pin DIP
Industrial Temperature Range: -40°C to
+85°C
PIN CONFIGURATION
TOP VIEW
Semiconductor
Dallas
DS21600/2/4
SO
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 011606
.
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................ 3
1.1 PIN NAME CROSS-REFERENCE TO LXP60X ......................................................................... 3
2. FUNCTIONAL DESCRIPTION............................................................................... 4
2.1 MODE SELECT..................................................................................................................... 4
2.2 FRAME-SYNC INPUT............................................................................................................. 4
3. OUTPUT JITTER.................................................................................................... 4
3.1 JITTER TRANSFER................................................................................................................ 5
4. OPERATING PARAMETERS................................................................................. 7
5. PACKAGE INFORMATION.................................................................................. 11
6. REVISION HISTORY............................................................................................ 12
LIST OF FIGURES
Figure 1-1. Block Diagram........................................................................................................................3
Figure 3-1. Nominal Jitter Transer for 2.048MHz to 1.544MHz Conversion.............................................5
Figure 3-2. Nominal Jitter Transfer for 1.544MHz to 2.048MHz Conversion............................................6
Figure 4-1. DS21600/DS21602 High-to-Low Frequency Conversion Frame-Sync Alignment .................8
Figure 4-2. DS21604 High-To-Low Frequency Conversion Frame-Sync Alignment................................9
Figure 4-3. DS21600 Low-to-High Frequency Conversion Frame-Sync Alignment .................................9
Figure 4-4. DS21602 Low-to-High Frequency Conversion Frame-Sync Alignment ...............................10
Figure 4-5. DS21604 Low-to-High Frequency Conversion Frame-Sync Alignment ...............................10
LIST OF TABLES
Table 1-A. Pin Description........................................................................................................................3
Table 1-B. Pin Name Cross-Reference to LXP60x...................................................................................3
Table 2-A. Frequency Conversions (MHz) ...............................................................................................4
Table 3-A. Output Jitter Specifications .....................................................................................................4
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1. PIN DESCRIPTION
Table 1-A. Pin Description
PIN
DIP SO
—
1, 3, 6, 8, 10,
11, 13, 15
1 2 SYNCOUT Output
2 4 CLKOUT2 Output
3 5 CLKIN Input
4 7 CLKOUT1 Output
5 9 Vss Supply Ground
6 12 SEL Input Clock Mode Select. Conversion mode select.
7 14 SYNCIN Input
8 16 VDD Supply Positive Supply, 3.3V or 5V ±5%
1.1 Pin Name Cross-Reference to LXP60X Table 1-B. Pin Name Cross-Reference to LXP60x
DS21600/DS21602
/DS21604
SYNCOUT FSO Synchronization Pulse Output
CLKOUT2 HFO Clock 2 Output
CLKIN CLKI Clock Input
CLKOUT1 CLKO Clock 1 Output
VSS GND Ground
SEL SEL Clock Mode Select
SYNCIN FSI Synchronization Pulse Input
N.C. N.C. No Connect
VDD V
LXP600ALXP602/L
Figure 1-1. Block Diagram
CLKIN
Dallas Semiconductor
DS21600/DS21602/DS21604
SEL
SYNCIN
NAME TYPE FUNCTION
N.C. — No Connect
Synchronization Output. An 8kHz output that can be
synchronized to the clock outputs.
Clock Output 2. T1 or E1 carrier clock output referenced to
CLKIN.
Clock Input. Reference Clock Input. CLKOUT1 and CLKOUT2
will be referenced to this clock.
Clock Output 1. T1 or E1 carrier clock output referenced to
CLKIN.
Synchronization Input. Used to synchronize the clock outputs
and SYNCOUT to CLKIN and SYNCIN. SYNCIN should be tied
high or low when not in use.
XP604
Positive Supply
CC
ANALOG
PLL
FUNCTION
FEEDBACK
CIRCUIT
OUTPUT
DIVIDER
FRAME SYNC
GENERATOR
CLKOUT2
CLKOUT1
SYNCOUT
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2. FUNCTIONAL DESCRIPTION
A clock input at CLKIN is converted to an alternate clock rate available on CLKOUT1. A higher multiple-rate clock
also is available on CLKOUT2. Additionally, an 8kHz clock locked to CLKIN is always available at the SYNCOUT
pin. The SEL pin controls clock-rate conversion selection.
2.1 Mode Select
The SEL pin is used to select the operating frequencies. Table 2-A shows the SEL state for the various operating
modes of the DS21600, DS21602, and DS21604.
Table 2-A. Frequency Conversions (MHz)
PART SEL CLKIN CLKOUT1 CLKOUT2
DS21600
DS21602
DS21604
0 1.544 2.048 6.144
1 2.048 1.544 6.176
0 1.544 2.048 8.192
1 2.048 1.544 6.176
0 1.544 4.096 8.192
1 4.096 1.544 6.176
2.2 Frame-Sync Input
In all cases, CLKOUT1 and CLKOUT2 are frequency-locked to CLKIN. CLKOUT1, CLKOUT2, and SYNCOUT
are phased-locked to SYNCIN when SYNCIN is asserted. The signal applied to SYNCIN can be 8kHz or some
integer subrate such as 1kHz, 2kHz, or 4kHz. Phase synchronization occurs within a maximum of 50ms when
SYNCIN is 8kHz.
3. OUTPUT JITTER
Table 3-A shows the output jitter specifications for 2.048MHz (or 4.096MHz) to 1.544MHz conversions (SEL = 1)
and 1.544MHz to 2.048MHz (or 4.096MHz) conversions (SEL = 0).
Table 3-A. Output Jitter Specifications
CLKIN
(MHz)
1.544 2.048
2.048 or
4.096
CLKOUT1
(MHz)
1.544
FREQUENCY
BAND
SPECIFICATION VALUE TYP MAX UNITS
20Hz–100kHz G.823 1.500 0.018 0.035 UI
18kHz–100kHz G.823 0.200 0.012 0.025 UI
No bandlimiting TR62411 0.050 0.010 0.020 UI
10Hz–40kHz TR62411 0.025 0.005 0.010 UI
8kHz–40kHz TR62411 0.025 0.006 0.012 UI
P-P
P-P
P-P
P-P
P-P
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3.1 Jitter Transfer
Figure 3-1 and Figure 3-2 show jitter transfer for 2.048MHz-to-1.544MHz conversions and vice versa.
Figure 3-1. Nominal Jitter Transfer for 2.048MHz-to-1.544MHz Conversion
2
1.8
1.6
1.4
1.2
1
0.8
JITTER GAIN (ns/ns)
0.6
0.4
0.2
0
0 10 20 70 30 40 50 60 80
JITTER FREQUENCY (kHz)
NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS21600/DS21602/DS21604 IS ABOUT 1.6 FOR CONVERSION FROM T1
TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR
THE DS21600/DS21602/DS21604 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE
LXP6XX DEVICES SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz).
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Figure 3-2. Nominal Jitter Transfer for 1.544MHz-to-2.048MHz Conversion
2.00
1.80
1.60
1.40
1.20
1.00
0.80
JITTER GAIN (ns/ns)
0.60
0.40
0.20
0.00
0 5 10 35 15 20 25 30 40
JITTER FREQUENCY (kHz)
NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS21600/DS21602/DS21604 IS ABOUT 1.6 FOR CONVERSION
FROM T1 TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE
JITTER GAIN FOR THE DS21600/DS21602/DS21604 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK
JITTER GAIN FOR THE LXP6XX DEVICES SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz).
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4. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…………………………………………………………..-1.0V to +6.0V
Operating Temperature Range for DS21600SN, DS21602SN, DS21604SN……………………….-40°C to +85°C
Storage Temperature Range…………………………………………………………………………….-55°C to +125°C
Soldering Temperature..…………………………………………………….See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40°C to +85°C)
PARAMETER SYMBOL
Logic 1 VIH (Note 1) 2.0 5.5 V
Logic 0 VIL (Note 1) -0.3 +0.8 V
Supply Voltage VDD
CONDITIONS
3.3V 3.135 3.3 3.465
5V 4.75 5 5.25
MIN TYP MAX UNITS
V
DC CHARACTERISTICS
(V
= 3.3V/5V 5%, TA = -40°C to +85°C.)
DD
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current IDD (Note 2) 14 mA
Input Leakage IIL (Note 3) -1.0 +1.0
Output Leakage ILO 1.0
Output Current (2.4V) IOH -1.0 mA
Output Current (0.4V) IOL +4.0 mA
A
A
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AC TIMING
(
(
(
(Figure 4-1, Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capture Range on CLKIN
Lock Range on CLKIN
CLKIN Duty Cycle
SYNCIN Setup to CLKIN Rising tSU (Note 1) 46 ns
SYNCIN Hold After CLKIN Rising tHI (Note 1) 30 ns
SYNCIN Pulse Width tPW (Note 1) 76
CLKOUT1 Delay from CLKIN Rising tD
CLKOUT1 Duty Cycle CD (Note 1) 50 %
SYNCOUT Delay from CLKOUT2 tDF (Note 1) -5 30 ns
SYNCOUT Pulse Width t
CLKOUT1 Delay from CLKOUT2
Rising
Rise/Fall Time on CLKIN, SYNCIN
Rise/Fall Time on CLKOUT1,
SYNCOUT, CLKOUT2 (Note 4)
Note 1:
Note 2:
Note 3:
Note 4:
Guaranteed by design.
100pF load on all outputs.
< VDD.
0V < V
IN
100pF load on CLKOUT1, SYNCOUT, CLKOUT2.
Figure 4-1. DS21600/DS21602 High-to-Low Frequency Conversion Frame-Sync
Alignment
CLKIN
2.048MHz)
SYNCIN
CLKOUT1
1.544MHz)
SYNCOUT
(Note 1) ±10,000 ppm
(Note 1) ±10,000 ppm
(Note 1) 35 65 %
CLKIN
period
3.3V (Note 1) -15 0 +41
5V (Note 1) -15 0 +22
(Note 1)
SPW
3.3V (Note 1) -15 0 +15 ns
t
DH
tRF
t
RF
3.3V (Note 1) 60
5V (Note 1) 40
3.3V (Note 1) 75
5V (Note 1) 40
CLKOUT
1 period
ns
ns
ns
ns
ns
tSU tHI
tPW
tD
t
SPW
t
DH
tDF
CLKOUT2
6.176MHz)
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Figure 4-2. DS21604 High-To-Low Frequency Conversion Frame-Sync Alignment
(
(
(
(
CLKIN
4.096MHz)
tHI tSU
SYNCIN
CLKOUT1
1.544MHz)
tPW
tD
tDH
SYNCOUT
t
SPW
CLKOUT2
6.176MHz)
t
DF
Figure 4-3. DS21600 Low-to-High Frequency Conversion Frame-Sync Alignment
CLKIN
(1.544MHz)
SYNCIN
CLKOUT1
(2.048MHz)
SYNCOUT
CLKOUT2
6.144MHz)
tSU
tPW
tD
tHI
t
SPW
tDH
tDF
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Figure 4-4. DS21602 Low-to-High Frequency Conversion Frame-Sync Alignment
(
CLKIN
(1.544MHz)
SYNCIN
tSU
tPW
t
HI
CLKOUT1
(2.048MHz)
SYNCOUT
tD
tDH
t
SP
tDF
CLKOUT2
8.192MHz)
Figure 4-5. DS21604 Low-to-High Frequency Conversion Frame-Sync Alignment
CLKIN
(1.544MHz)
SYNCIN
CLKOUT1
(4.096MHz)
SYNCOUT
CLKOUT2
(8.192MHz
SPW
tDH
t
HI
tDF
tSU
tPW
tD
T
)
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5. PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 SO W16+11 21-0042
8 PDIP P8+8 21-0043
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6. REVISION HISTORY
REVISION DESCRIPTION
082100 Preliminary release.
083100 Added package specifications.
090100 Correct operating voltage range.
011101 Added mechanical drawing for DIP package.
092801
032002 Updated jitter specifications.
032803 Added 3.3V operation specifications.
113004
112105
011606 Added lead-free packages to Ordering Information on page 1.
Added jitter specifications and pin list for all packages; added timing
diagrams.
Added the spec for soldering temperature in the Absolute Maximum Ratings
section.
Changed timing specs in DC Characteristics and AC Timing tables to
guaranteed by design.
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No
circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
© 2006 Maxim Integrated Products
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