MAXIM DS21354, DS21554 Technical data
查询DS21354L供应商
3.3V/5V E1 Single-Chip Transceivers
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21354/DS213554 single-chip transceivers
(SCTs) contain all the necessary functions to connect to
E1 lines. The devices are upward-compatible versions
of the DS2153 and DS2154 SCTs. The on-board
clock/data recovery circuitry coverts the AMI/HDB3 E1
waveforms to an NRZ serial stream. Both devices
automatically adjust to E1 22AWG (0.6mm) twistedpair cables from 0 to over 2km in length. They can
generate the necessary G.703 waveshapes for both 75W
coax and 120W twisted cables. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is
also used for extracting and inserting signaling data, Si,
and Sa-bit information. The on-board HDLC controller
can be used for Sa-bit links or DS0s. The devices
contain a set of internal registers that the user can
access to control the operation of the units. Quick
access through the parallel control port allows a single
controller to handle many E1 lines. The devices fully
meet all the latest E1 specifications, including ITU-T
G.703, G.704, G.706, G.823, G.732, and I.431, ETS
300 011, 300 233, and 300 166, as well as CTR12 and
CTR4.
PIN CONFIGURATION
TOP VIEW
Dallas
Semiconductor
DS21354/DS21554
100
1
LQFP
DS21354/DS21554
FEATURES
§ Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
§ On-Board Long- and Short-Haul Line Interface
for Clock/Data Recovery and Waveshaping
§ 32-Bit or 128-Bit Crystal-Less Jitter Attenuator
§ Frames to FAS, CAS, CCS, and CRC4 Formats
§ Integral HDLC Controller with 64-Byte Buffers
Configurable for Sa Bits, DS0, or Sub-DS0
Operation
§ Dual Two-Frame Elastic Store Slip Buffers that
can Connect to Asynchronous Backplanes up to
8.192MHz
§ Interleaving PCM Bus Operation
§ 8-Bit Parallel Control Port that can be used
Directly on Either Multiplexed or
Nonmultiplexed Buses (Intel or Motorola)
§ Extracts and Inserts CAS Signaling
§ Detects and Generates Remote and AIS Alarms
§ Programmable Output Clocks for Fractional E1,
H0, and H12 Applications
§ Fully Independent Transmit and Receive
Functionality
§ Full Access to Si and Sa Bits Aligned with
CRC-4 Multiframe
§ Four Separate Loopback Functions for Testing
Functions
§ Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
§ IEEE 1149.1 JTAG-Boundary Scan Architecture
§ Pin Compatible with DS2154/52/352/552 SCTs
§ 3.3V (DS21354) or 5V (DS21554) Supply; Low-
Power CMOS
§ 100-pin LQFP package (14mm x 14mm)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS21354L
DS21354LN -40°C to +85°C 100 LQFP
DS21554L
DS21554LN -40°C to +85°C 100 LQFP
0°C to +70°C 100 LQFP
0°C to +70°C 100 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
TABLE OF CONTENTS
1. INTRODUCTION.................................................................................................................. 6
1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7
1.2. DOCUMENT REVISION HISTORY .............................................................................................................8
2. BLOCK DIAGRAM .............................................................................................................. 9
3. PIN DESCRIPTION............................................................................................................ 10
3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14
3.1.1. Transmit-Side Pins ..............................................................................................................................14
3.1.2. Receive-Side Pins ...............................................................................................................................17
3.1.3. Parallel Control Port Pins ....................................................................................................................20
3.1.4. JTAG Test Access Port Pins...............................................................................................................22
3.1.5. Interleave Bus Operation Pins ............................................................................................................22
3.1.6. Line Interface Pins ..............................................................................................................................23
3.1.7. Supply Pins .........................................................................................................................................24
4. PARALLEL PORT............................................................................................................. 25
4.1. REGISTER MAP ........................................................................................................................................25
5. CONTROL, ID, AND TEST REGISTERS .......................................................................... 30
5.1. POWER-UP SEQUENCE ..........................................................................................................................30
5.2. SYNCHRONIZATION AND RESYNCHRONIZATION ...............................................................................32
5.3. FRAMER LOOPBACK ...............................................................................................................................36
5.4. AUTOMATIC ALARM GENERATION ........................................................................................................38
5.5. REMOTE LOOPBACK ...............................................................................................................................40
5.6. LOCAL LOOPBACK ...................................................................................................................................40
6. STATUS AND INFORMATION REGISTERS .................................................................... 43
6.1. CRC4 SYNC COUNTER............................................................................................................................45
7. ERROR COUNT REGISTERS........................................................................................... 50
7.1. BPV OR CODE VIOLATION COUNTER ...................................................................................................50
7.2. CRC4 ERROR COUNTER.........................................................................................................................51
7.3. E-BIT COUNTER .......................................................................................................................................51
7.4. FAS ERROR COUNTER .................................................................................................................................52
8. DS0 MONITORING FUNCTION ........................................................................................ 53
9. SIGNALING OPERATION................................................................................................. 56
9.1. PROCESSOR-BASED SIGNALING ..........................................................................................................56
9.2. HARDWARE-BASED SIGNALING ............................................................................................................58
9.2.1. Receive Side .......................................................................................................................................58
9.2.2. Transmit Side ......................................................................................................................................59
10. PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 60
10.1. TRANSMIT-SIDE CODE GENERATION ................................................................................................60
10.1.1. Simple Idle Code Insertion and Per-Channel Loopback .....................................................................60
10.1.2. Per-Channel Code Insertion ...............................................................................................................61
10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62
11. CLOCK BLOCKING REGISTERS..................................................................................... 63
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
12. ELASTIC STORES OPERATION...................................................................................... 65
12.1. RECEIVE SIDE .......................................................................................................................................65
12.2. TRANSMIT SIDE.....................................................................................................................................65
13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION.................................. 66
13.1. HARDWARE SCHEME ...........................................................................................................................66
13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME .........................................................66
13.3. INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME....................................................68
14. HDLC CONTROLLER FOR THE SA BITS OR DS0 ......................................................... 70
14.1. GENERAL OVERVIEW...........................................................................................................................70
14.2. HDLC STATUS REGISTERS..................................................................................................................71
14.3. BASIC OPERATION DETAILS ...............................................................................................................72
14.3.1. Example: Receive an HDLC Message................................................................................................72
14.3.2. Example: Transmit an HDLC Message...............................................................................................72
14.4. HDLC REGISTER DESCRIPTION..........................................................................................................73
15. LINE INTERFACE FUNCTIONS........................................................................................ 80
15.1. RECEIVE CLOCK AND DATA RECOVERY.......................................................................................................81
15.2. TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................................81
15.3. JITTER ATTENUATOR..................................................................................................................................82
15.4. PROTECTED INTERFACES ...........................................................................................................................86
15.5. RECEIVE MONITOR MODE ..........................................................................................................................89
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................... 90
16.1. INSTRUCTION REGISTER.............................................................................................................................95
16.2. TEST REGISTERS.......................................................................................................................................96
17. INTERLEAVED PCM BUS OPERATION.......................................................................... 98
17.1. CHANNEL INTERLEAVE ...............................................................................................................................99
17.2. FRAME INTERLEAVE ...................................................................................................................................99
18. FUNCTIONAL TIMING DIAGRAMS................................................................................ 100
18.1. RECEIVE .................................................................................................................................................100
18.2. TRANSMIT ...............................................................................................................................................104
19. OPERATING PARAMETERS.......................................................................................... 111
20. AC TIMING PARAMETERS AND DIAGRAMS ............................................................... 112
20.1. MULTIPLEXED BUS AC CHARACTERISTICS ................................................................................................112
20.2. NONMULTIPLEXED BUS AC CHARACTERISTICS..........................................................................................115
20.3. RECEIVE-SIDE AC CHARACTERISTICS ......................................................................................................117
20.4. TRANSMIT AC CHARACTERISTICS.............................................................................................................121
21. PACKAGE INFORMATION............................................................................................. 124
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
LIST OF FIGURES
Figure 2-1. DS21354/554 Block Diagram ............................................................................................................................. 9
Figure 15-1. Basic External Analog Connections .............................................................................................................. 83
Figure 15-2. Optional Crystal Connection........................................................................................................................... 83
Figure 15-3. Jitter Tolerance................................................................................................................................................. 84
Figure 15-4. Jitter Attenuation .............................................................................................................................................. 84
Figure 15-5. Transmit Waveform Template ........................................................................................................................ 85
Figure 15-6. Protected Interface Example for the DS21554 ............................................................................................ 87
Figure 15-7. Protected Interface Example for the DS21354 ............................................................................................ 88
Figure 15-8. Typical Monitor Port Application .................................................................................................................... 89
Figure 16-1. JTAG Functional Block Diagram.................................................................................................................... 91
Figure 16-2. TAP Controller State Diagram ........................................................................................................................ 94
Figure 17-1. IBO Basic Configuration Using Four SCTs .................................................................................................. 99
Figure 18-1. Receive-Side Timing...................................................................................................................................... 100
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)................................................................. 100
Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101
Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode ................................................................................ 102
Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode ............................................................................. 103
Figure 18-7. Transmit-Side Timing .................................................................................................................................... 104
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)................................................................ 104
Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................................. 105
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ........................................... 105
Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode ............................................................................. 106
Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode.......................................................................... 107
Figure 18-13. G.802 Timing ................................................................................................................................................ 108
Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart ........................................................................ 109
Figure 18-15. DS21354/DS21554 Transmit Data Flow .................................................................................................. 110
Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)........................................................................................... 113
Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1)................................................................................................. 113
Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1) ............................................................................................ 114
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0).......................................................................................... 115
Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) .......................................................................................... 116
Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0).................................................................................. 116
Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) .................................................................................. 116
Figure 20-8. Receive-Side AC Timing ............................................................................................................................... 118
Figure 20-9. Receive System Side AC Timing................................................................................................................. 119
Figure 20-10. Receive Line Interface AC Timing............................................................................................................. 120
Figure 20-11. Transmit-Side AC Timing............................................................................................................................ 122
Figure 20-12. Transmit System Side AC Timing.............................................................................................................. 123
Figure 20-13. Transmit Line Interface Side AC Timing................................................................................................... 123
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
LIST OF TABLES
Table 3-1. Pin Description Sorted by Pin Number ............................................................................................................. 10
Table 3-2. Pin Description by Symbol ................................................................................................................................. 12
Table 4-1. Register Map Sorted by Address ...................................................................................................................... 25
Table 5-1. Device ID Bit Map ................................................................................................................................................ 30
Table 5-2. SYNC/RESYNC Criteria ..................................................................................................................................... 32
Table 6-1. Alarm Criteria ....................................................................................................................................................... 46
Table 14-1. HDLC Controller Register List ......................................................................................................................... 70
Table 15-1. Line Build-Out Select in LICR for the DS21554 ............................................................................................ 81
Table 15-2. Line Build-Out Select in LICR for the DS21354 ............................................................................................ 82
Table 15-3. Transformer Specifications .............................................................................................................................. 82
Table 15-4. Receive Monitor Mode Gain ............................................................................................................................ 89
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture ........................................................................................... 95
Table 16-2. ID Code Structure.............................................................................................................................................. 96
Table 16-3. Device ID Codes................................................................................................................................................ 96
Table 16-4. Boundary Scan Control Bits............................................................................................................................. 97
Table 17-1. IBO Master Device Select ................................................................................................................................98
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
1. INTRODUCTION
The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new
features listed below. All the original features of the DS2153 and DS2154 have been retained, and the
software created for the original devices is transferable into the DS21354/DS21554.
New Features in the DS21354 and DS21554
FEATURE SECTION
HDLC controller with 64-Byte Buffers for Sa Bits or DS0s or Sub DS0s 14
Interleaving PCM Bus Operation 17
IEEE 1149.1 JTAG-Boundary Scan Architecture 16
3.3V (DS21354 Only) Supply 1.1 and 2
Line Interface Support for the G.703 2.048 Synchronization Interface 15
Customer Disconnect Indication (...101010...) Generator 5.6
Open-Drain Line Driver Option 5.6
Additional Features in the DS21354 and DS21554
FEATURE SECTION
Option for nonmultiplexed bus operation 1.1 and 20.2
Crystal-less jitter attenuation 15.3
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing Interrupt generated on change of signaling data
Improved receive sensitivity: 0 to -43dB 1.1
Per-channel code insertion in both transmit and receive paths 10
Expanded access to Sa and Si bits 13
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 6
8.192MHz clock synthesizer 1.1
Per-channel loopback 10
Addition of hardware pins to indicate carrier loss and signaling freeze 1.1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able to corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks 1.1
Ability to monitor one DS0 channel in both the transmit and receive paths 8
Access to the data streams in between the framer/formatter and the elastic stores 1.1
AIS generation in the line interface that is independent of loopbacks 1.1 and 5
Transmit current limiter to meet the 50mA short circuit requirement 15
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 5.4
Automatic RAI generation to ETS 300 011 specifications 5.4
9
1.1
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
1.1. Functional Description
The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins
of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS21354/DS21554 contain an active filter that reconstructs the analogreceived signal for the nonlinear losses that occur in transmission. The devices have a usable receive
sensitivity of 0 to -43dB, which allows the device to operate on cables over 2km in length. The receiveside framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming
alarms including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receiveside elastic store can be enabled to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock, which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz clock or a 1.544MHz
clock.
The transmit-side framer is totally independent from the receive side in both the clock requirements and
characteristics. Data off a backplane can be passed through a transmit-side elastic store if necessary. The
transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125ms frame, there are 32 eight-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and
received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32.
Time slot 0 is identical to channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or
channel) is made up of eight bits, which are numbered 1 to 8. Bit number 1 is the most significant bit
(MSB) and is transmitted first. Bit number 8 is the least significant bit (LSB) and is transmitted last. The
term “locked” refers to two clock signals that are phase or frequency locked, or derived from a common
clock (i.e., a 1.544MHz clock may be locked to a 2.048MHz clock if they share the same 8kHz
component). Throughout this data sheet, the following abbreviations are used:
NAME FUNCTION
FAS Frame-Alignment Signal
CAS Channel-Associated Signaling
MF Multiframe
Si International Bits
CRC4 Cyclical Redundancy Check
CCS Common-Channel Signaling
Sa Additional Bits
E-Bit CRC4 Error Bits
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
1.2. Document Revision History
REVISION DESCRIPTION
012799 Initial release
012899
Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz
timing
020399 Corrected definition and label of TUDR bit in the THIR register.
021199 Corrected address of IBO register in text.
040199 Added Receive Monitor Mode section
041599 Added section on Protected Interfaces
050799 Corrected pin number and description of FMS in JTAG section
072999 Added list of tables and figures
091499
092399
Added 10mF cap to interface examples
Corrected definition of DS in pin description.
072401 Typo corrected in JTAG Test Access Port Pins.
Added note to the Receive Information Register, FAS Resync Criteria Met.
Corrected Figures 20-1, 20-2, 20-3 with respect to CS.
021004
Corrected typo in Figure 18-14 (RCR1.1 reference corrected).
Corrected formatting issues.
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2. BLOCK DIAGRAM
/
Figure 2-1. DS21354/554 Block Diagram
RSIGF
RCHCLK
RCHBLK
RLINK
RLOS/LOTC
RCL
RCLK
RLCLK
8MCLK
Synthesizer
8.192MHz Clock
RSER
RSYSCLK
RSIG
RSYNC
Interleave
Bus
RMSYNC
RFSYNC
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
RDATA
TESO
TDATA
TSYNC
TSSYNC
Interleave
TSIG
TSYSCLK
TSER
Bus
TCHBLK
TLINK
TCLK
TLCLK
TCHCLK
CO
RPOSI
RCLKI
RNEGI
RNEGO
RCLKO
RPOSO
8XCLK
XTALD
MCLK
Buffer
Signaling
Control
Framer
Receive Side
32.768MHz
Clock / Data
Reco very
RSYSCLK
Store
Elastic
DS21354
DS21554
DATA
SYNC
CLOCK
Framer Loopback
Remote Loopback
Jitter Attenuator
Either transmit or receive path
Local Loopback
Receive
Line I/F
Timing Control
Hardware
Signaling
Insertion
LOTC
Store
Elastic
Sync Control
SYNC
CLOCK
Formatter
Transmit Side
r
T
i
m
s
t
n
a
L
I
i
e
/
n
F
MUX
HDLC/BOC
Controller
Sa / DS0
INT*
Sa
DATA
(routed to all blocks)
Parallel & Test Control Port
MUX
JTAG PORT
MUX
D0 to D7 /
AD0 to AD7
8
A0 to A6
7
ALE(AS) / A7
RD*(DS*)
WR*(R/W*)
BTS
CS*
TEST
TPOSO
TCLKO
TNEGO
TNEGI
TCLKI
TPOSI
LIUC
JTDO
JTDI
JTCLK
JTMS
J
S
R
*
T
CI
Timing
HDLC/BOC
Controller
Sa / DS0
LIUC
MUX
16.384 MH z
VCO / PLL
RTIP
RRING
TTIP
TRING
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
3. PIN DESCRIPTION
Table 3-1. Pin Description Sorted by Pin Number
PIN NAME TYPE FUNCTION
1 RCHBLK O Receive Channel Block
2 JTMS I IEEE 1149.1 Test Mode Select
3 8MCLK O 8.192 MHz Clock
4 JTCLK I IEEE 1149.1 Test Clock Signal
5
JTRST
6 RCL O Receive Carrier Loss
7 JTDI I IEEE 1149.1 Test Data Input
8, 9, 15,
23, 26, 27,
N.C. — No Connect. Do not connect any signal to this pin.
28
10 JTDO O IEEE 1149.1 Test Data Output
11 BTS I Bus Type Select
12 LIUC I Line Interface Connect
13 8XCLK O Eight Times Clock
14 TEST I Test
16 RTIP I Receive Analog Tip Input
17 RRING I Receive Analog Ring Input
18 RVDD – Receive Analog Positive Supply
19, 20, 24 RVSS – Receive Analog Signal Ground
21 MCLK I Master Clock Input
22 XTALD O Quartz Crystal Driver
25
INT
29 TTIP O Transmit Analog Tip Output
30 TVSS – Transmit Analog Signal Ground
31 TVDD – Transmit Analog Positive Supply
32 TRING O Transmit Analog Ring Output
33 TCHBLK O Transmit Channel Block
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
36 CI I Carry In
37 TSYNC I/O Transmit Sync
38 TPOSI I Transmit Positive Data Input
39 TNEGI I Transmit Negative Data Input
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
42 TNEGO O Transmit Negative Data Output
43 TPOSO O Transmit Positive Data Output
44, 61,
81,83
45, 60, 80,
84
DVDD — Digital Positive Supply
DVSS — Digital Signal Ground
46 TCLK I Transmit Clock
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
I IEEE 1149.1 Test Reset, Active Low
O Interrupt, Active Low
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
PIN NAME TYPE FUNCTION
49 TESO O Transmit Elastic Store Output
50 TDATA I Transmit Data
51 TSYSCLK I Transmit System Clock
52 TSSYNC I Transmit System Sync
53 TCHCLK O Transmit Channel Clock
54 CO O Carry Out
55 MUX I Bus Operation
56 D0/AD0 I/O Data Bus Bit0/Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE (AS)/A7 I Address Latch Enable/Address Bus Bit 7
74
75
76
77
RD (DS)
CS
FMS
WR (R/W)
I Read Input (Data Strobe), Active Low
I Chip Select, Active Low
I Framer Mode Select
I Write Input (Read/Write), Active Low
78 RLINK O Receive Link Data
79 RLCLK O Receive Link Clock
82 RCLK O Receive Clock
85 RDATA O Receive Data
86 RPOSI I Receive Positive Data Input
87 RNEGI I Receive Negative Data Input
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
90 RNEGO O Receive Negative Data Output
91 RPOSO O Receive Positive Data Output
92 RCHCLK O Receive Channel Clock
93 RSIGF O Receive Signaling Freeze Output
94 RSIG O Receive Signaling Output
95 RSER O Receive Serial Data
96 RMSYNC O Receive Multiframe Sync
97 RFSYNC O Receive Frame Sync
98 RSYNC I/O Receive Sync
99 RLOS/LOTC O Receive Loss Of Sync/ Loss Of Transmit Clock
100 RSYSCLK I Receive System Clock
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Table 3-2. Pin Description by Symbol
PIN NAME TYPE FUNCTION
3 8MCLK O 8.192MHz Clock
13 8XCLK O Eight-Times Clock
66 A0 I Address Bus Bit 0
67 A1 I Address Bus Bit 1
68 A2 I Address Bus Bit 2
69 A3 I Address Bus Bit 3
70 A4 I Address Bus Bit 4
71 A5 I Address Bus Bit 5
72 A6 I Address Bus Bit 6
73 ALE (AS)/A7 I Address Latch Enable/Address Bus Bit 7
11 BTS I Bus Type Select
36 CI I Carry In
54 CO O Carry Out
75
CS
56 D0/AD0 I/O Data Bus Bit0/ Address/Data Bus Bit 0
57 D1/AD1 I/O Data Bus Bit1/ Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
62 D4/AD4 I/O Data Bus Bit4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
44, 61, 81, 83 DVDD — Digital Positive Supply
45, 60, 80, 84 DVSS — Digital Signal Ground
76 FMS I Framer Mode Select
25
INT
4 JTCLK I IEEE 1149.1 Test Clock Signal
7 JTDI I IEEE 1149.1 Test Data Input
10 JTDO O IEEE 1149.1 Test Data Output
2 JTMS I IEEE 1149.1 Test Mode Select
5
JTRST
12 LIUC I Line Interface Connect
21 MCLK I Master Clock Input
55 MUX I Bus Operation
8, 9, 15, 23, 26,
27, 28
N.C. — No Connect. Do not connect any signal to this pin.
1 RCHBLK O Receive Channel Block
92 RCHCLK O Receive Channel Clock
6 RCL O Receive Carrier Loss
82 RCLK O Receive Clock
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
74
RD (DS)
85 RDATA O Receive Data
97 RFSYNC O Receive Frame Sync
79 RLCLK O Receive Link Clock
I Chip Select, Active Low
O Interrupt
I IEEE 1149.1 Test Reset, Active Low
I Read Input (Data Strobe), Active Low
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PIN NAME TYPE FUNCTION
78 RLINK O Receive Link Data
99 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock
96 RMSYNC O Receive Multiframe Sync
87 RNEGI I Receive Negative Data Input
90 RNEGO O Receive Negative Data Output
86 RPOSI I Receive Positive Data Input
91 RPOSO O Receive Positive Data Output
17 RRING I Receive Analog Ring Input
95 RSER O Receive Serial Data
94 RSIG O Receive Signaling Output
93 RSIGF O Receive Signaling Freeze Output
98 RSYNC I/O Receive Sync
100 RSYSCLK I Receive System Clock
16 RTIP I Receive Analog Tip Input
18 RVDD — Receive Analog Positive Supply
19, 20, 24 RVSS — Receive Analog Signal Ground
33 TCHBLK O Transmit Channel Block
53 TCHCLK O Transmit Channel Clock
46 TCLK I Transmit Clock
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
50 TDATA I Transmit Data
49 TESO O Transmit Elastic Store Output
14 TEST I Test
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
39 TNEGI I Transmit Negative Data Input
42 TNEGO O Transmit Negative Data Output
38 TPOSI I Transmit Positive Data Input
43 TPOSO O Transmit Positive Data Output
32 TRING O Transmit Analog Ring Output
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
52 TSSYNC I Transmit System Sync
37 TSYNC I/O Transmit Sync
51 TSYSCLK I Transmit System Clock
29 TTIP O Transmit Analog Tip Output
31 TVDD — Transmit Analog Positive Supply
30 TVSS — Transmit Analog Signal Ground
77
WR (R/W)
I Write Input (Read/Write), Active Low
22 XTALD O Quartz Crystal Driver
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3.1. Pin Function Description
3.1.1. Transmit-Side Pins
Signal Name:
Signal Description:
Signal Type:
TCLK
Transmit Clock
Input
A 2.048MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
Signal Description:
Signal Type:
TSER
Transmit Serial Data
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
TCHCLK
Transmit Channel Clock
Output
A 256kHz clock that pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is
enabled. Useful for parallel to serial conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
TCHBLK
Transmit Channel Block
Output
A user-programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384kbps (H0),
768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for
external per-channel loopback, and for per-channel conditioning. See Section 12 for details.
Signal Name:
Signal Description:
Signal Type:
TSYSCLK
Transmit System Clock
Input
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the transmit-side elastic store
function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See
Section 17
for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option.
Signal Name:
Signal Description:
Signal Type:
TLCLK
Transmit Link Clock
Output
4kHz to 20kHz demand clock (Sa bits) for the TLINK input. See Section 17 for details.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Signal Name:
Signal Description:
Signal Type:
TLINK
Transmit Link Data
Input
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination
of the Sa bit positions (Sa4 to Sa8). See Section 13 for details.
Signal Name:
Signal Description:
Signal Type:
TSYNC
Transmit Sync
Input/Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR1.1,
the DS21354/DS21554 can be programmed to output either a frame or multiframe pulse at this pin. This
pin can also be configured as an input via TCR1.0. See Section 18 for details.
Signal Name:
Signal Description:
Signal Type:
TSSYNC
Transmit System Sync
Input
Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit-side elastic store.
Signal Name:
Signal Description:
Signal Type:
TSIG
Transmit Signaling Input
Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM E1 data stream.
Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
TESO
Transmit Elastic Store Data Output
Output
Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic
store is enabled or not. This pin is normally tied to TDATA.
Signal Name:
Signal Description:
Signal Type:
TDATA
Transmit Data
Input
Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This
pin is normally tied to TESO.
Signal Name:
Signal Description:
Signal Type:
TPOSO
Transmit Positive Data Output
Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR2.2) control bit. This pin is normally
tied to TPOSI.
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Signal Name:
Signal Description:
Signal Type:
TNEGO
Transmit Negative Data Output
Output
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is
normally tied to TNEGI.
Signal Name:
Signal Description:
Signal Type:
TCLKO
Transmit Clock Output
Output
Buffered output of signal that is clocking data through the transmit-side formatter. This pin is normally
tied to TCLKI.
Signal Name:
Signal Description:
Signal Type:
TPOSI
Transmit Positive Data Input
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally
connected to TPOSO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ
applications.
Signal Name:
Signal Description:
Signal Type:
TNEGI
Transmit Negative Data Input
Input
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally
connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ
applications.
Signal Name:
Signal Description:
Signal Type:
TCLKI
Transmit Clock Input
Input
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high.
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3.1.2. Receive-Side Pins
Signal Name:
Signal Description:
Signal Type:
RLINK
Receive Link Data
Output
Updated with the fully recovered E1 data stream on the rising edge of RCLK.
Signal Name:
Signal Description:
Signal Type:
RLCLK
Receive Link Clock
Output
4kHz to 20kHz clock (Sa bits) for the RLINK output. See Section 13 for details.
Signal Name:
Signal Description:
Signal Type:
RCLK
Receive Clock
Output
2.048MHz clock that is used to clock data through the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
RCHCLK
Receive Channel Clock
Output
A 256kHz clock that pulses high during the LSB of each channel. Synchronous with RCLK when the
receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Useful for parallel to serial conversion of channel data.
Signal Name:
Signal Description:
Signal Type:
RCHBLK
Receive Channel Block
Output
A user-programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK
when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384kbps service,
768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for
external per-channel loopback, and for per-channel conditioning. See Section 10 for details.
Signal Name:
Signal Description:
Signal Type:
RSER
Receive Serial Data
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
RSYNC
Receive Sync
Input/Output
An extracted pulse, one RCLK wide, is output at this pin that identifies either frame or CAS/CRC
multiframe boundaries. If the receive-side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Signal Name:
Signal Description:
Signal Type:
RFSYNC
Receive Frame Sync
Output
An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.
Signal Name:
Signal Description:
Signal Type:
RMSYNC
Receive Multiframe Sync
Output
If the receive-side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin
that identifies multiframe boundaries. If the receive-side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Signal Name:
Signal Description:
Signal Type:
RDATA
Receive Data
Output
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
RSYSCLK
Receive System Clock
Input
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receive-side elastic store. See
Section 17 for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option.
Signal Name:
Signal Description:
Signal Type:
RSIG
Receive Signaling Output
Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
RLOS/LOTC
Receive Loss of Sync / Loss of Transmit Clock
Output
A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5ms.
Signal Name:
Signal Description:
Signal Type:
RCL
Receive Carrier Loss
Output
Set high when the line interface detects a carrier loss.
Signal Name:
Signal Description:
Signal Type:
RSIGF
Receive Signaling Freeze
Output
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert
downstream equipment of the condition.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Signal Name:
Signal Description:
Signal Type:
8MCLK
8MHz Clock
Output
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
RPOSO
Receive Positive Data Input
Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied
to RPOSI.
Signal Name:
Signal Description:
Signal Type:
RNEGO
Receive Negative Data Input
Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
tied to RNEGI.
Signal Name:
Signal Description:
Signal Type:
RCLKO
Receive Clock Output
Output
Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
Signal Name:
Signal Description:
Signal Type:
RPOSI
Receive Positive Data Input
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the
LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
RNEGI
Receive Negative Data Input
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the
LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
RCLKI
Receive Clock Input
Input
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be
internally connected to RCLKO by tying the LIUC pin high.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
3.1.3. Parallel Control Port Pins
Signal Name:
Signal Description:
Signal Type:
INT
Interrupt
Output
Active-low, open-drain output that flags host controller during conditions and change of conditions
defined in the Status Registers 1 and 2 and the HDLC Status Register.
Signal Name:
Signal Description:
Signal Type:
FMS
Framer Mode Select
Input
Selects the DS2154 mode when high or the DS21354/DS21554 mode when low. If high, the JTRST is
internally pulled low. If low, JTRST has normal JTAG functionality. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
TEST
Tri-State Control
Input
Set high to tri-state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board-level testing.
Signal Name:
Signal Description:
Signal Type:
MUX
Bus Operation
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
AD0 to AD7
Data Bus [D0 to D7] or Address/Data Bus
Input
In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as an 8-bit multiplexed address/data bus.
Signal Name:
Signal Description:
Signal Type:
A0 to A6
Address Bus
Input
In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:
Signal Description:
Signal Type:
BTS
Bus Type Select
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function
listed in parentheses ().
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
Signal Name:
Signal Description:
Signal Type:
RD (DS)
Read Input—Data Strobe
Input
In Intel Mode, RD determines when data is read from the device. In Motorola Mode, DS is used to write
to the device. See the Bus Timing Diagrams section.
Signal Name:
Signal Description:
Signal Type:
CS
Chip Select
Input
Must be low to read or write to the device. CS is an active-low signal.
Signal Name:
Signal Description:
Signal Type:
ALE (AS)/A7
Address Latch Enable (Address Strobe) or A7
Input
In nonmultiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus
operation (MUX = 1), serves to demultiplex the bus on a positive-going edge.
Signal Name:
Signal Description:
Signal Type:
WR (R/W)
Write Input (Read/Write)
Input
WR is an active-low signal.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
3.1.4. JTAG Test Access Port Pins
Signal Name:
Signal Description:
Signal Type:
JTRST
IEEE 1149.1 Test Reset
Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10kW pullup resistor. When FMS = 1, this pin is tied low internally.
Tie JTRST low if JTAG is not used and the framer is in DS21354/DS21554 mode (FMS low).
Signal Name:
Signal Description:
Signal Type:
JTMS
IEEE 1149.1 Test Mode Select
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
JTCLK
IEEE 1149.1 Test Clock Signal
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
JTDI
IEEE 1149.1 Test Data Input
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW
pullup resistor.
Signal Name:
Signal Description:
Signal Type:
JTDO
IEEE 1149.1 Test Data Output
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
3.1.5. Interleave Bus Operation Pins
Signal Name:
Signal Description:
Signal Type:
CI
Carry In
Input
A rising edge on this pin causes RSER and RSIG to come out of high-Z state and TSER and TSIG to start
sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of
data. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
CO
Carry Out
Output
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
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3.1.6. Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
MCLK
Master Clock Input
Input
A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally
for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048MHz may be applied
across MCLK and XTALD instead of the TTL level clock source.
Signal Name:
Signal Description:
Signal Type:
XTALD
Quartz Crystal Driver
Output
A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of a TTL level clock
source at MCLK. Leave open circuited if a TTL clock source is applied at MCLK.
Signal Name:
Signal Description:
Signal Type:
8XCLK
Eight-Times Clock
Output
A 16.384MHz clock that is frequency locked to the 2.048MHz clock provided from the clock/data
recovery block (if the jitter attenuator is enabled on the receive side) or from the TCLKI pin (if the jitter
attenuator is enabled on the transmit side). Can be internally disabled via TEST2 register if not needed.
Signal Name:
Signal Description:
Signal Type:
LIUC
Line Interface Connect
Input
Tie low to separate the line interface circuitry from the framer/formatter circuitry and activate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the
framer/formatter circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When
LIUC is tied high, the TPOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.
Signal Name:
Signal Description:
Signal Type:
RTIP and RRING
Receive Tip and Ring
Input
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the E1 line. See
Section 15
for details.
Signal Name:
Signal Description:
Signal Type:
TTIP and TRING
Transmit Tip and Ring
Output
Analog line-driver outputs. These pins connect via a step-up transformer to the E1 line. See Section 15
for details.
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3.1.7. Supply Pins
Signal Name:
Signal Description:
Signal Type:
DVDD
Digital Positive Supply
Supply
5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the RVDD and TVDD pins.
Signal Name:
Signal Description:
Signal Type:
RVDD
Receive Analog Positive Supply
Supply
5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the DVDD and TVDD pins.
Signal Name:
Signal Description:
Signal Type:
TVDD
Transmit Analog Positive Supply
Supply
5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the RVDD and DVDD pins.
Signal Name:
Signal Description:
Signal Type:
DVSS
Digital Signal Ground
Supply
0.0V. Should be tied to the RVSS and TVSS pins.
Signal Name:
Signal Description:
Signal Type:
RVSS
Receive Analog Signal Ground
Supply
0.0V. Should be tied to DVSS and TVSS.
Signal Name:
Signal Description:
Signal Type:
TVSS
Transmit Analog Signal Ground
Supply
0.0V. Should be tied to DVSS and RVSS.
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4. PARALLEL PORT
The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed
(MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel
or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high,
Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams
in Section 18 for more details.
4.1. Register Map
Table 4-1. Register Map Sorted by Address
ADDRESS TYPE REGISTER NAME
00 R BPV or Code Violation Count 1 VCR1
01 R BPV or Code Violation Count 2 VCR2
02 R CRC4 Error Count 1/FAS Error Count 1 CRCCR1
03 R CRC4 Error Count 2 CRCCR2
04 R E-Bit Count 1/FAS Error Count 2 EBCR1
05 R E-Bit Count 2 EBCR2
06 R/W Status 1 SR1
07 R/W Status 2 SR2
08 R/W Receive Information RIR
09 — Not used (set to 00h)
0A — Not used (set to 00h)
0B — Not used (set to 00h)
0C — Not used (set to 00h)
0D — Not used (set to 00h)
0E — Not used (set to 00h)
0F R Device ID IDR
10 R/W Receive Control 1 RCR1
11 R/W Receive Control 2 RCR2
12 R/W Transmit Control 1 TCR1
13 R/W Transmit Control 2 TCR2
14 R/W Common Control 1 CCR1
15 R/W Test 1 TEST1 (set to 00h)
16 R/W Interrupt Mask 1 IMR1
17 R/W Interrupt Mask 2 IMR2
18 R/W Line Interface Control Register LICR
19 R/W Test 2 TEST2 (set to 00h)
1A R/W Common Control 2 CCR2
1B R/W Common Control 3 CCR3
1C R/W Transmit Sa Bit Control TSaCR
1D R/W Common Control 6 CCR6
1E R Synchronizer Status SSR
1F R Receive Non-Align Frame RNAF
20 R/W Transmit Align Frame TAF
21 R/W Transmit Non-Align Frame TNAF
22 R/W Transmit Channel Blocking 1 TCBR1
23 R/W Transmit Channel Blocking 2 TCBR2
24 R/W Transmit Channel Blocking 3 TCBR3
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS TYPE REGISTER NAME
25 R/W Transmit Channel Blocking 4 TCBR4
26 R/W Transmit Idle 1 TIR1
27 R/W Transmit Idle 2 TIR2
28 R/W Transmit Idle 3 TIR3
29 R/W Transmit Idle 4 TIR4
2A R/W Transmit Idle Definition TIDR
2B R/W Receive Channel Blocking 1 RCBR1
2C R/W Receive Channel Blocking 2 RCBR2
2D R/W Receive Channel Blocking 3 RCBR3
2E R/W Receive Channel Blocking 4 RCBR4
2F R Receive Align Frame RAF
30 R Receive Signaling 1 RS1
31 R Receive Signaling 2 RS2
32 R Receive Signaling 3 RS3
33 R Receive Signaling 4 RS4
34 R Receive Signaling 5 RS5
35 R Receive Signaling 6 RS6
36 R Receive Signaling 7 RS7
37 R Receive Signaling 8 RS8
38 R Receive Signaling 9 RS9
39 R Receive Signaling 10 RS10
3A R Receive Signaling 11 RS11
3B R Receive Signaling 12 RS12
3C R Receive Signaling 13 RS13
3D R Receive Signaling 14 RS14
3E R Receive Signaling 15 RS15
3F R Receive Signaling 16 RS16
40 R/W Transmit Signaling 1 TS1
41 R/W Transmit Signaling 2 TS2
42 R/W Transmit Signaling 3 TS3
43 R/W Transmit Signaling 4 TS4
44 R/W Transmit Signaling 5 TS5
45 R/W Transmit Signaling 6 TS6
46 R/W Transmit Signaling 7 TS7
47 R/W Transmit Signaling 8 TS8
48 R/W Transmit Signaling 9 TS9
49 R/W Transmit Signaling 10 TS10
4A R/W Transmit Signaling 11 TS11
4B R/W Transmit Signaling 12 TS12
4C R/W Transmit Signaling 13 TS13
4D R/W Transmit Signaling 14 TS14
4E R/W Transmit Signaling 15 TS15
4F R/W Transmit Signaling 16 TS16
50 R/W Transmit Si Bits Align Frame TSiAF
51 R/W Transmit Si Bits Non-Align Frame TSiNAF
52 R/W Transmit Remote Alarm Bits TRA
53 R/W Transmit Sa4 Bits TSa4
54 R/W Transmit Sa5 Bits TSa5
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS TYPE REGISTER NAME
55 R/W Transmit Sa6 Bits TSa6
56 R/W Transmit Sa7 Bits TSa7
57 R/W Transmit Sa8 Bits TSa8
58 R Receive Si Bits Align Frame RSiAF
59 R Receive Si Bits Non-Align Frame RSiNAF
5A R Receive Remote Alarm Bits RRA
5B R Receive Sa4 Bits RSa4
5C R Receive Sa5 Bits RSa5
5D R Receive Sa6 Bits RSa6
5E R Receive Sa7 Bits RSa7
5F R Receive Sa8 Bits RSa8
60 R/W Transmit Channel 1 TC1
61 R/W Transmit Channel 2 TC2
62 R/W Transmit Channel 3 TC3
63 R/W Transmit Channel 4 TC4
64 R/W Transmit Channel 5 TC5
65 R/W Transmit Channel 6 TC6
66 R/W Transmit Channel 7 TC7
67 R/W Transmit Channel 8 TC8
68 R/W Transmit Channel 9 TC9
69 R/W Transmit Channel 10 TC10
6A R/W Transmit Channel 11 TC11
6B R/W Transmit Channel 12 TC12
6C R/W Transmit Channel 13 TC13
6D R/W Transmit Channel 14 TC14
6E R/W Transmit Channel 15 TC15
6F R/W Transmit Channel 16 TC16
70 R/W Transmit Channel 17 TC17
71 R/W Transmit Channel 18 TC18
72 R/W Transmit Channel 19 TC19
73 R/W Transmit Channel 20 TC20
74 R/W Transmit Channel 21 TC21
75 R/W Transmit Channel 22 TC22
76 R/W Transmit Channel 23 TC23
77 R/W Transmit Channel 24 TC24
78 R/W Transmit Channel 25 TC25
79 R/W Transmit Channel 26 TC26
7A R/W Transmit Channel 27 TC27
7B R/W Transmit Channel 28 TC28
7C R/W Transmit Channel 29 TC29
7D R/W Transmit Channel 30 TC30
7E R/W Transmit Channel 31 TC31
7F R/W Transmit Channel 32 TC32
80 R/W Receive Channel 1 RC1
81 R/W Receive Channel 2 RC2
82 R/W Receive Channel 3 RC3
83 R/W Receive Channel 4 RC4
84 R/W Receive Channel 5 RC5
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS TYPE REGISTER NAME
85 R/W Receive Channel 6 RC6
86 R/W Receive Channel 7 RC7
87 R/W Receive Channel 8 RC8
88 R/W Receive Channel 9 RC9
89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15
8F R/W Receive Channel 16 RC16
90 R/W Receive Channel 17 RC17
91 R/W Receive Channel 18 RC18
92 R/W Receive Channel 19 RC19
93 R/W Receive Channel 20 RC20
94 R/W Receive Channel 21 RC21
95 R/W Receive Channel 22 RC22
96 R/W Receive Channel 23 RC23
97 R/W Receive Channel 24 RC24
98 R/W Receive Channel 25 RC25
99 R/W Receive Channel 26 RC26
9A R/W Receive Channel 27 RC27
9B R/W Receive Channel 28 RC28
9C R/W Receive Channel 29 RC29
9D R/W Receive Channel 30 RC30
9E R/W Receive Channel 31 RC31
9F R/W Receive Channel 32 RC32
A0 R/W Transmit Channel Control 1 TCC1
A1 R/W Transmit Channel Control 2 TCC2
A2 R/W Transmit Channel Control 3 TCC3
A3 R/W Transmit Channel Control 4 TCC4
A4 R/W Receive Channel Control 1 RCC1
A5 R/W Receive Channel Control 2 RCC2
A6 R/W Receive Channel Control 3 RCC3
A7 R/W Receive Channel Control 4 RCC4
A8 R/W Common Control 4 CCR4
A9 R Transmit DS0 Monitor TDS0M
AA R/W Common Control 5 CCR5
AB R Receive DS0 Monitor RDS0M
AC R/W Test 3 TEST3
AD — Not used (set to 00h)
AE — Not used (set to 00h)
AF — Not used (set to 00h)
B0 R/W HDLC Control Register HCR
B1 R/W HDLC Status Register HSR
B2 R/W HDLC Interrupt Mask Register HIMR
B3 R/W Receive HDLC Information Register RHIR
B4 R/W Receive HDLC FIFO Register RHFR
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
ADDRESS TYPE REGISTER NAME
B5 R/W Interleave Bus Operation Register IBO
B6 R/W Transmit HDLC Information Register THIR
B7 R/W Transmit HDLC FIFO Register THFR
B8 R/W Receive HDLC DS0 Control Register 1 RDC1
B9 R/W Receive HDLC DS0 Control Register 2 RDC2
BA R/W Transmit HDLC DS0 Control Register 1 TDC1
BB R/W Transmit HDLC DS0 Control Register 2 TDC2
BC — Not used (set to 00h)
BD — Not used (set to 00h)
BE — Not used (set to 00h)
BF — Not used (set to 00h)
Note 1:
Note 2:
Test Registers are used only by the factory. These registers must be cleared (set to all zeros) on power-up initialization to ensure
proper operation.
Register banks Cxh, Dxh, Exh, and Fxh are not accessible.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
5. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the
control registers are only accessed when the system is first powered up. Once the device has been
initialized, the control registers need only to be accessed when there is a change in the system
configuration. There are two receive control registers (RCR1 and RCR2), two transmit control registers
(TCR1 and TCR2), and six common control registers (CCR1 to CCR6). Each of the 10 registers is
described in this section.
There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed
to a one, indicating that an E1 SCT is present. The next three MSBs are used to indicate which E1 device
is present—DS2154, DS21354, or DS21554. The T1 pin-for-pin compatible SCTs have a logic zero in
the MSB position with the following three MSBs indicating which T1 SCT is present—DS2152,
DS21352, or DS21552. Table 5-1 represents the possible variations of these bits and the associated SCT.
Table 5-1. Device ID Bit Map
SCT T1/E1 BIT 6 BIT 5 BIT 4
DS2152 0 0 0 0
DS21352 0 0 0 1
DS21552 0 0 1 0
DS2154 1 0 0 0
DS21354 1 0 0 1
DS21554 1 0 1 0
The lower four bits of the IDR are used to display the die revision of the chip. The test registers at
addresses 09, 15, 19, and AC hex are used by the factory in testing the DS21354/DS21554. On power-up,
the test registers should be set to 00h in order for the DS21354/DS21554 to operate properly. Certain bits
of TEST3 are used to select monitor mode functions. Please see Section 15.5 for further details.
5.1.
On power-up, after the supplies are stable the DS21354/DS21554 should be configured for operation by
writing to all the internal registers (this includes setting the test registers to 00h) since the contents of the
internal registers cannot be predicted on power-up. The LIRST (CCR5.7) should be toggled from zero to
one to reset the line-interface circuitry (it will take the device about 40ms to recover from the LIRST bit
being toggled). Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bits (CCR6.0 and
CCR6.1) should be toggled from a zero to a one (this step can be skipped if the elastic stores are
disabled).
Power-Up Sequence
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