MAXIM DS2154 User Manual
r
100
Enhanced E1 Single-Chip Transceive
www.maxim-ic.com
FEATURES
Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceiver Functionality
On-Board Long- and Short-Haul Line
Interface for Clock/Data Recovery and
Waveshaping
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Asynchronous
Backplanes Up to 8.192MHz
8-Bit Parallel Control Port That can be Used
Directly on Either Multiplexed or
Nonmultiplexed Buses (Intel or Motorola)
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits Aligned
with CRC Multiframe
Four Separate Loopbacks for Testing
Functions
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2152 T1 Enhanced
Single-Chip Transceiver
5V Supply; Low-Power CMOS
100-Pin, 14mm2 LQFP Package
PIN CONFIGURATION
TOP VIEW
DS2154
1
LQFP
(14mm x 14mm)
ORDERING INFORMATION
PART
DS2154L
DS2154L+
DS2154LN
DS2154LN+
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
+Denotes lead-free/RoHS-compliant package.
PINPACKAGE
100 LQFP
100 LQFP
100 LQFP
100 LQFP
DS2154
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
1 of 87 REV: 011706
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DS2154
TABLE OF CONTENTS
1 DETAILED DESCRIPTION....................................................................................................6
1.1 INTRODUCTION .............................................................................................................................6
1.1.1 New Features......................................................................................................................................... 6
1.2 FUNCTIONAL DESCRIPTION ........................................................................................................... 7
1.3 READER’S NOTE ........................................................................................................................... 7
2 PIN DESCRIPTION................................................................................................................9
2.1 TRANSMIT SIDE DIGITAL PINS...................................................................................................... 11
2.2 RECEIVE SIDE DIGITAL PINS........................................................................................................ 12
2.3 PARALLEL CONTROL PORT PINS ................................................................................................. 13
2.4 LINE INTERFACE PINS .................................................................................................................14
2.5 SUPPLY PINS..............................................................................................................................14
3 PARALLEL PORT ...............................................................................................................20
4 CONTROL, ID, AND TEST REGISTERS ............................................................................ 20
4.1 FRAMER LOOPBACK....................................................................................................................29
4.2 LOCAL LOOPBACK.......................................................................................................................29
4.3 REMOTE LOOPBACK....................................................................................................................29
4.4 POWER-UP SEQUENCE ...............................................................................................................30
4.5 AUTOMATIC ALARM GENERATION ................................................................................................ 30
5 STATUS AND INFORMATION REGISTERS ...................................................................... 31
5.1 CRC4 SYNC COUNTER............................................................................................................... 33
6 ERROR COUNT REGISTERS............................................................................................. 39
6.1 BPV OR CODE VIOLATION COUNTER...........................................................................................39
6.2 CRC4 ERROR COUNTER ............................................................................................................40
6.3 E-BIT COUNTER ......................................................................................................................... 40
6.4 FAS ERROR COUNTER ............................................................................................................... 41
7 DS0 MONITORING FUNCTION .......................................................................................... 42
8 SIGNALING OPERATION...................................................................................................46
8.1 PROCESSOR-BASED SIGNALING..................................................................................................46
8.2 HARDWARE-BASED SIGNALING ................................................................................................... 49
8.2.1 Receive Side ........................................................................................................................................ 49
8.2.2 Transmit Side ....................................................................................................................................... 49
9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK .....................................51
9.1 TRANSMIT SIDE CODE GENERATION............................................................................................51
9.1.1 Simple Idle Code Insertion and Per-Channel Loopback...................................................................... 51
9.1.2 Per-Channel Code Insertion ................................................................................................................ 52
9.2 RECEIVE SIDE CODE GENERATION ..............................................................................................53
10 CLOCK BLOCKING REGISTERS..................................................................................55
11 ELASTIC STORES OPERATION ...................................................................................57
11.1 RECEIVE SIDE ............................................................................................................................ 57
11.2 TRANSMIT SIDE .......................................................................................................................... 57
12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION................................58
12.1 HARDWARE SCHEME .................................................................................................................. 58
12.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ........................................................... 58
12.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ..................................................... 61
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DS2154
13 LINE INTERFACE FUNCTION .......................................................................................63
13.1 RECEIVE CLOCK AND DATA RECOVERY .......................................................................................64
13.2 TRANSMIT WAVESHAPING AND LINE DRIVING ...............................................................................64
13.3 JITTER ATTENUATOR .................................................................................................................. 65
14 TIMING DIAGRAMS .......................................................................................................69
15 DC CHARACTERISTICS................................................................................................76
16 AC CHARACTERISTICS................................................................................................77
17 PACKAGE INFORMATION ............................................................................................ 87
17.1 100-PIN LQFP (56-G5002-000)................................................................................................. 87
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DS2154
LIST OF FIGURES
Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver ...................................................................... 8
Figure 13-1. External Analog Connections...............................................................................................66
Figure 13-2. Jitter Tolerance ....................................................................................................................67
Figure 13-3. Transmit Waveform Template..............................................................................................67
Figure 13-4. Jitter Attenuation ..................................................................................................................68
Figure 14-1. Receive Side Timing ............................................................................................................69
Figure 14-2. Receive Side Boundary Timing (with Elastic Store Disabled)..............................................69
Figure 14-3. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled) .............................70
Figure 14-4. Receive Side 2.048MHz Boundary Timing (with Elastic Store Enabled) .............................70
Figure 14-5. Transmit Side Timing ...........................................................................................................71
Figure 14-6. Transmit Side Boundary Timing...........................................................................................71
Figure 14-7. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................72
Figure 14-8. Transmit Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ............................72
Figure 14-9. G.802 Timing........................................................................................................................ 73
Figure 14-10. Synchronization Flow Chart ...............................................................................................74
Figure 14-11. Transmit Data Flow ............................................................................................................ 75
Figure 16-1. Intel Bus Read AC Timing (BTS = 0/MUX = 1) ....................................................................77
Figure 16-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1).....................................................................78
Figure 16-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)....................................................................... 78
Figure 16-4. Receive Side AC Timing ......................................................................................................80
Figure 16-5. Receive System Side AC Timing .........................................................................................81
Figure 16-6. Receive Line Interface AC Timing........................................................................................ 81
Figure 16-7. Transmit Side AC Timing .....................................................................................................83
Figure 16-8. Transmit System Side AC Timing ........................................................................................84
Figure 16-9. Transmit Line Interface Side AC Timing...............................................................................84
Figure 16-10. Intel Bus Read AC Timing (BTS = 0/MUX = 0) ..................................................................85
Figure 16-11. Intel Bus Write AC Timing (BTS=0/MUX=0).......................................................................86
Figure 16-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) ........................................................... 86
Figure 16-13. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) ...........................................................86
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DS2154
LIST OF TABLES
Table 2-1. Register Map ...........................................................................................................................15
Table 4-1. Sync/Resync Criteria...............................................................................................................21
Table 5-1. Alarm Criteria ..........................................................................................................................35
Table 13-1. Line Build-Out Select in LICR................................................................................................ 64
Table 13-2. Transformer Specifications....................................................................................................65
Table 15-1. Recommended DC Operating Conditions ............................................................................. 76
Table 15-2. Capacitance ..........................................................................................................................76
Table 15-3. DC Characteristics ................................................................................................................76
Table 16-1. AC Characteristics—Multiplexed Parallel Port (MUX = 1).....................................................77
Table 16-2. AC Characteristics—Receive Side........................................................................................79
Table 16-3. AC Characteristics—Transmit Side.......................................................................................82
Table 16-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 0) .............................................. 85
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DS2154
1 DETAILED DESCRIPTION
The DS2154 enhanced single-chip transceiver (SCT) contains all the necessary functions for connection
to E1 lines. The device is an upward compatible version of the DS2153 single-chip transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The
DS2154 automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to over 2km in length.
The device can generate the necessary G.703 waveshapes for both 75Ω coax and 120Ω twisted cables.
The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit
or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data
stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa bit information.
The device contains a set of internal registers that the user can access to control the operation of the unit.
Quick access via the parallel control port allows a single controller to handle many E1 lines. The device
fully meets all the latest E1 specifications including ITU G.703, G.704, G.706, G.823, G.932, and I.431
as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
1.1 Introduction
The DS2154 is a superset version of the popular DS2153Q E1 single-chip transceiver offering the new
features listed below. All the original features of the DS2153Q have been retained and software created
for the original devices is transferable into the DS2154.
1.1.1 New Features
Option for nonmultiplexed bus operation
Crystal-less jitter attenuation
Additional hardware signaling capability including:
– Receive signaling reinsertion to a backplane multiframe sync
– Availability of signaling in a separate PCM data stream
– Signaling freezing
– Interrupt generated on change of signaling data
Improved receive sensitivity: 0dB to -43dB
Per-channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192MHz clock synthesizer
Per-channel loopback
Addition of hardware pins to indicate carrier loss and signaling freeze
Line interface function can be completely decoupled from the framer/formatter to allow:
– Interface to optical, HDSL, and other NRZ interfaces
– Ability to “tap” the transmit and receive bipolar data streams for monitoring purposes
– Ability to corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50mA short circuit requirement
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
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DS2154
1.2 Functional Description
The analog AMI/HDB3 waveform off the E1 line is transformer-coupled into the RRING and RTIP pins
of the DS2154. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS2154 contains an active filter that reconstructs the analog received
signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive side framer
locates the FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms,
including carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive side elastic
store can be enabled in order to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock that is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048MHz clock or a 1.544MHz clock. The RSYSCLK
can be a bursty clock with speeds up to 8.192MHz.
The transmit side of the DS2154 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2154 will drive the E1 line from the
TTIP and TRING pins via a coupling transformer. The line driver contains a current limiter that restricts
the maximum current into a 1Ω load to less than 50mA (RMS).
1.3 Reader’s Note
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
time slots in an E1 system numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32
time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to
channel 1, time slot 1 is identical to Channel 2, and so on. Each time slot (or channel) is made up of 8 bits
numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is
transmitted last. Throughout this data sheet, the following abbreviations are used:
FAS Frame Alignment Signal
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
CAS Channel Associated Signaling
MF Multiframe
Sa Additional Bits
Si International Bits
E-Bit CRC4 Error Bits
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Figure 1-1. DS2154 Enhanced E1 Single-Chip Transceiver
DS2154
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2 PIN DESCRIPTION
PIN NAME TYPE FUNCTION
1 RCHBLK O Receive Channel Block
2, 4, 5,
7–10, 15, 23,
26, 27, 28,
36, 54, 76
3 8MCLK O 8.192MHz Clock
6 RCL O Receive Carrier Loss
11 BTS I Bus Type Select
12 LIUC I Line Interface Connect
13 8XCLK O Eight Times Clock
14 TEST I Test
16 RTIP I Receive Analog Tip Input
17 RRING I Receive Analog Ring Input
18 RVDD — Receive Analog Positive Supply
19, 20, 24 RVSS — Receive Analog Signal Ground
21 MCLK I Master Clock Input
22 XTALD O Quartz Crystal Driver
25
29 TTIP O Transmit Analog Tip Output
30 TVSS — Transmit Analog Signal Ground
31 TVDD — Transmit Analog Positive Supply
32 TRING O Transmit Analog Ring Output
33 TCHBLK O Transmit Channel Block
34 TLCLK O Transmit Link Clock
35 TLINK I Transmit Link Data
37 TSYNC I/O Transmit Sync
38 TPOSI I Transmit Positive Data Input
39 TNEGI I Transmit Negative Data Input
40 TCLKI I Transmit Clock Input
41 TCLKO O Transmit Clock Output
42 TNEGO O Transmit Negative Data Output
43 TPOSO O Transmit Positive Data Output
44, 61, 81,
83
45, 60, 80,
84
46 TCLK I Transmit Clock
47 TSER I Transmit Serial Data
48 TSIG I Transmit Signaling Input
49 TESO O Transmit Elastic Store Output
50 TDATA I Transmit Data
51 TSYSCLK I Transmit System Clock
52 TSSYNC I Transmit System Sync
53 TCHCLK O Transmit Channel Clock
55 MUX I Bus Operation
56 D0/AD0 I/O Data Bus Bit 0/Address/Data Bus Bit 0
N.C. —
INT
O Active-Low Interrupt
No Connection. These pins should be left o
DVDD — Digital Positive Supply
DVSS — Digital Signal Ground
DS2154
pen circuited.
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PIN NAME TYPE FUNCTION
57 D1/AD1 I/O Data Bus Bit 1/Address/Data Bus Bit 1
58 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus Bit 2
59 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
62 D4/AD4 I/O Data Bus Bit 4/Address/Data Bus Bit 4
63 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
64 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
65 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7
66–72 A0–A6 I Address Bus Bit 0
73 A7/ALE I Address Bus Bit 7/Address Latch Enable
74 RD(DS) I Active-Low Read Input (Data Strobe)
DS2154
75
CS
I Active-Low Chip Select
77 WR(R/W) I Active-Low Write Input (Read/Write)
78 RLINK O Receive Link Data
79 RLKCLK O Receive Link Clock
82 RCLK O Receive Clock
85 RDATA O Receive Data
86 RPOSI I Receive Positive Data Input
87 RNEGI I Receive Negative Data Input
88 RCLKI I Receive Clock Input
89 RCLKO O Receive Clock Output
90 RNEGO O Receive Negative Data Output
91 RPOSO O Receive Positive Data Output
92 RCHCLK O Receive Channel Clock
93 RSIGF O Receive Signaling Freeze Output
94 RSIG O Receive Signaling Output
95 RSER O Receive Serial Data
96 RMSYNC O Receive Multiframe Sync
97 RFSYNC O Receive Frame Sync
98 RSYNC I/O Receive Sync
99 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock
100 RSYSCLK I Receive System Clock
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DS2154
2.1 Transmit Side Digital Pins
PIN NAME FUNCTION
Transmit Clock. A 2.048MHz primary clock. Used to clock data through the transmit
46 TCLK
47 TSER
53 TCHCLK
33 TCHBLK
51 TSYSCLK
34 TLCLK
35 TLINK
37 TSYNC
52 TSSYNC
48 TSIG
49 TESO
50 TDATA
43 TPOSO
42 TNEGO
41 TCLKO
side formatter. Must be present for the parallel control port to operate properly. If not
present, the Loss of Transmit Clock (LOTC) function can provide a clock.
Transmit Serial Data. Transmit NRZ serial data. Sampled on the falling edge of
TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled.
Transmit Channel Clock. A 256kHz clock that pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled.
Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
Transmit Channel Block. A user-programmable output that can be forced high or low
during any of the 32 E1 channels. Synchronous with TCLK when the transmit side
elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic
store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in
applications where not all E1 channels are used such as Fractional E1, 384kbps (H0),
768kbps, 1920kbps (H12), or ISDN-PRI. Also useful for locating individual channels in
drop-and-insert applications, for external per-channel loopback, and for per-channel
conditioning. See Section 10
Transmit System Clock. 1.544MHz or 2.048MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use
the transmit side elastic store. Can be burst at rates up to 8.192MHz.
Transmit Link Clock. 4 kHz or 20kHz demand clock (Sa bits) for the TLINK input.
See Section 12
Transmit Link Data. If enabled, this pin will be sampled on the falling edge of TCLK
for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section
12
for details.
Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries
for the transmit side. This pin can also be programmed to output either a frame or
multiframe pulse. It is always synchronous with TCLK. See Section 14
Transmit System Sync. Only used when the transmit side elastic store is enabled. A
pulse at this pin will establish either frame or multiframe boundaries for the transmit
side. Should be tied low in applications that do not use the transmit side elastic store.
Always synchronous with TSYSCLK.
Transmit Signaling Input. When enabled, this input will sample signaling bits for
insertion into outgoing PCM E1 data stream. Sampled on the falling edge of TCLK
when the transmit side elastic store is disabled. Sampled on the falling edge of
TSYSCLK when the transmit side elastic store is enabled. See Section 14
Transmit Elastic Store Data Output. Updated on the rising edge of TCLK with data
out of the transmit side elastic store whether the elastic store is enabled or not. This pin
is normally tied to TDATA.
Transmit Data. Sampled on the falling edge of TCLK with data to be clocked through
the transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. Can be programmed to source NRZ data
via the Output Data Format (TCR1.7) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output. Updated on the rising edge of TCLKO with the
bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output. Buffered clock that is used to clock data through the transmit
side formatter (i.e., either TCLK or RCLKO if Loss of Transmit Clock is enabled and in
effect, or RCLKI if remote loopback is enabled). This pin is normally tied to TCLKI.
for details.
for details.
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for details.
for details.
PIN NAME FUNCTION
Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data to be
38 TPOSI
39 TNEGI
40 TCLKI
transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the
LIUC pin high.
Transmit Negative Data Input. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TNEGO by tying the
LIUC pin high.
Transmit Clock Input. Line interface transmit clock. Can be internally connected to
TCLKO by tying the LIUC pin high.
2.2 Receive Side Digital Pins
PIN NAME FUNCTION
78 RLINK
79 RLCLK
82 RCLK
92 RCHCLK
1 RCHBLK
95 RSER
98 RSYNC
97 RFSYNC
96 RMSYNC
85 RDATA
100 RSYSCLK
94 RSIG
99 RLOS/LOTC
Receive Link Data. Updated with the full recovered E1 datastream on the rising edge
of RCLK.
Receive Link Clock. A 4kHz to 20kHz clock (Sa bits) for the RLINK output. See
Section 12
Receive Clock. 2.048MHz clock that is used to clock data through the receive side
framer.
Receive Channel Clock. A 256kHz clock that pulses high during the LSB of each
channel. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for
parallel to serial conversion of channel data.
Receive Channel Block. A user-programmable output that can be forced high or low
during any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used, such as Fractional E1, 384kbps service, 768kbps, or
ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications,
for external per-channel loopback, and for per-channel conditioning. See Section 10
details.
Receive Serial Data. Received NRZ serial data. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated on the rising edges of
RSYSCLK when the receive side elastic store is enabled.
Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which
identifies either frame or CAS/CRC4 multiframe boundaries. If the receive side elastic
store is enabled, then this pin can be enabled to be an input at which a frame or
multiframe boundary pulse synchronous with RSYSCLK is applied.
Receive Frame Sync. An extracted 8kHz pulse, one RCLK wide, is output at this pin
that identifies frame boundaries.
Receive Multiframe Sync. An extracted pulse, one RSYSCLK wide, is output at this
pin, which identifies multiframe boundaries. If the receive side elastic store is disabled,
then this output will output multiframe boundaries associated with RCLK.
Receive Data. Updated on the rising edge of RCLK with the data out of the receive side
framer.
Receive System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic
store function is enabled. Should be tied low in applications that do not use the elastic
store. Can be burst at rates up to 8.192MHz.
Receive Signaling Output. Outputs signaling bits in a PCM format. Updated on rising
edges of RCLK when the receive side elastic store is disabled. Updated on the rising
edges of RSYSCLK when the receive side elastic store is enabled. See Section 14
Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is
for details.
DS2154
for
.
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PIN NAME FUNCTION
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high
when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5µs.
Receive Carrier Loss. Set high when the line interface detects a loss of carrier. Note: A
6 RCL
test mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in
place of detection at RTIP and RRING.
93 RSIGF
3 8MCLK
91 RPOSO
90 RNEGO
89 RCLKO
Receive Signaling Freeze. Set high when the signaling data is frozen via either
automatic or manual intervention. Used to alert downstream equipment of the condition.
8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at
the RCLK pin.
Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar
data out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output. Buffered recovered clock from the E1 line. This pin is normally
tied to RCLKI.
Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be
86 RPOSI
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be
87 RNEGI
clocked through the receive side framer. RPOSI and RNEGI can be tied together for a
NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input. Clock used to clock data through the receive side framer. This pin
88 RCLKI
is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC
pin high. RCLKI must be present for the parallel control port to operate properly.
2.3 Parallel Control Port Pins
PIN NAME FUNCTION
25
INT
14 TEST
55 MUX
56–65
D0–D7/
AD0–AD7
66–72 A0–A6
11 BTS
Interrupt. Flags host controller during conditions and change of conditions defined in
the Status Registers 1 and 2. Active-low, open-drain output.
Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel
control port). Set low for normal operation. Useful in board-level testing.
Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select
multiplexed bus operation.
Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as
the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus
timing. This pin controls the function of the
RD ( DS ), ALE(AS), and WR (R/ W ) pins.
If BTS = 1, then these pins assume the function listed in parentheses.
DS2154
74
RD(DS)
Read Input (Data Strobe).
RD and DS are active-low signals when MUX = 1. DS is
active high when MUX = 0. See the bus timing diagrams.
75
CS
Chip Select. Must be low to read or write to the device.
CS is an active-low signal.
A7 or Address Latch Enable (Address Strobe). In nonmultiplexed bus operation
73 ALE(AS)
(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),
serves to demultiplex the bus on a positive-going edge.
77
WR(R/W)
Write Input (Read/Write).
WR is an active-low signal.
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2.4 Line Interface Pins
PIN NAME FUNCTION
Master Clock Input. A 2.048MHz (±50ppm) clock source with TTL levels is applied at
21 MCLK
22 XTALD
13 8XCLK
12 LIUC
16, 17
29, 32
RTIP,
RRING
TTIP,
TRING
this pin. This clock is used internally for both clock/data recovery and for jitter
attenuation. A quartz crystal of 2.048MHz may be applied across MCLK and XTALD
instead of the TTL level clock source.
Quartz Crystal Driver. A quartz crystal of 2.048MHz may be applied across MCLK
and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a
TTL clock source is applied at MCLK.
Eight Times Clock. A 16.384MHz clock that is frequency locked to the 2.048MHz
clock provided from the clock/data recovery block (if the jitter attenuator is enabled on
the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit
side). Can be internally disabled via the TEST2 register if not needed.
Line Interface Connect. Tie low to separate the line interface circuitry from the
framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/
RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When
LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be
tied low.
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect
via a 1:1 transformer to the E1 line. See Section 13
Transmit Tip and Ring. Analog line driver outputs. These pins connect via a 1:1.15 or
1:1.36 step-up transformer to the E1 line. See Section 13
for details.
for details.
2.5 Supply Pins
PIN NAME FUNCTION
44, 61,
81, 83
18 RVDD
31 TVDD
45, 60,
80, 84
19, 20,
24
30 TVSS Transmit Analog Ground. 0V. Should be tied to the RVSS and DVSS pins.
DVDD Digital Positive Supply. 5.0V ±5%. Should be tied to the RVDD and TVDD pins.
Receive Analog Positive Supply. 5.0V ±5%. Should be tied to the DVDD and TVDD
pins.
Transmit Analog Positive Supply. 5.0V ±5%. Should be tied to the RVDD and DVDD
pins.
DVSS Digital Signal Ground. Should be tied to the RVSS and TVSS pins.
RVSS Receive Analog Signal Ground. 0V. Should be tied to the DVSS and TVSS pins.
DS2154
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Table 2-1. Register Map
DS2154
ADDRESS R/W
00 R BPV or Code Violation Count 1 VCR1
01 R BPV or Code Violation Count 2 VCR2
02 R CRC4 Error Count 1/FAS Error Count 1 CRCCR1
03 R CRC4 Error Count 2 CRCCR2
04 R E-Bit Count 1/FAS Error Count 2 EBCR1
05 R E-Bit Count 2 EBCR2
06 R/W Status 1 SR1
07 R/W Status 2 SR2
08 R/W Receive Information RIR
09, 0A–0E,
1D
0F R Device ID Register IDR
10 R/W Receive Control 1 RCR1
11 R/W Receive Control 2 RCR2
12 R/W Transmit Control 1 TCR1
13 R/W Transmit Control 2 TCR2
14 R/W Common Control 1 CCR1
15 R/W Test 1 TEST1 (set to 00h)
16 R/W Interrupt Mask 1 IMR1
17 R/W Interrupt Mask 2 IMR2
18 R/W Line Interface Control LICR
19 R/W Test 2 TEST2 (set to 00h)
1A R/W Common Control 2 CCR2
1B R/W Common Control CCR3
1C R/W Transmit Sa Bit Control TSaCR
1E R Synchronizer Status SSR
1F R Receive Non-Align Frame RNAF
20 R/W Transmit Align Frame TAF
21 R/W Transmit Non-Align Frame TNAF
22 R/W Transmit Channel Blocking 1 TCBR1
23 R/W Transmit Channel Blocking 2 TCBR2
24 R/W Transmit Channel Blocking 3 TCBR3
25 R/W Transmit Channel Blocking 4 TCBR4
26 R/W Transmit Idle 1 TIR1
27 R/W Transmit Idle 2 TIR2
28 R/W Transmit Idle 3 TIR3
29 R/W Transmit Idle 4 TIR4
—
Not Present —
DESCRIPTION NAME
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REGISTER
REGISTER
ADDRESS R/W
DESCRIPTION NAME
2A R/W Transmit Idle Definition TIDR
2B R/W Receive Channel Blocking 1 RCBR1
2C R/W Receive Channel Blocking 2 RCBR2
2D R/W Receive Channel Blocking 3 RCBR3
2E R/W Receive Channel Blocking 4 RCBR4
2F R Receive Align Frame RAF
30 R Receive Signaling 1 RS1
31 R Receive Signaling 2 RS2
32 R Receive Signaling 3 RS3
33 R Receive Signaling 4 RS4
34 R Receive Signaling 5 RS5
35 R Receive Signaling 6 RS6
36 R Receive Signaling 7 RS7
37 R Receive Signaling 8 RS8
38 R Receive Signaling 9 RS9
39 R Receive Signaling 10 RS10
3A R Receive Signaling 11 RS11
3B R Receive Signaling 12 RS12
3C R Receive Signaling 13 RS13
3D R Receive Signaling 14 RS14
3E R Receive Signaling 15 RS15
3F R Receive Signaling 16 RS16
40 R/W Transmit Signaling 1 TS1
41 R/W Transmit Signaling 2 TS2
42 R/W Transmit Signaling 3 TS3
43 R/W Transmit Signaling 4 TS4
44 R/W Transmit Signaling 5 TS5
45 R/W Transmit Signaling 6 TS6
46 R/W Transmit Signaling 7 TS7
47 R/W Transmit Signaling 8 TS8
48 R/W Transmit Signaling 9 TS9
49 R/W Transmit Signaling 10 TS10
4A R/W Transmit Signaling 11 TS11
4B R/W Transmit Signaling 12 TS12
4C R/W Transmit Signaling 13 TS13
4D R/W Transmit Signaling 14 TS14
4E R/W Transmit Signaling 15 TS15
4F R/W Transmit Signaling 16 TS16
DS2154
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REGISTER
ADDRESS R/W
DESCRIPTION NAME
50 R/W Transmit Si Bits Align Frame TSiAF
51 R/W Transmit Si Bits Non-Align Frame TSiNAF
52 R/W Transmit Remote Alarm Bits TRA
53 R/W Transmit Sa4 Bits TSa4
54 R/W Transmit Sa5 Bits TSa5
55 R/W Transmit Sa6 Bits TSa6
56 R/W Transmit Sa7 Bits TSa7
57 R/W Transmit Sa8 Bits TSa8
58 R Receive Si Bits Align Frame RSiAF
59 R Receive Si Bits Non-Align Frame RSiNAF
5A R Receive Remote Alarm Bits RRA
5B R Receive Sa4 Bits RSa4
5C R Receive Sa5 Bits RSa5
5D R Receive Sa6 Bits RSa6
5E R Receive Sa7 Bits RSa7
5F R Receive Sa8 Bits RSa8
60 R/W Transmit Channel 1 TC1
61 R/W Transmit Channel 2 TC2
62 R/W Transmit Channel 3 TC3
63 R/W Transmit Channel 4 TC4
64 R/W Transmit Channel 5 TC5
65 R/W Transmit Channel 6 TC6
66 R/W Transmit Channel 7 TC7
67 R/W Transmit Channel 8 TC8
68 R/W Transmit Channel 9 TC9
69 R/W Transmit Channel 10 TC10
6A R/W Transmit Channel 11 TC11
6B R/W Transmit Channel 12 TC12
6C R/W Transmit Channel 13 TC13
6D R/W Transmit Channel 14 TC14
6E R/W Transmit Channel 15 TC15
6F R/W Transmit Channel 16 TC16
70 R/W Transmit Channel 17 TC17
71 R/W Transmit Channel 18. TC18
72 R/W Transmit Channel 19 TC19
73 R/W Transmit Channel 20 TC20
74 R/W Transmit Channel 21 TC21
75 R/W Transmit Channel 22 TC22
DS2154
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REGISTER
ADDRESS R/W
DESCRIPTION NAME
76 R/W Transmit Channel 23 TC23
77 R/W Transmit Channel 24 TC24
78 R/W Transmit Channel 25 TC25
79 R/W Transmit Channel 26 TC26
7A R/W Transmit Channel 27 TC27
7B R/W Transmit Channel 28 TC28
7C R/W Transmit Channel 29 TC29
7D R/W Transmit Channel 30 TC30
7E R/W Transmit Channel 31 TC31
7F R/W Transmit Channel 32 TC32
80 R/W Receive Channel 1 RC1
81 R/W Receive Channel 2 RC2
82 R/W Receive Channel 3 RC3
83 R/W Receive Channel 4 RC4
84 R/W Receive Channel 5 RC5
85 R/W Receive Channel 6 RC6
86 R/W Receive Channel 7 RC7
87 R/W Receive Channel 8 RC8
88 R/W Receive Channel 9 RC9
89 R/W Receive Channel 10 RC10
8A R/W Receive Channel 11 RC11
8B R/W Receive Channel 12 RC12
8C R/W Receive Channel 13 RC13
8D R/W Receive Channel 14 RC14
8E R/W Receive Channel 15 RC15
8F R/W Receive Channel 16 RC16
90 R/W Receive Channel 17 RC17
91 R/W Receive Channel 18 RC18
92 R/W Receive Channel 19 RC19
93 R/W Receive Channel 20 RC20
94 R/W Receive Channel 21 RC21
95 R/W Receive Channel 22 RC22
96 R/W Receive Channel 23 RC23
97 R/W Receive Channel 24 RC24
98 R/W Receive Channel 25 RC25
99 R/W Receive Channel 26 RC26
9A R/W Receive Channel 27 RC27
9B R/W Receive Channel 28 RC28
DS2154
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REGISTER
ADDRESS R/W
DESCRIPTION NAME
9C R/W Receive Channel 29 RC29
9D R/W Receive Channel 30 RC30
9E R/W Receive Channel 31 RC31
9F R/W Receive Channel 32 RC32
A0 R/W Transmit Channel Control 1 TCC1
A1 R/W Transmit Channel Control 2 TCC2
A2 R/W Transmit Channel Control 3 TCC3
A3 R/W Transmit Channel Control 4 TCC4
A4 R/W Receive Channel Control 1 RCC1
A5 R/W Receive Channel Control 2 RCC2
A6 R/W Receive Channel Control 3 RCC3
A7 R/W Receive Channel Control 4 RCC4
A8 R/W Common Control 4 CCR4
A9 R Transmit DS0 Monitor TDS0M
AA R/W Common Control 5 CCR5
AB R Receive DS0 Monitor RDS0M
AC R/W Test 3 TEST3 (set to 00h)
AD R/W Not Used (set to 00h)
AE R/W Not Used (set to 00h)
AF R/W Not Used (set to 00h)
DS2154
Note 1: Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure proper
operation.
Note 2: Register banks Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
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DS2154
3 PARALLEL PORT
The DS2154 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an
external microcontroller or microprocessor. The DS2154 can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parentheses. See the timing diagrams in the
AC Electrical Characteristics in Section 16 for more details.
4 CONTROL, ID, AND TEST REGISTERS
The operation of the DS2154 is configured via a set of nine control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the DS2154 has been initialized,
the control registers will only need to be accessed when there is a change in the system configuration.
There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and
TCR2), and five Common Control Registers (CCR1 to CCR5). Each of the nine registers is described in
this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed
to a 1 indicating that the DS2154 is present. The pin-for-pin compatible T1 version of the DS2154 is the
DS2152, which also has an ID register at address 0Fh. The user can read the MSB to determine which
chip is present because the MSB is set to 1 in the DS2154, and is set to 0 in the DS2152. The lower 4 bits
of the IDR are used to display the die revision of the chip.
The Test Registers at addresses 15, 19, and AC hex are used by the factory in testing the DS2154. On
power-up, the Test Registers should be set to 00 hex for the DS2154 to operate properly.
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(MSB) (LSB)
T1E1 0 0 0 ID3 ID2 ID1 ID0
SYMBOL
T1E1 IDR.7
ID3 IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the
ID2 IDR.1
ID1 IDR.2
ID0 IDR.0 Chip Revision Bit 0. LSB of a decimal code that represents the
POSITION NAME AND DESCRIPTION
T1 or E1 Chip Determination Bit.
0 = T1 chip
1 = E1 chip
chip revision.
Chip Revision Bit 2.
Chip Revision Bit 1.
chip revision.
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DS2154
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10 Hex)
(MSB) (LSB)
RSMF RSM RSIO — — FRC SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSM RCR1.6
RSIO RCR1.5 RSYNC I/O Select. (Note: This bit must be set to 0 when
— RCR1.4,
RCR1.3
FRC RCR1.2
SYNCE RCR1.1
RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated.
RSYNC Mode Select.
0 = frame mode (see the timing in Section 14)
1 = multiframe mode (see the timing in Section 14)
RCR2.1 = 0.)
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Not Assigned. Should be set to 0 when written.
Frame Resync Criteria.
0 = resync if FAS received in error three consecutive times
1 =resync if FAS or bit 2 of non-FAS is received in error three
consecutive times
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
Must be cleared and set again for a subsequent resync.
Table 4-1. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
FAS present in frame N and N + 2, and
FAS not present in frame N + 1
FAS
Two valid MF alignment words found
CRC4
within 8ms
Valid MF alignment word found and
CAS
previous time slot 16 contains code
other than all 0s
SYNC CRITERIA RESYNC CRITERIA ITU SPEC.
Three consecutive incorrect
FAS received
Alternate (RCR1.2 = 1) the
above criteria is met or three
consecutive incorrect bit 2 of
G.706
4.1.1
4.1.2
non-FAS received
21 of 87
915 or more CRC4 code
words out of 1000 received in
error
Two consecutive MF
alignment words received in
error
G.706
4.2 and 4.3.2
G.732
5.2
DS2154
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB) (LSB)
Sa8S Sa7S Sa6S Sa5S Sa4S RBCS RESE —
SYMBOL POSITION NAME AND DESCRIPTION
Sa8S RCR2.7 Sa8 Bit Select. Set to 1 to have RLCLK pulse at the Sa8 bit
position; set to 0 to force RLCLK low during Sa8 bit position.
See Section 14 for timing details.
Sa7S RCR2.6 Sa7 Bit Select. Set to 1 to have RLCLK pulse at the Sa7 bit
position; set to 0 to force RLCLK low during Sa7 bit position.
See Section 14 for timing details.
Sa6S RCR2.5 Sa6 Bit Select. Set to 1 to have RLCLK pulse at the Sa6 bit
position; set to 0 to force RLCLK low during Sa6 bit position.
See Section 14 for timing details.
Sa5S RCR2.4 Sa5 Bit Select. Set to 1 to have RLCLK pulse at the Sa5 bit
position; set to 0 to force RLCLK low during Sa5 bit position.
See Section 14 for timing details.
Sa4S RCR2.3 Sa4 Bit Select. Set to 1 to have RLCLK pulse at the Sa4 bit
position; set to 0 to force RLCLK low during Sa4 bit position.
See Section 14 for timing details.
RBCS RCR2.2
RESE RCR2.1
— RCR2.0 Not Assigned. Should be set to 0 when written.
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
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DS2154
TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex)
(MSB) (LSB)
ODF TFPT T16S TUA1 TSiS TSA1 TSM TSIO
SYMBOL POSITION NAME AND DESCRIPTION
ODF TCR1.7
Output Data Format.
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
TFPT TCR1.6
Transmit Time Slot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
T16S TCR1.5
Transmit Time Slot 16 Data Select.
0 = sample time slot 16 at TSER pin
1 = source time slot 16 from TS0 to TS15 registers
TUA1 TCR1.4
Transmit Unframed All 1s.
0 = transmit data normally
1 = transmit an unframed all 1’s code at TPOSO and TNEGO
TSiS TCR1.3
Transmit International Bit Select.
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1 TCR1.2
Transmit Signaling All 1s.
0 = normal operation
1 = force time slot 16 in every frame to all 1s
TSM TCR1.1 TSYNC Mode Select.
0 = frame mode (see the timing in Section 14
)
1 = CAS and CRC4 multiframe mode (see the timing in Section
14)
TSIO TCR1.0
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
Note: See Figure 14-11 for more details about how the Transmit Control Registers affect the operation of the DS2154.
23 of 87
DS2154
TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex)
(MSB) (LSB)
Sa8S Sa7S Sa6S Sa5S Sa4S ODM AEBE PF
SYMBOL POSITION NAME AND DESCRIPTION
Sa8S TCR2.7 Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK
pin; set to 0 to not source the Sa8 bit. See Section 14 for timing
details.
Sa7S TCR2.6 Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK
pin; set to 0 to not source the Sa7 bit. See Section 14 for timing
details.
Sa6S TCR2.5 Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK
pin; set to 0 to not source the Sa6 bit. See Section 14
details.
Sa5S TCR2.4 Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK
pin; set to 0 to not source the Sa5 bit. See Section 14
details.
Sa4S TCR2.3 Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK
pin; set to 0 to not source the Sa4 bit. See Section 14 for timing
details.
ODM TCR2.2
Output Data Mode.
0 = pulses at TPOSO and TNEGO are one full TCLKO period
wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
AEBE TCR2.1
Automatic E-Bit Enable.
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
PF TCR2.0
Function of RLOS/LOTC Pin.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
for timing
for timing
24 of 87
DS2154
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)
(MSB) (LSB)
FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4
SYMBOL POSITION NAME AND DESCRIPTION
FLB CCR1.7
Framer Loopback.
0 = loopback disabled
1 =loopback enabled
THDB3 CCR1.6
Transmit HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
TG802 CCR1.5 Transmit G.802 Enable. See Section 14 for details.
0 = do not force TCHBLK high during bit 1 of time slot 26
1 = force TCHBLK high during bit 1 of time slot 26
TCRC4 CCR1.4
Transmit CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
RSM CCR1.3
Receive Signaling Mode Select.
0 = CAS signaling mode
1 = CCS signaling mode
RHDB3 CCR1.2
Receive HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
RG802 CCR1.1 Receive G.802 Enable. See Section 14 for details.
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
RCRC4 CCR1.0
Receive CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
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DS2154
CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex)
(MSB) (LSB)
ECUS VCRFS AAIS ARA RSERC LOTCMC RFF RFE
SYMBOL POSITION NAME AND DESCRIPTION
ECUS CCR2.7 Error Counter Update Select. See Section 6 for details.
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
VCRFS CCR2.6 VCR Function Select. See Section 6 for details.
0 = count Bipolar Violations (BPVs)
1 = count Code Violations (CVs)
AAIS CCR2.5
ARA CCR2.4
RSERC CCR2.3
LOTCMC CCR2.2 Loss of Transmit Clock Mux Control. Determines whether the
RFF CCR2.1 Receive Force Freeze. Freezes receive side signaling at RSIG
RFE CCR2.0 Receive Freeze Enable. See Section 8.2 for details.
Automatic AIS Generation.
0 = disabled
1 = enabled
Automatic Remote Alarm Generation.
0 = disabled
1 = enabled
RSER Control.
0 = allow RSER to output data as received under all conditions
1 = force RSER to 1 under loss of frame alignment conditions
transmit side formatter should switch to the ever-present
RCLKO if the TCLK should fail to transition (see Figure 1-1).
0 = do not switch to RCLKO if TCLK stops
1 = switch to RCLKO if TCLK stops
(and RSER if CCR3.3 = 1); will override Receive Freeze Enable
(RFE). See Section 8.2 for details.
0 = do not force a freeze event
1 = force a freeze event
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER
if CCR3.3 = 1).
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DS2154
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB) (LSB)
TESE TCBFS TIRFS ESR RSRE THSE TBCS RCLA
SYMBOL POSITION NAME AND DESCRIPTION
TESE CCR3.7
Transmit Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
TCBFS CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
TIRFS CCR3.5 Transmit Idle Registers (TIR) Function Select. See Section 9
for details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
(i.e., Per-Channel Loopback function)
ESR CCR3.4 Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. ESR is level triggered.
Should be toggled after RSYSCLK and TSYSCLK have been
applied and are stable. Must be set and cleared again for a
subsequent reset. Do not leave this bit set high.
RSRE CCR3.3 Receive Side Signaling Re-Insertion Enable. See Section 8.2
for details.
0 = do not reinsert signaling bits into the data stream presented
at the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
THSE CCR3.2 Transmit Side Hardware Signaling Insertion Enable. See
Section 8.2
for details.
0 = do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
1 = insert signaling from the TSIG pin into the data stream
presented at the TSER pin
TBCS CCR3.1
Transmit Side Backplane Clock Select.
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz
RCLA CCR3.0
Receive Carrier Loss (RCL) Alternate Criteria.
0 = RCL declared upon 255 consecutive 0s (125µs)
1 = RCL declared upon 2048 consecutive 0s (1ms)
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