MAXIM DS2153Q Technical data

2 CS R

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FEATURES

 Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceiver Functionality

 On-Board Line Interface for Clock/Data

Recovery and Waveshaping

 32-Bit or 128-Bit Jitter Attenuator  Generates Line Build-Outs for Both 120Ω

and 75Ω Lines

 Frames to FAS, CAS, and CRC4 Formats  Dual On-Board Two-Frame Elastic Store Slip

Buffers That can Connect to Backplanes Up to 8.192MHz

 8-Bit Parallel Control Port That can be Used

on Either Multiplexed or Nonmultiplexed Buses

 Extracts and Inserts CAS Signaling  Detects and Generates Remote and AIS

Alarms

 Programmable Output Clocks for Fractional

E1, H0, and H12 Applications

 Fully Independent Transmit and Receive

Functionality

 Full Access to Both Si and Sa Bits  Three Separate Loopbacks for Testing  Large Counters for Bipolar and Code

Violations, CRC4 Codeword Errors, FAS Errors, and E Bits

 Pin Compatible with DS2151Q T1 Single-

Chip Transceiver

 5V Supply; Low-Power CMOS

ORDERING INFORMATION

PART

DS2153Q DS2153Q+ DS2153QN DS2153QN+

TEMP

RANGE

0°C to +70°C 0°C to +70°C

-40°C to +85°C

+Denotes lead-free/RoHS-compliant package.

PINPACKAGE

44 PLCC 44 PLCC 44 PLCC 44 PLCC

DS2153Q

E1 Single-Chip Transceive

PIN CONFIGURATION

Dallas

DS2153Q

T1SCT

ALE(AS)

WR (R/W)

RLIN

RLCL

DVSS

RCL

RCHCL

RSE

RSYNC

RLOS/LOTC

SYSCL

FUNCTIONAL BLOCKS

FRAMER

HAUL LINE

INTERFACE

LONG & SHORT

PARALLEL CONTROL

PORT

ACTUAL SIZE OF 44-PIN PLCC

D(DS) AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

ACLKI

RCHBL

DS2153Q

BTS

RTIP

RVDD

RRING

RVSS

XTAL1

XTAL2

PLCC

STORES

ELASTIC

TCHCLK

INT

TSER

TCLK

DVDD

TSYNC

TLINK

TLCLK

TCHBLK

TRING

TVDD

TVSS

TTIP

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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DS2153Q

TABLE OF CONTENTS

1 DETAILED DESCRIPTION....................................................................................................4

1.1 INTRODUCTION................................................................................................................................4

1.2 READER’S NOTE.............................................................................................................................. 4

2 PIN DESCRIPTION................................................................................................................6

2.1 DS2153Q REGISTER MAP...............................................................................................................8

3 PARALLEL PORT.................................................................................................................9

4 CONTROL AND TEST REGISTERS................................................................................... 10

4.1 LOCAL LOOPBACK .........................................................................................................................17

4.2 REMOTE LOOPBACK ......................................................................................................................17

4.3 FRAMER LOOPBACK ......................................................................................................................17

4.4 AUTOMATIC ALARM GENERATION................................................................................................... 17

4.5 POWER-UP SEQUENCE ................................................................................................................. 17

5 STATUS AND INFORMATION REGISTERS ......................................................................18

5.1 CRC4 SYNC COUNTER .................................................................................................................20

6 ERROR COUNT REGISTERS.............................................................................................26

6.1 BPV OR CODE VIOLATION COUNTER ............................................................................................. 26

6.2 CRC4 ERROR COUNTER ............................................................................................................... 27

6.3 E-BIT COUNTER ............................................................................................................................ 27

6.4 FAS BIT ERROR COUNTER ............................................................................................................28

7 SA DATA LINK CONTROL AND OPERATION..................................................................29

8 SIGNALING OPERATION................................................................................................... 30

9 TRANSMIT IDLE REGISTERS............................................................................................32

10 CLOCK BLOCKING REGISTERS....................................................................................33

11 ELASTIC STORES OPERATION.....................................................................................35

12 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................36

13 LINE INTERFACE FUNCTIONS.......................................................................................39

13.1 RECEIVE CLOCK AND DATA RECOVERY.......................................................................................40

13.2 TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................41

13.3 JITTER ATTENUATOR.................................................................................................................. 42

14 TIMING DIAGRAMS .........................................................................................................46

15 DC CHARACTERISTICS.................................................................................................. 52

16 AC CHARACTERISTICS.................................................................................................. 53

17 PACKAGE INFORMATION.............................................................................................. 60

17.1 44-PIN PLCC (56-G4003-001)..................................................................................................60

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DS2153Q

LIST OF FIGURES

Figure 1-1. DS2153Q Block Diagram .........................................................................................................5

Figure 13-1. External Analog Connections............................................................................................... 43

Figure 13-2. Jitter Tolerance ....................................................................................................................44

Figure 13-3. Transmit Waveform Template.............................................................................................. 44

Figure 13-4. Jitter Attenuation .................................................................................................................. 45

Figure 14-1. Receive Side Timing ............................................................................................................46

Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled) ............................................ 46

Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled................................................. 47

Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled.................................................. 47

Figure 14-5. Transmit Side Timing ...........................................................................................................48

Figure 14-6. Transmit Side Boundary Timing........................................................................................... 48

Figure 14-7. G.802 Timing........................................................................................................................ 49

Figure 14-8. Synchronization Flowchart ...................................................................................................50

Figure 14-9. Transmit Data Flow ..............................................................................................................51

Figure 16-1. Intel Bus Read AC Timing.................................................................................................... 54

Figure 16-2. Intel Bus Write AC Timing ....................................................................................................54

Figure 16-3. Motorola Bus AC Timing ......................................................................................................55

Figure 16-4. Receive Side AC Timing ......................................................................................................57

Figure 16-5. Transmit Side AC Timing .....................................................................................................59

LIST OF TABLES

Table 4-1. Sync/Resync Criteria............................................................................................................... 11

Table 5-1. Alarm Set and Clear Criteria ...................................................................................................22

Table 13-1. Source of RCLK Upon RCL................................................................................................... 40

Table 13-2. LBO Select in LICR ...............................................................................................................41

Table 13-3. Transformer Specifications....................................................................................................41

Table 13-4. Crystal Selection Guidelines .................................................................................................42

Table 15-1. Recommended DC Characteristics ....................................................................................... 52

Table 15-2. Capacitance ..........................................................................................................................52

Table 15-3. DC Characteristics ................................................................................................................52

Table 16-1. AC Characteristics—Parallel Port .........................................................................................53

Table 16-2. AC Characteristics—Receive Side........................................................................................ 56

Table 16-3. AC Characteristics—Transmit Side....................................................................................... 58

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DS2153Q

1 DETAILED DESCRIPTION

The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km. The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011, 300 233, TBR 12 and TBR 13.

1.1 Introduction

The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input.

The transmit side of the DS2153Q is totally independent from the receive side in both the clock requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP and TRING pins via a coupling transformer.

1.2 Reader’s Note

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations are used:

FAS Frame Alignment Signal CAS Channel Associated Signaling MF Multiframe Si International Bits CRC4 Cyclical Redundancy Check CCS Common Channel Signaling Sa Additional bits E-bit CRC4 Error bits

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Figure 1-1. DS2153Q Block Diagram

DS2153Q

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2 PIN DESCRIPTION

PIN NAME TYPE FUNCTION

1–4,

41–44

7 ALE(AS) I

9 RLINK O

10 RLCLK O

11 DVSS — Digital Signal Ground. 0.0V. Should be tied to local ground plane. 12 RCLK O Receive Clock. Recovered 2.048MHz clock.

13 RCHCLK O

14 RSER O

15 RSYNC I/O

16 RLOS/LOTC O

17 SYSCLK I

18 RCHBLK O

19 ACLKI I

AD4–AD7,

AD0–AD3

RD (DS)

WR (R/ W )

I/O Address/Data Bus. An 8-bit multiplexed address/data bus.

Active-Low Read Input (Data Strobe)

I Active-Low Chip Select. Must be low to read or write the port.

Address Latch Enable (Address Strobe). A positive going edge

serves to demultiplex the bus.

Active-Low Write Input (Read/Write) Receive Link Data. Outputs the full receive data stream including the

Sa bits. See Section 14

for timing details. Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK output. Controlled by RCR2. See Section 14

for timing details.

Receive Channel Clock. 256kHz clock that pulses high during the LSB of each channel. Useful for parallel to serial conversion of channel data. See Section 14

for timing details. Receive Serial Data. Received NRZ serial data, updated on rising edges of RCLK or SYSCLK. Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which identifies either frame (RCR1.6 = 0) or multiframe boundaries (RCR1.6 = 1). If the elastic store is enabled via the RCR2.1, then this pin can be enabled to be an input via RCR1.5 at which a frame boundary pulse is applied. See Section 14

for timing details. Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If TCR2.0 = 0, will toggle high when the synchronizer is searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle high if the TCLK pin has not toggled for 5µs. System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic store functions are enabled via either RCR2.1. Should be tied low in applications that do not use the elastic store. If tied high for at least 100µs, will force all output pins (including the parallel port) to tri-state. Receive Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional E1, 384kbps service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 14 timing details. Alternate Clock Input. Upon a receive carrier loss, the clock applied at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no clock is routed to this pin, then it should be tied to DVSS via a 1kΩ resistor.

DS2153Q

for

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PIN NAME TYPE FUNCTION

Bus Type Select. Strap high to select Motorola bus timing; strap low to

20 BTS I

select Intel bus timing. This pin controls the function of the ALE(AS), and

WR (R/ W ) pins. If BTS = 1, then these pins assume the

function listed in parentheses ().

21, 22

RTIP,

RRING

—

23 RVDD —

Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects to a 1:1 transformer (see Section 13

for details).

Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and TVDD pins.

24 RVSS — Receive Signal Ground. 0V. Should be tied to local ground plane.

25, 26

XTAL1,

XTAL2

INT1

INT2

—

29 TTIP —

Crystal Connections. A pullable 8.192MHz crystal must be applied to these pins. See Section 13

for crystal specifications.

Receive Alarm Interrupt 1. Flags host controller during alarm conditions defined in Status Register 1. Active low, open drain output. Receive Alarm Interrupt 2. Flags host controller during conditions defined in Status Register 2. Active low, open drain output. Transmit Tip. Analog line driver output; connects to a step-up transformer (see Section 13

for details).

30 TVSS — Transmit Signal Ground. 0V. Should be tied to local ground plane.

31 TVDD —

32 TRING —

Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and RVDD pins. Transmit Ring. Analog line driver outputs; connects to a step-up transformer (see Section 13

for details). Transmit Channel Block. A user-programmable output that can be forced high or low during any of the 32 E1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications

33 TCHBLK O

where not all E1 channels are used such as Fractional E1, 384kbps service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 14 timing details.

34 TLCLK O

35 TLINK I

Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK input. Controlled by TCR2. See Section 14

for timing details. Transmit Link Data. If enabled, this pin will be sampled on the falling edge of TCLK to insert the Sa bits. See Section 14

for timing details.

Transmit Sync. A pulse at this pin will establish either frame or

36 TSYNC I/O

37 DVDD —

multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be programmed to output either a frame or multiframe pulse at this pin. See Section 14

for timing details. Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD pins.

38 TCLK I Transmit Clock. 2.048MHz primary clock.

39 TSER I

Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge of TCLK. Transmit Channel Clock. 256kHz clock that pulses high during the

40 TCHCLK O

LSB of each channel. Useful for parallel to serial conversion of channel data. See Section 14

for timing details.

DS2153Q

RD (DS),

for

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DS2153Q

2.1 DS2153Q Register Map

ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME

00 R BPV or Code Violation Count 1 20 R/W Transmit Align Frame 01 R BPV or Code Violation Count 2 21 R/W Transmit Non-Align Frame 02 R CRC4 Count 1/FAS Error Count 1 22 R/W Transmit Channel Blocking 1 03 R CRC4 Error Count 2 23 R/W Transmit Channel Blocking 2 04 R E-Bit Count 1/FAS Error Count 2 24 R/W Transmit Channel Blocking 3 05 R E-Bit Count 2 25 R/W Transmit Channel Blocking 4 06 R Status 1 26 R/W Transmit Idle 1 07 R Status 2 27 R/W Transmit Idle 2 08 R/W Receive Information 28 R/W Transmit Idle 3 10 R/W Receive Control 1 29 R/W Transmit Idle 4 11 R/W Receive Control 2 2A R/W Transmit Idle Definition 12 R/W Transmit Control 1 2B R/W Receive Channel Blocking 1 13 R/W Transmit Control 2 2C R/W Receive Channel Blocking 2 14 R/W Common Control 1 2E R/W Receive Channel Blocking 3 15 R/W Test 1 2E R/W Receive Channel Blocking 4 16 R/W Interrupt Mask 1 2F R Receive Align Frame 17 R/W Interrupt Mask 2 30 R Receive Signaling 1 18 R/W Line Interface Control 31 R Receive Signaling 2

19 R/W Test 2 32 R Receive Signaling 3 1A R/W Common Control 2 33 R Receive Signaling 4 1B R/W Common Control 3 34 R Receive Signaling 5 1E R Synchronizer Status 35 R Receive Signaling 6

1F R Receive Non-Align Frame 36 R Receive Signaling 7

40 R/W Transmit Signaling 1 37 R Receive Signaling 8

41 R/W Transmit Signaling 2 38 R Receive Signaling 9

42 R/W Transmit Signaling 3 39 R Receive Signaling 10

43 R/W Transmit Signaling 4 3A R Receive Signaling 11

44 R/W Transmit Signaling 5 3B R Receive Signaling 12

45 R/W Transmit Signaling 6 3C R Receive Signaling 13

46 R/W Transmit Signaling 7 3D R Receive Signaling 14

47 R/W Transmit Signaling 8 3E R Receive Signaling 15

48 R/W Transmit Signaling 9 3F R Receive Signaling 16

49 R/W Transmit Signaling 10 4A R/W Transmit Signaling 11 4B R/W Transmit Signaling 12 4C R/W Transmit Signaling 13 4D R/W Transmit Signaling 14 4E R/W Transmit Signaling 15

4F R/W Transmit Signaling 16

Note: Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure proper operation.

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DS2153Q

3 PARALLEL PORT

The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14 for more details. The multiplexed bus on the DS2153Q saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS

WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or

RD pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions

high in Intel timing or as DS transitions low in Motorola timing.

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DS2153Q

4 CONTROL AND TEST REGISTERS

The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2), and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described in this section. The LICR is described in Section 13.

The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On powerup, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.

RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)

(MSB) (LSB)

RSMF RSM RSIO — — FRC SYNCE RESYNC

SYMBOL

RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is

RSM RCR1.6 RSYNC Mode Select.

RSIO RCR1.5 RSYNC I/O Select.

— RCR1.4 Not Assigned. Should be set to 0 when written.

— RCR1.3 Not Assigned. Should be set to 0 when written.

FRC RCR1.2 Frame Resync Criteria.

SYNCE RCR1.1 Sync Enable.

RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated. Must

POSITION NAME AND DESCRIPTION

programmed in the multiframe mode (RCR1.6 = 1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries

0 = frame mode (see the timing in Section 14) 1 = multiframe mode (see the timing in Section 14)

0 = RSYNC is an output (depends on RCR1.6) 1 = RSYNC is an input (only valid if elastic store enabled) (Note: this bit must be set to 0 when RCR2.1 = 0)

0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times

0 = auto resync enabled 1 = auto resync disabled

be cleared and set again for a subsequent resync.

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Table 4-1. Sync/Resync Criteria

FRAME OR

MULTIFRAME

SYNC CRITERIA RESYNC CRITERIA ITU SPEC

LEVEL

DS2153Q

FAS

CRC4

CAS

FAS present in frames N and N + 2, and FAS not present in frame N + 1.

Two valid MF alignment words found within 8ms.

Valid MF alignment word found and previous time slot 16 contains code other than all 0s.

Three consecutive incorrect FAS received.

Alternate (RCR1.2 = 1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received.

915 or more CRC4 codewords out of 1000 received in error.

Two consecutive MF alignment words received in error.

G.706

4.1.1

4.1.2

G.706

4.2

4.3.2

G.732

5.2

RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE —

SYMBOL

Sa8S RCR2.7 Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;

Sa7S RCR2.6 Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;

Sa6S RCR2.5 Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;

Sa5S RCR2.4 Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;

Sa4S RCR2.3 Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;

RSCLKM RCR2.2 Receive Side SYSCLK Mode Select.

RESE RCR2.1 Receive Side Elastic Store Enable.

— RCR2.0 Not Assigned. Should be set to 0 when written.

POSITION NAME AND DESCRIPTION

set to 0 to not report the Sa8 bit.

set to 0 to not report the Sa7 bit.

set to 0 to not report the Sa6 bit.

set to 0 to not report the Sa5 bit.

set to 0 to not report the Sa4 bit.

0 = if SYSCLK is 1.544MHz 1 = if SYSCLK is 2.048MHz

0=elastic store is bypassed 1=elastic store is enabled

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DS2153Q

TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex)

(MSB) (LSB)

— TFPT T16S TUA1 TSiS TSA1 TSM TSIO

SYMBOL

— TCR1.7 Not Assigned. Should be set to 0 when written to.

TFPT TCR1.6

T16S TCR1.5

TUA1 TCR1.4

TSiS TCR1.3

TSA1 TCR1.2

TSM TCR1.1

TSIO TCR1.0

Note: For details about how the Transmit Control Registers affect the operation of the DS2153Q, see

Figure 14-9.

POSITION NAME AND DESCRIPTION

Transmit Time Slot 0 Pass Through.

0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

Transmit Time Slot 16 Data Select. 0 = sample time slot 16 at TSER pin 1 = source time slot 16 from TS1 to TS16 registers

Transmit Unframed All Ones. 0 = transmit data normally 1 = transmit an unframed all ones code at TPOS and TNEG

Transmit International Bit Select. 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0)

Transmit Signaling All Ones. 0 = normal operation 1 = force time slot 16 in every frame to all ones

TSYNC Mode Select. 0 = frame mode (see the timing in Section 14 1 = CAS and CRC4 multiframe mode (see the timing in Section 14)

TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output

)

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DS2153Q

TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S — AEBE P16F

SYMBOL

Sa8S TCR2.7 Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK

Sa7S TCR2.6 Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK

Sa6S TCR2.5 Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK

Sa5S TCR2.4 Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK

Sa4S TCR2.3 Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK

— TCR2.2 Not Assigned. Should be set to 0 when written.

AEBE TCR2.1

P16F TCR2.0

POSITION NAME AND DESCRIPTION

pin; set to 0 to not source the Sa8 bit.

pin; set to 0 to not source the Sa7 bit.

pin; set to 0 to not source the Sa6 bit.

pin; set to 0 to not source the Sa5 bit.

pin; set to 0 to not source the Sa4 bit.

Automatic E-Bit Enable. 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction

Function of Pin 16. 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC)

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DS2153Q

CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)

(MSB) (LSB)

FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4

SYMBOL

FLB CCR1.7

THDB3 CCR1.6

TG802 CCR1.5 Transmit G.802 Enable. See Figure 14-7

TCRC4 CCR1.4

RSM CCR1.3

RHDB3 CCR1.2 Receive HDB3 Enable.

RG802 CCR1.1 Receive G.802 Enable. See Figure 14-7

RCRC4 CCR1.0

POSITION NAME AND DESCRIPTION

Framer Loopback.

0 = loopback disabled 1 = loopback enabled

Transmit HDB3 Enable. 0 = HDB3 disabled 1 = HDB3 enabled

for details. 0 = do not force TCHBLK high during bit 1 of time slot 26 1 = force TCHBLK high during bit 1 of time slot 26

Transmit CRC4 Enable. 0 = CRC4 disabled 1 = CRC4 enabled

Receive Signaling Mode Select. 0 = CAS signaling mode 1 = CCS signaling mode

0 = HDB3 disabled 1 = HDB3 enabled

for details. 0 = do not force RCHBLK high during bit 1 of time slot 26 1 = force RCHBLK high during bit 1 of time slot 26

Receive CRC4 Enable. 0 = CRC4 disabled 1 = CRC4 enabled

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DS2153Q

CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex)

(MSB) (LSB)

ECUS VCRFS AAIS ARA RSERC LOTCMC RLB LLB

SYMBOL

ECUS CCR2.7

VCRFS CCR2.6

AAIS CCR2.5

ARA CCR2.4

RSERC CCR2.3

LOTCMC CCR2.2 Loss of Transmit Clock Mux Control. Determines whether the

RLB CCR2.1

LLB CCR2.0

POSITION NAME AND DESCRIPTION

Error Counter Update Select.

0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames)

VCR Function Select. 0 = count Bipolar Violations (BPVs) 1 = count Code Violations (CVs)

Automatic AIS Generation. 0 = disabled 1 = enabled

Automatic Remote Alarm Generation. 0 = disabled 1 = enabled

RSER Control. 0 = allow RSER to output data as received under all conditions 1 = force RSER to 1 under loss of frame alignment conditions

transmit side formatter should switch to the ever present RCLK if the TCLK should fail to transition (see Figure 1-1). 0 = do not switch to RCLK if TCLK stops 1 = switch to RCLK if TCLK stops

Remote Loopback. 0 = loopback disabled 1 = loopback enabled

Local Loopback. 0 = loopback disabled 1 = loopback enabled

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DS2153Q

CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)

(MSB) (LSB)

TESE TCBFS TIRFS ESR LIRST — TSCLKM —

SYMBOL

TESE CCR3.7

TCBFS CCR3.6

TIRFS CCR3.5

ESR CCR3.4 Elastic Stores Reset. Setting this bit from a 1 to a 0 will force

LIRST CCR3.3 Line Interface Reset. Setting this bit from a 0 to a 1 will initiate

— CCR3.2 Not Assigned. Should be set to 0 when written.

TSCLKM CCR3.1 Transmit Backplane Clock Select. Must be set like RCR2.2.

— CCR3.0 Not Assigned. Should be set to 0 when written.

POSITION NAME AND DESCRIPTION

Transmit Elastic Store Enable.

0 = elastic store is disabled 1 = elastic store is enabled

Transmit Channel Blocking Registers (TCBR) Function Select.

0 = TCBRs define the operation of the TCHBLK output pin 1 = TCBRs define which signaling bits are to be inserted

Transmit Idle Registers (TIR) Function Select. 0 = TIRs define in which channels to insert idle code 1 = TIRs define in which channels to insert data from RSER

the elastic stores to a known depth. Should be toggled after SYSCLK has been applied and is stable. Must be set and cleared again for a subsequent reset. Do not leave this bit set high.

an internal reset that affects the slicer, AGC, clock recovery state machine, and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset.

0 = 1.544MHz 1 = 2.048MHz

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DS2153Q

4.1 Local Loopback

When CCR2.0 is set to a 1, the DS2153Q will be forced into Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. See Figure 1-1

for more details.

4.2 Remote Loopback

When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote Loopback (RLB). In this loopback, data recovered off the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line (with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be ignored. Data in this loopback will pass through the jitter attenuator. See Figure 1-1

for more details.

4.3 Framer Loopback

When CCR1.7 is set to a 1, the DS2153Q will enter a Framer Loopback (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur:

1) Data will be transmitted at TTIP and TRING.

2) Data off the E1 line at RTIP and RRING will be ignored.

The RCLK output will be replaced with the TCLK input.

4.4 Automatic Alarm Generation

When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the DS2153Q will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1 at the same time.

4.5 Power-Up Sequence

On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to all of the internal registers (this includes setting the Test Register) since the contents of the internal registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the line interface circuitry (it will take the DS2153Q about 40ms to recover from the LIRST being toggled). Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0 (this step can be skipped if the elastic stores are disabled).

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5 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real-time status of the DS2153Q: Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion (except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again or if the alarm is still present.

The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register will be updated with current value and it will be cleared. When a 0 is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically ANDed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS2153Q with higher-order software languages.

The SSR register operates differently than the other three. It is a read-only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2 pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2), respectively.

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