32-Bit or 128-Bit Jitter Attenuator
Generates Line Build-Outs for Both 120Ω
and 75Ω Lines
Frames to FAS, CAS, and CRC4 Formats
Dual On-Board Two-Frame Elastic Store Slip
Buffers That can Connect to Backplanes Up
to 8.192MHz
8-Bit Parallel Control Port That can be Used
on Either Multiplexed or Nonmultiplexed
Buses
Extracts and Inserts CAS Signaling
Detects and Generates Remote and AIS
Alarms
Programmable Output Clocks for Fractional
E1, H0, and H12 Applications
Fully Independent Transmit and Receive
Functionality
Full Access to Both Si and Sa Bits
Three Separate Loopbacks for Testing
Large Counters for Bipolar and Code
Violations, CRC4 Codeword Errors, FAS
Errors, and E Bits
Pin Compatible with DS2151Q T1 Single-
Chip Transceiver
5V Supply; Low-Power CMOS
ORDERING INFORMATION
PART
DS2153Q
DS2153Q+
DS2153QN
DS2153QN+
TEMP
RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
+Denotes lead-free/RoHS-compliant package.
PINPACKAGE
44 PLCC
44 PLCC
44 PLCC
44 PLCC
DS2153Q
E1 Single-Chip Transceive
PIN CONFIGURATION
Dallas
DS2153Q
T1SCT
ALE(AS)
WR (R/W)
RLIN
RLCL
DVSS
RCL
RCHCL
RSE
RSYNC
RLOS/LOTC
SYSCL
FUNCTIONAL BLOCKS
FRAMER
HAUL LINE
INTERFACE
LONG & SHORT
PARALLEL CONTROL
PORT
ACTUAL SIZE OF 44-PIN PLCC
D(DS) AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
19
18
ACLKI
RCHBL
2
DS2153Q
20
21
22
23
BTS
RTIP
RVDD
RRING
44
24
RVSS
43
42
25
26
XTAL1
XTAL2
PLCC
STORES
ELASTIC
TCHCLK
40
41
39
38
37
36
35
34
33
32
31
30
29
27
28
INT
INT
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
Table 15-3. DC Characteristics ................................................................................................................52
Table 16-1. AC Characteristics—Parallel Port .........................................................................................53
Table 16-2. AC Characteristics—Receive Side........................................................................................ 56
Table 16-3. AC Characteristics—Transmit Side....................................................................................... 58
3 of 60
DS2153Q
1 DETAILED DESCRIPTION
The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1
lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial
stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.
The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board
jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a
set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access
via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the
latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,
300 233, TBR 12 and TBR 13.
1.1 Introduction
The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of
the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2153Q is totally independent from the receive side in both the clock
requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1
transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation
mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP
and TRING pins via a coupling transformer.
1.2 Reader’s Note
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.
These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is
identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made
up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB
and is transmitted last. Throughout this data sheet, the following abbreviations are used:
FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International Bits
CRC4 Cyclical Redundancy Check
CCS Common Channel Signaling
Sa Additional bits
E-bit CRC4 Error bits
4 of 60
Figure 1-1. DS2153Q Block Diagram
DS2153Q
5 of 60
2 PIN DESCRIPTION
PIN NAME TYPE FUNCTION
1–4,
41–44
5
6
7 ALE(AS) I
8
9 RLINK O
10 RLCLK O
11 DVSS — Digital Signal Ground. 0.0V. Should be tied to local ground plane.
12 RCLK O Receive Clock. Recovered 2.048MHz clock.
13 RCHCLK O
14 RSER O
15 RSYNC I/O
16 RLOS/LOTC O
17 SYSCLK I
18 RCHBLK O
19 ACLKI I
AD4–AD7,
AD0–AD3
RD (DS)
CS
WR (R/ W )
I/O Address/Data Bus. An 8-bit multiplexed address/data bus.
I
Active-Low Read Input (Data Strobe)
I Active-Low Chip Select. Must be low to read or write the port.
Address Latch Enable (Address Strobe). A positive going edge
serves to demultiplex the bus.
I
Active-Low Write Input (Read/Write)
Receive Link Data. Outputs the full receive data stream including the
Sa bits. See Section 14
for timing details.
Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK
output. Controlled by RCR2. See Section 14
for timing details.
Receive Channel Clock. 256kHz clock that pulses high during the
LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 14
for timing details.
Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin, which identifies either frame (RCR1.6 = 0) or multiframe
boundaries (RCR1.6 = 1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 14
for timing
details.
Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0 = 0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle
high if the TCLK pin has not toggled for 5µs. System Clock. 1.544MHz or 2.048MHz clock. Only used when the
elastic store functions are enabled via either RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100µs, will force all output pins (including the parallel port) to
tri-state.
Receive Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14
timing details.
Alternate Clock Input. Upon a receive carrier loss, the clock applied
at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS via a 1kΩ
resistor.
DS2153Q
for
6 of 60
PIN NAME TYPE FUNCTION
Bus Type Select. Strap high to select Motorola bus timing; strap low to
20 BTS I
select Intel bus timing. This pin controls the function of the
ALE(AS), and
WR (R/ W ) pins. If BTS = 1, then these pins assume the
function listed in parentheses ().
21, 22
RTIP,
RRING
—
23 RVDD —
Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section 13
for details).
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and
TVDD pins.
24 RVSS — Receive Signal Ground. 0V. Should be tied to local ground plane.
25, 26
27
28
XTAL1,
XTAL2
INT1
INT2
—
O
O
29 TTIP —
Crystal Connections. A pullable 8.192MHz crystal must be applied to
these pins. See Section 13
for crystal specifications.
Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain output.
Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
Transmit Tip. Analog line driver output; connects to a step-up
transformer (see Section 13
for details).
30 TVSS — Transmit Signal Ground. 0V. Should be tied to local ground plane.
31 TVDD —
32 TRING —
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and
RVDD pins.
Transmit Ring. Analog line driver outputs; connects to a step-up
transformer (see Section 13
for details).
Transmit Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
33 TCHBLK O
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14
timing details.
34 TLCLK O
35 TLINK I
Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK
input. Controlled by TCR2. See Section 14
for timing details.
Transmit Link Data. If enabled, this pin will be sampled on the falling
edge of TCLK to insert the Sa bits. See Section 14
for timing details.
Transmit Sync. A pulse at this pin will establish either frame or
36 TSYNC I/O
37 DVDD —
multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q
can be programmed to output either a frame or multiframe pulse at this
pin. See Section 14
for timing details.
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD
pins.
38 TCLK I Transmit Clock. 2.048MHz primary clock.
39 TSER I
Transmit Serial Data. Transmit NRZ serial data, sampled on the
falling edge of TCLK.
Transmit Channel Clock. 256kHz clock that pulses high during the
40 TCHCLK O
LSB of each channel. Useful for parallel to serial conversion of channel
data. See Section 14
for timing details.
DS2153Q
RD (DS),
for
7 of 60
DS2153Q
2.1 DS2153Q Register Map
ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME
00 R BPV or Code Violation Count 1 20 R/W Transmit Align Frame
01 R BPV or Code Violation Count 2 21 R/W Transmit Non-Align Frame
02 R CRC4 Count 1/FAS Error Count 1 22 R/W Transmit Channel Blocking 1
03 R CRC4 Error Count 2 23 R/W Transmit Channel Blocking 2
04 R E-Bit Count 1/FAS Error Count 2 24 R/W Transmit Channel Blocking 3
05 R E-Bit Count 2 25 R/W Transmit Channel Blocking 4
06 R Status 1 26 R/W Transmit Idle 1
07 R Status 2 27 R/W Transmit Idle 2
08 R/W Receive Information 28 R/W Transmit Idle 3
10 R/W Receive Control 1 29 R/W Transmit Idle 4
11 R/W Receive Control 2 2A R/W Transmit Idle Definition
12 R/W Transmit Control 1 2B R/W Receive Channel Blocking 1
13 R/W Transmit Control 2 2C R/W Receive Channel Blocking 2
14 R/W Common Control 1 2E R/W Receive Channel Blocking 3
15 R/W Test 1 2E R/W Receive Channel Blocking 4
16 R/W Interrupt Mask 1 2F R Receive Align Frame
17 R/W Interrupt Mask 2 30 R Receive Signaling 1
18 R/W Line Interface Control 31 R Receive Signaling 2
19 R/W Test 2 32 R Receive Signaling 3
1A R/W Common Control 2 33 R Receive Signaling 4
1B R/W Common Control 3 34 R Receive Signaling 5
1E R Synchronizer Status 35 R Receive Signaling 6
1F R Receive Non-Align Frame 36 R Receive Signaling 7
40 R/W Transmit Signaling 1 37 R Receive Signaling 8
41 R/W Transmit Signaling 2 38 R Receive Signaling 9
42 R/W Transmit Signaling 3 39 R Receive Signaling 10
43 R/W Transmit Signaling 4 3A R Receive Signaling 11
44 R/W Transmit Signaling 5 3B R Receive Signaling 12
45 R/W Transmit Signaling 6 3C R Receive Signaling 13
46 R/W Transmit Signaling 7 3D R Receive Signaling 14
47 R/W Transmit Signaling 8 3E R Receive Signaling 15
48 R/W Transmit Signaling 9 3F R Receive Signaling 16
Note: Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure
proper operation.
8 of 60
DS2153Q
3 PARALLEL PORT
The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external
microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14
for more details. The multiplexed bus on the DS2153Q saves pins because the address information and
data information share the same signal paths. The addresses are presented to the pins in the first portion of
the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses
must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from
the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS
or
WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or
RD pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions
high in Intel timing or as DS transitions low in Motorola timing.
9 of 60
DS2153Q
4 CONTROL AND TEST REGISTERS
The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers
are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the
control registers only need to be accessed when there is a change in the system configuration. There are
two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),
and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described
in this section. The LICR is described in Section 13.
The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On powerup, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)
(MSB) (LSB)
RSMF RSM RSIO — — FRC SYNCE RESYNC
SYMBOL
RSMF RCR1.7 RSYNC Multiframe Function. Only used if the RSYNC pin is
RSM RCR1.6 RSYNC Mode Select.
RSIO RCR1.5 RSYNC I/O Select.
— RCR1.4 Not Assigned. Should be set to 0 when written.
— RCR1.3 Not Assigned. Should be set to 0 when written.
FRC RCR1.2 Frame Resync Criteria.
SYNCE RCR1.1 Sync Enable.
RESYNC RCR1.0 Resync. When toggled from low to high, a resync is initiated. Must
POSITION NAME AND DESCRIPTION
programmed in the multiframe mode (RCR1.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
0 = frame mode (see the timing in Section 14)
1 = multiframe mode (see the timing in Section 14)
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled) (Note:
this bit must be set to 0 when RCR2.1 = 0)
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
0 = auto resync enabled
1 = auto resync disabled
be cleared and set again for a subsequent resync.
10 of 60
Table 4-1. Sync/Resync Criteria
FRAME OR
MULTIFRAME
SYNC CRITERIA RESYNC CRITERIA ITU SPEC
LEVEL
DS2153Q
FAS
CRC4
CAS
FAS present in frames N
and N + 2, and FAS not
present in frame N + 1.
Two valid MF alignment
words found within 8ms.
Valid MF alignment word
found and previous time slot
16 contains code other than
all 0s.
Three consecutive incorrect FAS received.
Alternate (RCR1.2 = 1) the above criteria
is met or three consecutive incorrect bit 2
of non-FAS received.
915 or more CRC4 codewords out of 1000
received in error.
Two consecutive MF alignment words
received in error.
G.706
4.1.1
4.1.2
G.706
4.2
4.3.2
G.732
5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB) (LSB)
Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE —
SYMBOL
Sa8S RCR2.7 Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;
Sa7S RCR2.6 Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;
Sa6S RCR2.5 Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;
Sa5S RCR2.4 Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;
Sa4S RCR2.3 Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;
RSCLKM RCR2.2 Receive Side SYSCLK Mode Select.
RESE RCR2.1 Receive Side Elastic Store Enable.
— RCR2.0 Not Assigned. Should be set to 0 when written.
POSITION NAME AND DESCRIPTION
set to 0 to not report the Sa8 bit.
set to 0 to not report the Sa7 bit.
set to 0 to not report the Sa6 bit.
set to 0 to not report the Sa5 bit.
set to 0 to not report the Sa4 bit.
0 = if SYSCLK is 1.544MHz
1 = if SYSCLK is 2.048MHz
0=elastic store is bypassed
1=elastic store is enabled
11 of 60
DS2153Q
TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex)
(MSB) (LSB)
— TFPT T16S TUA1 TSiS TSA1 TSM TSIO
SYMBOL
— TCR1.7 Not Assigned. Should be set to 0 when written to.
TFPT TCR1.6
T16S TCR1.5
TUA1 TCR1.4
TSiS TCR1.3
TSA1 TCR1.2
TSM TCR1.1
TSIO TCR1.0
Note: For details about how the Transmit Control Registers affect the operation of the DS2153Q, see
Figure 14-9.
POSITION NAME AND DESCRIPTION
Transmit Time Slot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
Transmit Time Slot 16 Data Select.
0 = sample time slot 16 at TSER pin
1 = source time slot 16 from TS1 to TS16 registers
Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all ones code at TPOS and TNEG
Transmit International Bit Select.
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
Transmit Signaling All Ones.
0 = normal operation
1 = force time slot 16 in every frame to all ones
TSYNC Mode Select.
0 = frame mode (see the timing in Section 14
1 = CAS and CRC4 multiframe mode (see the timing in Section 14)
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
)
12 of 60
DS2153Q
TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex)
(MSB) (LSB)
Sa8S Sa7S Sa6S Sa5S Sa4S — AEBE P16F
SYMBOL
Sa8S TCR2.7 Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK
Sa7S TCR2.6 Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK
Sa6S TCR2.5 Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK
Sa5S TCR2.4 Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK
Sa4S TCR2.3 Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK
— TCR2.2 Not Assigned. Should be set to 0 when written.
AEBE TCR2.1
P16F TCR2.0
POSITION NAME AND DESCRIPTION
pin; set to 0 to not source the Sa8 bit.
pin; set to 0 to not source the Sa7 bit.
pin; set to 0 to not source the Sa6 bit.
pin; set to 0 to not source the Sa5 bit.
pin; set to 0 to not source the Sa4 bit.
Automatic E-Bit Enable.
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
Function of Pin 16.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
13 of 60
DS2153Q
CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)
(MSB) (LSB)
FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4
SYMBOL
FLB CCR1.7
THDB3 CCR1.6
TG802 CCR1.5 Transmit G.802 Enable. See Figure 14-7
TCRC4 CCR1.4
RSM CCR1.3
RHDB3 CCR1.2 Receive HDB3 Enable.
RG802 CCR1.1 Receive G.802 Enable. See Figure 14-7
RSER Control.
0 = allow RSER to output data as received under all conditions
1 = force RSER to 1 under loss of frame alignment conditions
transmit side formatter should switch to the ever present RCLK
if the TCLK should fail to transition (see Figure 1-1).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
Local Loopback.
0 = loopback disabled
1 = loopback enabled
15 of 60
DS2153Q
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB) (LSB)
TESE TCBFS TIRFS ESR LIRST — TSCLKM —
SYMBOL
TESE CCR3.7
TCBFS CCR3.6
TIRFS CCR3.5
ESR CCR3.4 Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
LIRST CCR3.3 Line Interface Reset. Setting this bit from a 0 to a 1 will initiate
— CCR3.2 Not Assigned. Should be set to 0 when written.
TSCLKM CCR3.1 Transmit Backplane Clock Select. Must be set like RCR2.2.
— CCR3.0 Not Assigned. Should be set to 0 when written.
POSITION NAME AND DESCRIPTION
Transmit Elastic Store Enable.
0 = elastic store is disabled
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be set and cleared
again for a subsequent reset. Do not leave this bit set high.
an internal reset that affects the slicer, AGC, clock recovery state
machine, and jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent
reset.
0 = 1.544MHz
1 = 2.048MHz
16 of 60
DS2153Q
4.1 Local Loopback
When CCR2.0 is set to a 1, the DS2153Q will be forced into Local Loopback (LLB). In this loopback,
data will continue to be transmitted as normal through the transmit side of the SCT. Data being received
at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator. See Figure 1-1
for more details.
4.2 Remote Loopback
When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote Loopback (RLB). In this loopback,
data recovered off the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line
(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to
pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be
ignored. Data in this loopback will pass through the jitter attenuator. See Figure 1-1
for more details.
4.3 Framer Loopback
When CCR1.7 is set to a 1, the DS2153Q will enter a Framer Loopback (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted at TTIP and TRING.
2) Data off the E1 line at RTIP and RRING will be ignored.
The RCLK output will be replaced with the TCLK input.
4.4 Automatic Alarm Generation
When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of
the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
DS2153Q will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be
transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1
at the same time.
4.5 Power-Up Sequence
On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to
all of the internal registers (this includes setting the Test Register) since the contents of the internal
registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the
line interface circuitry (it will take the DS2153Q about 40ms to recover from the LIRST being toggled).
Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0
(this step can be skipped if the elastic stores are disabled).
17 of 60
DS2153Q
5 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real-time status of the DS2153Q:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically ANDed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2153Q with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2),
respectively.
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DS2153Q
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB) (LSB)
TESF TESE JALT RESF RESE CRCRC FASRC CASRC
SYMBOL
TESF RIR.7 Transmit Elastic Store Full. Set when the elastic store fills and
TESE RIR.6 Transmit Elastic Store Empty. Set when the elastic store
JALT RIR.5 Jitter Attenuator Limit Trip. Set when the jitter attenuator
RESF RIR.4 Elastic Store Full. Set when the elastic store buffer fills and a
RESE RIR.3 Elastic Store Empty. Set when the elastic store buffer empties
CRCRC RIR.2 CRC Resync Criteria Met. Set when 915/1000 codewords are
FASRC RIR.1 FAS Resync Criteria Met. Set when three consecutive FAS
CASRC RIR.0 CAS Resync Criteria Met. Set when two consecutive CAS MF
POSITION NAME AND DESCRIPTION
a frame is deleted.
empties and a frame is repeated.
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
frame is deleted.
and a frame is repeated.
received in error.
words are received in error.
alignment words are received in error.
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DS2153Q
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)
(MSB) (LSB)
CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA
SYMBOL
POSITION NAME AND DESCRIPTION
CSC5 SSR.7 CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4 SSR.6
CRC4 Sync Counter Bit 4.
CSC3 SSR.5
CRC4 Sync Counter Bit 3.
CSC2 SSR.4
CRC4 Sync Counter Bit 2.
CSC0 SSR.3 CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next
to LSB bit is not accessible. This bit will toggle each time the
CRC4 MF search times out at 8ms.
FASSA SSR.2 FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CASSA SSR.1 CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4SA SSR.0 CRC4 MF Sync Active. Set while the synchronizer is searching
for the CRC4 MF alignment word.
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is
cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the
amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of
CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then
the search should be abandoned and proper action taken. The CRC4 sync counter will rollover.
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DS2153Q
SR1: STATUS REGISTER 1 (Address = 06 Hex)
(MSB) (LSB)
RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS
SYMBOL
RSA1 SR1.7 Receive Signaling All 1s. Set when the contents of time slot 16
RDMA SR1.6 Receive Distant MF Alarm. Set when bit 6 of time slot 16 in
RSA0 SR1.5 Receive Signaling All 0s. Set when over a full MF, time slot 16
RSLIP SR1.4 Receive Elastic Store Slip Occurrence. Set when the elastic store
RUA1 SR1.3 Receive Unframed All 1s. Set when an unframed all 1s code is
RRA SR1.2 Receive Remote Alarm. Set when a remote alarm is received at
RCL SR1.1 Receive Carrier Loss. Set when 255 consecutive 0s have been
RLOS SR1.0 Receive Loss of Sync. Set when the device is not synchronized to
POSITION NAME AND DESCRIPTION
contains less than three 0s over 16 consecutive frames. This alarm
is not disabled in the CCS signaling mode.
frame 0 has been set for two consecutive multiframes. This alarm
is not disabled in the CCS signaling mode.
contains all 0s.
has either repeated or deleted a frame of data.
received at RTIP and RRING.
RTIP and RRING.
detected at RTIP and RRING.
the receive E1 stream.
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Table 5-1. Alarm Set and Clear Criteria
DS2153Q
ALARM SET CRITERIA CLEAR CRITERIA
RSA1
(receive signaling
all 1s)
RSA0
(receive signaling
all 0s)
RDMA
(receive distant
Over 16 consecutive frames (one full
MF) time slot 16 contains less than
three 0s
Over 16 consecutive frames (one full
MF) time slot 16 contains all 0s
Bit 6 in time slot 16 of frame 0 set to
1 for two consecutive MF
Over 16 consecutive frames (one full
MF) time slot 16 contains three or more
0s
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single 1
Bit 6 in time slot 16 of frame 0 set to 0
for a two consecutive MF
multiframe alarm)
RUA1
(receive unframed
Less than three 0s in two frames
(512 bits)
More than two 0s in two frames (512
bits)
all 1s)
RRA
(receive remote
Bit 3 of non-align frame set to 1 for
three consecutive occasions
Bit 3 of non-align frame set to 0 for
three consecutive occasions
alarm)
RCL
(receive carrier
255 consecutive 0s received In 255-bit times, at least 32 1s are
received
loss)
CCITT
SPEC.
G.732
4.2
G.732
5.2
O.162
2.1.5
O.162
1.6.1.2
O.162
2.1.4
G.775
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DS2153Q
SR2: STATUS REGISTER 2 (Address = 07 Hex)
(MSB) (LSB)
RMF RAF TMF SEC TAF LOTC RCMF TSLIP
SYMBOL
RMF SR2.7 Receive CAS Multiframe. Set every 2ms (regardless if CAS
RAF SR2.6 Receive Align Frame. Set every 250ms at the beginning of align
TMF SR2.5
SEC SR2.4 1-Second Timer. Set on increments of 1 second based on RCLK. If
TAF SR2.3
LOTC SR2.2 Loss of Transmit Clock. Set when the TCLK pin has not
RCMF SR2.1 Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries;
TSLIP SR2.0 Transmit Elastic Store Slip. Set when the elastic store has either
POSITION NAME AND DESCRIPTION
signaling is enabled or not) on receive multiframe boundaries. Used
to alert the host that signaling data is available.
frames. Used to alert the host that Si and Sa bits are available in the
RAF and RNAF registers.
Transmit Multiframe. Set every 2µs (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the host
that signaling data needs to be updated.
CCR2.7 = 1, then this bit will be set every 62.5ms instead of once a
second.
Transmit Align Frame. Set every 250µs at the beginning of align
frames. Used to alert the host that the TAF and TNAF registers
need to be updated.
transitioned for one channel time (or 3.9µs). Will force pin 16 high
if enabled via TCR2.0. Based on RCLK.
will continue to be set every 2ms on an arbitrary boundary if CRC4
is disabled.
There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4
SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either 1-second boundaries (CCR2.7 = 0) or every 62.5ms
(CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5ms. The user can use the interrupt
from the timer to determine when to read these registers. The user has a full second (or 62.5ms) to read
the counters before the data is lost.
6.1 BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either Bipolar Violations (BPVs) or Code Violations (CVs). If CCR2.6 = 0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 codewords
are not counted as BPVs. If CCR2.6 = 1, then the VCR counts code violations as defined in CCITT
O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most
applications, the DS2153Q should be programmed to count BPVs when receiving AMI code and to count
CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync
conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would
have to be greater than 10**-2 before the VCR would saturate.
V15 VCR1.7 MSB of the 16-bit bipolar or code violation count.
V0 VCR2.0 LSB of the 16-bit bipolar or code violation count.
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DS2153Q
6.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
Note: The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.
(See note) (See note) (See note) (See note) (See note)
POSITION NAME AND DESCRIPTION
CRC9 CRC8 CRCCR1
6.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
(See note)(See note)(See note)(See note)(See note)(See note)
EB9 EB8 EBCR1
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 EBCR2
SYMBOL
POSITION NAME AND DESCRIPTION
EB9 EBCR1.1 MSB of the 10-bit E-bit count.
EB0 EBCR2.0 LSB of the 10-bit E-bit count.
Note: The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
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DS2153Q
6.4 FAS Bit Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is
disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error
count in a 1-second period is 4000, this counter cannot saturate.
FASCR1: FAS BIT COUNT REGISTER 1 (Address = 02 Hex)
FASCR2: FAS BIT COUNT REGISTER 2 (Address = 04 Hex)
Note 1: The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter.
Note 2: The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter.
POSITION NAME AND DESCRIPTION
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DS2153Q
7 Sa DATA LINK CONTROL AND OPERATION
The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit
positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and
TNAF) or via two external pins (RLINK and TLINK).
On the receive side, the Sa bits are always reported in the internal RNAF register (see Section 12 for more
details). All five Sa bits are always output at the RLINK pin. See Section 14 for detailed timing. Via
RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the
user to create a clock that can be used to capture the needed Sa bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register
(TCR1.6 = 0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source
any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through
the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via
the TLINK pin and the TLINK pin should be tied to the TSER pin. See the timing diagrams and the
transmit data flow diagram in Section 14 for examples.
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DS2153Q
8 SIGNALING OPERATION
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parentheses are the channel associated with a
particular signaling bit. The channel numbers have been assigned as described in the ITU documents. For
example, channel 1 is associated with time slot 1 and channel 30 is associated with time slot 31. There is
a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to
TS16). The signaling registers are detailed below.
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex)
Remote Alarm Bit (integrated and reported in SR1.6)
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been
loaded with data. The user has 2ms to retrieve the data before it is lost.
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DS2153Q
TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address = 40 to 4F Hex)
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two time slots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the
DS2153Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift
register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2
(SR2.5) to know when to update the signaling bits. The bit will be set every 2ms and the user has 2ms to
update the TSRs before the old data will be retransmitted.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000, or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a 1. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to 1. In CCS signaling
mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2ms to load the data
before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit
Channel Blocking Registers (TCBRs) to determine on a channel by channel basis which signaling bits are
to be inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from
the TSER pin (the corresponding bit in the TCBRs = 0). See the Transmit Data Flow diagram in
Section 14 for more details.
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DS2153Q
9 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS2153Q that can be used to custom tailor the data that is to be
transmitted onto the E1 line, on a channel-by-channel basis. Each of the 32 E1 channels can be forced to
have a user-defined idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1 (26)
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2 (27)
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3 (28)
CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TIR4 (29)
SYMBOL POSITION NAME AND DESCRIPTION
CH32 TIR4.7
Transmit Idle Registers.
0 = do not insert the Idle Code into this channel
CH1 TIR1.0 1 = insert the Idle Code into this channel
Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be
sourced from the RSER pin.
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represents a time slot in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via
the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel-by-channel basis, if data
from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding
bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the
TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow
diagram in Section 14 for more details.
MSB of the Idle Code
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DS2153Q
10 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either
high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in
Section 14 for an example. The TCBRs have an alternate mode of use. Via the CCR3.6 bit, the user has
the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be
inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the
TSER pin (the corresponding bit in the TCBR = 0). See the Transmit Data Flow diagram in Section 14
for more details.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address = 2B to 2E Hex)
Note: If CCR3.6 = 1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1 implies that signaling data for
that channel is to be sourced from the Transmit Signaling (TS) registers.
0 = force the TCHBLK pin to remain low during this
channel time
1 = force the TCHBLK pin high during this channel time
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DS2153Q
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1
(MSB) (LSB)
CH20 CH4 CH19 CH3 CH18 CH2 CH17* CH1* TCBR1
CH24 CH8 CH23 CH7 CH22 CH6 CH21 CH5 TCBR2
CH28 CH12 CH27 CH11 CH26 CH10 CH25 CH9 TCBR3
CH32 CH16 CH31 CH15 CH30 CH14 CH29 CH13 TCBR4
*CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote
Alarm bits.
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DS2153Q
11 ELASTIC STORES OPERATION
The DS2153Q has an on-board two-frame (512 bits) elastic store. This elastic store can be enabled via
RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544MHz
(RCR2.2 = 0) or 2.048MHz (RCR2.2 = 1) clock at the SYSCLK pin. If the elastic store is enabled, then
the user has the option of either providing a frame sync at the RSYNC pin (RCR1.5 = 1) or having the
RSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5 = 0). If the user wishes to
obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses
occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544MHz
clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted
(forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will
be deleted. Also, in 1.544MHz applications, the RCHBLK output will not be active in channels 25
through 32 (or in other words, RCBR4 is not active). See Section 14 for more details. If the 512-bit
elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of
data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to 1. If the buffer fills,
then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to 1.
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DS2153Q
12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive
side, the RAF and RNAF registers will always report the data as it received in the Additional and
International bit locations. The RAF and RNAF registers are updated with the setting of the Receive
Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the
RAF and RNAF registers. It has 250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa
bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. See the register
descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 14 for more details.
The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and
data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of
these three sections is controlled by the Line Interface Control Register (LICR), which is described
below.
LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)
(MSB) (LSB)
LB2 LB1 LB0 EGL JAS JABDS DJA TPD LICR
SYMBOL POSITION NAME AND DESCRIPTION
LB2 LICR.7 Line Build-Out Select Bit 2. Sets the transmitter build
out; see the Table 13-2.
LB1 LICR.6 Line Build-Out Select Bit 1. Sets the transmitter build
out; see the Table 13-2.
LB0 LICR.5 Line Build-Out Select Bit 0. Sets the transmitter build
out; see the Table 13-2.
EGL LICR.4 Receive Equalizer Gain Limit.
0 = -12dB
1 = -30dB
JAS LICR.3
JABDS LICR.2
DJA LICR.1
TPD LICR.0
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP
and TRING pins
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DS2153Q
13.1 Receive Clock and Data Recovery
The DS2153Q contains a digital clock recovery system. See Figure 1-1 and Figure 13-1 for more details.
The DS2153Q couples to the receive E1 twisted pair or coax via a 1:1 transformer. See Table 13-3 for
transformer details. The DS2153Q automatically adjusts to the E1 signal being received at the RTIP and
RRING pins and can handle E1 twisted pair cables of 0.6mm (22 AWG) from 0 to 1.5km in length. The
crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses both edges of the clock from the PLL circuit to
form a 32 times oversampler that is used to recover the clock and data. This oversampling technique
offers outstanding jitter tolerance (see Figure 13-2).
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI waveform
presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive
Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or
from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to
determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to
prevent the device from falsely sensing a clock. See Table 13-1. If the jitter attenuator is either placed in
the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to
the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path
(as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty
cycle. See the receive AC timing characteristics in Section 16 for more details.
Table 13-1. Source of RCLK Upon RCL
ACLKI PRESENT?
RECEIVE SIDE JITTER
ATTENUATOR
Yes ACLKI via the jitter attenuator ACLKI
No Centered crystal TCLK via the jitter attenuator
TRANSMIT SIDE JITTER
ATTENUATOR
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DS2153Q
13.2 Transmit Waveshaping and Line Driving
The DS2153Q uses a set of laser-trimmed delay lines along with a precision digital-to-analog converter
(DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the
DS2153Q meet the ITU specifications. See Figure 13-3. The user will select which waveform is to be
generated by properly programming the L0 to L2 bits in the Line Interface Control Register (LICR). The
DS2153Q can set up in a number of various configurations depending on the application. See Table 13-2
and Figure 1-1.
Table 13-2. LBO Select in LICR
L2 L1 L0 APPLICATION TRANSFORMER
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 0
1 0 0
N.M. = not meaningful
75Ω normal
120Ω normal
75Ω normal with protection
resistors
120Ω normal with protection
resistors
75Ω with high return loss
75Ω with high return loss
120Ω with high return loss
1:1.15 step-up N.M. 0
1:1.15 step-up N.M. 0
1:1.15 step-up N.M. 8.2
1:1.15 step-up N.M. 8.2
1:1.15 step-up 21 27
1:1.36 step-up 21 18
1:1.36 step-up 21 27
RETURN LOSS
(dB)
Rt (Ω)
Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less than 0.005UI
P-P
broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms that they
create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1
transmit shielded twisted pair or coax via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 13-1.
For the devices to create the proper waveforms, the transformer used must meet the specifications listed
in Table 13-3.
Table 13-3. Transformer Specifications
SPECIFICATION RECOMMENDED VALUE
Turns Ratio
Primary Inductance
Leakage Inductance
1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%
600µH minimum
1.0µH maximum
Intertwining Capacitance 60pF maximum
DC Resistance
1.2Ω maximum
41 of 60
DS2153Q
13.3 Jitter Attenuator
The DS2153Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 13-4
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 13-4
connected to the XTAL1 and XTAL2 pins.
The jitter attenuator divides the clock provided by the 8.192MHz crystal at the XTAL1 and XTAL2 pins
to create an output clock that contains very little jitter. On-board circuitry will pull the crystal (by
switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming
E1 signal. If the incoming jitter exceeds either 120UI
(buffer depth is 128 bits) or 28UI
P-P
is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4
to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter
Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
Table 13-4. Crystal Selection Guidelines
PARAMETER SPECIFICATION
Parallel Resonant Frequency 8.192MHz
Mode Fundamental
Load Capacitance 18pF to 20pF (18.5pF nominal)
Tolerance
±50ppm
Pullability CL = 10pF, delta frequency = +175ppm to
+250ppm
CL = 45pF, delta frequency = -175ppm to -250ppm
Effective Series Resistance
30Ω maximum
Crystal Cut AT
. The jitter attenuator can be placed in
must be
(buffer depth
P-P
42 of 60
Figure 13-1. External Analog Connections
DS2153Q
NOTE 1: ALL RESISTOR VALUES ARE ±1%.
NOTE 2: THE R
OVERVOLTAGE.
NOTE 3: THE RR RESISTORS ARE USED TO TERMINATE THE RECEIVE E1 LINE.
NOTE 4: FOR 75Ω TERMINATION, R
NOTE 5: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE.
RESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS OR TO PROTECT THE DEVICE FROM
T
= 37.5Ω/FOR 12Ω TERMINATION RR = 60Ω.
R
43 of 60
Figure 13-2. Jitter Tolerance
DS2153Q
Figure 13-3. Transmit Waveform Template
44 of 60
Figure 13-4. Jitter Attenuation
DS2153Q
45 of 60
14 TIMING DIAGRAMS
Figure 14-1. Receive Side Timing
DS2153Q
NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0).
NOTE 2: RSYNC IN THE MULTIFRAME MODE (RCR1.6 = 1).
NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE Sa4 BIT.
NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE Sa BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.
NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS WITH THE FAS WORD.
Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled)
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 2: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 BITS.
NOTE 3: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 AND Sa8 BITS.
NOTE 4: RLINK IS PROGRAMMED TO OUTPUT THE Sa5 AND Sa7 BITS.
NOTE 5: SHOWN IS A NON-ALIGN FRAME BOUNDARY.
46 of 60
Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled
DS2153Q
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO
CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO 1).
NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 3: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
47 of 60
Figure 14-5. Transmit Side Timing
NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0).
NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1).
NOTE 3: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT.
NOTE 4: THIS DIAGRAM ASSEMBLES BOTH THE CAS MF AND THE CRC4 BEGIN WITH THE ALIGN FRAME.
Figure 14-6. Transmit Side Boundary Timing
DS2153Q
NOTE 1: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BITS.
NOTE 5: TLINK IS PROGRAMMED TO SOURCE THE SA7 AND SA8 BITS.
NOTE 6: SHOWN IS A NON-ALIGN FRAME BOUNDARY.
NOTE 7: SEE Figure 14-3 AND Figure 14-4 FOR DETAILS ON TIMING WITH THE TRANSMIT SIDE ELASTIC STORE ENABLED.
48 of 60
Figure 14-7. G.802 Timing
DS2153Q
NOTE 1: RCHBLK OR TCHBLK IS PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 TO 15, 17 TO 25, AND
DURING BIT 1 OF TIME SLOT 26.
49 of 60
Figure 14-8. Synchronization Flowchart
DS2153Q
50 of 60
Figure 14-9. Transmit Data Flow
DS2153Q
NOTE 1: TCLK MUST BE TIED TO RCLK (OR SYSCLK IF THE ELASTIC STORE IS ENABLED) AND TSYNC MUST BE TIED
TO RSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER.
51 of 60
DS2153Q
15 DC CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V
Operating Temperature Range
Commercial……………………………………………………………...……………...0°C to 70°C
Industrial…………………………………………………………………………….-40°C to +85°C
Storage Temperature ………………………………………………………………………-55°C to +125°C
Soldering Temperature...………………………………………..See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
Table 15-1. Recommended DC Characteristics
(TA = 0°C to +70°C for DS2153Q, TA = -40°C to +85°C for DS2153QN.)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
Logic 1 VIH 2.0 VDD + 0.3 V
Logic 0 VIL -0.3 +0.8 V
Supply
DS2153Q 4.75 5.25
DS2153QN
VDD
4.80 5.25
V 1
Table 15-2. Capacitance
(TA = +25°C)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 pF
Output Capacitance C
7 pF
OUT
Table 15-3. DC Characteristics
(VDD = 5V ±5%, TA = 0°C to +70°C for DS2153Q; VDD = 5V +5%/-4%, TA = -40°C to +85°C for
DS2153QN.)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
Supply Current at 5V IDD 65 mA 2
Input Leakage IIL -1.0 +1.0
Output Leakage ILO 1.0
µA
µA
3
4
Output Current (2.4V) IOH -1.0 mA
Output Current (0.4V) IOL +4.0 mA
NOTES:
1) Applies to RVDD, TVDD, and DVDD.
2) TCLK =2.048MHz.
3) 0V < V
< VDD.
IN
4) Applies to INT1 and INT1 when tri-stated.
52 of 60
DS2153Q
16 AC CHARACTERISTICS
Table 16-1. AC Characteristics—Parallel Port
(VDD = 5V ±5%, TA = 0°C to +70°C for DS2153Q; VDD = 5V +5%/-4%, TA = -40°C to +85°C for
DS2153QN.) (See Figure 16-1
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
, Figure 16-2, and Figure 16-3.)
Cycle Time t
Pulse Width, DS Low or RD
High
Pulse Width, DS High or RD
Low
250 ns
CYC
PWEL 150 ns
PWEH 100 ns
Input Rise/Fall Times tR, tF 30 ns
t
R/ W Hold Time
R/ W Setup Time before DS
High
CS Setup Time before DS,
WR or RD Active
CS Hold Time
Read Data Hold Time t
Write Data Hold Time t
Muxed Address Valid to AS
or ALE Fall
Muxed Address Hold Time t
Delay Time DS, WR or RD
to AS or ALE Rise
Pulse Width AS or ALE High PW
Delay Time, AS or ALE to
DS, WR or RD
Output Data Delay Time from
DS or RD
Data Setup Time t
10 ns
RWH
t
50 ns
RWS
tCS 20 ns
tCH 0 ns
10 50 ns
DHR
0 ns
DHW
t
20 ns
ASL
10 ns
AHL
t
25 ns
ASD
40 ns
ASH
t
20 ns
ASED
20 100 ns
t
DDR
80 ns
DSW
53 of 60
Figure 16-1. Intel Bus Read AC Timing
DS2153Q
Figure 16-2. Intel Bus Write AC Timing
54 of 60
Figure 16-3. Motorola Bus AC Timing
DS2153Q
55 of 60
DS2153Q
Table 16-2. AC Characteristics—Receive Side
(VDD = 5V ±5%, TA = 0°C to +70°C for DS2153Q; VDD = 5V +5%/-4%, TA = -40°C to +85°C for
DS2153QN.) (See Figure 16-4.)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
ACLKI/RCLK Period tCP 488 ns
RCLK Pulse Width
tCH 180 244 ns
1
tCL 180 244 ns
RCLK Pulse Width
SYSCLK Period
tCH 90 244 ns
tCL 200 244 ns
2
tSP 648 ns 3
tSP 488 ns 4
SYSCLK Pulse Width
RSYNC Setup to SYSCLK
Falling
tSH 50 ns
t
50
SL
tSU 25 tSH -5 ns
RSYNC Pulse Width tPW 50 ns
SYSCLK Rise/Fall Times tR, tF 25 ns
Delay RCLK or SYSCLK to
RSER Valid
Delay RCLK or SYSCLK to
RCHCLK
Delay RCLK or SYSCLK to
RCHBLK
Delay RCLK or SYSCLK to
RSYNC
tDD 70 ns
tD1 50 ns
tD2 50 ns
tD3 50 ns
Delay RCLK to RLCLK tD4 50 ns
Delay RCLK to RLINK Valid tD5 50 ns
NOTES:
1) Jitter attenuator enabled in the receive side path.
2) Jitter attenuator disabled or enabled in the transmit path.
3) SYSCLK = 1.544MHz.
4) SYSCLK = 2.048MHz.
56 of 60
Figure 16-4. Receive Side AC Timing
DS2153Q
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. NO TIMING RELATIONSHIP BETWEEN RLCLK/RLINK
AND RSYNC IS IMPLIED.
NOTE 4: RCLK CAN EXHIBIT A SHORT HIGH TIME IF THE JITTER ATTENUATOR IS EITHER DISABLED OR IN THE TRANSMIT PATH.
57 of 60
DS2153Q
Table 16-3. AC Characteristics—Transmit Side
(VDD = 5V ±5%, TA = 0°C to +70°C for DS2153Q; VDD = 5V +5%/-4%, TA = -40°C to +85°C for
DS2153QN.) (See Figure 16-5.)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES
TCLK Period tP 488 ns
TCLK Pulse Width
tCH 75 ns
tCL 75 ns
TSER and TLINK Set up to
TCLK Falling
TSER and TLINK Hold from
TCLK Falling
TSYNC Set up to TCLK
Falling
tSU 25 ns 1
t
25 ns 1
HD
25 tCH -5
t
SU
TSYNC Pulse Width tPW
TCLK Rise/Fall Times tR, tF 25 ns
Delay TCLK to TCHCLK tD1 50 ns
Delay TCLK to TCHBLK tD2 50 ns
Delay TCLK to TSYNC tD3 50 ns
Delay TCLK to TLCLK tD4 50 ns
NOTES:
1) If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and
the parameters tSU and tHD still apply.
58 of 60
Figure 16-5. Transmit Side AC Timing
DS2153Q
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
NOTE 3: NO TIMING RELATIONSHIP BETWEEN TSYNC AND TLCLK/TLINK IS IMPLIED.
59 of 60
DS2153Q
17 PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
17.1 44-Pin PLCC (56-G4003-001)
60 of 60
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.