The DS21455 and DS21458 are quad monolithic
devices featuring independent transceivers that
can be software configured for T1, E1, or J1
operation. Each is composed of a line interface
unit (LIU), framer, HDLC controllers, and a
TDM backplane interface, and is controlled via
an 8-bit parallel port configured for Intel or
Motorola bus operations. The DS21455* is a
direct replacement for the older DS21Q55 quad
MCM device. The DS21458, in a smaller
package (17mm CSBGA) and featuring an
improved controller interface, is software
compatible with the older DS21Q55.
*The JTAG function on the DS21455/DS21458 is a single
controller for all four transceivers, unlike the DS21Q55, which has
a JTAG controller-per-transceiver architecture.
APPLICATIONS
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS21455
DS21455N -40°C to +85°C
DS21458
DS21458N -40°C to +85°C
DALLAS is a registered trademark of Dallas Semiconductor Corp.
MAXIM is a re
0°C to +70°C
0°C to +70°C
istered trademark of Maxim Integrated Products, Inc.
256 BGA
(27mm x 27mm)
256 BGA
(27mm x 27mm)
256 CSBGA
(17mm x 17mm)
256 CSBGA
(17mm x 17mm)
DS21455/DS21458
Quad T1/E1/J1 Transceivers
FEATURES
Four Independent Transceivers, Each Having
the Following Features:
§ Short- and Long-Haul Line Interface for
Clock/Data Recovery and Waveshaping
§ CMI Coder/Decoder
§ Crystal-Less Jitter Attenuator
§ Fully Independent Transmit and Receive
Functionality
§ Dual HDLC Controllers
§ On-Chip Programmable BERT Generator
and Detector
§ Internal Software-Selectable Receiveand Transmit-Side Termination Resistors
for 75Ω/100Ω/120Ω T1 and E1
Interfaces
§ Dual Two-Frame Elastic-Store Slip
Buffers that can Connect to
Asynchronous Backplanes Up to
16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Network Clock
§ Programmable Output Clocks for
Fractional T1, E1, H0, and H12
Applications
§ Interleaving PCM Bus Operation
§ 8-Bit Parallel Control Port, Multiplexed
or Nonmultiplexed, Intel or Motorola
§ IEEE 1149.1 JTAG-Boundary Scan
§ 3.3V Supply with 5V Tolerant Inputs and
Outputs
§ DS21455 Directly Replaces DS21Q55
§ Signaling System 7 (SS7) Support
§ RAI-CI, AIS-CI Support
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
5. PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1 T
5.2 R
5.3 P
5.4 E
5.5 JTAG T
5.6 L
5.7 S
5.8 P
5.9 P
6. PARALLEL PORT .........................................................................................................................................41
6.1 R
7. SPECIAL PER-CHANNEL REGISTER OPERATION ..................................................................................46
26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................................179
27. BERT FUNCTION .......................................................................................................................................186
Figure 14-1. Normal Signal Flow Diagram ................................................................................................................ 80
Figure 17-1. Simplified Diagram of Receive Signaling Path...................................................................................... 93
Figure 17-2.Simplified Diagram of Transmit Signaling Path.................................................................................... 100
Figure 35-2. TAP Controller State Diagram............................................................................................................. 219
Figure 36-1. Receive Side D4 Timing...................................................................................................................... 228
Figure 36-2. Receive Side ESF Timing ................................................................................................................... 229
Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled)............................................................ 230
Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) ........................................... 231
Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................... 232
Figure 36-6. Transmit Side D4 Timing..................................................................................................................... 233
Figure 36-7. Transmit Side ESF Timing .................................................................................................................. 234
Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled) ........................................................... 235
Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) .......................................... 236
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................ 237
Figure 36-11. Receive Side Timing ......................................................................................................................... 238
Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled) .......................................................... 239
Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled) ................... 240
Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled) .................. 241
Table 35-1. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE............................................................ 220
Table 35-2. ID CODE STRUCTURE ....................................................................................................................... 221
Table 35-3. DEVICE ID CODES.............................................................................................................................. 221
Table 35-4. BOUNDARY SCAN CONTROL BITS .................................................................................................. 223
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
1. DESCRIPTION
The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be
software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer,
HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured
for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad
MCM device. The DS21458, which comes in a smaller package (17mm CSBGA) and features an
improved controller interface, is software compatible with the older DS21Q55.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit
interface is responsible for generating the necessary waveshapes for driving the network and providing
the correct source impedance depending on the type of media used. T1 waveform generation includes
DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform
generation includes G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The receive interface
provides network termination and recovers clock and data from the network. The receive sensitivity
adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for
E1 applications and 0dB to 15dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase
jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz
MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications)
and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI
coder/decoder for interfacing to optical networks.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane
interface section. The framer inserts the appropriate synchronization framing patterns and alarm
information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression)
and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes
to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data
and frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and
receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time
slots, portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus
reducing the amount of processor overhead required to manage the flow of data. In addition, built-in
support for reducing the processor time required handles SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system.
Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1
network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also
manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up
to eight transceivers (two DS21455s/DS21458s) to share a high-speed backplane.
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The parallel port provides access for control and configuration of all the DS21455/DS21458’s features.
The Extended System Information Bus (ESIB) function allows up to eight transceivers, two DS21455s or
two DS21458s to be accessed via a single read for interrupt status or other user-selectable alarm status
information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit
loop-up and loop-down code generation and detection.
* The JTAG function on the DS21455/DS21458 is a single controller for all four transceivers, unlike
the DS21Q55, which has a JTAG controller-per-transceiver architecture.
§ User-defined Idle Code Generation on a per-channel basis in both transmit and receive paths
§ Digital milliwatt code generation on the receive path
§ ANSI T1.403-1998 support
§ G.965 V5.2 link detect
§ RAI-CI detection and generation
§ AIS-CI detection and generation
§ Ability to monitor one DS0 channel in both the transmit and receive paths
§ In-band repeating-pattern generators and detectors
- Three independent generators and detectors
- Patterns from 1 bit to 8 bits or 16 bits in length
§ RCL, RLOS, RRA, and RAIS alarms interrupt on change of state
§ Flexible signaling support
- Software- or hardware-based
- Interrupt generated on change of signaling data
- Receive-signaling freeze on loss of sync, carrier loss, or frame slip
§ Hardware pins to indicate carrier loss and signaling freeze
§ Automatic RAI generation to ETS 300 011 specifications
§ Expanded access to Sa and Si bits
§ Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2.6 System Interface
§ Dual two-frame, independent receive and transmit elastic stores
- Independent control and clocking
- Controlled-slip capability with status
- Minimum-delay mode supported
§ Supports T1 to E1 conversion
§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
§ Programmable output clocks for fractional T1, E1, H0, and H12 applications
§ Interleaving PCM bus operation with rates of 4.096MHz, 8.192MHz, and 16.384MHz
§ Hardware-signaling capability
- Receive-signaling reinsertion to a backplane, multiframe sync
- Availability of signaling in a separate PCM data stream
- Signaling freezing
§ Access to the data streams in between the framer/formatter and the elastic stores (DS21455)
§ User-selectable synthesized clock output
2.7 HDLC Controllers
§ Two independent HDLC controllers
§ Fast load and unload features for FIFOs
§ SS7 support for FISU transmit and receive
§ Independent 128-byte Rx and Tx buffers with interrupt support
§ Access FDL, Sa, or single/multiple DS0 channels
§ DS0 access includes Nx64 or Nx56
§ Compatible with polled or interrupt-driven environments
§ Bit Oriented Code (BOC) support
2.8 Test and Diagnostics
§ Programmable Bit Error Rate Testing (BERT)
§ Pseudorandom patterns including QRSS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion for single bit or continuous
§ Insertion options include continuous and absolute number with selectable insertion rates
§ Total-bit and errored-bit counters
§ Payload Error Insertion
§ Errors can be inserted over the entire frame or selected channels
§ F-bit corruption for line testing
§ Loopbacks (remote, local, analog, and per-channel payload loopback)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
2.9 Extended System Information Bus
§ Host can read interrupt and alarm status on up to eight ports (two devices) with a single-bus read
2.10 Control Port
§ 8-bit parallel control port
§ Multiplexed or nonmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt-driven environments
§ Software access to device ID and silicon revision
§ Software-reset supported with automatic clear on power-up
§ Hardware reset pin
Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In
each 125ms T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is
sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1
to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to
refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
3. BLOCK DIAGRAM
Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and
This section describes the differences between the DS21455 and DS21458.
4.1 Package
DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the
DS21Q55.)
DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA
4.2 Controller Interface
DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver.
DS21458: The CPU interface has 10 address lines with a single chip select. The upper address lines, A8
and A9, act as coded transceiver selects.
4.3 ESIB Function
The ESIB function provides a fast method of determining interrupt and alarm status when multiple ports
(up to 8) are being controlled by a single processor.
DS21455: The three ESIB signals are brought out for each transceiver. The user must externally
configure the ESIB group.
DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable
the connection of another DS21458 into an 8-port ESIB.
4.4 Framer/LIU Interim Signals
Access to the clock and bipolar data signals between the framer and LIU function may be used for
specialized applications. An internal MUX connects the framer and LIU if these signals are unused. The
MUX is controlled via the LIUC/TPD pin and LIUC bit in the LBCR register. The unused inputs must be
connected to ground.
DS21455: The user has access to all clock and data signals between the framer and LIU on all
transceivers as shown in Figure 4-1
DS21458: The user has limited access to clock and data signals between the framer and LIU on all
transceivers as shown in Figure 4-2
.
.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 4-1. DS21455 Framer/LIU Interim Signals
Rx
LIU
Tx
LIU
Rx
LIU
RPOSO
RNEGO
RCLKO
MUX
RPOSO
RNEGO
RCLKO
RPOSI
RNEGI
RCLKI
TPOSI
TNEGI
TCLKI
RPOSI
RNEGI
RCLKI
MUX
TPOSO
TNEGO
TCLKO
MUX
Rx
FRAMER
Tx
FRAMER
Rx
FRAMER
RPOSO
RNEGO
RCLKO
RPOSI
RNEGI
RCLKI
#1#2
Rx
FRAMER
Rx
MUX
LIU
Tx
Tx
LIU
MUX
RPOSO
RNEGO
RCLKO
TPOSI
TNEGI
TCLKI
RPOSI
RNEGI
RCLKI
TPOSO
TNEGO
TCLKO
FRAMER
#4#3
Rx
FRAMER
Rx
MUX
LIU
Tx
LIU
MUX
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
Tx
FRAMER
Tx
FRAMER
LIUC
Tx
LIU
MUX
TPOSI
TNEGI
TCLKI
TPOSO
TNEGO
TCLKO
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 4-2. DS21458 Framer/LIU Interim Signals
Rx
LIU
RPOSO1
RNEGO1
RCLKO1
Rx
FRAMER
#1
Rx
LIU
RPOSO2
RNEGO2
RCLKO2
#2
Rx
FRAMER
Tx
LIU
Rx
LIU
Tx
LIU
RPOSO3
RNEGO3
RCLKO3
TPOSO1
TNEGO1
TCLKO1
Tx
FRAMER
Rx
FRAMER
Tx
FRAMER
#3
Tx
LIU
Rx
LIU
Tx
LIU
Tx
FRAMER
TPOSO2
TNEGO2
TCLKO2
RPOSO4
RNEGO4
RCLKO4
#4
Rx
FRAMER
Tx
FRAMER
TPOSO3
TNEGO3
TCLKO3
TPOSO4
TNEGO4
TCLKO4
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
5. PIN FUNCTION DESCRIPTION
5.1 Transmit Side Pins
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.
Signal Name:
Signal Description:
Signal Type:
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on
the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a
gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is
disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the
transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for
locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic-store function
is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See the Interleaved PCM Bus Operation section for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
Signal Name:
Signal Description:
Signal Type:
Demand clock for the transmit link data [TLINK] input.
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fsbit position (D4) or the Z-bit position (ZBTSI) or any combination of the Sa bit positions (E1).
TCLK
Transmit Clock
Input
TSER
Transmit Serial Data
Input
TCHCLK
Transmit Channel Clock
Output
TCHBLK
Transmit Channel Block
Output
TSYSCLK
Transmit System Clock
Input
TLCLK
Transmit Link Clock
Output
TLINK
Transmit Link Data
Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output
either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to
output double-wide pulses at signaling frames in T1 mode.
Signal Name:
Signal Description:
Signal Type:
Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe
boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.
Signal Name:
Signal Description:
Signal Type:
When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge
of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side
elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is enabled or not.
This pin is normally tied to TDATA.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is normally tied to
TESO.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source
NRZ data via the output-data format (IOCR1.0)-control bit. This pin is normally tied to TPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to
TNEGI.
Signal Name:
Signal Description:
Signal Type:
Buffered clock that is used to clock data through the transmit-side formatter (either TCLK or RCLKI). This pin is normally
tied to TCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of this function
TNEGI can be tied together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function
and TNEGI can be tied together in NRZ applications.
Signal Name:
Signal Description:
Signal Type:
Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
Signal Description:
Signal Type:
T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame.
E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name:
Signal Description:
Signal Type:
T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output.
E1 Mode: A 4kHz to 20kHz clock.
Signal Name:
Signal Description:
Signal Type:
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a
gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is
disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion
of channel data.
Signal Name:
Signal Description:
Signal Type:
A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with
RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is
enabled. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and
for per-channel conditioning. See the Channel Blocking Registers section.
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive-side elastic store is enabled.
RLINK
Receive Link Data
Output
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock
Output
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
RSER
Receive Serial Data
Output
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe
(IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide
pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input
via IOCR1.4 at which a frame or multiframe boundary pulse is applied.
Signal Name:
Signal Description:
Signal Type:
An extracted 8kHz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is output at this pin,
which identifies multiframe boundaries.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
Signal Description:
Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic-store function is enabled.
Should be tied low in applications that do not use the receive-side elastic store. See the Interleaved PCM Bus Operation
section for details on 4.096MHz and 8.192MHz operation using the IBO.
Signal Name:
Signal Description:
Signal Type:
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled.
Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
A dual-function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5ms.
Signal Name:
Signal Description:
Signal Type:
Set high when the line interface detects a carrier loss.
Signal Name:
Signal Description:
Signal Type:
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of
the condition.
RSYNC
Receive Sync
Input/Output
RFSYNC
Receive Frame Sync
Output
RMSYNC
Receive Multiframe Sync
Output
RDATA
Receive Data
Output
RSYSCLK
Receive System Clock
Input
RSIG
Receive Signaling Output
Output
RLOS/LOTC
Receive Loss of Sync/Loss of Transmit Clock
Output
RCL
Receive Carrier Loss
Output
RSIGF
Receive Signaling Freeze
Output
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.
Signal Name:
Signal Description:
Signal Type:
Buffered recovered clock from the network. This pin is normally tied to RCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied
together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin
description for a full explanation of the LIUC/TPD function.
Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function
BPCLK
Backplane Clock
Output
RPOSO
Receive Positive-Data Output
Output
RNEGO
Receive Negative-Data Output
Output
RCLKO
Receive Clock Output
Output
RPOSI (DS21455 Only)
Receive Positive Data Input
Input
RNEGI (DS21455 Only)
Receive Negative Data Input
Input
RCLKI (DS21455 Only)
Receive Clock Input
Input
.
5.3 Parallel Control Port Pins
Signal Name:
Signal Description:
Signal Type:
Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.
Signal Name:
Signal Description:
Signal Type:
A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21455/DS21458 register set. A reset clears all
configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will tri-state all output and I/O
pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
INT
Interrupt
Output
TSTRST
Tri-State Control and Device Reset
Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
MUX
Bus Operation
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
Signal Description:
Signal Type:
AD0 to AD7
Data Bus [D0 to D7] or Address/Data Bus
Input/Output
In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an
8-bit, multiplexed address/data bus.
Signal Name:
Signal Description:
Signal Type:
A0 to A6
Address Bus
Input
In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins
are not used and should be tied low.
Signal Name:
Signal Description:
Signal Type:
A8 and A9 (DS21458 Only)
Address Bus
Input
Upper address pins for nonmultiplexed (MUX = 0), and multiplexed (MUX = 1) bus operation,.
Signal Name:
Signal Description:
Signal Type:
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the
ALE (AS), and
WR (R/W) pins. If BTS = 1, then these pins assume the function listed in parentheses ().
BTS
Bus Type Select
Input
RD (DS),
Signal Name:
Signal Description:
Signal Type:
RD and DS are active-low signals. DS active HIGH when MUX = 0. See the bus timing diagrams.
RD (DS)
Read Input-Data Strobe
Input
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to Transceiver 1 of the device.
CS1 (DS21455 Only)
Chip Select for Transceiver 1
Input
CS1 is an active-low signal.
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to Transceiver 2 of the device.
CS2 (DS21455 Only)
Chip Select for Transceiver 2
Input
CS2 is an active-low signal.
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to Transceiver 3 of the device.
CS3 (DS21455 Only)
Chip Select for Transceiver 3
Input
CS3 is an active-low signal.
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to Transceiver 4 of the device.
CS4 (DS21455 Only)
Chip Select for Transceiver 4
Input
CS4 is an active-low signal.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
Must be low to read or write to the device.
Signal Name:
Signal Description:
Signal Type:
In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it
serves to demultiplex the bus on a positive-going edge.
Signal Name:
Signal Description:
Signal Type:
WR is an active-low signal.
CS (DS21458 Only)
Chip Select
Input
CS is an active-low signal.
ALE (AS)/A7
Address Latch Enable (Address Strobe) or A7
Input
WR (R/W)
Write Input (Read/Write)
Input
5.4 Extended System Information Bus
Signal Name:
Signal Description:
Signal Type:
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
Signal Name:
Signal Description:
Signal Type:
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
Signal Name:
Signal Description:
Signal Type:
Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
ESIBS0
Extended System Information Bus Select 0
Input/Output
ESIBS1
Extended System Information Bus Select 1
Input/Output
ESIBRD
Extended System Information Bus Read
Input/Output
5.5 JTAG Test Access Port Pins
Signal Name:
Signal Description:
Signal Type:
JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to
high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST
low. JTRST is pulled HIGH internally via a 10kW resistor operation.
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1
states. This pin has a 10kW pullup resistor.
JTRST
IEEE 1149.1 Test Reset
Input
JTMS
IEEE 1149.1 Test Mode Select
Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left
unconnected.
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
5.6 Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
Signal Description:
Signal Type:
A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and
E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in
T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name:
Signal Description:
Signal Type:
This is a dual function pin depending on the state of the LTS bit in the LBCR register (LBCR.7).
MCLK1
Master Clock Input for Transceivers 1 and 2
Input
MCLK2
Master Clock Input for Transceivers 3 and 4
Input
LIUC/TPD (DS21455), TPD (DS21458)
Line Interface Unit Connect/Transmit Power-Down
Input
LTS = 0: In this mode the LIUC/TPD pin, along with the LIUC bit of the LBCR register controls the connection between the
framer and the LIU. This function is only available on the DS21455
Table 14-1
LTS = 1: In this mode the LIUC/TPD pin along with the TPD bit in the LIC1 register (LIC1.0) controls the state of the
Transmit Power-Down function. See the TPD bit description in Section 25
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Section 25
Signal Name:
Signal Description:
Signal Type:
Analog line-driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Section 25
.
RTIP and RRING
Receive Tip and Ring
Input
TTIP and TRING
Transmit Tip and Ring
Output
27 of 270
. See the LIUC bit description in Section 14 and
and Table 25-1.
for details.
for details.
5.7 Supply Pins
Signal Name:
Signal Description:
Signal Type:
3.3V ±5%. Should be tied to the RVDD and TVDD pins.
Signal Name:
Signal Description:
Signal Type:
3.3V ±5%. Should be tied to the DVDD and TVDD pins.
Signal Name:
Signal Description:
Signal Type:
3.3V ±5% Should be tied to the RVDD and DVDD pins.
Signal Name:
Signal Description:
Signal Type: Supply
Should be tied to the RVSS and TVSS pins.
Signal Name:
Signal Description:
Signal Type:
0.0V. Should be tied to DVSS and TVSS.
Signal Name:
Signal Description:
Signal Type:
0.0V. Should be tied to DVSS and RVSS.
DVDD
Digital Positive Supply
Supply
RVDD
Receive Analog Positive Supply
Supply
TVDD
Transmit Analog Positive Supply
Supply
DVSS
Digital Signal Ground
RVSS
Receive Analog Signal Ground
Supply
TVSS
Transmit Analog Signal Ground
Supply
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
5.8 Pin Descriptions
Table 5-1. DS21455 PIN DESCRIPTION
PIN NAME TYPE FUNCTION
U3 A0 I Address Bus Bit 0 (Lsb)
L17 A1 I Address Bus Bit 1
V2 A2 I Address Bus Bit 2
T4 A3 I Address Bus Bit 3
V8 A4 I Address Bus Bit 4
H4 A5 I Address Bus Bit 5
U8 A6 I Address Bus Bit 6
P4 A7/ALE (AS) I Address Bus Bit 7 (Msb)/Address Latch Enable
M1 BPCLK1 O Backplane Clock, Transceiver 1
H17 BPCLK2 O Backplane Clock, Transceiver 2
F4 BPCLK3 O Backplane Clock, Transceiver 3
V13 BPCLK4 O Backplane Clock, Transceiver 4
P2 BTS I Bus Type Select (0 = Intel/1 = Motorola)
P3
A14
B5
K17
U11 D0/AD0 I/O Data Bus Bit 0/Address/Data Bus Bit 0 (Lsb)
J19 D1/AD1 I/O Data Bus Bit 1/Address/Data Bus Bit 1
W15 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus Bit 2
U7 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
U9 D4/AD4 I/O Data Bus Bit 4/Address/Data Bus Bit 4
U5 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
V4 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
U4 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7 (Msb)
J3 DVDD — Digital Positive Supply
N4 DVDD — Digital Positive Supply
U2 DVDD — Digital Positive Supply
V5 DVDD — Digital Positive Supply
B12 DVDD — Digital Positive Supply
C12 DVDD — Digital Positive Supply
C16 DVDD — Digital Positive Supply
D18 DVDD — Digital Positive Supply
A9 DVDD — Digital Positive Supply
B3 DVDD — Digital Positive Supply
B6 DVDD — Digital Positive Supply
C4 DVDD — Digital Positive Supply
G20 DVDD — Digital Positive Supply
M17 DVDD — Digital Positive Supply
M20 DVDD — Digital Positive Supply
P18 DVDD — Digital Positive Supply
H3 DVSS — Digital Signal Ground
U6 DVSS — Digital Signal Ground
W8 DVSS — Digital Signal Ground
A17 DVSS — Digital Signal Ground
A20 DVSS — Digital Signal Ground
B11 DVSS — Digital Signal Ground
A5 DVSS — Digital Signal Ground
CS1
CS2
CS3
CS4
I Chip Select for Transceiver 1
I Chip Select for Transceiver 2
I Chip Select for Transceiver 3
I Chip Select for Transceiver 4
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN NAME TYPE FUNCTION
B7 DVSS — Digital Signal Ground
B9 DVSS — Digital Signal Ground
H20 DVSS — Digital Signal Ground
L20 DVSS — Digital Signal Ground
N17 DVSS — Digital Signal Ground
J4 ESIBRD1 I/O Extended System Information Bus Read for Transceiver 1
C13 ESIBRD2 I/O Extended System Information Bus Read for Transceiver 2
C3 ESIBRD3 I/O Extended System Information Bus Read for Transceiver 3
U13 ESIBRD4 I/O Extended System Information Bus Read for Transceiver 4
W6 ESIBS0_1 I/O Extended System Information Bus 0 for Transceiver 1
F18 ESIBS0_2 I/O Extended System Information Bus 0 for Transceiver 2
D7 ESIBS0_3 I/O Extended System Information Bus 0 for Transceiver 3
T20 ESIBS0_4 I/O Extended System Information Bus 0 for Transceiver 4
V9 ESIBS1_1 I/O Extended System Information Bus 1 for Transceiver 1
B17 ESIBS1_2 I/O Extended System Information Bus 1 for Transceiver 2
A6 ESIBS1_3 I/O Extended System Information Bus 1 for Transceiver 3
J20 ESIBS1_4 I/O Extended System Information Bus 1 for Transceiver 4
U1
INT
Interrupt for All Four Transceivers
O
Y15 JTCLK I JTAG Clock
N1 JTDI I JTAG Data Input
V19 JTDO O JTAG Data Output
W13 JTMS I JTAG Test Mode Select
V18 JTRST I Jtag Reset
K2 LIUC/TPD I Line Interface Connect for All Four Transceivers or Transmit Power-Down Enable
T1 MCLK1 I Master Clock for Transceiver 1 and Transceiver 3
W20 MCLK2 I Master Clock for Transceiver 2 and Transceiver 4
U10 MUX I Mux Bus Select
M2 RCHBLK1 O Receive Channel Block for Transceiver 1
G17 RCHBLK2 O Receive Channel Block for Transceiver 2
G4 RCHBLK3 O Receive Channel Block for Transceiver 3
Y12 RCHBLK4 O Receive Channel Block for Transceiver 4
J1 RCHCLK1 O Receive Channel Clock for Transceiver 1
D14 RCHCLK2 O Receive Channel Clock for Transceiver 2
F3 RCHCLK3 O Receive Channel Clock for Transceiver 3
U14 RCHCLK4 O Receive Channel Clock for Transceiver 4
N3 RCLK1 O Receive Clock Output from the Framer on Transceiver 1
B13 RCLK2 O Receive Clock Output from the Framer on Transceiver 2
E3 RCLK3 O Receive Clock Output from the Framer on Transceiver 3
M18 RCLK4 O Receive Clock Output from the Framer on Transceiver 4
M4 RCLKI1 I Receive Clock Input for the LIU on Transceiver 1
A15 RCLKI2 I Receive Clock Input for the LIU on Transceiver 2
A4 RCLKI3 I Receive Clock Input for the LIU on Transceiver 3
R17 RCLKI4 I Receive Clock Input for the LIU on Transceiver 4
M3 RCLKO1 O Receive Clock Output from the LIU on Transceiver 1
C14 RCLKO2 O Receive Clock Output from the LIU on Transceiver 2
B4 RCLKO3 O Receive Clock Output from the LIU on Transceiver 3
T17 RCLKO4 O Receive Clock Output from the LIU On Transceiver 4
N2
RD (DS)
I Read Input (Data Strobe)
K4 RFSYNC1 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 1
D17 RFSYNC2 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 2
A2 RFSYNC3 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 3
V14 RFSYNC4 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 4
F1 RLCLK1 O Receive Link Clock for Transceiver 1
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