MAXIM DS21455, DS21458 Technical data

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GENERAL DESCRIPTION
*The JTAG function on the DS21455/DS21458 is a single
controller for all four transceivers, unlike the DS21Q55, which has a JTAG controller-per-transceiver architecture.
APPLICATIONS
Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS21455
DS21455N -40°C to +85°C
DS21458
DS21458N -40°C to +85°C
DALLAS is a registered trademark of Dallas Semiconductor Corp. MAXIM is a re
0°C to +70°C
0°C to +70°C
istered trademark of Maxim Integrated Products, Inc.
256 BGA (27mm x 27mm) 256 BGA (27mm x 27mm) 256 CSBGA (17mm x 17mm) 256 CSBGA (17mm x 17mm)
DS21455/DS21458
Quad T1/E1/J1 Transceivers
FEATURES
Four Independent Transceivers, Each Having the Following Features:
§ Complete T1 (DS1)/ISDN-PRI/J1 Transceiver Functionality
§ Complete E1 (CEPT) PCM-30/ISDN­PRI Transceiver Functionality
§ Short- and Long-Haul Line Interface for Clock/Data Recovery and Waveshaping
§ CMI Coder/Decoder
§ Crystal-Less Jitter Attenuator
§ Fully Independent Transmit and Receive
Functionality
§ Dual HDLC Controllers
§ On-Chip Programmable BERT Generator
and Detector
§ Internal Software-Selectable Receive­and Transmit-Side Termination Resistors for 75Ω/100Ω/120Ω T1 and E1 Interfaces
§ Dual Two-Frame Elastic-Store Slip Buffers that can Connect to Asynchronous Backplanes Up to
16.384MHz
§ 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to Recovered Network Clock
§ Programmable Output Clocks for Fractional T1, E1, H0, and H12 Applications
§ Interleaving PCM Bus Operation
§ 8-Bit Parallel Control Port, Multiplexed
or Nonmultiplexed, Intel or Motorola
§ IEEE 1149.1 JTAG-Boundary Scan
§ 3.3V Supply with 5V Tolerant Inputs and
Outputs
§ DS21455 Directly Replaces DS21Q55
§ Signaling System 7 (SS7) Support
§ RAI-CI, AIS-CI Support
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
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REV: 040804
.
DOCUMENT REVISION HISTORY
REVISION CHANGES
040804 New Product Release.
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
TABLE OF CONTENTS
1. DESCRIPTION ................................................................................................................................................9
1.1 S
2. FEATURE HIGHLIGHTS ...............................................................................................................................11
2.1 G
2.2 L
2.3 C
2.4 J
2.5 F
2.6 S
2.7 HDLC C
2.8 T
2.9 E
2.10 C
3. BLOCK DIAGRAM ........................................................................................................................................15
4. DS21455/DS21458 DELTA...........................................................................................................................17
4.1 P
4.2 C
4.3 ESIB F
4.4 F
5. PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1 T
5.2 R
5.3 P
5.4 E
5.5 JTAG T
5.6 L
5.7 S
5.8 P
5.9 P
6. PARALLEL PORT .........................................................................................................................................41
6.1 R
7. SPECIAL PER-CHANNEL REGISTER OPERATION ..................................................................................46
8. PROGRAMMING MODEL.............................................................................................................................48
8.1 P
8.2 I
8.3 S
8.4 I
8.5 I
9. CLOCK MAP .................................................................................................................................................52
10. T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................53
10.1 T1 C
10.2 T1 T
10.3 AIS-CI
10.4 T1 R
10.5 T1 I
11. E1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................64
11.1 E1 C
11.2 A
11.3 E1 I
12. COMMON CONTROL AND STATUS REGISTERS.....................................................................................71
TANDARDS ...................................................................................................................... 10
ENERAL .......................................................................................................................... 11
INE INTERFACE ................................................................................................................ 11
LOCK SYNTHESIZER ........................................................................................................ 11
ITTER ATTENUATOR ......................................................................................................... 12
RAMER/FORMATTER ........................................................................................................ 12
YSTEM INTERFACE........................................................................................................... 13
ONTROLLERS ....................................................................................................... 13
EST AND DIAGNOSTICS .................................................................................................... 13
XTENDED SYSTEM INFORMATION BUS .............................................................................. 14
ONTROL PORT ................................................................................................................ 14
ACKAGE.......................................................................................................................... 17
ONTROLLER INTERFACE................................................................................................... 17
UNCTION................................................................................................................ 17
RAMER/LIU INTERIM SIGNALS .......................................................................................... 17
RANSMIT SIDE PINS ......................................................................................................... 20
ECEIVE SIDE PINS ........................................................................................................... 22
ARALLEL CONTROL PORT PINS ........................................................................................ 24
XTENDED SYSTEM INFORMATION BUS .............................................................................. 26
EST ACCESS PORT PINS........................................................................................ 26
INE INTERFACE PINS ........................................................................................................ 27
UPPLY PINS .................................................................................................................... 28
IN DESCRIPTIONS............................................................................................................ 29
ACKAGES........................................................................................................................ 39
EGISTER MAP ................................................................................................................. 41
OWER-UP SEQUENCE...................................................................................................... 49
8.1.1 Master Mode Register ........................................................................................................ 49
NTERRUPT HANDLING ....................................................................................................... 50
TATUS REGISTERS .......................................................................................................... 50
NFORMATION REGISTERS.................................................................................................. 51
NTERRUPT INFORMATION REGISTERS ................................................................................ 51
ONTROL REGISTERS .................................................................................................. 53
RANSMIT TRANSPARENCY........................................................................................... 58
AND RAI-CI GENERATION AND DETECTION ............................................................. 59
ECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION ................................................. 60
NFORMATION REGISTER............................................................................................... 62
ONTROL REGISTERS .................................................................................................. 64
UTOMATIC ALARM GENERATION ....................................................................................... 68
11.2.1 Auto AIS ...........................................................................................................................68
11.2.2 Auto RAI ...........................................................................................................................68
11.2.3 Auto E-Bit .........................................................................................................................68
11.2.4 G.706 CRC-4 Interworking ............................................................................................68
NFORMATION REGISTERS ............................................................................................ 69
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13. I/O PIN CONFIGURATION OPTIONS ..........................................................................................................78
14. LOOPBACK CONFIGURATIONS ................................................................................................................80
14.1 P
ER-CHANNEL PAYLOAD LOOPBACK .................................................................................. 83
15. ERROR COUNT REGISTERS ......................................................................................................................85
15.1 L
INE CODE VIOLATION COUNT REGISTER (LCVCR)............................................................ 86
15.1.1 T1 Operation....................................................................................................................86
15.1.2 E1 Operation....................................................................................................................86
15.2 P
ATH CODE VIOLATION COUNT REGISTER (PCVCR) .......................................................... 88
15.2.1 T1 Operation....................................................................................................................88
15.2.2 E1 Operation....................................................................................................................88
15.3 F
RAMES OUT OF SYNC COUNT REGISTER (FOSCR) .......................................................... 89
15.3.1 T1 Operation....................................................................................................................89
15.3.2 E1 Operation....................................................................................................................89
15.4 E-B
IT COUNTER REGISTER (EBCR)................................................................................... 90
16. DS0 MONITORING FUNCTION ...................................................................................................................91
16.1 T
16.2 R
RANSMIT DS0 MONITOR REGISTERS ................................................................................ 91
ECEIVE DS0 MONITOR REGISTERS.................................................................................. 92
17. SIGNALING OPERATION ............................................................................................................................93
17.1 R
ECEIVE SIGNALING .......................................................................................................... 93
17.1.1 Processor-Based Receive Signaling............................................................................94
17.1.2 Hardware-Based Receive Signaling ............................................................................94
17.2 T
RANSMIT SIGNALING ...................................................................................................... 100
17.2.1 Processor-Based Transmit Signaling ........................................................................100
17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode.............................104
17.2.3 Software Signaling Insertion Enable Registers, T1 Mode ......................................106
18. PER-CHANNEL IDLE CODE GENERATION ............................................................................................108
18.1 I
DLE CODE PROGRAMMING EXAMPLES ............................................................................. 109
19. CHANNEL BLOCKING REGISTERS.........................................................................................................113
20. ELASTIC STORES OPERATION...............................................................................................................116
20.1 R
ECEIVE SIDE ................................................................................................................. 119
20.1.1 T1 Mode .........................................................................................................................119
20.1.2 E1 Mode .........................................................................................................................119
20.2 T
RANSMIT SIDE ............................................................................................................... 120
20.2.1 T1 Mode .........................................................................................................................120
20.2.2 E1 Mode .........................................................................................................................120
20.3 E
20.4 M
LASTIC STORES INITIALIZATION ...................................................................................... 120
INIMUM-DELAY MODE ................................................................................................... 121
21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)................................................................122
22. T1 BIT ORIENTED CODE (BOC) CONTROLLER.....................................................................................123
22.1 T
22.2 R
RANSMIT BOC............................................................................................................... 123
ECEIVE BOC................................................................................................................. 123
23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) ........................................127
23.1 H
23.2 I
23.3 I
ARDWARE SCHEME (METHOD 1) .................................................................................... 127
NTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME (METHOD 2)............................. 127
NTERNAL REGISTER SCHEME BASED ON CRC-4 MULTIFRAME (METHOD 3)...................... 130
24. HDLC CONTROLLERS ..............................................................................................................................141
24.1 B
24.2 HDLC C
ASIC OPERATION DETAILS ............................................................................................. 141
ONFIGURATION................................................................................................... 143
24.2.1 FIFO Control ..................................................................................................................145
24.3 HDLC M
APPING.............................................................................................................. 146
24.3.1 Receive...........................................................................................................................146
24.3.2 Transmit .........................................................................................................................148
24.3.3 FIFO Information........................................................................................................... 153
24.3.4 Receive Packet Bytes Available ................................................................................. 153
24.3.5 HDLC FIFOS .................................................................................................................154
24.4 R
24.5 L
ECEIVE HDLC CODE EXAMPLE...................................................................................... 155
EGACY FDL SUPPORT (T1 MODE) ................................................................................. 155
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24.5.1 Receive Section ............................................................................................................155
24.5.2 Transmit Section ...........................................................................................................157
24.6 D4/SLC–96 O
PERATION ................................................................................................. 157
25. LINE INTERFACE UNIT (LIU) ....................................................................................................................158
25.1 LIU O
25.2 LIU R
PERATION .............................................................................................................. 159
ECEIVER ................................................................................................................ 159
25.2.1 Receive Level Indicator................................................................................................160
25.2.2 Receive G.703 Section 10 Synchronization Signal .................................................160
25.2.3 Monitor Mode................................................................................................................. 160
25.3 LIU T
RANSMITTER........................................................................................................... 161
25.3.1 Transmit Short-Circuit Detector/Limiter .....................................................................161
25.3.2 Transmit Open-Circuit Detector ..................................................................................161
25.3.3 Transmit BPV Error Insertion ......................................................................................162
25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode).............................162
25.4 MCLK P
25.5 J
ITTER ATTENUATOR ....................................................................................................... 162
25.6 CMI (C
25.7 LIU C
25.8 R
25.9 C
ECOMMENDED CIRCUITS................................................................................................ 173
OMPONENT SPECIFICATIONS.......................................................................................... 175
RESCALER ......................................................................................................... 162
ODE MARK INVERSION) OPTION ............................................................................ 163
ONTROL REGISTERS ............................................................................................... 164
26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION......................................179
27. BERT FUNCTION .......................................................................................................................................186
27.1 BERT R
27.2 BERT R
27.3 BERT B
27.4 BERT E
EGISTER DESCRIPTION ....................................................................................... 187
EPETITIVE PATTERN SET..................................................................................... 192
IT COUNTER ....................................................................................................... 193
RROR COUNTER ................................................................................................. 194
28. PAYLOAD ERROR INSERTION FUNCTION ............................................................................................195
28.1 N
UMBER OF ERROR REGISTERS ...................................................................................... 197
28.1.1 Number Of Errors Left Register ..................................................................................198
29. INTERLEAVED PCM BUS OPERATION ...................................................................................................199
29.1 C
29.2 F
HANNEL INTERLEAVE MODE ........................................................................................... 199
RAME INTERLEAVE MODE ............................................................................................... 199
30. EXTENDED SYSTEM INFORMATION BUS (ESIB) ..................................................................................202
31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER .....................................................................208
32. FRACTIONAL T1/E1 SUPPORT ................................................................................................................209
33. USER-PROGRAMMABLE OUTPUT PINS ................................................................................................210
34. TRANSMIT FLOW DIAGRAMS..................................................................................................................211
35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT .............................................216
35.1 I
35.2 T
35.3 B
35.4 B
35.5 I
NSTRUCTION REGISTER .................................................................................................. 220
EST REGISTERS............................................................................................................. 222
OUNDARY SCAN REGISTER ............................................................................................ 222
YPASS REGISTER .......................................................................................................... 222
DENTIFICATION REGISTER ............................................................................................... 222
36. FUNCTIONAL TIMING DIAGRAMS...........................................................................................................228
36.1 T1 M
36.2 E1 M
ODE ........................................................................................................................ 228
ODE........................................................................................................................ 238
37. OPERATING PARAMETERS .....................................................................................................................251
38. AC TIMING PARAMETERS AND DIAGRAMS..........................................................................................253
38.1 M
38.2 N
38.3 R
38.4 T
ULTIPLEXED BUS AC CHARACTERISTICS........................................................................ 253
ONMULTIPLEXED BUS AC CHARACTERISTICS ................................................................. 256
ECEIVE SIDE AC CHARACTERISTICS .............................................................................. 259
RANSMIT AC CHARACTERISTICS .................................................................................... 265
39. PACKAGE INFORMATION ........................................................................................................................269
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LIST OF FIGURES
Figure 3-1. DS21458 Block Diagram ......................................................................................................................... 15
Figure 3-2. DS21455 Block Diagram ......................................................................................................................... 16
Figure 4-1. DS21455 Framer/LIU Interim Signals ..................................................................................................... 18
Figure 4-2. DS21458 Framer/LIU Interim Signals ..................................................................................................... 19
Figure 5-1. DS21455 Pin Diagram, 27mm BGA ........................................................................................................ 39
Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA ................................................................................................... 40
Figure 8-1. Programming Sequence.......................................................................................................................... 48
Figure 9-1. Clock Map ............................................................................................................................................... 52
Figure 14-1. Normal Signal Flow Diagram ................................................................................................................ 80
Figure 17-1. Simplified Diagram of Receive Signaling Path...................................................................................... 93
Figure 17-2.Simplified Diagram of Transmit Signaling Path.................................................................................... 100
Figure 21-1. CRC-4 Recalculate Method ................................................................................................................ 122
Figure 25-1. Basic Balanced Network Connections ................................................................................................ 158
Figure 25-2. Basic Unbalanced Network Connections ............................................................................................ 159
Figure 25-3. Typical Monitor Application ................................................................................................................. 160
Figure 25-4. CMI Coding ......................................................................................................................................... 163
Figure 25-5. Basic Interface..................................................................................................................................... 173
Figure 25-6. Protected Interface Using Internal Receive Termination .................................................................... 174
Figure 25-7. E1 Transmit Pulse Template ............................................................................................................... 176
Figure 25-8. T1 Transmit Pulse Template ............................................................................................................... 176
Figure 25-9. Jitter Tolerance.................................................................................................................................... 177
Figure 25-10. Jitter Attenuation (T1 Mode).............................................................................................................. 177
Figure 25-11. Jitter Attenuation (E1 Mode) ............................................................................................................. 178
Figure 29-1. IBO Example ....................................................................................................................................... 201
Figure 30-1. DS21455 ESIB Group ......................................................................................................................... 203
Figure 30-2. DS21458 ESIB Group ......................................................................................................................... 204
Figure 34-1. T1 Transmit Data Flow ........................................................................................................................ 211
Figure 34-2. T1 Transmit Data Flow (continued) ..................................................................................................... 212
Figure 34-3. E1 Transmit Data Flow........................................................................................................................ 213
Figure 34-4. E1 Transmit Data Flow (continued)..................................................................................................... 214
Figure 34-5. E1 Transmit Data Flow (continued)..................................................................................................... 215
Figure 35-1. JTAG Functional Block Diagram ......................................................................................................... 216
Figure 35-2. TAP Controller State Diagram............................................................................................................. 219
Figure 36-1. Receive Side D4 Timing...................................................................................................................... 228
Figure 36-2. Receive Side ESF Timing ................................................................................................................... 229
Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled)............................................................ 230
Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) ........................................... 231
Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................... 232
Figure 36-6. Transmit Side D4 Timing..................................................................................................................... 233
Figure 36-7. Transmit Side ESF Timing .................................................................................................................. 234
Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled) ........................................................... 235
Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) .......................................... 236
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ........................................ 237
Figure 36-11. Receive Side Timing ......................................................................................................................... 238
Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled) .......................................................... 239
Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled) ................... 240
Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled) .................. 241
Figure 36-15. Receive IBO Channel Interleave Mode Timing ................................................................................. 242
Figure 36-16. Receive IBO Frame Interleave Mode Timing.................................................................................... 243
Figure 36-17. G.802 Timing, E1 Mode Only ............................................................................................................ 244
Figure 36-18. Transmit Side Timing ........................................................................................................................ 245
Figure 36-19. Transmit Side Boundary Timing (With Elastic Store Disabled)......................................................... 246
Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz (With Elastic Store Enabled) ................. 247
Figure 36-21. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled) .................. 248
Figure 36-22. Transmit IBO Channel Interleave Mode Timing ................................................................................ 249
Figure 36-23. Transmit IBO Frame Interleave Mode Timing................................................................................... 250
Figure 38-1. Intel Bus Read Timing (BTS = 0 / MUX = 1) ....................................................................................... 254
Figure 38-2. Intel Bus Write Timing (BTS = 0 / MUX = 1) ....................................................................................... 254
Figure 38-3. Motorola Bus Timing (BTS = 1 / MUX = 1).......................................................................................... 255
Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0) ....................................................................................... 257
Figure 38-5. Intel Bus Write Timing (BTS = 0 / MUX = 0) ....................................................................................... 257
Figure 38-6. Motorola Bus Read Timing (BTS = 1 / MUX = 0)................................................................................ 258
Figure 38-7. Motorola Bus Write Timing (BTS = 1 / MUX = 0) ................................................................................ 258
Figure 38-8. Receive Side Timing, Elastic Store Disabled (T1 Mode) .................................................................... 260
Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode) .................................................................... 261
Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode) ................................................................... 262
Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode) ................................................................... 263
Figure 38-12. Receive Line Interface Timing........................................................................................................... 264
Figure 38-13. Transmit Side Timing ........................................................................................................................ 266
Figure 38-14. Transmit Side Timing, Elastic Store Enabled.................................................................................... 267
Figure 38-15. Transmit Line Interface Timing.......................................................................................................... 268
Figure 39-1. DS21458 (17mm CSBGA) .................................................................................................................. 269
Figure 39-2. DS21455 (27mm BGA) ....................................................................................................................... 270
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LIST OF TABLES
Table 5-1. DS21455 PIN DESCRIPTION .................................................................................................................. 29
Table 5-2. DS21458 PIN DESCRIPTION .................................................................................................................. 34
Table 6-1. REGISTER MAP SORTED BY ADDRESS .............................................................................................. 41
Table 10-1. T1 ALARM CRITERIA ............................................................................................................................ 63
Table 11-1. E1 SYNC/RESYNC CRITERIA .............................................................................................................. 65
Table 11-2 AUTO E-BIT CONDITIONS..................................................................................................................... 68
Table 11-3. E1 ALARM CRITERIA ............................................................................................................................ 70
Table 14-1. LIUC CONTROL..................................................................................................................................... 82
Table 15-1. T1 LINE CODE VIOLATION COUNTING OPTIONS ............................................................................. 86
Table 15-2. E1 LINE CODE VIOLATION COUNTING OPTIONS............................................................................. 86
Table 15-3. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS ............................................................. 88
Table 15-4. T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS.............................................................. 89
Table 17-1. TIME SLOT NUMBERING SCHEMES................................................................................................. 101
Table 18-1. IDLE CODE ARRAY ADDRESS MAPPING......................................................................................... 108
Table 20-1. ELASTIC STORE DELAY AFTER INITIALIZATION ............................................................................ 120
Table 24-1. HDLC CONTROLLER REGISTERS .................................................................................................... 142
Table 25-1. TPD CONTROL.................................................................................................................................... 164
Table 25-2. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0)............................. 165
Table 25-3. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1)............................ 165
Table 25-4. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0) ............................. 165
Table 25-5. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1) ............................ 165
Table 25-6. TRANSFORMER SPECIFICATIONS................................................................................................... 175
Table 28-1. TRANSMIT ERROR INSERTION SETUP SEQUENCE ...................................................................... 195
Table 28-2. ERROR INSERTION EXAMPLES ....................................................................................................... 197
Table 35-1. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE............................................................ 220
Table 35-2. ID CODE STRUCTURE ....................................................................................................................... 221
Table 35-3. DEVICE ID CODES.............................................................................................................................. 221
Table 35-4. BOUNDARY SCAN CONTROL BITS .................................................................................................. 223
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
1. DESCRIPTION
The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad MCM device. The DS21458, which comes in a smaller package (17mm CSBGA) and features an improved controller interface, is software compatible with the older DS21Q55.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75 coax and 120 twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 43dB or 0dB to 12dB for E1 applications and 0dB to 15dB or 0dB to 36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications) and can be placed in either transmit or receive data paths. An additional feature of the LIU is a CMI coder/decoder for interfacing to optical networks.
On the transmit side, clock/data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns and alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receive-side framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane interface section.
Both the transmit and receive path have two HDLC controllers. The HDLC controllers transmit and receive data via the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot, or to FDL (T1) or Sa bits (E1). Each controller has 128-bit FIFOs, thus reducing the amount of processor overhead required to manage the flow of data. In addition, built-in support for reducing the processor time required handles SS7 applications.
The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (two DS21455s/DS21458s) to share a high-speed backplane.
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The parallel port provides access for control and configuration of all the DS21455/DS21458’s features. The Extended System Information Bus (ESIB) function allows up to eight transceivers, two DS21455s or two DS21458s to be accessed via a single read for interrupt status or other user-selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.
* The JTAG function on the DS21455/DS21458 is a single controller for all four transceivers, unlike
the DS21Q55, which has a JTAG controller-per-transceiver architecture.
1.1 Standards
§ ANSI: T1.403-1995, T1.231-1993, T1.408
§ AT&T: TR54016, TR62411
§ ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161
§ ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12
§ Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only)
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2. FEATURE HIGHLIGHTS
2.1 General
§ DS21455: 27mm, 1.27 pitch BGA, compatible replacement for the DS21Q55
§ DS21458: 17mm, 1.00 pitch CSBGA
§ 3.3V supply with 5V tolerant inputs and outputs
§ Evaluation kits
§ IEEE 1149.1 JTAG-boundary scan
§ Driver source code available from the factory
2.2 Line Interface
§ Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be
2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. Option to use 1.544MHz, 3.088MHz,
6.276MHz, or 12.552MHz for T1-only operation
§ Fully software configurable
§ Short- and long-haul applications
§ Automatic receive sensitivity adjustments
§ Ranges include 0dB to -43dB or 0dB to -12dB for E1 applications; 0dB to -36dB or 0dB to -15dB
for T1 applications
§ Receive level indication in 2.5dB steps from -42.5dB to -2.5dB
§ Internal receive termination option for 75, 100, and 120 lines
§ Monitor application gain settings of 20dB, 26dB, and 32dB
§ G.703 receive-synchronization signal-mode
§ Flexible transmit-waveform generation
§ T1 DSX-1 line build-outs
§ T1 CSU line build-outs of -7.5dB, -15dB, and -22.5dB
§ E1 waveforms include G.703 waveshapes for both 75 coax and 120 twisted cables
§ AIS generation independent of loopbacks
§ Alternating ones and zeros generation
§ Square-wave output
§ Open-drain output option
§ NRZ format option
§ Transmitter power-down
§ Transmitter 50mA short-circuit limiter with exceeded indication of current limit
§ Transmit open-circuit-detected indication
§ Line interface function can be completely decoupled from the framer/formatter
2.3 Clock Synthesizer
§ Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
§ Derived from recovered line clock or master clock
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2.4 Jitter Attenuator
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use
1.544MHz for T1 operation
§ Can be placed in either the receive or transmit path or disabled
§ Limit trip indication
2.5 Framer/Formatter
§ Fully independent transmit and receive functionality
§ Full receive- and transmit-path transparency
§ T1 framing formats include D4, ESF, J1-D4, J1-ESF and SLC-96
§ Japanese J1 support for CRC6 and yellow alarm
§ E1 framing formats include FAS, CAS, and CRC-4
§ Detailed alarm- and status-reporting with optional interrupt support
§ Large path- and line-error counters for:
- T1 – BPV, CV, CRC6, and framing bit errors
- E1 – BPV, CV, CRC-4, E-bit, and frame alignment errors
- Timed or manual update modes
§ User-defined Idle Code Generation on a per-channel basis in both transmit and receive paths
§ Digital milliwatt code generation on the receive path
§ ANSI T1.403-1998 support
§ G.965 V5.2 link detect
§ RAI-CI detection and generation
§ AIS-CI detection and generation
§ Ability to monitor one DS0 channel in both the transmit and receive paths
§ In-band repeating-pattern generators and detectors
- Three independent generators and detectors
- Patterns from 1 bit to 8 bits or 16 bits in length
§ RCL, RLOS, RRA, and RAIS alarms interrupt on change of state
§ Flexible signaling support
- Software- or hardware-based
- Interrupt generated on change of signaling data
- Receive-signaling freeze on loss of sync, carrier loss, or frame slip
§ Hardware pins to indicate carrier loss and signaling freeze
§ Automatic RAI generation to ETS 300 011 specifications
§ Expanded access to Sa and Si bits
§ Option to extend carrier-loss criteria to a 1ms period as per ETS 300 233
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2.6 System Interface
§ Dual two-frame, independent receive and transmit elastic stores
- Independent control and clocking
- Controlled-slip capability with status
- Minimum-delay mode supported
§ Supports T1 to E1 conversion
§ Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
§ Programmable output clocks for fractional T1, E1, H0, and H12 applications
§ Interleaving PCM bus operation with rates of 4.096MHz, 8.192MHz, and 16.384MHz
§ Hardware-signaling capability
- Receive-signaling reinsertion to a backplane, multiframe sync
- Availability of signaling in a separate PCM data stream
- Signaling freezing
§ Access to the data streams in between the framer/formatter and the elastic stores (DS21455)
§ User-selectable synthesized clock output
2.7 HDLC Controllers
§ Two independent HDLC controllers
§ Fast load and unload features for FIFOs
§ SS7 support for FISU transmit and receive
§ Independent 128-byte Rx and Tx buffers with interrupt support
§ Access FDL, Sa, or single/multiple DS0 channels
§ DS0 access includes Nx64 or Nx56
§ Compatible with polled or interrupt-driven environments
§ Bit Oriented Code (BOC) support
2.8 Test and Diagnostics
§ Programmable Bit Error Rate Testing (BERT)
§ Pseudorandom patterns including QRSS
§ User-defined repetitive patterns
§ Daly pattern
§ Error insertion for single bit or continuous
§ Insertion options include continuous and absolute number with selectable insertion rates
§ Total-bit and errored-bit counters
§ Payload Error Insertion
§ Errors can be inserted over the entire frame or selected channels
§ F-bit corruption for line testing
§ Loopbacks (remote, local, analog, and per-channel payload loopback)
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2.9 Extended System Information Bus
§ Host can read interrupt and alarm status on up to eight ports (two devices) with a single-bus read
2.10 Control Port
§ 8-bit parallel control port
§ Multiplexed or nonmultiplexed buses
§ Intel or Motorola formats
§ Supports polled or interrupt-driven environments
§ Software access to device ID and silicon revision
§ Software-reset supported with automatic clear on power-up
§ Hardware reset pin
Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125ms T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a
1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
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3. BLOCK DIAGRAM
Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and
DS21455.
Figure 3-1. DS21458 Block Diagram
MCLK1
MCLK2
TRANSCEIVER #4
TRANSCEIVER #3
RTIP
RRING
TTIP
TRING
TPD
8XCLK
MASTER
CLOCK
RECEIVE
LIU
CLOCK & DATA
RECOVERY
TRANSMIT
LIU
WAVESHAPE
GENERATION
DS21458
(1 OF 4 TRANSCEIVERS)
LOCAL
LOOP BACK
JITTER
ATTEN.
TX
OR RX
PATH
JITTER
ATTEN.
REMOTE
LOOP BACK
RNEGO
TRANSCEIVER #2
RCLKORPOSO
2 HDLCs
FRAMER
LOOP BACK
ALARM MONITORING
SIGNALING EXTRACTION
HDB3/B8ZS DECODER
CRC RECALCULATE(E1)
SIGNALING INSERTION
2 HDLCs
BERT
RECEIVE FRAMER
SYNCHRONIZATION
HDLC EXTRACTION
DS0 CONDITIONING
TRANSMIT
FRAMER
FRAMING
ALARM INSERTION
HDLC INSERTION DS0 CONDITIONING HDB3/B8ZS CODER
BERT
BACKPLANE
CLOCK
RECEIVE
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
TRANSMIT
TRANSMIT
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTERLEAVE BUS
RATE CONVERSION
PAYLOAD LOOPBACK
BPCLK
RSYSCLK RCLK RSER RSIG RSIGF RSYNC RFSYNC RMSYNC RCHCLK RCHBLK RLCLK RLINK
TSYSCLK TCLK TSER TSIG TSYNC TSSYNC TCHCLK TCHBLK TLCLK TLINK
RLOS/LOTC
JTDI
JTAG
JTCLK
JTRST
JTMS
ESIBS0
ESIB
ESIBRDJTDO
ESIBS1
TPOSI
TCLKO
TNEGO
CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
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Figure 3-2. DS21455 Block Diagram
MCLK1 MCLK2
DS21455/DS21458 Quad T1/E1/J1 Transceivers
TRANSCEIVER #4
TRANSCEIVER #3
TRANSCEIVER #2
RTIP
RRING
TTIP
TRING
LIUC/TPD
8XCLK
MASTER
CLOCK
RECEIVE
LIU
CLOCK & DATA
RECOVERY
TRANSMIT
LIU
WAVESHAPE
GENERATION
JITTER
ATTEN.
TRANSMIT
OR RECEIVE
PATH
JITTER
ATTEN.
RPOSO
RNEGO
RCLKO
MUX
RPOSI
RNEGI
RCLKI
DS21455
2 HDLCs
MUX
ALARM MONITORING
SIGNALING EXTRACTION
HDB3/B8ZS DECODER
CRC RECALCULAION(E1)
SIGNALING INSERTION
2 HDLCs
BERT
RECEIVE FRAMER
SYNCHRONIZATION
HDLC EXTRACTION DS0 CONDITIONING
TRANSMIT
FRAMER
FRAMING
ALARM INSERTION
HDLC INSERTION
DS0 CONDITIONING
HDB3/B8ZS CODER
BERT
BACKPLANE
CLOCK
RECEIVE
BACKPLANE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTER LEAVE BUS
RATE CONVERSION
TRANSMIT
TRANSMIT
BACKPLANE
BACKPLANE
INTERFACE
INTERFACE
ELASTIC STORES
SIGNALING BUFFERS
INTER LEAVE BUS
RATE CONVERSION
BPCLK
RSYSCLK RCLK RSER RSIG RSIGF RSYNC RFSYNC RMSYNC RCHCLK RCHBLK RLCLK RLINK
TSYSCLK TCLK TSER TSIG TSYNC TSSYNC TCHCLK TCHBLK TLCLK TLINK
RLOS/LOTC
JTAG
JTCLK
JTDI
JTRST
JTMS
ESIBS0
ESIBS1
ESIB
ESIBRDJTDO
TPOSI
TPOSI TPOSI
TNEGI
TPOSO
TCLKI
TNEGO
TCLKO
CPU INTERFACE
MUX/NON-MUX, INTEL/MOTOROLA
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4. DS21455/DS21458 DELTA
This section describes the differences between the DS21455 and DS21458.
4.1 Package
DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the DS21Q55.)
DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA
4.2 Controller Interface
DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver.
DS21458: The CPU interface has 10 address lines with a single chip select. The upper address lines, A8
and A9, act as coded transceiver selects.
4.3 ESIB Function
The ESIB function provides a fast method of determining interrupt and alarm status when multiple ports (up to 8) are being controlled by a single processor.
DS21455: The three ESIB signals are brought out for each transceiver. The user must externally configure the ESIB group.
DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable the connection of another DS21458 into an 8-port ESIB.
4.4 Framer/LIU Interim Signals
Access to the clock and bipolar data signals between the framer and LIU function may be used for specialized applications. An internal MUX connects the framer and LIU if these signals are unused. The MUX is controlled via the LIUC/TPD pin and LIUC bit in the LBCR register. The unused inputs must be connected to ground.
DS21455: The user has access to all clock and data signals between the framer and LIU on all transceivers as shown in Figure 4-1
DS21458: The user has limited access to clock and data signals between the framer and LIU on all transceivers as shown in Figure 4-2
.
.
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Figure 4-1. DS21455 Framer/LIU Interim Signals
Rx
LIU
Tx
LIU
Rx
LIU
RPOSO RNEGO RCLKO
MUX
RPOSO RNEGO RCLKO
RPOSI RNEGI RCLKI
TPOSI TNEGI TCLKI
RPOSI RNEGI RCLKI
MUX
TPOSO TNEGO TCLKO
MUX
Rx
FRAMER
Tx
FRAMER
Rx
FRAMER
RPOSO RNEGO RCLKO
RPOSI RNEGI RCLKI
#1 #2
Rx
FRAMER
Rx
MUX
LIU
Tx
Tx
LIU
MUX
RPOSO RNEGO RCLKO
TPOSI TNEGI TCLKI
RPOSI RNEGI RCLKI
TPOSO TNEGO TCLKO
FRAMER
#4#3
Rx
FRAMER
Rx
MUX
LIU
Tx
LIU
MUX
TPOSI TNEGI TCLKI
TPOSO TNEGO TCLKO
Tx
FRAMER
Tx
FRAMER
LIUC
Tx
LIU
MUX
TPOSI TNEGI TCLKI
TPOSO TNEGO TCLKO
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Figure 4-2. DS21458 Framer/LIU Interim Signals
Rx
LIU
RPOSO1 RNEGO1 RCLKO1
Rx
FRAMER
#1
Rx
LIU
RPOSO2 RNEGO2 RCLKO2
#2
Rx
FRAMER
Tx
LIU
Rx
LIU
Tx
LIU
RPOSO3 RNEGO3 RCLKO3
TPOSO1 TNEGO1 TCLKO1
Tx
FRAMER
Rx
FRAMER
Tx
FRAMER
#3
Tx
LIU
Rx
LIU
Tx
LIU
Tx
FRAMER
TPOSO2 TNEGO2 TCLKO2
RPOSO4 RNEGO4 RCLKO4
#4
Rx
FRAMER
Tx
FRAMER
TPOSO3 TNEGO3 TCLKO3
TPOSO4 TNEGO4 TCLKO4
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5. PIN FUNCTION DESCRIPTION
5.1 Transmit Side Pins
Signal Name: Signal Description: Signal Type: A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter.
Signal Name: Signal Description: Signal Type: Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name: Signal Description: Signal Type: A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Can also be programmed to output a gated transmit-bit clock for fractional T1/E1 applications. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
Signal Name: Signal Description: Signal Type: A user-programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit-side elastic store is disabled. Synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning.
Signal Name: Signal Description: Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic-store function is enabled. Should be tied low in applications that do not use the transmit-side elastic store. See the Interleaved PCM Bus Operation section for details on 4.096MHz, 8.192MHz, and 16.384MHz operation using the IBO.
Signal Name: Signal Description: Signal Type: Demand clock for the transmit link data [TLINK] input. T1 Mode: A 4kHz or 2kHz (ZBTSI) clock. E1 Mode: A 4kHz to 20kHz clock.
Signal Name: Signal Description: Signal Type: If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs­bit position (D4) or the Z-bit position (ZBTSI) or any combination of the Sa bit positions (E1).
TCLK Transmit Clock Input
TSER Transmit Serial Data Input
TCHCLK Transmit Channel Clock Output
TCHBLK Transmit Channel Block Output
TSYSCLK Transmit System Clock Input
TLCLK Transmit Link Clock Output
TLINK Transmit Link Data Input
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Signal Name: Signal Description: Signal Type: A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to output double-wide pulses at signaling frames in T1 mode.
Signal Name: Signal Description: Signal Type: Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the transmit-side elastic store.
Signal Name: Signal Description: Signal Type: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of TCLK with data out of the transmit-side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA.
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of TCLK with data to be clocked through the transmit-side formatter. This pin is normally tied to TESO.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. Can be programmed to source NRZ data via the output-data format (IOCR1.0)-control bit. This pin is normally tied to TPOSI.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI.
Signal Name: Signal Description: Signal Type: Buffered clock that is used to clock data through the transmit-side formatter (either TCLK or RCLKI). This pin is normally tied to TCLKI.
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of this function TNEGI can be tied together in NRZ applications.
TSYNC Transmit Sync Input/Output
TSSYNC Transmit System Sync Input
TSIG Transmit Signaling Input Input
TESO Transmit Elastic Store-Data Output Output
TDATA Transmit Data Input
TPOSO Transmit Positive-Data Output Output
TNEGO Transmit Negative-Data Output Output
TCLKO Transmit Clock Output Output
TPOSI (DS21455 Only) Transmit Positive-Data Input Input
. TPOSI and
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Signal Name: Signal Description: Signal Type: Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function and TNEGI can be tied together in NRZ applications.
Signal Name: Signal Description: Signal Type: Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function.
TNEGI (DS21455 Only) Transmit Negative-Data Input Input
. TPOSI
TCLKI (DS21455 Only) Transmit Clock Input Input
5.2 Receive Side Pins
Signal Name: Signal Description: Signal Type: T1 Mode: Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. E1 Mode: Updated with the full E1 data stream on the rising edge of RCLK.
Signal Name: Signal Description: Signal Type: T1 Mode: A 4kHz or 2kHz (ZBTSI) clock for the RLINK output. E1 Mode: A 4kHz to 20kHz clock.
Signal Name: Signal Description: Signal Type:
1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer.
Signal Name: Signal Description: Signal Type: A 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel can also be programmed to output a gated receive-bit clock for fractional T1/E1 applications. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
Signal Name: Signal Description: Signal Type: A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. See the Channel Blocking Registers section.
Signal Name: Signal Description: Signal Type: Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
RLINK Receive Link Data Output
RLCLK Receive Link Clock Output
RCLK Receive Clock Output
RCHCLK Receive Channel Clock Output
RCHBLK Receive Channel Block Output
RSER Receive Serial Data Output
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Signal Name: Signal Description: Signal Type: An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input via IOCR1.4 at which a frame or multiframe boundary pulse is applied.
Signal Name: Signal Description: Signal Type: An extracted 8kHz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries.
Signal Name: Signal Description: Signal Type: An extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), is output at this pin, which identifies multiframe boundaries.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name: Signal Description: Signal Type:
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic-store function is enabled. Should be tied low in applications that do not use the receive-side elastic store. See the Interleaved PCM Bus Operation section for details on 4.096MHz and 8.192MHz operation using the IBO.
Signal Name: Signal Description: Signal Type: Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name: Signal Description: Signal Type: A dual-function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5ms.
Signal Name: Signal Description: Signal Type: Set high when the line interface detects a carrier loss.
Signal Name: Signal Description: Signal Type: Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert downstream equipment of the condition.
RSYNC Receive Sync Input/Output
RFSYNC Receive Frame Sync Output
RMSYNC Receive Multiframe Sync Output
RDATA Receive Data Output
RSYSCLK Receive System Clock Input
RSIG Receive Signaling Output Output
RLOS/LOTC Receive Loss of Sync/Loss of Transmit Clock Output
RCL Receive Carrier Loss Output
RSIGF Receive Signaling Freeze Output
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Signal Name: Signal Description: Signal Type: A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Signal Name: Signal Description: Signal Type: Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RNEGI.
Signal Name: Signal Description: Signal Type: Buffered recovered clock from the network. This pin is normally tied to RCLKI.
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function.
Signal Name: Signal Description: Signal Type: Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function.
Signal Name: Signal Description: Signal Type: Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function
BPCLK Backplane Clock Output
RPOSO Receive Positive-Data Output Output
RNEGO Receive Negative-Data Output Output
RCLKO Receive Clock Output Output
RPOSI (DS21455 Only) Receive Positive Data Input Input
RNEGI (DS21455 Only) Receive Negative Data Input Input
RCLKI (DS21455 Only) Receive Clock Input Input
.
5.3 Parallel Control Port Pins
Signal Name: Signal Description: Signal Type: Flags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.
Signal Name: Signal Description: Signal Type: A dual-function pin. A zero-to-one transition issues a hardware reset to the DS21455/DS21458 register set. A reset clears all configuration registers. Configuration register contents are set to zero. Leaving TSTRST high will tri-state all output and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing.
INT
Interrupt Output
TSTRST Tri-State Control and Device Reset Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name: Signal Description: Signal Type:
MUX Bus Operation Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name: Signal Description: Signal Type:
AD0 to AD7 Data Bus [D0 to D7] or Address/Data Bus Input/Output
In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an 8-bit, multiplexed address/data bus.
Signal Name: Signal Description: Signal Type:
A0 to A6 Address Bus Input
In nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Signal Name: Signal Description: Signal Type:
A8 and A9 (DS21458 Only) Address Bus Input
Upper address pins for nonmultiplexed (MUX = 0), and multiplexed (MUX = 1) bus operation,.
Signal Name: Signal Description: Signal Type: Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the ALE (AS), and
WR (R/W) pins. If BTS = 1, then these pins assume the function listed in parentheses ().
BTS Bus Type Select Input
RD (DS),
Signal Name: Signal Description: Signal Type:
RD and DS are active-low signals. DS active HIGH when MUX = 0. See the bus timing diagrams.
RD (DS)
Read Input-Data Strobe Input
Signal Name: Signal Description: Signal Type: Must be low to read or write to Transceiver 1 of the device.
CS1 (DS21455 Only)
Chip Select for Transceiver 1 Input
CS1 is an active-low signal.
Signal Name: Signal Description: Signal Type: Must be low to read or write to Transceiver 2 of the device.
CS2 (DS21455 Only)
Chip Select for Transceiver 2 Input
CS2 is an active-low signal.
Signal Name: Signal Description: Signal Type: Must be low to read or write to Transceiver 3 of the device.
CS3 (DS21455 Only)
Chip Select for Transceiver 3 Input
CS3 is an active-low signal.
Signal Name: Signal Description: Signal Type: Must be low to read or write to Transceiver 4 of the device.
CS4 (DS21455 Only)
Chip Select for Transceiver 4 Input
CS4 is an active-low signal.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name: Signal Description: Signal Type: Must be low to read or write to the device.
Signal Name: Signal Description: Signal Type: In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge.
Signal Name: Signal Description: Signal Type:
WR is an active-low signal.
CS (DS21458 Only)
Chip Select Input
CS is an active-low signal.
ALE (AS)/A7 Address Latch Enable (Address Strobe) or A7 Input
WR (R/W)
Write Input (Read/Write) Input
5.4 Extended System Information Bus
Signal Name: Signal Description: Signal Type: Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
Signal Name: Signal Description: Signal Type: Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
Signal Name: Signal Description: Signal Type: Used to group two DS21455/DS21458s into a bus-sharing mode for alarm and status reporting. See the Extended System Information Bus (ESIB) section for more details.
ESIBS0 Extended System Information Bus Select 0 Input/Output
ESIBS1 Extended System Information Bus Select 1 Input/Output
ESIBRD Extended System Information Bus Read Input/Output
5.5 JTAG Test Access Port Pins
Signal Name: Signal Description: Signal Type: JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST low. JTRST is pulled HIGH internally via a 10kW resistor operation.
Signal Name: Signal Description: Signal Type: This pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1 states. This pin has a 10kW pullup resistor.
JTRST IEEE 1149.1 Test Reset Input
JTMS IEEE 1149.1 Test Mode Select Input
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
Signal Name: Signal Description: Signal Type: This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name: Signal Description: Signal Type: Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor.
Signal Name: Signal Description: Signal Type: Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.
JTCLK IEEE 1149.1 Test Clock Signal Input
JTDI IEEE 1149.1 Test Data Input Input
JTDO IEEE 1149.1 Test Data Output Output
5.6 Line Interface Pins
Signal Name: Signal Description: Signal Type: A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name: Signal Description: Signal Type: A (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 and E1 modes. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS21455/DS21458 in T1-only operation a 1.544MHz (50ppm) clock source can be used. MCLK1 and MCLK2 can be driven from a common clock.
Signal Name: Signal Description: Signal Type: This is a dual function pin depending on the state of the LTS bit in the LBCR register (LBCR.7).
MCLK1 Master Clock Input for Transceivers 1 and 2 Input
MCLK2 Master Clock Input for Transceivers 3 and 4 Input
LIUC/TPD (DS21455), TPD (DS21458) Line Interface Unit Connect/Transmit Power-Down Input
LTS = 0: In this mode the LIUC/TPD pin, along with the LIUC bit of the LBCR register controls the connection between the
framer and the LIU. This function is only available on the DS21455
Table 14-1
LTS = 1: In this mode the LIUC/TPD pin along with the TPD bit in the LIC1 register (LIC1.0) controls the state of the Transmit Power-Down function. See the TPD bit description in Section 25
Signal Name: Signal Description: Signal Type: Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Section 25
Signal Name: Signal Description: Signal Type: Analog line-driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Section 25
.
RTIP and RRING Receive Tip and Ring Input
TTIP and TRING Transmit Tip and Ring Output
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. See the LIUC bit description in Section 14 and
and Table 25-1.
for details.
for details.
5.7 Supply Pins
Signal Name: Signal Description: Signal Type:
3.3V ±5%. Should be tied to the RVDD and TVDD pins.
Signal Name: Signal Description: Signal Type:
3.3V ±5%. Should be tied to the DVDD and TVDD pins.
Signal Name: Signal Description: Signal Type:
3.3V ±5% Should be tied to the RVDD and DVDD pins.
Signal Name: Signal Description: Signal Type: Supply Should be tied to the RVSS and TVSS pins.
Signal Name: Signal Description: Signal Type:
0.0V. Should be tied to DVSS and TVSS.
Signal Name: Signal Description: Signal Type:
0.0V. Should be tied to DVSS and RVSS.
DVDD Digital Positive Supply Supply
RVDD Receive Analog Positive Supply Supply
TVDD Transmit Analog Positive Supply Supply
DVSS Digital Signal Ground
RVSS Receive Analog Signal Ground Supply
TVSS Transmit Analog Signal Ground Supply
DS21455/DS21458 Quad T1/E1/J1 Transceivers
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
5.8 Pin Descriptions
Table 5-1. DS21455 PIN DESCRIPTION
PIN NAME TYPE FUNCTION
U3 A0 I Address Bus Bit 0 (Lsb)
L17 A1 I Address Bus Bit 1
V2 A2 I Address Bus Bit 2 T4 A3 I Address Bus Bit 3 V8 A4 I Address Bus Bit 4 H4 A5 I Address Bus Bit 5 U8 A6 I Address Bus Bit 6
P4 A7/ALE (AS) I Address Bus Bit 7 (Msb)/Address Latch Enable
M1 BPCLK1 O Backplane Clock, Transceiver 1
H17 BPCLK2 O Backplane Clock, Transceiver 2
F4 BPCLK3 O Backplane Clock, Transceiver 3
V13 BPCLK4 O Backplane Clock, Transceiver 4
P2 BTS I Bus Type Select (0 = Intel/1 = Motorola) P3
A14
B5 K17 U11 D0/AD0 I/O Data Bus Bit 0/Address/Data Bus Bit 0 (Lsb)
J19 D1/AD1 I/O Data Bus Bit 1/Address/Data Bus Bit 1
W15 D2/AD2 I/O Data Bus Bit 2/Address/Data Bus Bit 2
U7 D3/AD3 I/O Data Bus Bit 3/Address/Data Bus Bit 3
U9 D4/AD4 I/O Data Bus Bit 4/Address/Data Bus Bit 4
U5 D5/AD5 I/O Data Bus Bit 5/Address/Data Bus Bit 5
V4 D6/AD6 I/O Data Bus Bit 6/Address/Data Bus Bit 6
U4 D7/AD7 I/O Data Bus Bit 7/Address/Data Bus Bit 7 (Msb)
J3 DVDD Digital Positive Supply N4 DVDD Digital Positive Supply U2 DVDD Digital Positive Supply V5 DVDD Digital Positive Supply
B12 DVDD Digital Positive Supply C12 DVDD Digital Positive Supply C16 DVDD Digital Positive Supply D18 DVDD Digital Positive Supply
A9 DVDD Digital Positive Supply B3 DVDD Digital Positive Supply B6 DVDD Digital Positive Supply C4 DVDD Digital Positive Supply
G20 DVDD Digital Positive Supply M17 DVDD Digital Positive Supply M20 DVDD Digital Positive Supply
P18 DVDD Digital Positive Supply
H3 DVSS — Digital Signal Ground U6 DVSS — Digital Signal Ground
W8 DVSS — Digital Signal Ground A17 DVSS — Digital Signal Ground A20 DVSS — Digital Signal Ground B11 DVSS — Digital Signal Ground
A5 DVSS — Digital Signal Ground
CS1 CS2 CS3 CS4
I Chip Select for Transceiver 1 I Chip Select for Transceiver 2 I Chip Select for Transceiver 3 I Chip Select for Transceiver 4
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DS21455/DS21458 Quad T1/E1/J1 Transceivers
PIN NAME TYPE FUNCTION
B7 DVSS — Digital Signal Ground
B9 DVSS — Digital Signal Ground H20 DVSS — Digital Signal Ground L20 DVSS — Digital Signal Ground N17 DVSS — Digital Signal Ground
J4 ESIBRD1 I/O Extended System Information Bus Read for Transceiver 1
C13 ESIBRD2 I/O Extended System Information Bus Read for Transceiver 2
C3 ESIBRD3 I/O Extended System Information Bus Read for Transceiver 3 U13 ESIBRD4 I/O Extended System Information Bus Read for Transceiver 4
W6 ESIBS0_1 I/O Extended System Information Bus 0 for Transceiver 1 F18 ESIBS0_2 I/O Extended System Information Bus 0 for Transceiver 2
D7 ESIBS0_3 I/O Extended System Information Bus 0 for Transceiver 3 T20 ESIBS0_4 I/O Extended System Information Bus 0 for Transceiver 4
V9 ESIBS1_1 I/O Extended System Information Bus 1 for Transceiver 1 B17 ESIBS1_2 I/O Extended System Information Bus 1 for Transceiver 2
A6 ESIBS1_3 I/O Extended System Information Bus 1 for Transceiver 3
J20 ESIBS1_4 I/O Extended System Information Bus 1 for Transceiver 4
U1
INT
Interrupt for All Four Transceivers
O
Y15 JTCLK I JTAG Clock
N1 JTDI I JTAG Data Input V19 JTDO O JTAG Data Output
W13 JTMS I JTAG Test Mode Select
V18 JTRST I Jtag Reset
K2 LIUC/TPD I Line Interface Connect for All Four Transceivers or Transmit Power-Down Enable
T1 MCLK1 I Master Clock for Transceiver 1 and Transceiver 3
W20 MCLK2 I Master Clock for Transceiver 2 and Transceiver 4
U10 MUX I Mux Bus Select
M2 RCHBLK1 O Receive Channel Block for Transceiver 1
G17 RCHBLK2 O Receive Channel Block for Transceiver 2
G4 RCHBLK3 O Receive Channel Block for Transceiver 3 Y12 RCHBLK4 O Receive Channel Block for Transceiver 4
J1 RCHCLK1 O Receive Channel Clock for Transceiver 1
D14 RCHCLK2 O Receive Channel Clock for Transceiver 2
F3 RCHCLK3 O Receive Channel Clock for Transceiver 3
U14 RCHCLK4 O Receive Channel Clock for Transceiver 4
N3 RCLK1 O Receive Clock Output from the Framer on Transceiver 1 B13 RCLK2 O Receive Clock Output from the Framer on Transceiver 2
E3 RCLK3 O Receive Clock Output from the Framer on Transceiver 3
M18 RCLK4 O Receive Clock Output from the Framer on Transceiver 4
M4 RCLKI1 I Receive Clock Input for the LIU on Transceiver 1
A15 RCLKI2 I Receive Clock Input for the LIU on Transceiver 2
A4 RCLKI3 I Receive Clock Input for the LIU on Transceiver 3 R17 RCLKI4 I Receive Clock Input for the LIU on Transceiver 4
M3 RCLKO1 O Receive Clock Output from the LIU on Transceiver 1
C14 RCLKO2 O Receive Clock Output from the LIU on Transceiver 2
B4 RCLKO3 O Receive Clock Output from the LIU on Transceiver 3 T17 RCLKO4 O Receive Clock Output from the LIU On Transceiver 4
N2
RD (DS)
I Read Input (Data Strobe)
K4 RFSYNC1 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 1 D17 RFSYNC2 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 2
A2 RFSYNC3 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 3 V14 RFSYNC4 O Receive Frame Sync (Before the Receive Elastic Store) for Transceiver 4
F1 RLCLK1 O Receive Link Clock for Transceiver 1
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