MAXIM DS21348, DS21Q348 User Manual

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FEATURES

DS21348/DS21Q348

3.3V E1/T1/J1 Line Interface

PIN CONFIGURATIONS

 Complete E1, T1, or J1 Line Interface Unit

(LIU)

 Supports Both Long-Haul And Short-Haul

Trunks

 Internal Software-Selectable Receive-Side

Termination for 75Ω/100Ω/120Ω

 3.3V Power Supply  32-Bit or 128-Bit Crystal-Less Jitter

Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.544MHz for T1

 Generates the Appropriate Line Build-Outs,

with and without Return loss, for E1 and DSX-1 and CSU Line Build-Outs for T1

 AMI, HDB3, and B8ZS, Encoding/Decoding  16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz Clock Output Synthesized to Recovered Clock

 Programmable Monitor Mode for Receiver  Loopbacks and PRBS Pattern Generation/

Detection with Output for Received Errors

 Generates/Detects In-Band Loop Codes,

1 to 16 Bits Including CSU Loop Codes

 8-Bit Parallel or Serial Interface with

Optional Hardware Mode

 Muxed and Nonmuxed Parallel Bus Supports

Intel or Motorola

 Detects/Generates Blue (AIS) Alarms  NRZ/Bipolar Interface for Tx/Rx Data I/O  Transmit Open-Circuit Detection  Receive Carrier Loss (RCL) Indication

(G.775)

 High-Impedance State for TTIP and TRING  50mA (RMS) Current Limiter

TOP VIEW

DS21348

44 TQFP

DS21Q348

49 CSBGA

(7mm x 7mm)

See Section 8 for 144-pin CSBGA pinout.

ORDERING INFORMATION

PART CHANNEL

DS21348TN Single -40°C to +85°C 44 TQFP

DS21348TN+ Single -40°C to +85°C 44 TQFP

DS21348T Single 0°C to +70°C 44 TQFP DS21348T+ Single 0°C to +70°C 44 TQFP DS21348GN Single -40°C to +85°C 49 CSBGA

DS21348GN+ Single -40°C to +85°C 49 CSBGA DS21348G Single 0°C to +70°C 49 CSBGA DS21348G+ Single 0°C to +70°C 49 CSBGA

DS21Q348N Four -40°C to +85°C 144 CSBGA DS21Q348 Four 0°C to +70°C 144 CSBGA

+ Denotes lead-free/RoHS-compliant package.

TEMP

RANGE

PIN-PACKAGE

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

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DS21348/DS21Q348

DETAILED DESCRIPTION

The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1 waveshapes in 75Ω or 120Ω applications and DSX-1 line build-outs or CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK is available for use as a backplane system clock (where n = 1, 2, 4, or 8).

The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an 8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12, TBR13, and CTR4.

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DS21348/DS21Q348

1. INTRODUCTION.................................................................................................................. 6

1.1 DOCUMENT REVISION HISTORY...............................................................................................6

2. PIN DESCRIPTION............................................................................................................ 10

2.1 PIN DESCRIPTIONS ........................................................................................................................14

3. HARDWARE MODE .......................................................................................................... 25

3.1 REGISTER MAP .............................................................................................................................25

3.2 PARALLEL PORT OPERATION .........................................................................................................26

3.3 SERIAL PORT OPERATION..............................................................................................................26

4. CONTROL REGISTERS.................................................................................................... 29

4.1 DEVICE POWER-UP AND RESET .....................................................................................................32

5. STATUS REGISTERS ....................................................................................................... 36

6. DIAGNOSTICS .................................................................................................................. 41

6.1 IN-BAND LOOP CODE GENERATION AND DETECTION ......................................................................41

6.2 LOOPBACKS ..................................................................................................................................46

6.2.1 Remote Loopback (RLB) .....................................................................................................................46

6.2.2 Local Loopback (LLB) .......................................................................................................................... 46

6.2.3 Analog Loopback (ALB) ....................................................................................................................... 46

6.2.4 Dual Loopback (DLB)........................................................................................................................... 46

6.3 PRBS GENERATION AND DETECTION ............................................................................................47

6.4 ERROR COUNTER..........................................................................................................................47

6.4.1 Error Counter Update........................................................................................................................... 48

6.5 ERROR INSERTION ........................................................................................................................48

7. ANALOG INTERFACE ...................................................................................................... 49

7.1 RECEIVER .....................................................................................................................................49

7.2 TRANSMITTER ...............................................................................................................................50

7.3 JITTER ATTENUATOR .....................................................................................................................50

7.4 G.703 SYNCHRONIZATION SIGNAL .................................................................................................51

8. DS21Q348 QUAD LIU ....................................................................................................... 58

9. DC CHARACTERISTICS................................................................................................... 62

10. THERMAL CHARACTERISTICS....................................................................................... 63

11. AC CHARACTERISTICS................................................................................................... 64

12. PACKAGE INFORMATION ............................................................................................... 73

12.1 44-PIN TQFP (56-G4012-001) .....................................................................................................73

12.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001) ...........................................................................74

12.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001) .....................................................................75

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DS21348/DS21Q348

LIST OF FIGURES

Figure 1-1. DS21348 Block Diagram..........................................................................................................7

Figure 1-2. Receive Logic...........................................................................................................................8

Figure 1-3. Transmit Logic..........................................................................................................................9

Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package) .................................. 22

Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package) ............................................ 23

Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) .............................................24

Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 ......................................................... 27

Figure 3-2. Serial Port Operation for Read Access Mode 2 .....................................................................27

Figure 3-3. Serial Port Operation for Read Access Mode 3 .....................................................................27

Figure 3-4. Serial Port Operation for Read Access Mode 4 .....................................................................28

Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2..............................................28

Figure 3-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4..............................................28

Figure 7-1. Basic Interface .......................................................................................................................52

Figure 7-2. Protected Interface Using Internal Receive Termination........................................................ 53

Figure 7-3. Protected Interface Using External Receive Termination.......................................................54

Figure 7-4. E1 Transmit Pulse Template..................................................................................................55

Figure 7-5. T1 Transmit Pulse Template ..................................................................................................56

Figure 7-6. Jitter Tolerance ......................................................................................................................57

Figure 7-7. Jitter Attenuation .................................................................................................................... 57

Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout .....................................................................................61

Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) ....................................................... 65

Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) .......................................................65

Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = 0).......................................................... 66

Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) ....................................................... 68

Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) .......................................................68

Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................69

Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) ................................................ 69

Figure 11-8. Serial Bus Timing (BIS1 = 1, BIS0 = 0)................................................................................70

Figure 11-9. Receive Side Timing ............................................................................................................71

Figure 11-10. Transmit Side Timing .........................................................................................................72

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DS21348/DS21Q348

LIST OF TABLES

Table 2-1. Bus Interface Selection ...........................................................................................................10

Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10

Table 2-3. Pin Assignment in Serial Port Mode........................................................................................11

Table 2-4. Pin Assignment in Hardware Mode .........................................................................................12

Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering).....14

Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering) .......16

Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering) ........ 18

Table 2-8. Loopback Control in Hardware Mode......................................................................................21

Table 2-9. Transmit Data Control in Hardware Mode...............................................................................21

Table 2-10. Receive Sensitivity Settings ..................................................................................................21

Table 2-11. Monitor Gain Settings............................................................................................................21

Table 2-12. Internal Rx Termination Select ..............................................................................................21

Table 2-13. MCLK Selection.....................................................................................................................22

Table 3-1. Register Map ...........................................................................................................................25

Table 4-1. MCLK Selection.......................................................................................................................30

Table 4-2. Receive Equalizer Sensitivity Settings ....................................................................................32

Table 4-3. Backplane Clock Select...........................................................................................................34

Table 4-4. Monitor Gain Settings..............................................................................................................34

Table 4-5. Internal Rx Termination Select ................................................................................................34

Table 5-1. Received Alarm Criteria ..........................................................................................................36

Table 5-2. Receive Level Indication .........................................................................................................40

Table 6-1. Transmit Code Length.............................................................................................................41

Table 6-2. Receive Code Length..............................................................................................................42

Table 6-3. Definition of Received Errors...................................................................................................47

Table 6-4. Function of ECRS Bits and RNEG Pin ....................................................................................48

Table 7-1. Line Build-Out Select for E1 in Register CCR4 (ETS = 0)....................................................... 51

Table 7-2. Line Build-Out Select for T1 in Register CCR4 (ETS = 1)....................................................... 51

Table 7-3. Transformer Specifications for 3.3V Operation .......................................................................51

Table 8-1. DS21Q348 Pin Assignment..................................................................................................... 58

Table 9-1. Recommended DC Operating Conditions ...............................................................................62

Table 9-2. Capacitance ............................................................................................................................62

Table 9-3. DC Characteristics ..................................................................................................................62

Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package.......................................................63

Table 10-2. Theta-JA (θJA) vs. Airflow.......................................................................................................63

Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) ..................................... 64

Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1)...............................67

Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) ...........................................................70

Table 11-4. AC Characteristics—Receive Side........................................................................................71

Table 11-5. AC Characteristics—Transmit Side.......................................................................................72

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DS21348/DS21Q348

1. INTRODUCTION

The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination. The device recovers clock and data from the analog signal and passes it through the jitter attenuation MUX outputting the received line clock at RCLK and bipolar or NRZ data at RPOS and RNEG. The DS21348 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive circuitry is also configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input at TPOS and TNEG is sent via the jitter attenuation mux to the waveshaping circuitry and line driver. The DS21348 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1.

1.1 Document Revision History

REVISION DESCRIPTION

011801 Data sheet revised for 3.3V only.

092101

101104 Corrected typos and removed all instances of 5V operation.

113004

011206 Added lead-free packages to Ordering Information table on page 1.

Added supply current measurements Added thermal characteristics of quad package

Updated the storage and soldering temperature specs in the Absolute Maximum Ratings section.

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Figure 1-1. DS21348 Block Diagram

DS21348/DS21Q348

RRING

RTIP

TRING

TTIP

BIS1

BIS0

VSS

Power Connections

VSM

VDD

JACLK

VCO / PLL

Termination

Optional

nalog Loopback

MUX (the Serial, Parallel, and Hardware Interfaces share device pins)

Filte

Unframed Insertion

Line Drivers

Peak Detect

ll Ones

CSU Filters

Recovery

Clock / Data

Remote Loopback (Dual Mode)

Wave Shaping

Jitter

ttenuato

MUX

Local Loopback

Jitter Attenuation

(can be placed in either transmit or receive path)

MCLK

2.048MHz to

1.544MHz PLL

Remote Loopback

16.384MHz or

8.192MHz or

4.096MHz or

2.048MHz Synthesizer

M U

See Figure 3-2

MUX RCL/LOTC

See Figure 1-3

Control and Test Port

(routed to all blocks)

BPCLK

RPOS

RCLK

RNEG

PBEO

TPOS TCLK

TNEG

RST

TEST

Serial Interface

SDI

SCLK

DS21348

Hardware

Interface

D0 to D7 /

D0 to AD7

Control and

Interrupt

Parallel Interface

SDO

PBTS

R(R/W)

LE(AS)

D(DS)

0 to A4

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Figure 1-2. Receive Logic

DS21348/DS21Q348

From Remote Loopback

Routed to All Blocks

4 or 8 Zero Detect

16 Zero Detect

RIR1.7 RIR1.6

Clock Invert

CCR2.0

CCR2.3

CCR6.2/ CCR6.0/ CCR6.1

B8ZS/HDB3 Decoder

RIR1.5

All Ones Detector

NRZ Data

BPV/CV/EXZ

Loop Code Detector

SR.6 SR.7SR.4 RIR1.3

PRBS Detector

SR.0

CCR1.4

mux

16-Bit Error Counter (ECR)

RCLK

RPOS

mux

RNEG

CCR1.6

PBEO

CCR6.0

rx bd

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Figure 1-3. Transmit Logic

DS21348/DS21Q348

To Remote Loopback

CCR3.1

BPV Insert

Routed to All Blocks

CCR1.6

OR Gate

mux

CCR3.4

PRBS Generator

Loop Code Generator

JACLK (derived from MCLK)

OR Gate

Clock Invert

CCR2.1

TPOS

TNEG

TCLK

CCR3.3

CCR2.2

CCR3.0

mux

B8ZS/ HDB3 Coder

RCLK

mux

OR Gate

Logic Error Insert

CCR1.1

CCR1.2

AND Gate

CCR1.0

To LOTC Output Pin

Loss Of Transmit Clock Detect

SR.5

tx bd

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DS21348/DS21Q348

2. PIN DESCRIPTION

The DS21348 can be controlled in a parallel port mode, serial port mode, or hardware mode (Table 2-2,

Table 2-3, and Table 2-4).

Table 2-1. Bus Interface Selection

BIS1 BIS0 PBTS MODE

0 0 0 Muxed Intel 0 0 1 Muxed Motorola 0 1 0 Nonmuxed Intel 0 1 1 Nonmuxed Motorola 1 0 — Serial Port 1 1 — Hardware

Table 2-2. Pin Assignment in Parallel Port Mode

DS21348T DS21348G

C3 I

I/O

2 C2 I 3 B1 I

PARALLEL

PORT MODE

RD (DS)

WR (R/W)

4 D2 I ALE (AS) 5 C1 I NA 6 D3 I NA 7 D1 I/O A4 8 E1 I A3

9 F2 I A2 10 F1 I A1 11 G1 I A0 12 E3 I/O D7/AD7 13 F3 I/O D6/AD6 14 G2 I/O D5/AD5 15 F4 I/O D4/AD4 16 G3 I/O D3/AD3 17 E4 I/O D2/AD2 18 G4 I/O D1/AD1 19 F5 I/O D0/AD0 20 G5 I VSM 21 F6 — VDD 22 G6 — VSS 23 E5 I/O

INT

24 E6 O PBEO 25 F7 O RCL/LOTC 26 D6 I TEST 27 D5 I RTIP

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DS21348T DS21348G

28 D7 I RRING 29 C6 I 30 C7 I MCLK 31 B6 O BPCLK 32 B7 I BIS0 33 A7 I BIS1 34 C5 O TTIP 35 B5 — VSS 36 A6 — VDD 37 B4 O TRING 38 C4 O RPOS 39 A4 O RNEG 40 B3 O RCLK 41 A3 I TPOS 42 B2 I TNEG 43 A2 I TCLK 44 A1 I PBTS

I/O

DS21348/DS21Q348

PARALLEL

PORT MODE

HRST

Table 2-3. Pin Assignment in Serial Port Mode

DS21348T DS21348G

C3 I

I/O

2 C2 I NA

3 B1 I NA

4 D2 I NA

5 C1 I SCLK

6 D3 I SDI

7 D1 I/O SDO

8 E1 I ICES

9 F2 I OCES 10 F1 I NA 11 G1 I NA 12 E3 I/O NA 13 F3 I/O NA 14 G2 I/O NA 15 F4 I/O NA 16 G3 I/O NA 17 E4 I/O NA 18 G4 I/O NA 19 F5 I/O NA 20 G5 I VSM 21 F6 — VDD 22 G6 — VSS

SERIAL

PORT MODE

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DS21348T DS21348G

I/O

23 E5 I/O

SERIAL

PORT MODE

INT

24 E6 O PBEO 25 F7 O RCL/LOTC 26 D6 I TEST 27 D5 I RTIP 28 D7 I RRING 29 C6 I

HRST

30 C7 I MCLK 31 B6 O BPCLK 32 B7 I BIS0 33 A7 I BIS1 34 C5 O TTIP 35 B5 — VSS 36 A6 — VDD 37 B4 O TRING 38 C4 O RPOS 39 A4 O RNEG 40 B3 O RCLK 41 A3 I TPOS 42 B2 I TNEG 43 A2 I TCLK 44 A1 I NA

DS21348/DS21Q348

Table 2-4. Pin Assignment in Hardware Mode

I/O

DS21348T DS21348G

C3 I EGL 2 C2 I ETS 3 B1 I NRZE 4 D2 I SCLKE 5 C1 I L2 6 D3 I L1 7 D1 I/O L0 8 E1 I DJA 9 F2 I JAMUX

10 F1 I JAS 11 G1 I HBE 12 E3 I/O CES 13 F3 I/O TPD 14 G2 I/O TX0 15 F4 I/O TX1 16 G3 I/O LOOP0

HARDWARE

MODE

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DS21348T DS21348G

17 E4 I/O LOOP1 18 G4 I/O MM0 19 F5 I/O MM1 20 G5 I VSM 21 F6 — VDD 22 G6 — VSS 23 E5 I/O RT1 24 E6 O PBEO 25 F7 O RCL 26 D6 I TEST 27 D5 I RTIP 28 D7 I RRING 29 C6 I 30 C7 I MCLK 31 B6 O BPCLK 32 B7 I BIS0 33 A7 I BIS1 34 C5 O TTIP 35 B5 — VSS 36 A6 — VDD 37 B4 O TRING 38 C4 O RPOS 39 A4 O RNEG 40 B3 O RCLK 41 A3 I TPOS 42 B2 I TNEG 43 A2 I TCLK 44 A1 I RT0

I/O

DS21348/DS21Q348

HARDWARE

MODE

HRST

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DS21348/DS21Q348

2.1 Pin Descriptions Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,

DS21348T Pin Numbering)

NAME PIN I/O FUNCTION

Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 =

A0 to A4 11 to 7 I

ALE (AS) 4 I

BIS0/BIS1 32/33 I

BPCLK 31 O

D0/AD0 to

D7/AD7

HRST

INT

1 I

19 to 12 I/O

29 I

23 O

MCLK 30 I

N/A — I Not Assigned. Should be tied low.

PBEO 24 O

1), serves as the address bus. In multiplexed bus operation (BIS1 = 0, BIS0 = 0), these pins are not used and should be tied low. Address Latch Enable (Address Strobe). When using the parallel port (BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to demultiplex the bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1), should be tied low. Bus Interface Select Bits 0 and 1. Used to select bus interface option. See Table 2-1

for details.

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz output. Chip Select, Active Low. This active-low signal must be low to read or write to the device. Data Bus/Address/Data Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 = 0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus. Hardware Reset, Active Low. Bringing HRST low resets the DS21348, setting all control bits to their default state of all zeros. Interrupt, Active Low. Flags host controller during conditions and change of conditions defined in the Status Register. Active low, open drain output. Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is optional.

PRBS Bit Error Output. The receiver will constantly search for a 215-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if out of synchronization with the PRBS pattern. Goes low when synchronized to the PRBS pattern. Any errors in the received pattern after synchronization will cause a positive going pulse (with same period as E1 or T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.

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NAME PIN I/O FUNCTION

Parallel Bus Type Select. When using the parallel port (BIS1 = 0),

set high to select Motorola bus timing, set low to select Intel bus

PBTS 44 I

timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins. If PBTS = 1 and BIS1 = 0, then these pins assume the Motorola function listed in parentheses (). In serial port mode, this pin should be tied low.

RCLK 40 O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING. Read Input (Data Strobe), Active Low. DS is active low when in

RD (DS)

2 I

nonmultiplexed, Motorola mode. See the bus timing diagrams in Section 11. Receive Carrier Loss/Loss of Transmit Clock. An output which

RCL/

LOTC

25 O

will toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high if the TCLK pin has not been toggled for 5 µsec ± 2 µsec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware

mode. Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out

RNEG 39 O

of the line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ mode, data will be output on RPOS while a received error will cause a positive-going pulse synchronous with RCLK at RNEG. See Section 6.4 for details. Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the

RPOS 38 O

line interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ mode, data will be output on RPOS while a received error will cause a positive-going pulse synchronous with RCLK at RNEG. See Section 6.4 for details.

RTIP/

RRING

27/28 I

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the line. See Section 5 for details. Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to

TCLK 43 I

clock data through the transmit side formatter. Can be sourced internally by MCLK or RCLK. See Common Control Register 1 and

Figure 1-3.

Tri-State Control. Set high to tri-state all outputs and I/O pins

TEST 26 I

(including the parallel control port). Set low for normal operation. Useful in board level testing. Transmit Negative Data. Sampled on the falling edge (CCR2.1 =

TNEG 42 I

0) or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the line. Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)

TPOS 41 I

or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.

DS21348/DS21Q348

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NAME PIN I/O FUNCTION

DS21348/DS21Q348

TTIP/

TRING

34/37 O

Transmit Tip and Ring [TTIP AND TRING]. Analog line driver outputs. These pins connect via a step-up transformer to the line. See Section 5

for details. VDD 21/36 — Positive Supply. 3.3V ±5% VSM 20 I Voltage Supply Mode. Should be low for 3.3V operation.

VSS 22/35 —

WR (R/W)

3 I

Signal Ground Write Input (Read/Write), Active Low. See the bus timing

diagrams in Section 11.

Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering)

NAME PIN I/O FUNCTION

BIS0/BIS1 32/33 I

BPCLK 31 O

HRST

1 I

29 I

ICES 8 I

INT

23 O

MCLK 30 I

NA — I Not Assigned. Should be tied low.

OCES 9 I

PBEO 24 O

Bus Interface Select Bits 0 and 1. Used to select bus interface option. See Table 2-1 for details. Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz clock output that is referenced to RCLK selectable via CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz output. Chip Select, Active Low. Active-low signal must be low to read or write to the device. Hardware Reset, Active Low. Bringing HRST low will reset the DS21348 setting all control bits to their default state of all zeros. Input Clock Edge Select. Selects whether the serial port data input (SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of SCLK. Interrupt, Active Low. Flags host controller during conditions and change of conditions defined in the Status Register. Active-low, open-drain output. Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is optional.

Output Clock Edge Select. Selects whether the serial port data output (SDO) is valid on the rising (OCES = 1) or falling edge (OCES = 0) of SCLK. PRBS Bit Error Output. The receiver will constantly search for a

-1 or a 220-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if out of synchronization with the PRBS pattern. Goes low when synchronized to the PRBS pattern. Any errors in the received pattern after synchronization will cause a positive going pulse (with same period as E1 or T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.

16 of 76

NAME PIN I/O FUNCTION

DS21348/DS21Q348

RCLK 40 O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING. Receive Carrier Loss/Loss of Transmit Clock. An output which

RCL/LOTC 25 O

will toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high if the TCLK pin has not been toggled for 5µs ± 2µs

(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode. Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out

RNEG 39 O

RPOS 38 O

RTIP/

RRING

27/28 I

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the line. See Section 5 for details.

SCLK 5 I Serial Clock. Serial bus clock input.

SDI 6 I

SDO 7 O

Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge (ICES = 1) of SCLK. Serial Data Output. Valid on the falling edge (OCES = 0) or the rising edge (OCES = 1) of SCLK. Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to

TCLK 43 I

clock data through the transmit side formatter. Can be sourced internally by MCLK or RCLK. See Common Control Register 1 and

Figure 1-3

Tri-State Control. Set high to tri-state all outputs and I/O pins

TEST 26 I

(including the parallel control port). Set low for normal operation. Useful in board-level testing. Transmit Negative Data. Sampled on the falling edge (CCR2.1 =

TNEG 42 I

0) or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the line. Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0)

TPOS 41 I

or the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.

TTIP/TRIN

34/37 O

Transmit Tip and Ring [TTIP and TRING]. Analog line-driver outputs. These pins connect via a step-up transformer to the line. See Section 5 for details.

VDD 21/36 — Positive Supply. 3.3V ±5% VSM 20 I Voltage Supply Mode. Should be tied low for 3.3V operation.

VSS 22/35 —

Signal Ground

17 of 76

DS21348/DS21Q348

Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering)

NAME PIN I/O FUNCTION

BIS0/BIS1 32/33 I

Bus Interface Select Bits 0 and 1. Used to select bus interface option. BIS0 = 1 and BIS1 = 1 selects hardware mode.

BPCLK 31 O Backplane Clock. 16.384MHz output.

Receive and Transmit Clock Edge Select. Selects which RCLK edge to update RPOS and RNEG and which TCLK edge to sample TPOS and TNEG.

CES 12 I

0 = update RNEG/RPOS on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK 1 = update RNEG/RPOS on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK

Disable Jitter Attenuator.

DJA 8 I

0 = jitter attenuator enabled 1 = jitter attenuator disabled Receive Equalizer Gain Limit. This pin controls the sensitivity of the receive equalizer.

EGL E1 (ETS = 0)

EGL 1 I

0 = -12dB (short haul) 1 = -43dB (long haul)

EGL T1 (ETS = 1)

0 = -36dB (long haul) 1 = -30dB (limited long haul) E1/T1 Select.

ETS 2 I

0 = E1 1 = T1 Receive and Transmit HDB3/B8ZS Enable

HBE 11 I

0 = enable HDB3 (E1)/B8ZS (T1) 1 = disable HDB3 (E1)/B8ZS (T1)

HRST

29 I

JAMUX 9 I

JAS 10 I

L0/L1/L2 7/6/5 I

LOOP0/

LOOP1

16/17 I

Hardware Reset. Bringing HRST low will reset the DS21348.

Jitter Attenuator Mux. Controls the source for JACLK.

See Figure 1-1 and Table 2-13.

E1 (ETS = 0) JAMUX

MCLK = 2.048MHz 0

T1 (ETS = 1)

MCLK = 2.048MHz 1 MCLK = 1.544MHz 0

Jitter Attenuator Select

0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Transmit LIU Waveshape Select Bits 0 and 1 [H/W Mode]. These inputs determine the waveshape of the transmitter (Table 7-1 and Table 7-2

. Loopback Select Bits 0 and 1 [H/W Mode]. These inputs determine the active loopback mode (if any). See Table 2-8.

18 of 76

NAME PIN I/O FUNCTION

Master Clock. A 2.048MHz (±50ppm) clock source with TTL

levels is applied at this pin. This clock is used internally for both

MCLK 30 I

clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is optional. G.703 requires an accuracy of ±50ppm for

both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.

MM0/MM1 18/19 I

Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs determine if the receive equalizer is in a monitor mode (Table 2-11).

NA — I Not Assigned. Should be tied low.

NRZ Enable [H/W Mode]

NRZE 3 I

0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive going pulse when device receives a BPV, CV, or EXZ. PRBS Bit Error Output. The receiver will constantly search for a QRSS (T1) or a 215-1 (E1) PRBS depending whether T1 or E1 mode is selected. Remains high if out of synchronization with the

PBEO 24 O

PRBS pattern. Goes low when synchronized to the PRBS pattern. Any errors in the received pattern after synchronization will cause a positive going pulse (with same period as E1 or T1 clock) synchronous with RCLK.

RCLK 40 O

RCL 25 O

Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING. Receive Carrier Loss. An output which will toggle high during a receive carrier loss. Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of RCLK with the bipolar data out of the

RNEG 39 O

line interface. Set NRZE to a one for NRZ applications. In NRZ mode, data will be output on RPOS while a received error will cause a positive-going pulse synchronous with RCLK at RNEG. See Section 6.4

for details. Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of RCLK with bipolar data out of the line

RPOS 38 O

interface. Set NRZE pin to a one for NRZ applications. In NRZ mode, data will be output on RPOS while a received error will cause a positive-going pulse synchronous with RCLK at RNEG. See

RT0/RT1 44/23 I

RTIP/

RRING

27/28 I

section 6.4 Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These inputs determine the receive termination. See Table 2-12. Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the line. See Section 5 for details.

for details.

Receive and Transmit Synchronization Clock Enable

SCLKE 4 I

0 = disable 2.048MHz synchronization transmit and receive mode 1 = enable 2.048 Hz synchronization transmit and receive mode

TCLK 43 I

Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock data through the transmit side formatter.

19 of 76

DS21348/DS21Q348

NAME PIN I/O FUNCTION

Tri-State Control. Set high to tri-state all outputs and I/O pins

TEST 26 I

(including the parallel control port). Set low for normal operation. Useful in board-level testing. Transmit Negative Data. Sampled on the falling edge (CES = 0) or

TNEG 42 I

the rising edge (CES = 1) of TCLK for data to be transmitted out onto the line.

Transmit Power-Down

TPD 13 I

0 = normal transmitter operation 1 = powers down the transmitter and tri-states the TTIP and TRING pins Transmit Positive Data. Sampled on the falling edge (CES = 0) or

TPOS 41 I

the rising edge (CES = 1) of TCLK for data to be transmitted out onto the line. Transmit Tip and Ring [TTIP and TRING]. Analog line driver

TTIP/TRING 34/37 O

outputs. These pins connect via a step-up transformer to the line. See Section 5 for details.

TX0/TX1 14/15 I

Transmit Data Source Select Bits 0 and 1 [H/W Mode]. These inputs determine the source of the transmit data. See Table 2-9.

VDD 21/36 — Positive Supply. 3.3V ±5% VSM 20 I Voltage Supply Mode. Should be tied low for 3.3V operation.

VSS 22/35 —

Signal Ground

Note: G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces.

20 of 76

Table 2-8. Loopback Control in Hardware Mode

DS21348/DS21Q348

LOOPBACK SYMBOL

CONTROL

BIT

LOOP1 LOOP0

Remote Loopback RLB CCR6.6 1 1

Local Loopback LLB CCR6.7 1 0

Analog Loopback ALB CCR6.4 0 1

No Loopback — — 0 0

Table 2-9. Transmit Data Control in Hardware Mode

TRANSMIT DATA SYMBOL

Transmit Unframed

All Ones

Transmit Alternating

Ones and Zeros Transmit PRBS

TUA1 CCR3.7 1 1

TAOZ CCR3.5 1 0

TPRBSE

TPOS and TNEG — — 0 0

CONTROL

BIT

CCR3.4

TX1 TX0

0 1

Table 2-10. Receive Sensitivity Settings

EGL

(CCR4.4)

0 0 (E1) -12dB (short haul) 1 0 (E1) -43dB (long haul) 1 1 (T1) -30dB (limited long haul) 0 1 (T1) -36dB (long haul)

ETS

(CCR1.7)

RECEIVE SENSITIVITY

Table 2-11. Monitor Gain Settings

MM1

(CCR5.5)

0 0 Normal operation (no boost) 0 1 20 1 0 26 1 1 32

MM0

(CCR5.4)

INTERNAL LINEAR

GAIN BOOST (dB)

Table 2-12. Internal Rx Termination Select

RT1

(CCR5.1)

0 0 Internal receive-side termination disabled 0 1 1 0 1 1

RT0

(CCR5.0)

INTERNAL RECEIVE

TERMINATION CONFIGURATION

Internal receive-side 120Ω enabled Internal receive-side 100Ω enabled Internal receive-side 75Ω enabled

21 of 76

Table 2-13. MCLK Selection

DS21348/DS21Q348

MCLK

(MHz)

JAMUX

(CCR1.3)

ETS

(CCR1.7)

2.048 0 0

2.048 1 1

1.544 0 1

Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = 1 or 0) (TQFP Package)

1 2 RD (DS)

3 WR (R/ 4 ALE (AS) 5 NA 6 NA 7 A4 8 A3 9 A2 10 A1 11 A0

44 PBTS

42 TNEG

43 TCLK

)

40 RCLK

41 TPOS

DS21348

Parallel Port

Operation

(NOTE: TIE ALL NA PINS LOW)

39 RNEG

38 RPOS

37 TRING

D0/D0 19 AD1/D1 18 AD2/D2 17 AD3/D3 16 AD4/D4 15 AD5/D5 14 AD6/D6 13 AD7/D7 12

36 VDD

VSM 20

34 TTIP

35 VSS

RCL/LOTC 25

VDD 21

VSS 22

BIS1 33

BIS0 32

BPCLK 31

MCLK 30

RST 29

RRING 28

RTIP 27

TEST 26

PBEO 24

NT 23

tie low

TIE LOW (MUX) OR HIGH (NONMUX)

22 of 76

TIE LOW

DS21348/DS21Q348

Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package)

TIE LOW

2 NA 3 NA 4 NA 5 SCLK 6 SDI 7 SDO 8 ICES 9 OCES 10 NA 11 NA

44 PBTS

NA 12

40 RCLK

41 TPOS

42 TNEG

43 TCLK

DS21348

Serial Port

Operation

(NOTE: TIE ALL NA PINS LOW)

NA 16

NA 15

NA 14

NA 13

39 RNEG

NA 17

38 RPOS

NA 18

37 TRING

NA 19

36 VDD

35 VSS

VSM 20

VDD 21

TIE LOW

34 TT IP

BIS1 33

BIS0 32

BPCLK 31

MCLK 30

RST 29

RRING 28

RTIP 27

TEST 26

RCL/LOTC 25

PBEO 24

NT 23

VSS 22

TIE HIGH TIE LOW

23 of 76

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TABLE OF CONTENTS

LIST OF FIGURES