The DS1862 is a closed-loop laser-driver control IC with
built-in digital diagnostics designed for XFP MSA. The
laser control function incorporates average power control (APC) and allows extinction ratio control though a
temperature indexed look-up table (LUT). The DS1862
monitors up to seven analog inputs, including temperature and monitor diode (MD) current, which are used to
regulate the laser bias current and extinction ratio.
Warning and alarm thresholds can be programmed to
generate an interrupt if monitored signals exceed tolerance. Calibration is also provided internally using independent gain and offset scaling registers for each of
the monitored analog signals. Settings such as programmed calibration data are stored in password-protected EEPROM memory. Programming is accomplished
through an I
2
C-compatible interface, which can also be
used to access diagnostic functionality.
Applications
Laser Control and Monitoring 10Gbps Optical
Transceiver Modules (XFP)
Laser Control and Monitoring
Digital Diagnostics in Optical Transmission
Features
♦ Implements XFP MSA Requirements for Digital
Diagnostics, Serial ID, and User Memory
♦ I2C-Compatible Serial Interface
♦ Automatic Power Control (APC)
♦ Extinction Ratio Control with Look-Up Table
♦ Seven Monitored Channels for Digital Diagnostics
(Five Basic Plus Two Auxiliary)
♦ Internal Calibration of Monitored Channels
(Temp, V
CC2/3
, Bias Current, Transmitted, and
Received Power)
♦ Programmable Quick-Trip Logic for Turning
Off Laser for Eye Safety
♦ Access to Monitoring and ID Information
♦ Programmable Alarm and Warning Thresholds
♦ Operates from 3.3V or 5V Supply
♦ 25-Pin CSBGA, 5mm x 5mm Package
♦ Internal or External Temperature Sensor
♦ -40°C to +100°C Operating Temperature Range
♦ One 8-Bit Buffered DAC
DS1862
XFP Laser Control and Digital Diagnostic IC
______________________________________________
Maxim Integrated Products
1
Pin Configuration
Rev 1; 12/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+
Denotes lead-free package.
Ordering Information
Typical Operating Circuit appears at end of data sheet.
= +2.9V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on Any Open-Drain Pin
Relative to Ground.............................................-0.5V to +6.0V
Voltage on MOD-DSEL, SDA, SCL, FETG, THRSET, TX-D,
= +1.6V to +3.6V, TA= -40°C to +100°C, unless otherwise noted.)
Note 1: All voltages are referenced to ground. Current into IC is positive, out of the IC is negative.
Note 2: Secondary power supply is used to support optional variable power-supply feature of the XFP module. If V
CC2
is not used,
(i.e., signal conditioners using 3.3V supply) V
CC2
should be connected to the V
CC3
.
Note 3: Input signals (i.e., TX-D, MOD-DESEL, and P-DOWN/RST have internal pullup resistors.
Note 4: Guaranteed by design. Simulated over process and 50µA < I
BMD
< 1500µA.
Note 5: C
B
—total capacitance of one bus line in picofarads.
Note 6: EEPROM write begins after a stop condition occurs.
Note 7: This is the maximum and minimum voltage on the MODSET and BIASSET pins required to meet accuracy and drift specifi-
cations.
Note 8: For V
THRSET
, offset may be as much as 10mV.
Note 9: This is the uncalibrated offset provided by the factory; offset adjustment is available on this channel.
Note 10: % FS refers to calibrated FS in case of internal calibration, and uncalibrated FS in the case of external calibration.
Uncalibrated FS is set in the factory and specified in this data sheet FS (factory). Calibrated FS is set by the user, allowing
a change in any monitored channel scale.
The DS1862’s block diagram is described in detail
within the following sections and memory map/memory
description.
Automatic Power Control (APC)
The DS1862’s APC is accomplished by closed-loop
adjustment of the bias current (BIASSET) until the feedback current (BMD) from a photodiode matches the
value determined by the APC registers. The relationship between the APC register and I
BMD
is given by:
I
BMD
= 5.859µA x APCC<7:0> +
(1.464µA x APCF<1:0>)
where APCC<7:0> is the 8-bit value in Table 04h, byte
84h that controls the coarse BMD current and
APCF<1:0> is the 2-bit value that controls the fine BMD
current.
The BMD pin appears as a voltage source in series with
two resistors. The overall equivalent resistance of the
BMD input pin can be closely approximated by the plot
in Figure 8. The voltage that appears on the BMD pin,
assuming no external current load, is 1.2V if BMD is in
sink-current mode (SRC_SINK_B = 0) or 2.0V if BMD is
set to source current (SRC_SINK_B = 1). This allows the
photodiode to be referenced to either V
CC3
or GND.
When the control loop is at steady state, the BMD current
setting matches the current that is measured by the I
BMD
voltage across the internal resistance. During a transient
period, the DS1862 adjusts the current drive on the
BIASSET pin to bring the loop into steady state. The
DS1862 is designed to support loop gains of 1/20 to 10.
On power-up, the BMD current ramps up to the previously saved current setting in EEPROM APC registers.
While operating, the DS1862 monitors the BMD current.
If it begins to deviate from the desired (set) I
BMD
value,
then, again, the current on the BIASSET pin is adjusted
to compensate.
Extinction Ratio Control
Look-Up Table (LUT)
The DS1862 uses a temperature indexed look-up table
(LUT) to control the extinction ratio. The MODSET pin is
capable of sinking current based on the 8-bit binary
value that is controlling it. The DS1862 also features a
user-configurable current range to increase extinction
ratio resolution. Five current ranges, as described in
Table 1, are available to control the current entering
MODSET.
If the largest current range is selected, the maximum
value of FFh (from LUT) corresponds to a 1200µA sink
current. Regardless of current range, the MODSET
value always consists of 256 steps, including zero.
I
MODSET
can be controlled automatically with the temperature-based look-up table, or by three other manual
methods.
Automatic temperature addressed look-up is accomplished by an internal or external temperature sensor
controlling an address pointer. This pointer indexes
through 127 previously loaded 8-bit current values
stored in the LUT. Each one of the 127 temperature
slot locations corresponds to a 2°C increment over
the -40°C to +102°C temperature range. Any temperature above or below these points causes the code in
the first or last temperature slot to be indexed. Both the
internal temperature sensor and an external sensor
connected to AUX2MON are capable of providing a
signal to control the extinction ratio automatically with
an indexed LUT. Table 2 illustrates the relationship
between the temperature and the memory locations in
the LUT.
Automatic and manual control of MODSET is controlled
by two bits: TEN and AEN that reside in Table 04h, Byte
B2h. By default (from factory) TEN and AEN are both
set, causing complete automatic temperature-based
look-up. If TEN and/or AEN are altered, then the
DS1862 is set to one of the manual modes. Table 3
describes manual mode functionality.
Table 2. Temperature Look-Up Table
Table 3. Truth Table for TEN and AEN Bits
TEMPERATURE (°C)
< -4080h
-4080h
-3881h
-3682h
——
+96C4h
+98C5h
+100C6h
+102C7h
> +102C7h
CORRESPONDING LOOK-UP
TABLE ADDRESS
TEN AENDS1862 LUT FUNCTIONALITY
Manual mode that allows users to write a value
directly to the LUT Value register (Table 04h,
00
01
10
11
Byte B1h) to drive MODSET. While in this mode,
the LUT index pointer register is not being
updated, and no longer drives the LUT Value
register.
Manual mode that allows users to write a value
directly to the LUT Value register (Table 04h,
Byte B1h) to drive MODSET. While in this mode,
the LUT index pointer register is still being
updated, however it no longer drives the LUT
Value register.
Manual mode that allows users to write a value to
the LUT index pointer (Table 04h, Byte B0), then
the DS1862 updates the LUT Value register
(Table 04h, Byte B1h) based on the user’s index
pointer.
Automatic mode (factory default). This mode
automatically indexes the LUT based on
temperature, placing the resulting LUT address
in the LUT index pointer register (Table 04h, Byte
B0h). Then the MODSET setting is transferred
from that LUT address to the LUT Value register
(Table 04h, Byte B1h). Lastly the I
to the new MODSET code.
The DS1862 has seven monitored voltage signals that
are polled in a round-robin multiplexed sequence and
are updated with the frame rate, t
FRAME
. All channels
are read as 16-bit values, but have 13-bit resolution,
and with the exception of temperature measurements,
all channels are stored as unsigned values. The resulting
16-bit value for all monitored channels, except internal
temperature, is calculated by internally averaging the
analog-to-digital result 8 times. The resulting internal
temperature monitor channel is averaged 16 times. See
the
Internal Calibration
section for a complete descrip-
tion of each channel’s method(s) of internal calibration.
The AUX1MON, AUX2MON, and V
CC2/3
monitor channels are optional and can be disabled. This feature
allows for shorter frame rate for the essential monitor
channels. Channels that can not be disabled are: internal temperature, BMD, RSSI, and IBIASMON. A table of
full-scale (FS) signal values (using factory internal calibration without right shifting) and the resulting FS code
values for all seven channels is provided below.
Measuring Temperature—Internal or External
The DS1862 is capable of measuring temperature on
three different monitor channels: internal temperature
sensor, AUX1MON, and AUX2MON. Only the internal
temperature and AUX2MON channels are capable of
indexing the LUT to control the extinction ratio. To use
an external temperature sensor on AUX2MON, the
TEMP_INT/EXT bit in Table 04h, Byte 8Bh, must be set.
While AUX2MON controls the extinction ratio, the internal temperature sensor does not stop running; despite
extinction ratio control by AUX2MON, it is this internal
temperature signal that continues to control the status
of temperature flags. Also when TEMP_INT/EXT = 1, the
internal temperature clamps at -40°C and +103.9375°C,
and when TEMP_INT/EXT = 0 it clamps at -120°C and
+127.984°C. AUX2MON, however, does have its own flag
to indicate an out-of-tolerance condition and assert the
INTERRUPT pin.
Both AUX1MON and AUX2MON can be used to measure temperature as a function of voltage on their
respective pins. They can be enabled by selecting
either 0h or 4h from Table 5. Internal (or external) calibration may be required to transmute the input voltage
to the desired two’s-complement digital code, readable
from the result registers in lower memory, Bytes 6Ah,
6Bh and 6Ch, 6Dh.
Measuring V
CC2/3
The DS1862 has the flexibility to internally measure
either V
CC2
or V
CC3
to monitor supply voltage. V
CC2
or
V
CC3
is user selectable by the V
CC2/3
_Sel bit in Table
01h, Byte DCh. To remove V
CC2/3
from the round-robin
monitor update scheme, despite having V
CC2
or V
CC3
selected to be monitored, the Reserve_EN bit in Table
04h, Byte 8Bh can be programmed to a 0. The analog
power-on-reset flag, POA, indicates the status of V
CC3
power supply. Even though POA seems to behave similarly to V
CC2/3
monitor channel, it is completely sepa-
rate and has no connection.
Measuring APC and Laser Parameters—BMD,
IBIASMON, RSSI
BMD and BIASSET are used to control and monitor the
laser functionality. Regardless of the set BMD current in
the APC register, the DS1862 measures BMD pin current and uses this value not only to adjust the current
on the BIASSET pin, but also to monitor TX-P as well.
The IBIASMON pin is used to input a voltage signal to
the DS1862 that can be used to monitor the bias current through the laser. This monitor channel does not
drive the HIGHBIAS quick-trip (QT) alarms for safety
fault functionality, current on the BIASSET pin is monitored by the DS1862 to control the HIGHBIAS quick
trip. Similar to TX-P, the RSSI pin is used to measure
the received power, RX-P.
Measuring Voltage Quantities
using AUX1MON and AUX2MON
AUX1MON and AUX2MON are auxiliary monitor inputs
that may be used to measure additional parameters.
AUX1/2MON feature a user-selectable register that
determines the measured value’s units (i.e., voltage,
current, or temperature). In addition to indicating units,
some of the 4-bit op-codes, in Table 5, also place the
part in special modes used for alarms and faults internally. Whichever units’ scale is selected, the DS1862 is
only capable of measuring a positive voltage quantity,
therefore internal or external calibration may be
required to get the binary value to match the measured
quantity. A table of acceptable units and/or their corresponding user-programmable 4-bit op-code is provided below.
Alarms and Warning Flags
Based on Monitor Channels
All of the monitor channels feature alarm and warning
flags that are asserted automatically as user-programmed thresholds are internally compared with monitor channel results. Flags may be set, which, if not
masked, will generate an interrupt on the INTERRUPT
pin or generate a safety fault. Whenever V
CC2/3
,
AUX2MON, AUX1MON, RSSI, and internal temperature
go beyond their threshold trip points and the corresponding mask bit is 0, an interrupt is generated on the
INTERRUPT pin and a corresponding warning or alarm
flag is set. Similarly, a safety fault occurs whenever
BMD or BIASSET go beyond threshold trip points.
When this happens, the FETG pin immediately asserts
and BIASSET and MODSET currents are shut down.
Monitor Channel Conversion Example
Table 6 provides an example of how a 16-bit ADC code
corresponds to a real life measured voltage using the
factory-set calibration on either RSSI or IBIASMON. By
factory default, the LSB is set to 38.147µV.
To calculate V
CC2
, V
CC3
, AUX1MON, or AUX2MON,
convert the unsigned 16-bit value to decimal and multiply by 100µV.
To calculate the temperature (internal), treat the two’scomplement value binary number as an unsigned binary number, then convert it to decimal and divide by
256. If the result is grater than or equal to 128, subtract
256 from the result.
Temperature: high byte = -128°C to +127°C signed;
low byte = 1/256°C.
The DS1862 has two means for scaling an analog input
to a digital result. The two devices alter the gain and
offset of the signal to be calibrated. All of the inputs
except internal temperature have unique registers for
both the gain and the offset that can be found in Table
04h. See the table below for a complete description of
internal calibration capabilities including right-shifting
for all monitor channels.
To scale a specific input’s gain and offset, the relationship between the analog input and the expected digital
result must be known. The input that would produce a
corresponding digital result of all zeroes is the null
value (normally this input is GND). The input that would
produce a corresponding digital result of all ones is the
full-scale (FS) value minus one LSB. The FS value is
also found by multiplying an all ones digital value by
the weighted LSB. For example, a digital reading is 16
bits long, assume that the LSB is known to be 50µV,
then the FS value would be 216x 50µV = 3.2768V.
A binary search can be used to find the appropriate
gain value to achieve the desired FS of the converter.
Once the gain value is determined, then it can be
loaded into the appropriate channels’ Gain register.
This requires forcing two known voltages on to the
monitor input pin. For best results, one of the forced
voltages should be the NULL input and the other
should be 90% of FS. Since the LSB of the least significant bit in the digital reading register is known, the
expected digital results are also known for both the null
and FS value inputs. Figure 9 describes the hysteresis
built into the DS1862’s LUT functionality.
With the exception of BMD, which can source or sink
current, all monitored channels are high impedance
and are only capable of directly measuring a voltage. If
other measured quantities are desired, such as: light,
frequency, power, current etc., they must be converted
to a voltage. In this situation the user is not interested in
voltage measurement on the monitored channel, but
the measurement of the desired parameter. Only the
relationship between the indirect measured quantity
(light, frequency, power, current, etc.) to the expected
digital result must be known.
An example of gain scaling using the recommended
binary search procedure is provided with the following
pseudo-code.
To help will the computation, two integers need to be
defined: count 1 and count 2. CNT1 = NULL / LSB and
CNT2 = 90%FS / LSB. CLAMP is the largest result that
can be accommodated.
/* In addition, the requirement for LSB is 50µV. */
FS = 65536 * 50e-6; /* 3.2768 */
CNT1 = 0.5 / 50e-6;/* 10000 */
CNT2 = 0.90*FS / 50e-6;/* 58982 */
/* Thus the NULL input of 0.5V and the 90% of FS input
is 2.94912V. */
set the trim-offset-register to zero;
set Right-Shift register to zero (Typically zero.
See the
Right-Shifting
section);
gain_result = 0h;
CLAMP = FFF8h/2^(Right_Shift_Register);
For n = 15 down to 0
begin
gain_result = gain_result + 2^n;
Force the 90% FS input (2.94912V);
Meas2 = read the digital result from the part;
If Meas2 >= CLAMP then
gain_result = gain_result - 2^n;
Else
Force the NULL input (0.5V);
Meas1 = read the digital result from the part;
if (Meas2 - Meas1) > (CNT2 - CNT1) then
gain_result = gain_result - 2^n;
end;
Set the gain register to gain_result;
The gain register is now set and the resolution of the
conversion will best match the expected LSB. The next
step is to calibrate the offset of the DS1862. With the
correct gain value written to the gain register, again
force the NULL input to the monitor pin. Read the digital result from the part (Meas1). The offset value is
equal to negative value of Meas1.
The calculated offset is now written to the DS1862 and
the gain-and offset-scaling procedure is complete.
Right-Shifting A/D Conversion Result
(Scalable Dynamic Ranging)
Right-shifting is a digital method used to regain some
of the lost ADC range of a calibrated system. If rightshifting is enabled, by simply loading a non-zero value
into the appropriate Right-Shifting Register, then the
DS1862 shifts the calibrated result just before it is
stored into the monitor channels’ register. If a system is
calibrated so the maximum expected input results in a
digital output value of less than 7FFFh (50% of FS),
then it is a candidate for using the right-shifting
method.
If the maximum desired digital output is less than
7FFFh, then the calibrated system is using less than 1/2
the ADC’s range. Similarly, if the maximum desired digital output is less than 1FFFh, then the calibrated system is only using 1/8th the ADC’s range. For example, if
an applied maximum analog signal yields a maximum
digital output less than 1FFCh, then only 1/8th of the
ADC’s range is used. Right-shifting improves the resolution of the measured signal as part of internal calibration. Without right-shifting, the 3 MS bits of the ADC will
never be used. In this example, a value of 3 for the
right-shifting maximizes the ADC range and a larger
gain setting must be loaded to achieve optimal conversion. No resolution is lost since this is a 13-bit converter
that is left justified. The value can be right-shifted 3
times without losing any resolution. The following table
describes when the right-shifting method can be effectively used.
The DS1862 is capable of generating an alarm and/or
warning whenever an analog monitored channel goes
out of a user-defined tolerance. Temperature, bias current (based on IBIASMON), receive power (based on
RSSI), AUX1MON, AUX2MON, and V
CC2/3
, are moni-
tored channels that generate latched flags. See the figure below for more detail pertaining to AUX1MON and
AUX2MON. Flags are latched into a high state the first
time a monitored channel goes out of the defined operating window and for each monitored signal there is a
Mask bit that can be set to prevent the corresponding
alarm or warning flag from being set. Once a flag is set,
it is cleared by simply reading its memory location.
The DS1862 also has flags that are set by certain logical
conditions on signal conditioner (SC) pins: SC-RX-LOL,
SC-RX-LOS, SC-TX-LOS. Similarly, for each latched
signal conditioner flag there are also mask bits that are
capable of preventing the alarm or warning flag from
causing an INTERRUPT pin to assert. Again, flags are
cleared automatically whenever their memory address
is read. See Figure 11 for more detail.
Quick-Trip Logic and FETG
Shutdown Functionality
In addition to alarms and warnings, the DS1862 also
has quick-trip (QT) functionality (sometimes referred to
as fast alarms) that is capable of shutting down the
LASER with the FETG pin in conjunction with shutting
down I
MODSET
and I
BIASSET
. I
BMD
and I
BIASSET
currents are measured and are compared with userdefined trip points to set the quick-trip flags: QT LOW
TX-P, QT HIGH TX-P, and QT HIGH BIAS. These flags
are also capable of being masked to prevent FETG
from being asserted when an out-of-tolerance condition
is detected. FETG is not asserted by setting the TX-D
pin, SOFT TX-D, or P-DOWN/RST pin to a high state,
however, I
The polarity of the FETG pin can also be reversed by
setting the FETG_POL bit. Once a safety fault has
occurred, the FETG pin and all of the attendant flags can
only be reset by pulsing the P-DOWN/RST pin high for the
reset time, t
RESET
, or by toggling the P-DOWN/RST bit in
Byte 6Eh, bit 4. See the
Power-Down/Reset Pin
section for
more details.
Power-Down/Reset Pin
The P-DOWN/RST pin is a multifunction input pin that
resets and/or powers down the DS1862. Since the pin is
internally pulled up, its normal state is released, which
corresponds to power-down mode. If the P-DOWN/RST
pin is released, or driven high, the DS1862 responds by
shutting down the MODSET and BIASSET currents.
Once the pin is pulled low, operation continues (if not
inhibited by a safety fault). Besides powering down the
DS1862, a high-going pulse with minimum reset time,
t
RESET
, can be applied to the P-DOWN/RST pin. This is
necessary to restart the DS1862, especially if it is in a
safety shutdown condition and needs to be restarted
after the safety condition has been rectified. See the
timing diagrams for proper pin timing.
Power-Down Functionality
During power-down mode I
BIASSET
and I
MODSET
drop
below 10µA, effectively shutting down the laser. FETG
is not asserted and safety faults do not occur during
this period. During power-down, I2C communication is
still active, but the signal conditioner pins EN1 and EN2
are noncontrollable and automatically change to the
states: EN1 = 1 and EN2 = 0. Other internal flags/signals that are based on the signal conditioner inputs still
reflect the status on the signal conditioner pins during
power-down. For example, RX-LOS still reflects the status of SC-RX-LOS, and MOD-NR still reflects the logical
states for the signal conditioner pins. Similarly, it is possible for FETG to be asserted, even though the BIASSET
and MODSET currents are shut down. However, during
power-down and a short period, t
PDR-OFF
, during powerup, TX-P Low flag is ignored (internally automatically
masked out) and does not contribute to FETG’s logic.
Figure 12. Safety Fault and Shutdown Logic
SHUTDOWN LOGIC
LATCHED-TX-FAULT
LATCH
BMD (PIN)
(TX-P CURRENT)
ADC
THRESHOLD
QT LOW
TX-P FLAG
LOW TX-P MASK
BMD (PIN)
(TX-P CURRENT)
BIASSET (PIN)
(BIASSET CURRENT)
SOFT TX-D
P-DOWN/RST (PIN)
TX-D (PIN)
SAFETY FLAG
SOFT P-DOWN/RST
ADC
THRESHOLD
ADC
THRESHOLD
HIGH TX-P MASK
BIAS HIGH MASK
SHUTDOWN
FLAG
QT HIGH
TX-P FLAG
QT BIAS
HIGH FLAG
QT LOW TX-P FLAG
QT HIGH TX-P FLAG
QT BIAS HIGH FLAG
During an asserted period of P-DOWN/RST (DS1862 in
power-down), and V
CC3
is cycled, the DS1862 remains
in power-down mode upon power-up. While in powerdown mode the INTERRUPT pin does not assert. Once
V
CC3
has returned, the reset done flag asserts after the
interrupt assert delay, t
INIT ON
.
Reset Functionality
Besides powering down the DS1862, the P-DOWN/RST
pin also functions to reset the DS1862. After a highgoing pulse of time t
RESET
, several events occur within
the DS1862. First, MODSET and BIASSET currents shut
down and are then reinstated. Second, between the rising edge of the reset pulse and the assertion of the
reset-done flag (t
INIT
), the low TX-P flag is ignored and
does not cause FETG to trip. After time t
INIT,
the low
TX-P flag becomes functional. Also, at this time, the
reset-done flag is asserted, causing an interrupt to be
generated. If there are no faults before t
INIT
, then no
interrupts are asserted on the INTERRUPT pin.
If V
CC3
is powered up while P-DOWN/RST is high, then
the reset-done flag must be cleared twice. The first time
the reset-done flag is generated by V
CC3
powering up,
the second time reset-done is generated by a falling
edge on P-DOWN/RST. If V
CC3
is continuously powered while P-DOWN/RST is low then only one resetdone flag needs to be cleared. See the timing
diagrams for graphical detail.
DS1862 Memory Map
Memory Organization
The DS1862 features six separate memory tables that
are internally organized into four byte rows. The Lower
Memory is addressed from 00h to 7Fh and contains
alarm and warning thresholds, flags, masks, several
control registers, password entry area (PE), and the
Table Select byte. Table 01h primarily contains user
EEPROM as well as several control bytes for various
functions. Table 02h is strictly user EEPROM that is protected by a host password. Table 03h is strictly used
for controlling the extinction ratio with an LUT. Table
04h is a multifunction space that contains internal calibration values for monitored channels, LUT index pointers, and miscellaneous control bytes. Table 05h is
factory programmed and stores SCALE values for use
with suggested external temperature sensors. Also, one
byte in Table 05h controls the THRSET voltage source
and is completely accessible without any password
protection. See the Memory section for a more complete detail of each byte’s function, as well as Table 11
for read/write permissions for each Byte. Many nonvolatile memory locations (listed within the
Detailed
Register Description
section) are actually SRAMShadowed EEPROM, which are controlled by the SEEB
bit in Table 4, Byte B2h.
The DS1862 incorporates SRAM-shadowed EEPROM
memory locations for key memory addresses that may
be rewritten many times. By default the Shadowed
EEPROM Bit, SEEB, is not set and these locations act
as ordinary EEPROM. By setting SEEB, these locations begin to function like SRAM cells, which allow an
infinite number of write cycles without concern of wearing out the EEPROM. This also eliminates the requirement for the EEPROM write time, tWR. Because
changes made with SEEB enabled do not affect the
EEPROM, these changes are not retained through
power cycles. The power-up value is the last value written with SEEB disabled. This function can be used to
limit the number of EEPROM writes during calibration or
to change the monitor thresholds periodically during
normal operation helping to reduce the number of times
EEPROM is written. The Memory Map description indicates which locations are shadowed-EEPROM.
...............................< R-all / W-all ><Volatile><00> Bit 0 can only be written if Table 01h, Byte DDh, bit
<0> is high. Bits <2:1> control EN2 and EN1, repectively.
02h → 39h
•
Alarms and warnings
.......< R-all / W-Module ><Shadowed Nonvolatile ><Note*> These registers set the 16-
bit threshold level for corresponding monitor channels. *Note: High alarm and warnings factory default to FFFFh, and low alarm shut warnings default to 0000h.
The DS1862 features two separate and independent
32-bit passwords for important memory locations. The
host password and the module password allow their
own allocated memory locations to be locked to prevent write and/or read access. To enhance the security
of the DS1862, the Password Entry and Setting bytes
can never be read.
To gain access to host-protected or module-protected
memory locations, the correct 32-bit value must be
entered in to the password entry bytes (PWE) in either a
single four-byte write, or four single-byte writes. To reprogram either password, simply enter the appropriate current password to gain memory access, write the new Host
or Module PW with one four-byte write, and finally reenter
the new password into the PWE to regain memory access.
Power-Up Sequence
The DS1862 does require a particular power-up
sequence to ensure proper functionality. V
CC3
should
always be applied first or at the same time as V
CC2
. If
this power-up sequence is not followed, then current can
be sourced out of V
CC2
as if it was connected to V
CC3
with a resistor internal to the DS1862. If V
CC2
is not used
then it should be externally connected to V
CC3
.
Signal Conditioners—
EN1 and EN2 and VTHRES
Signal Conditioners—EN1 and EN2
The EN1 and EN2 output pins are controlled by the bits
at address 01h, bits 2 and 1. The logic state of the pins
is directly analogous to the logical state of the register.
EN1 and EN2 automatically change to a high and low
state, respectively, during power-down mode as
described in the
Power-Down Functionality
section.
Signal Conditioners—VTHRES
A programmable voltage source, THRSET is also provided for use with signal conditioners. This source is
programmable from 0 to 1V in 256 increments.
I2C and Packet Error
Checking (PEC) Information
The DS1862 supports I2C data transfers as well as data
transfers with PEC. The slave address is unalterable
and is set to A0h. The DS1862, however, does have an
additional dedicated pin, MOD-DESEL, which acts as
an active-low chip select to enable communication. See
the
I2C Serial Interface
and the
I2C Operation Using
Packet Error Checking
sections for details.
Precision SCALE Register
Settings for AUX2MON
The DS1862 features a factory-trimmed SCALE value
for use with DS60 or LM50 temperature sensors. If
external temperature measurement on AUX2MON is
used with one of these two sensors, the 16-bit SCALE
value can be read from Table 05h and written into the
SCALE register in Table 04h, Byte 9Ch and 9Dh. This
option allows for the most precise setting for SCALE
without requiring additional trimming. Since the SCALE
register value is precisely trimmed at the factory, the
OFFSET register will always be a non-unique value and
can simply be written into are OFFSET register. For the
DS60, the value of EF0Ah in OFFSET completes the
internal calibration. For the LM50, the value of F380h in
OFFSET completes the internal calibration.
I2C Serial Interface
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start and stop conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See Figure 14 for
applicable timing.
Stop condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a stop condition. See Figure 14 for applicable timing.
Repeated start condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start
condition. See Figure 14 for applicable timing.
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (Figure 14). Data is
shifted into the device during the rising edge of the SCL.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 14) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one during the 9th bit. Timing (Figure 14)
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave address byte: Each slave on the I
2
C bus
responds to a slave addressing byte sent immediately
following a start condition. The slave address byte contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS1862’s slave address is 1010000Xb. The MODDESEL pin is used as a chip select, and allows the
device to respond or ignore I2C communication that
has A0h as the device address. By writing the correct
slave address with R/W = 0, the master indicates it will
write data to the slave. If R/W = 1, the master will read
data from the slave. If an incorrect slave address is
written, the DS1862 assumes the master is communicating with another I2C device and ignores the communications until the next start condition is sent.
Memory address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte transmitted during a write operation following the slave
address byte.
I2C Communication
Writing a single byte to a slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 4 data bytes, and generates a stop condition.
The DS1862 is capable of writing 1 to 4 bytes (referred
to as 1 row or page) with a single write transaction. This
is internally controlled by an address counter that
allows data to be written to consecutive addresses
without transmitting a memory address before each
data byte is sent. The address counter limits the write
to one row of the memory map. Attempts to write to
additional memory rows without sending a stop condition
between rows results in the address counter wrapping
around to the beginning address of the present row.
To prevent address wrapping from occurring, the master must send a stop condition at the end of the row,
and then wait for the bus free or EEPROM write time to
elapse. Then the master can generate a new start condition, write the slave address byte (R/W = 0), and the
first memory address of the next memory row before
continuing to write data.
Acknowledge polling: Any time EEPROM is written,
the DS1862 requires the EEPROM write time (tW) after
the stop condition to write the contents of the row to
EEPROM. During the EEPROM write time, the DS1862
does not acknowledge its slave address because it is
busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS1862, which
allows the next row to be written as soon as the DS1862
is ready to receive the data. The alternative to acknowledge polling is to wait for the maximum period of tWto
elapse before attempting to write again to the DS1862.
EEPROM write cycles: When EEPROM writes occur,
the DS1862 writes the whole EEPROM memory 4-byte
row even if only a single byte on the row was modified.
Writes that do not modify all 4 bytes on the row are
allowed and do not corrupt the remaining bytes of
memory on the same row. Because the whole row is
written, bytes on the row that were not modified during
the transaction are still subject to a write cycle. This
can result in a whole row being worn out over time by
writing a single byte repeatedly. Writing a row one byte
at a time wears out the EEPROM four times faster than
writing the entire row at once. The DS1862’s EEPROM
write cycles are specified in the
Nonvolatile Memory
Characteristics
table.
Reading a single byte from a slave: Unlike the write
operation that uses the memory address byte to define
where the data is to be written, the read operation
occurs at the present value of the memory address
counter. To read a single byte from the slave at the
location currently in the address counter; the master
generates a start condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a stop
condition.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master generates a start condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires
to read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
See Figure 15 for a read example using the repeated
start condition to specify the starting memory location.
Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the master reads the last byte it NACKs to indicate the end of
the transfer and generates a stop condition. This can
be done with or without modifying the address
counter’s location before the read cycle. If the address
counter reaches the last physical address, the internal
index pointer loops back to the first memory location in
a given memory table. For example, if address FFh in
Table 02h is read, the next byte of data to be returned
to the master is address 80h in Table 2, not 00h in
lower memory.
Packet error checking during reads is supported by the
DS1862. Information is transferred form the DS1862 in
much the same way as conventional I2C protocol, however, an extra CRC field is added and checked. The
still begins by sending the device address (A0h for
DS1862), then the index pointer to the memory address
of interest. The next byte transferred, however will be
the value of the intended number of bytes to be read.
The calculation of the CRC-8 includes and requires the
explicit starting memory address to be included as the
second transferred byte (dummy write byte). Next, the
slave transfers the data back as the master acknowledges. Only 1 to 128 bytes can be sequentially read
during one transmission while using PEC. After the
master reads the intended number of bytes, the CRC-8
value is transmitted by the DS1862. The master ends
the communication with a NACK and a STOP. See
Figure 16 for a graphical representation. The CRC-8 is
calculated starting with the MSB of the memory
address pointer, number of bytes to read, and the read
data. The master can then verify the CRC-8 value and
reject the read data if the CRC-8 value does not correspond to the received CRC value. The CRC-8 must be
calculated by using the following polynomial for both
reads and writes:
C(x) = X
8+X2
+ X + 1
Write Operation with
Packet Error Checking
Packet error checking during writes is also supported
by the DS1862. Information is written to the DS1862 in
much the same way as conventional I2C protocol, however, an extra CRC field is added and checked. The
master still begins by sending the device address, then
the index pointer to the memory address of interest.
The next byte however, will be the value of the intended
number of bytes to be written. The calculation of the
Figure 15. I2C Communications Examples
COMMUNICATIONS KEY
STARTACK
S
STOP
PN
REPEATED
SR
START
WRITE A SINGLE BYTE
S
101 00000
WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION
S
101 00000
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
101 00000
S
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
101 00000
S
A
NOT
ACK
XXXXXXXX
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
8-BITS ADDRESS OR DATA
A
MEMORY ADDRESS
A
MEMORY ADDRESS
MEMORY ADDRESS
A
A
MEMORY ADDRESS
A
A
ASR
SR
A
DATA
DATA
101 00000
101 00000
NOTE:
ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
CRC-8 includes and requires the explicit starting memory address to be included as the second transferred
byte. Next, the master transfers the data as the DS1862
acknowledges. Only 4 bytes can be sequentially written
during one transmission while using PEC. After the
master writes the intended number of bytes, the CRC-8
value should be transmitted. Following the CRC-8 byte
the master should transmit the CAB byte (CRC Add-on
Byte). At this point, the DS1862 sends an ACK if the
CRC-8 matches its internal calculated value or a NACK
if not. Finally the master should end the communication
and send a STOP. See Figure 16 for a graphical representation. The CRC-8 is calculated starting with the
MSB of the memory address pointer, number of bytes
to be written, and the written data. The master can then
poll the last ACK or NACK for successful transfer of
written data.
For more information on I2C PEC communications,
please refer to the XFP and/or SMBus 2.0 standard.
Applications Information
Calibrating APC and Extinction Ratio
Before calibrating, the APC register should be set to a
low value to ensure the laser’s maximum power level is
not exceeded before the power level is calibrated.
Additionally, the ER should be set to a minimum value
to ensure that a data test pattern does not cause the
laser to shut off. Once the APC and ER registers are at
minimal values, enable a data pattern and calibrate the
average power level.
Calibrating the Average Power Level
While sending data through the laser diode, increase
the value in the APC register until the light output
matches the desired average
power level. The average
power level is the arithmetic average of the ‘1’ and ‘0’
power levels.
Figure 16. I2C PEC Communications Examples
COMMUNICATIONS KEY
STARTACK
S
STOP
PN
REPEATED
SR
START
A
NOT
ACK
XXXXXXXX
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
8-BIT ADDRESS OR DATA
NOTE:
ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
THE FIRST BYTE SENT AFTER A START CONDITION IS
ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE
READ/WRITE BIT.
WRITE UP TO A 4-BYTE PAGE WITH A SINGLE TRANSACTION USING PEC
S
101 00000
DATA
READ 1–128 BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER
To achieve best results, it is recommended that the
power supply is decoupled with a 0.01µF or a 0.1µF
capacitor. Use high-quality, ceramic, surface-mount
capacitors, and mount the capacitors as close as possible to the V
CC2/VCC3
and GND pins to minimize lead
inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector bidirectional data pin on the
DS1862 that requires a pullup resistor to realize high
logic levels. Either an open-collector output with a
pullup resistor or a push-pull output driver can be utilized for the SCL input. Pullup resistor values should be
chosen to ensure that the rise and fall times listed in the
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
is a registered trademark of Dallas Semiconductor Corporation.
Heaney
Revision History
REVISION
NUMBER
0 2/06 Initial release. —
1 12/07
REVISION
DATE
DESCRIPTION
Removed I
Corrected password level control for B8h of Table 04h from <4> to <7>.
Corrected grammar for Byte 01h SRAM description: “bits” after “Byte DDh”
changed to “bit”.
Clarified the function of the DDh enable bits, added the following sentence to
the 6Eh Bit 3 description: “Mas ked by Bit 5 of B yte DDh in Table 01h.”
Clarified the function of the DDh enable bits, added the following sentence to
the 6Eh Bit 6 description: “Mas ked by Bit 6 of B yte DDh in Table 01h.”
Clarified the Read function of the Host PW Change and PWE descriptions,
added the following sentence to both descriptions: “A Read result is always
<FFh>.”
Corrected and clarified the Module pas sword value, changed the current
description to:
<R-never / W-Module><Shadowed Nonvolatile><00h> This is the 32-bit
location that the DS1862 uses to compare with the PWE to grant Module
password access. A Read result is always <FFh>.
Added Package Information table.
2
C disclaimer.
PAGES
CHANGED
1, 29–31, 35, 42
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