MAXIM DS1673 Technical data

BLE

BHE

查询DS1673-3供应商

www.maxim-ic.com

GENERAL DESCRIPTION

The DS1673 portable system controller is a circuit that incorporates many of the functions necessary for low-power portable products integrated into one chip. The device provides a real-time clock (RTC), NV RAM controller, microprocessor monitor, and a 3-channel, 8-bit analog-to-digital converter (ADC). Communication with the DS1673 is established through a simple 3-wire interface.

The RTC provides seconds, minutes, hours, day, date, month, and year information with leap year compensation. The RTC also provides an alarm interrupt. This interrupt works when the DS1673 is powered by the system power supply or when in battery-backup operation, so the alarm can be used to wake up a system that is powered down.

Automatic backup and write protection of an external SRAM is provided through the V

, CEOL, and

CCO

CEOH pins. The backup energy source used to power the RTC is also used to retain RAM data in the absence of V

through the V

pin. The chip-

CCO

enable outputs to RAM (CEOL and CEOH) are controlled during power transients to prevent data corruption.

ORDERING INFORMATION

PART*

VOLTAGE

(V)

DS1673E-3 3.0 20 TSSOP DS1673-3 DS1673E-3+ 3.0 20 TSSOP DS1673-3 DS1673E-5 5.0 20 TSSOP DS1673-5 DS1673E-3/

T&R DS1673E-3+ T&R DS1673E-5/ T&R

3.0 20 TSSOP DS1673-3

5.0 20 TSSOP DS1673-5

DS1673S-3 3.0 20 SO DS1673S-3 DS1673S-5 5.0 20 SO DS1673S-5

* All devices are specified over the 0°C to +70°C operating range. † A “‘+” anywhere on the top mark denotes a lead-free device.

+ Denotes a lead-free/RoHS-compliant device.

PINPACKAGE

TOP MARK†

DS1673

Portable System Controlle

FEATURES

§ Provides Real-Time Clock

Counts Seconds, Minutes, Hours, Date of the

Month, Month, Day of the Week, and Year with Leap Year Compensation Valid Up to 2100

Power-Control Circuitry Supports System

Power-On from Day/Time Alarm

§ Microprocessor Monitor Halts Microprocessor During Power Fail Automatically Restarts Microprocessor after

Power Failure Monitors Pushbutton for External Override Halts and Resets an Out-of-Control

Microprocessor

§ NV RAM Control Automatic Battery Backup and Write Protection to External SRAM

§ 3-Channel, 8-Bit ADC

§ Simple 3-Wire Interface

§ +3.0V or +5.0V Operation

PIN CONFIGURATION

TOP VIEW

SCLK

CEO

INT

GND

BAT

DS1673

CCO

I/O

TSSOP (4.4mm)

SO (300 mils)

13 12

IN0

IN1

1 of 18 REV: 080805

DS1673

DETAILED DESCRIPTION

The microprocessor monitor circuitry of the DS1673 provides three basic functions. First, a precision temperature-compensated reference and comparator circuit monitors the status of VCC. When an out-oftolerance condition occurs, an internal power-fail signal is generated which forces the reset to the active state. When VCC returns to an in-tolerance condition, the reset signals are kept in the active state for 250 ms to allow the power supply and processor to stabilize. The second microprocessor monitor function is pushbutton reset control. The DS1673 debounces a pushbutton input and guarantees an active reset pulse width of 250 ms. The third function is a watchdog timer. The DS1673 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to watchdog timeout.

The DS1673 also provides a 3-channel, 8-bit successive approximation analog-to-digital converter. The converter has an internal 2.55V (typical) reference voltage generated by an on-board band-gap circuit. The ADC is monotonic (no missing codes) and has an internal analog filter to reduce high frequency noise.

OPERATION

The block diagram in Figure 1 shows the main elements of the DS1673. The following paragraphs describe the function of each pin.

DS1673 BLOCK DIAGRAM Figure 1

2 of 18

PIN DESCRIPTION

PIN NAME FUNCTION

1 V

2 V

3 SCLK Serial Clock Input. Used to synchronize data movement on the serial interface. 4 I/O Data Input/Output. This pin is the bidirectional data pin for the 3-wire interface.

5 CS

6 CEI RAM Chip-Enable In. Must be driven low to enable the external RAM.

7 CEOL

8 CEOH

9 INT

10 GND Ground. DC power is provided to the device on this pin.

11 BHE

12 BLE

14,

15, 16

17, 18 X2, X1

19 VCC +3.0V or +5.0V Input DC Power

20 ST

Battery Input for Standard 3V Lithium Cell or Other Energy Source

BAT

External SRAM Power Supply Output. This pin is internally connected to V

CCO

is within nominal limits. However, during power-fail V

to the V

pin. Switchover occurs when VCC drops below V

BAT

Chip Select. Must be asserted high during a read or a write for communication over the 3-wire serial interface. CS has an internal 40kW pulldown resistor.

RAM Chip-Enable Out Low. Active-low chip-enable output for low-order SRAM byte.

RAM Chip-Enable Out High. Active-low chip-enable output for high-order SRAM byte.

Interrupt Output. This pin is an active-high output that can be used as an interrupt input to a microprocessor. The INT output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. The INT pin operates when the DS1673 is powered by V

or V

Byte High-Enable Input. This pin when driven low activates the CEOH output if CEI is also driven low.

Byte Low-Enable Input. This pin when driven low activates the CEOL output if CEI is also driven low.

Active-Low Reset. The RST pin functions as a microprocessor reset signal. This pin is driven low 1) when VCC is outside of nominal limits; 2) when the watchdog timer has

RST

timed out; 3) during the power-up reset period; and 4) in response to a pushbutton reset. The RST pin also functions as a pushbutton reset input. When the RST pin is driven low, the signal is debounced and timed such that a RST signal of at least 250ms is generated. This pin has an open-drain output with an internal 47kW pullup resistor.

AIN2, AIN1,

Analog Inputs. These pins are the three analog inputs for the 3-channel ADC.

AIN0

Connections for Standard 32.768kHz Quartz Crystal. For greatest accuracy, the DS1673 must be used with a crystal that has a specified load capacitance of 6pF. There is no need for external capacitors or resistors. Note: X1 and X2 are very highimpedance nodes. It is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real Time Clocks. The DS1673 does not function without a crystal.

Active-Low Strobe Input. The strobe input pin is used with the watchdog timer. If the ST pin is not driven low within the watchdog time period, the RST pin is driven low.

is internally connected

CCO

CCSW

BAT

when

DS1673

3 of 18

POWER-UP/POWER-DOWN CONSIDERATIONS

When VCC is applied to the DS1673 and reaches a level greater than V device becomes fully accessible after t When VCC drops below V

, the device is switched over to the V

CCSW

(250ms typical). Before t

RPU

supply.

BAT

DS1673

(power-fail trip point), the

CCTP

elapses, all inputs are disabled.

During power-up, when V

returns to an in-tolerance condition, the RST pin is kept in the active state

for 250ms (typical) to allow the power supply and microprocessor to stabilize.

ADDRESS/COMMAND BYTE

The command byte for the DS1673 is shown in Figure 2. Each data transfer is initiated by a command byte. Bits 0 through 6 specify the address of the registers to be accessed. The MSB (bit 7) is the Read/Write bit. This bit specifies whether the accessed byte will be read or written. A read operation is selected if bit 7 is a 0 and a write operation is selected if bit 7 is a one. The address map for the DS1673 is shown in Figure 3.

ADDRESS/COMMAND BYTE Figure 2

4 of 18

DS1673 ADDRESS MAP Figure 3

DS1673

CLOCK, CALENDAR, AND ALARM

The time and calendar information is accessed by reading/writing the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless of how they are written. Also note that registers 0Fh to 7Fh are reserved. These registers will always read 0 regardless of how they are written. The contents of the time, calendar, and alarm registers are in the Binary-Coded Decimal (BCD) format. The DS1673 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours).

The DS1673 also contains a time of day alarm. The alarm registers are located in registers 07h to 0Ah. Bit 7 of each of the alarm registers are mask bits (see Table 1). When all of the mask bits are logic 0, an alarm will occur once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time of day alarm registers. An alarm will be generated every day when mask bit of the day alarm register is set to 1. An alarm will be generated every hour when the day and hour alarm mask bits are set to 1. Similarly, an alarm will be generated every minute when the day, hour, and minute alarm mask bits are set to 1. When day, hour, minute, and seconds alarm mask bits are set to 1, an alarm will occur every second.

5 of 18

DS1673

TIME OF DAY ALARM BITS Table 1

ALARM REGISTER MASK BITS (BIT 7)

SECONDS MINUTES HOURS DAYS

1 1 1 1 Alarm once per second. 0 1 1 1 Alarm when seconds match. 0 0 1 1 Alarm when minutes and seconds match. 0 0 0 1 Alarm when hours, minutes and seconds match. 0 0 0 0 Alarm when day, hours, minutes and seconds

match.

DESCRIPTION

SPECIAL PURPOSE REGISTERS

The DS1673 has two additional registers (control register and status register) that control the RTC and interrupts.

CONTROL REGISTER

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

EOSC

WP AIS1 AIS0 0 0 0 AIE

EOSC (Enable Oscillator). This bit, when set to logic 0 will start the oscillator. When this bit is set to a

logic 1, the oscillator is stopped and the DS1673 is placed into a low-power standby mode with a current drain of less than 200nA when in battery-backup mode. When the DS1673 is powered by VCC, the

oscillator is always on regardless of the status of the EOSC bit; however, the RTC is incremented only

when EOSC is a logic 0.

WP (Write Protect). Before any write operation to the RTC or any other registers, this bit must be logic

0. When high, the write protect bit prevents a write operation to any register.

AIS0-AIS1 (Analog Input Select). These 2 bits are used to determine the analog input for the analog-todigital conversion. Table 2 lists the specific analog input that is selected by these 2 bits.

AIE (Alarm Interrupt Enable). When set to a logic 1, this bit permits the Interrupt Request Flag (IRQF) bit in the status register to assert INT. When the AIE bit is set to logic 0, the IRQF bit does not initiate the INT signal.

ANALOG INPUT SELECTION Table 2

AIS1 AIS0 ANALOG INPUT

0 0 NONE 0 1 AIN0 1 0 AIN1 1 1 AIN2

6 of 18

+ 12 hidden pages