The DS1672 incorporates a 32-bit counter and
power-monitoring functions. The 32-bit counter
is designed to count seconds and can be used to
derive time-of-day, week, month, month, and
year by using a software algorithm. A precision,
temperature-compensated reference and
comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an
internal power-fail signal is generated that forces
the reset to the active state. When VCC returns to
an in-tolerance condition, the reset signal is kept
in the active state for a period of time to allow
the power supply and processor to stabilize.
TYPICAL OPERATING CIRCUIT
FEATURES
32-Bit Counter
I2C* Serial Interface
Automatic Power-Fail Detect and Switch
Circuitry
Power-Fail Reset Output
Low-Voltage Oscillator Operation
(1.3V min)
Trickle-Charge Capability
Underwriters Laboratory (UL) Recognized
-40°C to +85°C Operating Temperature
Range
PIN CONFIGURATION
TOP VIEW
V
BACKUP
X1
X2
GND
*Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I
components in an I
to the I
2
2
C Standard Specification defined by Philips.
1
DS1672
2
3
4
µSOP
2
C system, provided that the system conforms
8
7
6
5
DIP
SO
C Patent Rights to use these
V
CC
ST
SCL
SDA
1 of 15 REV: 031406
ORDERING INFORMATION
PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK*
DS1672-2 -40°C to +85°C 2.0 8 DIP (300 mils) DS1672-2
DS1672-3 -40°C to +85°C 3.0 8 DIP (300 mils) DS1672-3
DS1672-33 -40°C to +85°C 3.3 8 DIP (300 mils) DS1672-33
DS1672S-2 -40°C to +85°C 2.0 8 SO (150 mils) DS1672-2
DS1672S-2+ -40°C to +85°C 2.0 8 SO (150 mils) D1672-2
DS1672S-3 -40°C to +85°C 3.0 8 SO (150 mils) DS1672-3
DS1672S-3+ -40°C to +85°C 3.0 8 SO (150 mils) D1672-3
DS1672S-33 -40°C to +85°C 3.3 8 SO (150 mils) DS167233
DS1672S-33+ -40°C to +85°C 3.3 8 SO (150 mils) D167233
DS1672
DS1672S-3/T&R -40°C to +85°C 3.0
DS1672S-3+T&R -40°C to +85°C 3.0
DS1672S-33/T&R -40°C to +85°C 3.3
DS1672S-33+T&R -40°C to +85°C 3.3
DS1672U-2 -40°C to +85°C 2.0
DS1672U-2+ -40°C to +85°C 2.0
DS1672U-3 -40°C to +85°C 3.0
DS1672U-3+ -40°C to +85°C 3.0
DS1672U-33 -40°C to +85°C 3.3
DS1672U-33+ -40°C to +85°C 3.3
DS1672U-33/T&R -40°C to +85°C 3.3
DS1672U-33+T&R -40°C to +85°C 3.3
8 SO (150 mils)/Tape
and Reel
8 SO (150 mils)/Tape
and Reel
8 SO (150 mils)/Tape
and Reel
8 SO (150 mils)/Tape
and Reel
+ Denotes a lead-free/RoHS-compliant device.
* A “+” anywhere on the top mark denotes a lead-free device. rr = 2-digit alphanumeric revision code.
2 of 15
DS1672
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +6.0V
Operating Temperature Range (noncondensing) ...…………………………………………-40°C to +85°C
Storage Temperature Range……………………………………………………………….-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect device
reliability.
Logic 0 VIL -0.5 +0.3 x VCC V 1
Backup Supply Voltage V
1.3 3.0 3.63 V 1
BACKUP
DC ELECTRICAL CHARACTERISTICS
(V
Active Supply Current I
Standby Current I
Power-Fail Voltage VPF
CCMIN
< VCC < V
CCMAX, TA
= -40°C to +85°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
600
CCA
500
CCS
µA
µA
2
3
2.70 2.88 2.97
2.45 2.6 2.7
V
1.58 1.7 1.8
V
Leakage Current I
BACKUP
BACKUPLKG
25 50 nA
Logic 0 Output (VOL = 0.4V) IOL 3 mA 1, 4
Logic 0
Output
(DS1672-2)
Note 1: All voltages referenced to ground.
Note 2: I
Note 3: I
Note 4: SDA and RST.
specified with SCL clocking at max frequency (400kHz), trickle charger disabled.
CCA
specified with VCC = V
CCS
(VCC > 2V;
V
= 0.4V)
OL
< 2V;
(V
CC
V
= 0.2 x VCC)
OL
CCTYP
I
OL
and SDA, SCL = V
CCTYP
3
mA 1, 4
3
, trickle charger disabled.
3 of 15
DS1672
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
V
V
Note 5: Using the recommended crystal on X1 and X2.
Current (Oscillator On) I
BACKUP
Current (Oscillator Off) I
BACKUP
BACKUPOSC
BACKUP
0.425 1
µA
5
200 nA
CRYSTAL SPECIFICATIONS
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Nominal Frequency fO 32.768 kHz
Series Resistance ESR 45 kΩ
Load Capacitance CL 6 pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal
Considerations for Dallas Real-Time Clocks for additional specifications
*
4 of 15
DS1672
AC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SCL Clock
Frequency
Bus Free Time
Between a STOP and
START Condition
Hold Time
(Repeated) START
Condition
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
Data Hold Time t
Data Setup Time t
Rise Time of Both
SDA and SCL
Signals
Fall Time of Both
SDA and SCL
Signals
Setup Time for STOP
Condition
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
HD:DAT
SU:DAT
t
R
t
F
t
SU:STO
Fast mode 100 400
kHz
Standard mode 100
Fast mode 1.3
µs
Standard mode 4.7
Fast mode 0.6
µs
6
Standard mode 4.0
Fast mode 1.3
Standard mode 4.7
µs
Fast mode 0.6
µs
Standard mode 4.0
Fast mode 0.6
µs
Standard mode 4.7
Fast mode 0 0.9
µs
7, 8
Standard mode 0
Fast mode 100
ns 9
Standard mode 250
Fast mode 20 + 0.1CB 300
ns 10
Standard mode 1000
Fast mode 20 + 0.1CB 300
ns 10
Standard mode 300
Fast mode 0.6
µs
Standard mode 4.0
Capacitive Load for
Each Bus Line
I/O Capacitance C
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V
order to bridge the undefined region of the falling edge of SCL.
Note 8:The maximum t
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
line is released.
Note 10: C
–Total capacitance of one bus line in pF.
B
has only to be met if the device does not stretch the LOW period (t
HD:DAT
400 pF 10
C
B
10 pF
I/O
) of the SCL signal.
LOW
≥ to 250ns must then be met. This will
SU:DAT
max + t
R
= 1000 + 250 = 1250ns before the SCL
SU:DAT
5 of 15
of the SCL signal) in
IHMIN
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