MAXIM DS1647, DS1647P User Manual

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PFO

OE

CE

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A5A4A

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Nonvolatile Timekeeping RAM

www.maxim-ic.com

FEATURES

 Integrates NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit, and
Lithium Energy Source

 Clock Registers Are Accessed Identically to

the Static RAM. These Registers are
Resident in the Eight Top RAM Locations.

 Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

 BCD Coded Year, Month, Date, Day, Hours,

Minutes, and Seconds with Leap Year
Compensation Valid Through 2099

 Power-Fail Write Protection Allows for

±10% VCC Power-Supply Tolerance

 DS1647 Only (DIP Module):

Standard JEDEC Byte-Wide 128k x 8 RAM

Pinout

 DS1647P Only (PowerCap® Module Board):

Surface Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal
Replaceable Battery (PowerCap)
Power-Fail Output
Pin-for-Pin Compatible with Other Densities

PIN CONFIGURATIONS

TOP VIEW

WE

of DS164XP Timekeeping RAM

ORDERING INFORMATION

PART

DS1647-120

DS1647-120+

DS1647P-120
DS1647P-

120+

DS9034PCX

DS9034PCX+

*DS9034PCX required (must be ordered separately).
**A “+” indicates lead-free. The top mark includes a “+” symbol on lead-free devices.

TEMP

RANGE

0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C
0°C to
+70°C

PIN­PACKAGE

32 EDIP
(0.740a)
32 EDIP
(0.740a)
34
PowerCap*
34
PowerCap*

TOP
MARK**

DS1647­120
DS1647­120
DS1647P­120
DS1647P­120

PowerCap DS9034PC

PowerCap DS9034PC

PowerCap is a registered trademark of Dallas Semiconductor.

N.C.

A15
A16

V

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

GND

CC

DS1647/DS1647P

A18

A16
A14
A12

DQ0
DQ1
DQ2

GND

32-Pin Encapsulated DIP Package

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

A7
A6
A5
A4
A3
A2
A1

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

X1 GND V
16
17

1
2

DS1647

3
4

5
6

7
8

9
10

11
12

13
14
15
16

(32 Pin 740)

DS1647P

BAT

32
31

30
29

28
27

26
25

24
23

22
21

20
19
18
17

X2

V

DQ7
DQ6
DQ5
DQ4
DQ3

34
33
32
31
30
29
28

27
26
25
24
23
22
21
20
19
18

CC

15
17

8

11

E

10

E

E

18
17
14

12
10

9
8

7
6

3
2
1
0

1 of 11 REV: 112906

PIN DESCRIPTION

PIN

PDIP PowerCap

1 34 A18
2 3 A16
3 32 A14
4 30 A12
5 25 A7
6 24 A6
7 23 A5
8 22 A4

9 21 A3
10 20 A2
11 19 A1
12 18 A0
23 28 A10
25 29 A11
26 27 A9
27 26 A8
28 31 A13
30 33 A17
31 2 A15
13 16 DQ0
14 15 DQ1
15 14 DQ2
17 13 DQ3
18 12 DQ4
19 11 DQ5
20 10 DQ6
21 9 DQ7
16 17 GND Ground
22 8 CE Active-Low Chip Enable
24 7 OE Active-Low Output Enable
29 6 WE Active-Low Write Enable
32 5 VCC Power-Supply Input

— 4

— 1 N.C. No Connection

—

NAME FUNCTION

Address Input

Data Input/Output

Data Input/Output

PFO

X1, X2,

V

BAT

Active-Low Power-Fail Output, Open Drain. This pin requires a
pullup resistor for proper operation.

Crystal Connections and Battery Connection

DS1647/DS1647P

2 of 11

DS1647/DS1647P

DESCRIPTION

The DS1647 is a 512k x 8 nonvolatile static RAM with a full-function real-time clock, which are both
accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any
JEDEC standard 512k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and
EEPROM, providing read/write nonvolatility and the addition of the real-time clock function. The real­time clock information resides in the eight uppermost RAM locations. The RTC registers contain year,
month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the
month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access
of incorrect data that can occur during clock update cycles. The double-buffered system also prevents
time loss as the timekeeping countdown continues unabated by access to time register data. The DS1647
also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of­tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.

PACKAGES

The DS1647 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1647P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.

CLOCK OPERATIONS—READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1647 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that clock accuracy is not
affected by the access of data. All of the DS1647 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.

The read bit must be a zero for a minimum of 500ms to ensure that the external registers are updated.

3 of 11

Figure 1. Block Diagram

DS1647/DS1647P

DS1647

Table 1. Truth Table

VCC

5V ±10%

<4.5V >V

<V

BAT

X X X Deselect High-Z CMOS Standby

BAT

X X X Deselect High-Z Data-Retention Mode

CE OE WE

MODE DQ POWER

VIH X X Deselect High-Z Standby

X X X Deselect High-Z Standby
VIL X VIL Write Data In Active
VIL VIL VIH Read Data Out Active
VIL VIH VIH Read High-Z Active

4 of 11

DS1647/DS1647P

SETTING THE CLOCK

The MSB Bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit halts
updates to the DS1647 registers. The user can then load them with the correct day, date and time data in
24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters
and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB for the second’s registers. Setting it
to a 1 stops the oscillator.

FREQUENCY TEST BIT

Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the
oscillator is running, the LSB of the second’s register will toggle at 512Hz. When the seconds register is
being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid
(i.e., CE low, OE low, and address for seconds register remain valid and stable).

CLOCK ACCURACY (DIP MODULE)

The DS1647 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also affected by the electrical environment and caution should be taken to
place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer
to Application Note 58.

CLOCK ACCURACY (POWERCAP MODULE)

The DS1647 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. Clock

accuracy is also affected by the electrical environment and caution should be taken to place the RTC in
the lowest-level EMI section of the PC board layout. For additional information, refer to Application
Note 58.

Table 2. Register Map—BANK1

ADDRESS

B

B

7

B

6

B

5

7FFFF — — — — — — — — Year 00–99

7FFFE X X X — — — — — Month 01–12
7FFFD X X — — — — — — Date 01–31
7FFFC X FT X X X — — — Day 01–07
7FFFB X X — — — — — — Hour 00–23
7FFFA X — — — — — — — Minutes 00–59

7FFF9

OSC

— — — — — — — Seconds 00–59

7FFF8 W R X X X X X X Control A

OSC = STOP BIT
W = WRITE BIT X = UNUSED

Note:

All indicated “X” bits are unused, but must be set to “0” when written to ensure proper clock operation.

R = READ BIT FT = FREQUENCY TEST

DATA

B

4

B

3

B

2

B

1

0

FUNCTION

5 of 11

DS1647/DS1647P

RETRIEVING DATA FROM RAM OR CLOCK

The DS1647 is in the read mode whenever WE (write enable) is high; CE (chip enable) is low. The
device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid
data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE
and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be
available at the latter of chip-enable access (t

) or at output enable access time (t

CEA

). The state of the

OEA

data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data
lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE
remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate
until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1647 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE. The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs t

after WE goes active.

WEZ

DATA-RETENTION MODE

When VCC is within nominal limits (VCC > 4.5V) the DS1647 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from all access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal (PFO) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.

BATTERY LONGEVITY

The DS1647 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the V
is sufficient to power the DS1647 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1647 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than

, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the

V

PF

DS1647 will be longer than 10 years since no lithium battery energy is consumed when VCC is present.

supply is not present. The capability of this internal power supply

CC

6 of 11

DS1647/DS1647P

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground…………………………….…………….…-0.3V to +6.0V
Operating Temperature Range (Noncondensing)………………………………………….….0°C to +70°C
Storage Temperature Range…………………………….…………………………………..-40°C to +85°C
Soldering Temperature (EDIP) (leads, 10 seconds)………………….……+260°C for 10 seconds (Note 7)
Soldering Temperature………………………………...See IPC/JEDEC J-STD-020 Specification (Note 7)

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS

(TA = 0°C to +70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Supply Voltage VCC 4.5 5.0 5.5 V 1

Logic 1 Voltage, All Inputs VIH 2.2 VCC + 0.3 V

Logic 0 Voltage, All Inputs VIL -0.3 +0.8 V

DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0°C to +70°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Average VCC Power Supply Current I
TTL Standby Current (CE = VIH)

CMOS Standby Current
(CE = VCC - 0.2V)

85 mA 2, 3

CC1

I

3 6 mA 2, 3

CC2

I

2 4.0 mA 2, 3

CC3

Input Leakage Current (Any Input)

Output Leakage Current

IIL -1 +1

IOL -1 +1

mA

mA

Output Logic 1 Voltage

2.4 V

V

(I

= -1.0mA) (DQ0–DQ7)

OUT

OH

Output Logic 0 Voltage

0.4 V

V

(I

= +2.1mA) (DQ0–DQ7, PFO)

OUT

OL

Write-Protection Voltage VPF 4.0 4.5 V

CAPACITANCE

(TA = +25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance on All Pins (Except DQ) CI 7 pF

Capacitance on DQ Pins CDQ 10 pF

7 of 11

DS1647/DS1647P

AC ELECTRICAL CHARACTERISTICS

(VCC = 5.0V ±10%, TA = 0°C to +70°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns

Address Access Time tAA 120 ns

t

CE Access Time
CE Data Off Time
OE Access Time
OE Data Off Time
OE to DQ Low-Z
CE to DQ Low-Z

Output Hold from Address tOH 5 ns

Write Cycle Time tWC 120 ns

Address Setup Time tAS 0 ns
CE Pulse Width

Address Hold from End of Write

Write Pulse Width t

WE Data Off Time
WE or CE Inactive Time

120 ns

CEA

t

40 ns

CEZ

t

100 ns

OEA

t

40 ns

OEZ

t

5 ns

OEL

t

5 ns

CEL

t

100 ns

CEW

t

5 5

AH1

t

30

AH2

75 ns

WEW

t

40 ns

WEZ

ns

6

tWR 10 ns

Data Setup Time tDS 85 ns

t

0 5

Data Hold Time High

DH1

t

25

DH2

ns

6

8 of 11

READ CYCLE TIMING

DS1647/DS1647P

WRITE CYCLE TIMING

9 of 11

DS1647/DS1647P

AC ELECTRICAL CHARACTERISTICS—POWER-UP/POWER-DOWN TIMING

(VCC = 5.0V ±10%, TA = 0°C to +70°C.)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VIH before Power-Down
VPF
VPF
VSO to VPF
VPF

to VPF

(MAX)

to VSO VCC Fall Time tFB 10

(MIN)

to VPF

(MIN)

(MIN) VCC

(MIN) VCC

(MAX) VCC

Fall Time tF 300

Rise Time tRB 1

Rise Time tR 0
Power-Up t
Expected Data-Retention Time +25°C
(Oscillator On)

POWER-DOWN/POWER-UP TIMING

tPD 0

ms
ms
ms
ms
ms

15 35 ms

REC

tDR 10 years 4

OUTPUT LOAD

10 of 11

AC TEST CONDITIONS

Output Load: 50pF + 1TTL Gate
Input Levels: 0 to 3V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns

NOTES:

1) All voltages are referenced to ground.

2) Typical values are at +25°C and nominal supplies.

3) Outputs are open.

DS1647/DS1647P

4) Each DS1647 has a built-in switch that disconnects the lithium source until V
user. The expected t

is defined for DIP modules as a cumulative time in the absence of VCC starting

DR

is first applied by the

CC

from the time power is first applied by the user.

5) t

6) t

AH1

AH2

, t

are measured from WE going high.

DH1

, t

are measured from CE going high.

DH2

7) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wave­soldering techniques as long as temperatures as long as temperature exposure to the lithium energy
source contained within does not exceed +85°C. Post-solder cleaning with water washing techniques
is acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for
details regarding the PowerCap package.

PACKAGE INFORMATION

For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.

28-pin 740 EDIP Module Document number: 56-G0002-001

32-pin PowerCap Module Document number: 56-G0003-001

11 of 11

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel D rive, Sunnyvale, CA 94086 408-737-7600

© 2006 Maxim Integrated Products • Printed USA

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.